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| EMIF10-LCD02F3 10 line EMI filter and ESD protection for LCD and cameras Main product characteristics: Where EMI filtering in ESD sensitive equipment is required : LCD for Mobile phones Computers and printers Communication systems MCU Boards Flip-Chip (24 bumps) Description The EMIF10-LCD02F3 is a 10 lines highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up 15kV. Pin Configuration (bump side) 5 O1 O3 O5 O7 O9 4 O2 O4 O6 O8 O10 3 GND 2 I1 I3 1 I2 I4 I6 I8 I10 A B C D E GND I5 I7 I9 GND Benefits GND Lead free package EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering 400 m pitch Compatible with high speed data rate Very low PCB space consuming: < 4mm2 Very thin package: 0.60 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reducing of parasitic elements through integration and wafer level packaging GND GND GND Ri/o = 70 Cline = 30pF Basic Cell Configuration Low-pass Filter Input Output Complies with the following standards: IEC61000-4-2: Level 4 15 kV (air discharge) 8 kV ( contact discharge) Order Code Part Number EMIF10-LCD02F3 Marking GY on inputs and outputs MIL STD 833E - Method 3015-6 Class 3 July 2005 Rev 1 1/8 www.st.com 8 1 Electrical characteristics (Tamb = 25C) EMIF10-LCD02F3 Table 1. Symbol Tj Top Tstg Absolute Maximum Ratings Parameter Junction temperature Operating temperature range Storage temperature range Value 125 -40 to + 85 -55 to +150 Unit C C C 1 Symbol VBR IRM VRM VCL IPP RI/O Cline Electrical characteristics (Tamb = 25C) Parameter I Breakdown voltage IF Leakage current @ VRM Stand-off voltage VCL VBR VRM VF IRM IR V Clamping voltage Peak pulse current Series resistance between Input & Output Input capacitance per line IPP Symbol VBR IRM RI/O Cline IR = 1 mA VRM = 3V Tolerance 20% Test conditions Min. 6 Typ. 8 50 70 Max. 10 200 Unit V nA Vline = 0V, VOSE = 30 mV, F =1 MHz 30 pF 2/8 EMIF10-LCD02F3 Figure 1. S21(dB) all lines attenuation Figure 2. measurement and Aplac simulation 1 Electrical characteristics (Tamb = 25C) Analog cross talk measurements 0.00 dB -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 100.0k 1.0M 10.0M f/Hz 100.0M Xtalk 1/2 1.0G Figure 3. ESD response to IEC61000-4-2 (+15kV air discharge) on one input and on one output Figure 4. ESD response to IEC61000-4-2 (-15kV air discharge) on one input and on one output Input 10V/d Input 10V/d Output 10V/d Output 10V/d 100ns/d 100ns/d Figure 5. Line capacitance versus applied voltage Cline (pF) 30 25 20 15 10 5 Vline (V) 0 0 1 2 3 4 5 6 3/8 2 Aplac model EMIF10-LCD02F3 2 Aplac model Figure 6. Device structure (one cell) Lbump I1 Rbump Rline Rbump Lbump O1 MODEL = D1 MODEL = D2 bulk bulk MODEL = D3 Rbump Cbump Cbump Lbump Rbump Cbump Lbump Rbump Cbump Lbump Rbump Lbump Rgnd Lgnd Rgnd Lgnd Rgnd Lgnd Rgnd Lgnd Figure 7. Aplac model variables aplacvar Rline 70 aplacvar C_d1 15p aplacvar C_d2 15p aplacvar C_d3 600p aplacvar Ls 950pH aplacvar Rs 150m aplacvar Lbump 50pH aplacvar Rbump 20m aplacvar Cbump 150f aplacvar Lgnd 50pH aplacvar Rgnd 100m aplacvar Rsub 10m Diode D1 BV=7 IBV=1m CJO=C_d1 M=0.28 RS=0.1 VJ=0.6 TT=100n Diode D2 BV=7 IBV=1m CJO=C_d2 M=0.28 RS=0.1 VJ=0.6 TT=100n Diode D3 BV=7 IBV=1m CJO=C_d3 M=0.28 RS=0.01 VJ=0.6 TT=100n 4/8 EMIF10-LCD02F3 3 Ordering information scheme 3 Ordering information scheme EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip 3 = Lead free Pitch = 400m, Bump = 255m yy - xxx zz F3 5/8 4 Package information EMIF10-LCD02F3 4 Figure 8. Package information Mechanical data 400m 40 255m 40 605m 55 400m 40 185m 10 185m 10 1.97mm 30m Figure 9. Foot print recommendations Figure 10. Marking Copper pad Diameter: 220m recommended 260m maximum Solder mask opening: 300m minimium 1.97mm 30m Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week) E Solder stencil opening : 220m recommended xxz y ww 6/8 EMIF10-LCD02F3 5 Flip-chip tape and reel specifications 5 Flip-chip tape and reel specifications Dot identifying Pin A1 location 4 +/- 0.1 O 1.5 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1 0.73 +/- 0.05 All dimensions in mm 8 +/- 0.3 STE STE STE xxz yww User direction of unreeling xxz yww xxz yww 4 +/- 0.1 6 Ordering information Part Number EMIF10-LCD02F3 Marking GY Package Flip-Chip Weight 5.0 mg Base qty 5000 Delivery mode Tape & reel (7") 7 Revision history Date 11-Jul-2005 Revision 1 Initial release. Changes 7/8 7 Revision history EMIF10-LCD02F3 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 8/8 |
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