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| FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller May 2005 FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Features Selectable 1-, 2-, or 3-phase operation at up to 1MHz per phase 2% Worst-case differential sensing error over temperature Externally adjustable 0.8V to 5V output from a 12V supply Logic-level PWM outputs for interface to external high-power drivers Active current balancing between all phases Built-in power-good/crowbar functions Programmable over current protection with adjustable latchoff delay Description The FAN5182 is a highly efficient multi-phase synchronous buck switching regulator controller optimized for converting a 12V main supply into a high-current low voltage supply for use in point-of-load (POL) applications. It uses a multi-loop PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for regulator size and efficiency. The phase relationship of the output signals can be programmed to provide 1, 2, or 3-phase operation, allowing for construction of up to three complementary interleaved buck switching stages. The FAN5182 also provides accurate and reliable over-current protection and adjustable current limiting. FAN5182 is specified over the commercial temperature range of 0C to +85C and is available in a 20-lead QSOP package. Applications Auxiliary supplies DDR memory supplies Point-of-load supplies Block Diagram VCC 1 RAMPADJ 9 RT 8 FAN5182 UVLO SHUTDOWN & BIAS EN 6 OSCILLATOR SET RESET EN 20 PWM1 + GND 14 950mV FB - + - CMP CURRENT BALANCING CIRCUIT + + - CMP RESET 1/ 2 / 3-PHASE DRIVER LOGIC RESET 19 PWM2 + - CMP 18 PWM3 650mV - CROWBAR DELAY CURRENT LIMIT PWRGD 5 1.05V FB - + 17 SW1 16 SW2 15 SW3 ILIMIT 10 EN CURRENT LIMIT CIRCUIT SOFT START - + 12 CSSUM DELAY 7 11 CSREF 13 CSCOMP - 3 COMP 4 FB + 800 mV REFERENCE 2 FBRTN (c)2005 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FAN5182 Rev. 1.0.1 FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Pin Assignment VCC 1 FBRTN 2 FB 3 COMP 4 PWRGD EN DELAY RT RAMPADJ ILIMIT 5 20 19 18 17 16 PWM1 PWM2 PWM3 SW1 SW2 SW3 GND CSCOMP CSSUM CSREF FAN5182 6 7 8 9 10 15 14 13 12 11 QSOP-20L Pin Description Pin # 1 2 3 Pin Name VCC FBRTN FB Supply Voltage for the Device. Pin Description Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider between the output and FBRTN connected to this pin sets the output voltage. This pin is also the reference point for the power good and crowbar comparators. Error Amplifier Output and Compensation Pin. Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current Limit Setpoint/Enable Output. An external resistor connected from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the FAN5182 EN input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the gain of the current sense amplifier. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. These are inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 4 5 6 7 COMP PWRGD EN DELAY 8 9 10 RT RAMPADJ ILIMIT 11 12 13 14 15-17 18-20 CSREF CSSUM CSCOMP GND SW3 To SW1 PWM3 To PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the FAN5009. Connecting the PWM3 output to GND causes that phase to turn off, allowing the FAN5182 to operate as a 1- or 2-phase controller. 2 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Absolute Maximum Ratings (Note 1) Parameter VCC FBRTN EN, DELAY, ILIMIT, RT, PWM1-PWM3, COMP SW1-SW3 All Other Inputs and Outputs Operating Junction Temperature, TJ Storage Temperature Lead Soldering Temperature (10 seconds) Lead Infrared Temperature (15 seconds) Thermal Resistance Junction-to-Case, (JC) Thermal Resistance Junction-to- Ambient, (JA) (Note 2) Min. -0.3 -0.3 -0.3 -5 -0.3 0 -65 Max. +15 +0.3 5.5 +25 VCC + 0.3 +125 +150 300 260 38 90 Unit V V V V V C C C C C/W C/W Recommended Operating Conditions Parameter Supply Voltage Range Operating Ambient Temperature Min 10.8 0 Typ 12 Max 13.2 +85 Unit V C Notes: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND. 2. Junction to ambient thermal resistance, JA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics. Measured with the device mounted on a board of FR-4 material, 0.063" thickness, no copper plane and zero airflow. 3 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Electrical Characteristics VCC = 12V, FBRTN = GND. Indicates specifications over operating ambient temperature range. (Note 1) Parameter OSCILLATOR Frequency Range Frequency Variation fOSC fPHASE RT = 332k, 3-phase TA = 25C, RT = 154k, 3-phase TA = 25C, RT = 100k, 3-phase RT = 100k to GND RAMPADJ - FB - 2K x IRAMPADJ (with IRAMPADJ set to 20 A) Symbol Conditions Min. 0.25 155 Typ. Max. 3 Units MHz kHz 200 400 600 2.0 245 Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range (Note 2) VOLTAGE ERROR AMPLIFIER Output Voltage Low Output Voltage High Accuracy Input Bias Current Line Regulation FBRTN Current Output Current DC Gain (Note 2) Gain Bandwidth Product (Note 2) Slew Rate (Note 2) CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current DC Gain (Note 2) Gain Bandwidth Product (Note 2) Slew Rate (Note 2) Input Common-Mode Range Output Voltage Low Output Voltage High Output Current CURRENT BALANCE CIRCUIT Common-Mode Range (Note 2) Input Resistance Input Current Input Current Matching VRT VRAMPADJ IRAMPADJ V +50 100 mV A -50 0 0.3 3.1 VFB IFB VFB IFBRTN IO(ERR) FB forced to VOUT - 3% COMP = FB CCOMP = 10pF VOS(CSA) IBIAS(CSSUM) GBW(CSA) CCSCOMP = 10pF CSSUM & CSREF 0 CSSUM-CSREF ( See Figure 1.) V V Referenced to FBRTN FB = 800mV VCC = 10V to 14V 784 -4 800 1 0.05 816 +4 mV A % A A dB MHz V/s 100 500 87 140 GBW(ERR) 20 10 -5.5 -50 70 10 10 +5.5 +50 mV nA dB MHz V/s VCC-2.5 0.1 V V V A VCC-2.5 ICSCOMP VSW(X)CM RSW(X) ISW(X) ISW(X) VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) SW(X) = 0V SW(X) = 0V SW(X) = 0V EN > 2V, RILIMIT = 250k EN < 0.8V, IILIMIT = -100A EN > 2V, RILIMIT = 250k 500 -600 20 4 -7 30 7 +200 40 10 +7 mV k A % CURRENT LIMIT COMPARATOR Output Voltage: Normal Mode Output Voltage: Shutdown Mode Output Current: Normal Mode Maximum Output Current 2.9 3 3.1 400 V mV A A 12 60 4 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Parameter Current Limit Threshold Voltage Current Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time (Note 2) SOFT-START Output Current, Soft-Start Mode Soft-Start Delay Time (Note 2) ENABLE INPUT Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Current POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Ouput Low Voltage Power Good Delay Time Crowbar Trip Point Crowbar Reset Point Crowbar Delay Point (Note 2) PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY DC Supply Current UVLO THreshold Voltage UVLO Hysteresis Symbol VCL Conditions VCSREF - VCSCOMP, RILIMIT = 250k VCL/IILIMIT RDELAY = 250k RDELAY = 250k RDELAY = 250k, CDELAY = 12nF During startup, DELAY < 2.4V RDELAY = 250k, CDELAY = 12nF Min. 105 Typ. 125 10.4 Max. 145 Units mV mV/A VDELAY(NM) VDELAY(OC) tDELAY IDELAY(SS) tDELAY(SS) VIL(EN) VIH(EN) IIN(EN) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) VCROWBAR tCROWBAR VOL(PWM) VOH(PWM) 2.9 1.7 3 1.8 1.5 3.1 1.9 V V ms A s 15 20 500 25 0.8 2.0 100 V V mV A mV mV mV ns -1 +1 Relative to FBRTN Relative to FBRTN IPWRGD(SINK) = 4mA Relative to FBRTN Relative to FBRTN Overvoltage to PWM going low 600 880 660 940 225 200 720 1000 400 0.970 550 1.05 650 400 1.105 750 V mV ns IPWM(SINK) = 400A IPWM(SOURCE) = -400A 160 4.0 5 500 mV V 5 6.5 0.7 6.9 0.9 10 7.3 1.1 mA V V VUVLO VCC rising Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 2. Guaranteed by design, not tested in production. 5 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Test Circuit FAN5182 VCC 12V 1 CSCOMP 39k 100nF 13 CSSUM + - 12 1k 11 CSREF + - 14 0.8V GND VOS = CSCOMP - 0.8V 40 Figure 1. Current Sense Amplifier VOS 6 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Typical Characteristics 3 1.002 MASTER CLOCK FREQUENCY (MHz) NORMALIZED VFB 1.000 2 0.998 0.996 0.994 1 0.992 0 0 0 50 100 150 200 RT VALUE (kW) 250 300 25 85 TEMPERATURE (C) Figure 4. Normalized VFB vs. Temperature Figure 2. Master Clock Frequency 5.4 TA = 25C 3-PHASE OPERATION 5.3 SUPPLY CURRENT (mA) 5.2 5.1 5.0 4.9 4.8 4.7 0 0.5 1 1.5 2 OSCILLATOR FREQUENCY (MHz) 2.5 3 Figure 3. Supply Current vs. Osc. Frequency 7 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Application Circuit L1 1H 12 V VIN + VIN RTN + C2 C1 2700F 2700F 16V 16V D1 (optional) C5 4.7F U2 FAN5009 1 2 3 4 C4 100nF Q1 FDD6296 BOOT PWM OD VCC HDRV 8 SW PGND LDRV 7 6 5 L2 600nH / 1.4m C6 2.2nF R1 2.2 1200F / 6.3V x 5 15m ESR (each) + C17 + C21 C3 1F Q2 FDD8896 VOUT 1.8 V 55A VOUT RTN D2 (optional) U3 FAN5009 1 2 3 4 C8 100nF C9 4.7F Q3 FDD6296 L3 600nH / 1.4m C10 2.2nF R2 2.2 Q4 FDD8896 4.7Fx10 6.3V MLCC BOOT PWM OD VCC HDRV 8 SW PGND LDRV 7 6 5 C7 1F D3 (optional) U4 FAN5009 1 2 3 4 C12 100nF C13 4.7F Q5 FDD6296 L4 600nH / 1.4m C14 2.2nF R3 2.2 Q6 FDD8896 BOOT PWM OD VCC HDRV 8 SW PGND LDRV 7 6 5 C11 1F R4 10 C15 1F RR 332k 1 2 3 4 5 6 7 U1 FAN5182 VCC FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ PWM1 20 PWM2 19 PWM3 18 SW1 17 SW2 16 SW3 15 GND 14 CSCOMP 13 CSSUM 12 CSREF 11 RSW2 * RSW3 * RPH3 RPH2 RPH1 140k 140k 140k RCS 100k CCS 5.6nF RSW1 * RB1 1.00k RA 6.04k CFB 100pF POWER GOOD ENABLE RB2 1.24k CA 1.2nF CDLY 68nF RDLY 261k RT 255k 8 9 10 ILIMIT RLIM 287k Figure 5. 1.8V, 55A Application Circuit ( Consult Fairchild Sales for an updated version of the Application Circuit ) 8 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Theory of Operation The FAN5182 combines a multi-loop, fixed frequency PWM control with multi-phase logic outputs for use in 1-, 2-, and 3-phase synchronous buck point-of-load power supplies. Multi-phase operation is important for producing the high current and low voltage demanded by auxiliary supplies in desktop computers, workstations, and servers. Handling high current in a singlephase converter places high thermal stress on components such as inductors and MOSFETs, therefore is not preferred. The multi-loop control of the FAN5182 ensures a stable, high performance topology for: * Balancing current and thermal between/among phases * Fast response at the lowest possible switching frequency and output decoupling * Reducing switching losses due to low frequency operation * Tight line and load regulation * Reducing output ripple due to multiphase cancellation * Better noise immunity to facilitate PCB layout 100A to allow accurate remote sensing. The internal error amplifier compares the precision reference to the FB pin to regulate the output voltage. Output Current Sensing The FAN5182 uses a current sense amplifier (CSA) to monitor the total output current for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured several ways depending on the objectives of the system design: * Output inductor DCR sensing without a thermistor for lowest cost * Output inductor DCR sensing with a thermistor for improved accuracy and moderate cost * Discrete resistor sensing for the best accuracy The positive input of the CSA is connected to the CSREF pin, and the CSREF is tied to the power supply output. The inverting input of the CSA, CSSUM, is the summing node of load current sense through sensing elements (such as the switch node side of the output inductors). The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. The current information is then given as the difference between CSREF and CSCOMP. This difference signal is then used as a differential input for the current limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have low input offset voltage. The CSA gain is determined by external resistors, so that it can be set very accurately. Start-up Sequence During start-up, the number of operational phases and their phase relationship are determined by the internal circuitry that monitors the PWM outputs. Normally, the FAN5182 operates as a 3-phase PWM controller. Grounding the PWM3 pin programs for 1- or 2-phase operation. When the FAN5182 is enabled, the controller outputs a voltage on PWM3 which is approximately 675mV. An internal comparator checks this pin's voltage versus a threshold of 300mV. If the PWM3 pin is grounded, it is below the threshold and the phase 3 is disabled. The output resistance of the PWM pin is approximately 5k during this detection period. Any external pull-down resistance connected to the PWM pin should not be less than 25k to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM3 output is not grounded, the 5k resistance is disconnected and PWM3 switches between 0V and 5V. If the PWM3 output is grounded, the controller will operate in 1 and/or 2-phase. The PWMs output logic-level signals in order to interface with external gate drivers such as the FAN5009. Since each phase is able to operate close to 100% duty cycle, more than one PWM output can be on at the same time. Current Control Loop and Thermal Balance The FAN5182 adopts low side MOSFET RDSON sensing for phase current balance. The sensed individual phase current is combined with a fixed internal ramp, then compared with the common voltage error amplifier output to balance phase current. This current balance information is independent of the average output current information used for current limit described previously. The magnitude of the internal ramp can be set to optimize transient response of the system. It also tracks the supply voltage for better line regulation and transient response. A resistor connected from the power supply input to the RAMPADJ pin determines the slope of the internal PWM ramp. Resistors RSW1 through RSW3 (see Figure 5) can be used for adjusting phase current balance. It's recommended to put placeholders for these resistors during the initial PCB layout, so that phase current balance fine adjustments can be made on bench if necessary. To increase the current in any given phase, make RSW for that phase larger (make RSW = 0 for the hottest phase as the starting point). Increasing RSW to 500 could typically make a substantial increase in this particular phase current. Increase each RSW value by small amounts to optimize phase current balance, starting with the coolest phase first. Master Clock Frequency The clock frequency of the FAN5182 is set by an external resistor connected from the RT pin to ground. The frequency setting follows the graph shown in Figure 2. To determine the frequency per phase, divide the clock frequency by the number of phases in use. One exception is single phase operation, in which the clock frequency is set to be twice the single phase frequency. Output Voltage Differential Sensing The FAN5182 uses a differential low offset voltage error amplifier to maintain 2% differential sensing accuracy over temperature. The output voltage is sensed between the FB and FBRTN pins. The power supply output connects to the FB pin through a resistor divider, and the FBRTN pin should be connected directly to the remote sense ground. The internal precision reference is referenced to FBRTN, which has a typical current of 9 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Voltage Control Loop A high gain-bandwidth voltage error amplifier is used for the voltage control loop. The non-inverting input of the error amplifier is derived from the internal 800mV reference. The output of the error amplifier, the COMP pin sets the termination voltage for the internal PWM ramps plus sensed phase current. The inverting input (FB) is tied to the center point of a resistor divider from the output voltage sense point. The closed loop compensation is realized through the compensator networks connecting to the FB and COMP pins. After the limit is reached, the 3V pull-up voltage source on the DELAY pin is disconnected, and the external DELAY capacitor discharges through the external resistor. A comparator monitors the DELAY pin voltage and shuts off the controller when the voltage drops below 1.8V. The current limit latch-off delay time is therefore set by the RC time constant discharging the DELAY voltage from 3V to 1.8V. Typical over-current latch-off waveforms are shown in Figure 7. Soft Start The soft-start rise time of the output voltage is set by a parallel capacitor and resistor between the DELAY pin and ground. The resistor capacitor (RC) time constant also determines the current limit latch off delay time as explained in the following section. In UVLO or when EN is logic low, the DELAY pin is held to ground. After the UVLO threshold is reached and EN is in logic high state, the DELAY capacitor is charged with an internal 20A current source. The output voltage follows the ramping voltage on the DELAY pin to limit the inrush current. The softstart time depends on the value of CDLY, with a secondary effect from RDLY. If either EN is logic low or VCC drops below UVLO, the DELAY capacitor resets to ground, and is ready for another soft-start cycle. Figure 6. Typical Startup Waveforms shows a typical soft-start sequence for the FAN5182. Figure 7. Over-current Latch-off Waveforms The controller continues to switch all phases during the latch-off delay time. If the over-current condition is removed before the 1.8V DELAY threshold being reached, the controller will resume its normal operation. The over current recovery characteristic also depends on the state of PWRGD. If the output voltage is within the PWRGD window during over current, the controller resumes normal operation once over current condition being removed. However, if over current causes the output voltage to drop below the PWRGD threshold, a soft-start cycle will be initiated. The latch-off function can be reset by either removing and reapplying VCC to the FAN5182 or by pulling the EN pin low for short time. To disable the over current latch-off function, the external resistor connecting between the DELAY pin and ground should be removed, and a high value resistor (>1M) should be connected from the DELAY pin to VCC. This prevents the DELAY capacitor from discharging, so the 1.8V threshold can never be reached. This pull-up resistor has some impact to the soft-start time, because the current through this pull-up resistor adds additional current to the internal 20A soft-start current. During start-up when the output voltage is below 200mV, a secondary current limit is activated. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit clamps the COMP voltage to 2V. An inherent per phase current limit protects individual phase if one or more phases cease to function because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Figure 6. Typical Startup Waveforms Current Limit and Latch-off Protection The FAN5182 compares a programmable current limit set point to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3V. The current through the external resistor is internally scaled to give a current limit threshold of 10.4mV/A. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the COMP voltage to maintain the power supply output current at the over current level. 10 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Power Good Monitoring The power good comparator monitors the output voltage via the FB pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in the electrical characteristic table. PWRGD goes low if the output voltage is outside of this specified range or whenever the EN pin is pulled low. Figure 8. shows the PWRGD response when the input power supply is switched off. Figure 8. Shutdown Waveforms As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the lowside MOSFETs) when the output voltage exceeds the crowbar trip point. This crowbar action stops once the output voltage falls below the reset threshold of approximately 650mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output over voltage is due to a short in the high-side MOSFET, this crowbar action can trip the input supply over current protection or blow the input fuse, protecting the load from being damaged. Enable and UVLO For the FAN5182 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is logic low, the FAN5182 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the FAN5009 drivers. Grounding the ILIMIT pin will disable the drivers such that both HDRV and LDRV are holding low. This feature is important in preventing fast discharge of the output capacitors when the controller shuts off. If the driver outputs are not being disabled, a negative output voltage can be generated due to high current being discharged from the output capacitors through the inductors. 11 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Application Information Design parameters for a typical high current point-of-load dc/dc buck converter shown in Figure 5 are as follows: * Input voltage (VIN) = 12V * Output voltage (VOUT) = 1.8V * Duty cycle (D) = 0.15 * Output current IO = 55A * Maximum output current (ILIM) = 110A * Number of phases (n) = 3 * Switching frequency per phase (fSW) = 250kHz a longer latch-off time should be used. RDLY should never be less than 200k. In this example, a delay time of 9ms results in RDLY = 259k. The closest standard 1% value is 261k. Inductor Selection The inductance determines the ripple current in the inductor. Small inductance leads to high ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, and vise versa. In any multiphase converters, it's recommended to design the peak-peak inductor ripple current to be less than 50% of the maximum inductor dc current. Equation 4 shows the relationship among the inductance, oscillator frequency, and peak-peak ripple current. Setting the Clock Frequency The FAN5182 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and the input and output capacitors. With n = 3 for three phases, a clock frequency of 750kHz sets the switching frequency (fSW) of each phase to 250kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Equation 1 shows that to achieve a 750kHz oscillator frequency, the correct value for RT is 255k. Alternatively, the value for RT can be calculated using V OUT x ( 1 - D ) I R = ------------------------------------f SW x L (4) Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. V OUT x R x x ( 1 - ( n x D ) ) L ---------------------------------------------------------------f SW x V RIPPLE where RX is the ESR of output bulk capacitors. (5) Solving Equation 5 for a 20mV peak-to-peak output ripple voltage and 3m RX yields 1.8V x 3m x ( 1 - ( 3 x 0.15 ) ) L --------------------------------------------------------------------------- = 594nH 250kHz x 20mV If the resulting ripple voltage is too low, the inductance can be reduced until the desired ripple voltage is achieved. In this example, a 600nH inductor is a good starting point that produces a calculated ripple current of 6.6A. The inductor should not saturate at the peak current of 21.6A, and should be able to handle the total power dissipation created by the copper and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase current. A large DCR can cause excessive power losses, whereas too small DCR can increases measurement error. For this design, a DCR of 1.4m was chosen. 1 R T = ------------------------------------- - 27k n x f SW x 4.7pF 1 R T = ------------------------------------------------- - 27k = 256k 3 x 250kHz x 4.7pF (1) where 4.7pF and 27k are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. The closest standard 1% value for this design is 255k. Soft-Start and Current Limit Latch-off Delay Time Because the soft start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft-start ramp. This ramp is generated with a 20A internal current source. The value of RDLY has a second-order impact on the soft-start time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200k, this effect is minor. The value for CDLY can be approximated using: Designing an Inductor Once the inductance and DCR are known, the next step is to either design an inductor or find a suitable standard inductor if one exists. Inductor design starts with choosing appropriate core material. Some candidate materials that have low core loss at high frequencies are powder cores (e.g. Kool-M(R) from Magnetics, Inc., or from Micrometals) and gapped soft ferrite cores (e.g. 3F3 or 3F4 from Philips). Powdered iron cores have higher core loss, and are used for low cost applications. The best choice for a core geometry is a closed-loop type, such as a potentiometer core, a PQ/U/E core, or a toroid core. Some useful references for magnetics design are * Magnetic Designer Software * Intusoft (www.intusoft.com) * Designing Magnetic Components for High-Frequency DC-DC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008 t SS V REF C DLY = 20A - --------------------- x ----------- V REF 2 x R DLY (2) where tSS is the desired soft-start time. Assuming an RDLY of 390k and a desired soft-start time of 3ms, CDLY is 71nF. The closest standard value for CDLY is 68nF. Once CDLY is chosen, RDLY can be calculated for the current limit latch-off time using: R DLY 1.96 x t DELAY = --------------------------------C DLY (3) If the result for RDLY is less than 200k, a smaller soft-start time should be considered by recalculating the equation for CDLY, or 12 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. * Coilcraft (847) 639-6400 www.coilcraft.com * Coiltronics (561) 752-5000 www.coiltronics.com * Sumida Electric Company (510) 668-0660 www.sumida.com * Vishay Intertechnology (402) 563-6866 www.vishay.com ( R B1 + R B2 ) V OUT = ------------------------------ x V REF R B1 (8) Rearranging Equation 8 to solve RB2 and assuming a 1%, 1k resistor for RB1 yields V OUT - V REF R B2 = -------------------------------- x R B1 V REF 1.8V - 0.8V R B2 = ----------------------------- x 1k = 1.25k 0.8V The closest standard 1% resistor value for RB2 is 1.24k. Power MOSFETs For this example, one high-side and one low-side N-channel power MOSFETs per phase have been selected. The main selection parameters for power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the FAN5009) dictates whether standard threshold or logic-level threshold MOSFETs can be used. With VGATE ~10V, logic-level threshold MOSFETs (VGS(TH) < 2.5V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With good current balance among phases, the current in each lowside MOSFET is the output current divided by the total number of low-side MOSFETs (nSF). Since conduction loss is dominant in low-side MOSFET, the following expression can represent total power dissipation in each synchronous MOSFET in terms of the ripple current per phase (IR) and the total output current (IO): Output Current Sense The output current can be measured by summing the voltage across each inductor and passing the signal through a low-pass filter. The CS amplifier is configured with resistors RPH(X) (for summing the voltage), and RCS and CCS (for the low-pass filter). The output current IO is set by the following equations: R PH ( x ) V DRP I O = --------------- x -----------R CS RL L C CS --------------------R L x R CS where: RL is the DCR of the output inductors. VDRP is the voltage drop from CSCOMP to CSREF. (6) (7) n x IR 2 IO 2 1 P SF = ( 1 - D ) x ------- + ----- x ------------- x R DS ( SF ) n SF n SF 12 (9) When load current reaches its limit, VDRP is at its maximum (VDRPMAX). VDRPMAX can be in the range of 100mV to 200mV. In this example, it is 110mV. One has the flexibility of choosing either RCS or RPH(X). It is recommended to select RCS equal to 100k, and then solve for RPH(X) by rearranging Equation 6. Knowing the maximum output current and the maximum allowed power dissipation, one can determine the required RDS(ON) for the MOSFET. For example, D-PAK MOSFETs operating up to ambient temperature of 50C, a safe limit for PSF is around 1W to 1.5W at 120C junction temperature. Therefore, in this example, RDS(SF) (per MOSFET) < 7.5m. This RDS(SF) is typically measured at junction temperature of about 120C In this example, we select a lower-side MOSFET with 4.8m at 120C. Another important consideration for choosing the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of feedback to input capacitance must be small (less than 10% is recommended) in order to preventing accidentally turning on the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the non-overlap dead time of the MOSFET driver (40ns typical for the FAN5009). The output impedance of the driver is approximately 2, and the typical MOSFET input gate resistances are about 1 to 2. Therefore, the total gate capacitance should be less than 6000pF. In the event there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000pF. The high-side (main) MOSFET power dissipation consists of two elements: conduction and switching losses. The switching loss is related to the main MOSFET's turn on and off time, and the current and voltage being switched. Based on the main I LIM R PH ( x ) = R L x R CS x ----------------------V DRPMAX 110A R PH ( x ) = 1.4m x 100k x ----------------- = 140k 110mV Next, use Equation 7 to solve for CCS. 600nH C CS ---------------------------------------- 4.29nF 1.4m x 100k Choose the closest standard value that is greater than the result given by Equation 7. This example uses a CCS value of 5.6nF. Output Voltage FAN5182 has an internal FBRTN referred 800mV voltage reference (VREF). The output voltage can be set by using a voltage divider consists of resistors RB1 and RB2: 13 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller MOSFET's switching speed (rise and fall time that the gate driver can offer) and MOSFET input capacitance, the following expression provides approximate switching loss for each main MOSFET: best combination of phase current balance, stability, and transient response. The following expression is used to determine the optimum value: P S ( MF ) where: V CC x I O n MF = 2 x f SW x --------------------- x R G x --------- x C ISS n MF n (10) AR x L R R = -----------------------------------------------------------------3 x A D x R DS ( ON ) ( SF ) x C R 0.2 x 600nH R R = --------------------------------------------------- = 333k 3 x 5 x 4.8m x 5pF where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. (13) nMF is the total number of main MOSFETs. RG is the total gate resistance (2 for the FAN5009 and about 1 for typical logic level n-channel MOSFETs, total RG = 3). CISS is the input capacitance of the main MOSFET. Note that adding more main MOSFETs (nMF) does not help to lower the switching loss for each main MOSFET, it can only reduces conduction loss. The most efficient way to reduce switching loss is to use low gate charge / capacitance devices. The conduction loss of the main MOSFET is given by the following equation: RDS(ON)(SF) is the equivalent low-side MOSFET on resistance. CR is the internal ramp capacitor value. The closest standard 1% resistor value is 332k.. The internal ramp voltage magnitude can be calculated by using P C ( MF ) n x IR 2 IO 2 1 = D x --------- + ----- x ------------- x R DS ( MF ) n MF 12 n MF ( V IN - V REF ) x A R x D V R = --------------------------------------------------------( R R + 2K ) x C R x f SW ( 12 - 0.8 ) x 0.2 x 0.15 V R = --------------------------------------------------------------------------------- = 805mV ( 332k + 2k ) x 5pF x 250kHz (14) (11) where RDS(MF) is the on resistance of the main MOSFET. Typically, for main MOSFETs, a low gate charge (CISS) device is preferred, but low gate charge MOSFETs usually have higher on resistance. Select a device that meets total power dissipation around 1.5W for a single D-PAK MOSFET. In this example, a FDD6296 is selected as the main MOSFET (three total; nMF = 3), with a CISS = 1440pF, and RDS(MF) = 9m (at TJ = 120C), and a FDD8896 is selected as the synchronous MOSFET (three total; nSF = 3), with CISS = 2525pF and RDS(SF) = 5.4m (at TJ = 120C). The synchronous MOSFET CISS is less than 6000pF. Solving for the power dissipation per MOSFET at IO = 55A and IR = 6.6A yields 1.56W for each synchronous MOSFET and 1.29W for each main MOSFET. These numbers comply with the power dissipation limit of around 1.5W per MOSFET. One more item that needs to be considered is the power dissipation in the driver for each phase. The gate drive loss is described in terms of the QG for the MOSFETs, and is given by the following equation The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves but transient response and stability degrade. The factor of three in the denominator of Equation 13 sets a ramp size with optimal balance for good stability, transient response, and thermal balance. Current Limit Setpoint The current limit threshold of the FAN5182 is set with a 3V source (VLIM) across RLIM with a gain of 10.4 mV/A (ALIM). RLIM can be found using A LIM x V LIM R LIM = -----------------------------V DRPMAX (15) f SW PDRV = ------- x (n MF xQ GMF + n SF xQ GSF) + I CC xV CC (12) n where: QGMF is the total gate charge for each main MOSFET. QGSF is the total gate charge for each synchronous MOSFET. ICC x VCC in equation (12) represents the driver's standby power dissipation. For the FAN5009, the maximum dissipation should be less than 400mW. In this example, with ICC = 5mA, QGMF = 25nC, and QGSF = 50nC, there is 285mW in each driver, which is below the 400mW dissipation limit. See the "Thermal Information" table in the FAN5009 datasheet for more details. If RLIM is greater than 500k, the actual current limit threshold may be lower than the intended value. Hence some adjustment for RLIM may be neeeed. Here, ILIM is the average current limit for the output of the supply. In this example, using the VDRPMAX value of 110mV from Equations 6 and 7 and choosing a peak current limit of 110A for ILIM results in RLIM = 284k, for which 287k is chosen as the nearest 1% value. The per phase current limit described earlier is determined by V COMP ( MAX ) - V R - V BIAS I R I PHLIM ----------------------------------------------------------------- + ---A D x R DS ( MAX ) 2 (16) Ramp Resistor Selection The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the 14 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Close Loop Compensation Design Optimum compensation of the FAN5182 assures the best possible load regulation and transient response of the regulator. The target of the compensation design is to achieve reasonably high control bandwidth with sufficient phase and gain margin. The power stage of the synchronous buck converter consists of two poles and one zero. A two-pole, one-zero compensator of the voltage error amplifier is adequate for proper compensation, if the output bulk capacitors are electrolytic types (low ESR zero). Equations 17 to 19 are able to yield an approximate starting point for the design. To further optimize the design, some bench adjustments may be necessary the design. In this example, the input capacitor bank is formed by two 2,700F, 16V aluminum electrolytic capacitors and three 4.7F ceramic capacitors. To reduce the input current di/dt to a level below the system requirement, in this example 0.1A/s, an additional small inductor (L > 370nH @ 10A) can be inserted between the converter and the supply bus. This inductor serves as a filter between the converter and the primary power source. Inductor DCR Temperature Correction With the inductor's DCR being used as the sense element, one needs to compensate for temperature changes in the inductor's winding if a highly accurate current limit setpoint is desired. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage of change in resistance to that of the inductor wire, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed. See Figure 9. for instructions on how to linearize the NTC and produce the desired temperature coefficient. PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET CA n x RX CX x RX = ------------------- x ------------------------------------------------------------------- 4 x R B2 V R ------------- x R L + ( A D x R DS ) V OUT (17) 4 x R B2 L x VR A D x R DS R A = --------------------------- x ------------------------- - ----------------------------- n x C x x R x R x x V OUT 2 x f SW x R x 1 C FB = --------------------------------------2 x n x f SW x R A (18) (19) If CX is 6000F (five 1200F capacitors in parallel) with an equivalent ESR of 3m, the equations above give the following compensation values: CA = 1.33nF RA = 6.05k CFB = 110pF Selecting the nearest standard value for each of these component yields CA = 1.2nF, RA = 6.04k, and CFB = 100pF. As mentioned above, this compensation design scheme is typically good for applications using electrolytic type capacitors, where the capacitor ESR zero can roughly cancel one of the power stage poles. However, for all ceramic capacitor types of applications, since the capacitor ESR zero can be very high, a three-pole, two-zero compensator has to be used. A complete Mathcad control design program is available from Fairchild upon request. FAN5182 RTH TO SWITCH NODES TO VOUT SENSE RPH1 RPH2 RPH3 CSCOMP 13 RCS1 CCS1 CCS2 RCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES CSSUM 12 CSREF 11 Figure 9. Temperature Compensation Circuit Values Follow the procedures and expressions shown below for calculation of RCS1, RCS2, and RTH (the thermistor value at 25C) based on a given RCS value. 1. Select an NTC according to type and value. Because we do not have a value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the NTC type, find its relative resistance value at two temperatures. The temperatures that work well are 50C and 90C. These resistance values are called A (RTH(50C)/ RTH(25C)) and B (RTH(90C)/RTH(25C)). Note that the NTC's relative value is always 1 at 25C. 3. Find the relative value of RCS required for each of these temperatures. This is based on the percentage of change needed, which in this example is initially 0.39%/C. These are called r1 (1/(1 + TC x (T1 - 25))) and r2 (1/(1 + TC x (T2 25))), where TC = 0.0039 for copper. T1 = 50C and T2 = 90C are chosen. From this, one can calculate that r1 = 0.9112 and r2 = 0.7978. Input Capacitor Selection and Input Current di/dt Reduction In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage variation, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by 1 I CRMS = D x I O x ------------ - 1 nxD 1 I CRMS = 0.15 x 55A x ------------------- - 1 = 9.1A 3 x 0.15 (20) Note that manufacturers often specify capacitor ripple current rating based on only 2,000 hours of life. Therefore, it is advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in 15 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller 4. Compute the relative values for RCS1, RCS2, and RTH using ( A - B) x r1 x r2 - A x ( 1- B ) x r2 + B x( 1- A ) x r1 r CS2 = ---------------------------------------------------------------------------------------------------------------------- (21) A x ( 1 - B ) x r1 - B x ( 1 - A ) x r2 - ( A - B ) (1 - A) r CS1 = ---------------------------------------------------------A 1 ------------------ - --------------------- 1 - r CS2 r 1 - r CS2 1 r TH = ----------------------------------------------1 1 ------------------- - ---------- 1 - r CS2 r CS1 (22) ringing. A snubber circuit is always recommended to partly kill the phase node switching noise. Whenever using a power dissipating component, for example, a power MOSFET that is soldered to the PCB, the proper use of vias, both directly on the mounting pad and immediately surrounding the mounting pad is recommended. Make a mirror image of the power pad being used on the component side to heatsink the MOSFETs on the opposite side of the PCB. Use large copper pour for high current traces to lower the electrical impedance and help dissipate heat. Do not make the switching node copper pour unnecessarily large, since it could radiate noise. An undisturbed solid power ground plane should be used as one of the inner layers. (23) 5. Calculate RTH = rTH RCS, then select the closest value of thermistor available. Also, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: Signal Circuitry Recommendations The output voltage is sensed from the FB and the FBRTN pins. To avoid differential mode noise pickup in these differential sensed traces, the loop area between the FB and FBRTN traces should be minimized. In other words, the FB and FBRTN traces should be routed adjacent to each other with minimum spacing on top of the analog / power ground plane back to the controller. The signal traces connecting to the switch nodes should be tied as close as possible to the inductor pins. The CSREF sense trace should be connected to the second nearest inductor pin to the controller. Detailed step-by-step PCB layout instructions are available from Fairchild upon request. R TH ( ACTUAL ) ) k = ---------------------------------------------R TH ( CALCULATED ) 6. Calculate values for RCS1 and RCS2 using (24) R CS1 = R CS x k x r CS1 R CS2 = R CS x ( ( 1 - k ) + ( k x r CS2 ) ) (25) (26) PCB Layout Guidelines General Recommendations To achieve the best possible performance, a PCB with at least four layers is recommended. When doing the layout, please keep in mind that each square unit of 1 ounce copper has resistance of ~0.53m at room temperature. Whenever high currents must be routed to a different PCB layers, vias should be used properly to create several parallel current paths so that the resistance and inductance introduced by these current paths are minimized, and the via current-rating is not exceeded. If critical signal traces must be routed close to power circuitry, a signal ground plane must be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground island should be used around and under the FAN5182 as a reference for the components associated with the controller. This analog ground should be connected to the power ground at a single point. The components around the FAN5182 should be close to the controller with short traces. The output capacitors should be placed as close as possible to the load. If the load is distributed, the capacitors should also be distributed in proportion to the respective load. Power Circuitry Recommendations The PCB layout starts with high frequency power component placement. Try to minimize stray inductance of the MOSFET half bridge which is composed of the input capacitors, and top and bottom MOSFETs. A good practice is to use short and wide traces or copper pours to minimize the inductance in the MOSFET half bridge. Failure to do so can lead to severe phase node 16 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller Mechanical Diagram 20 Pin - QSOP Symbol A A1 A2 B C D E e H h L N Inches Min. 0.053 0.004 0.008 0.007 Max. 0.069 0.010 0.061 0.012 0.010 Millimeters Min. 1.35 0.10 0.20 0.18 Max. 1.75 0.25 1.54 0.30 0.25 9 4. 3 4 Notes: Notes 1. 2. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. Dimensioning and tolerancing per ANSI Y14.5M-1982. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions shall not exceed 0.25mm (0.010 inch) per side. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. The chamber on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. "L" is the length of terminal for soldering to a substrate. "N" is the maximum number of terminals. Terminal numbers are shown for reference only. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 0.386 0.394 0.150 0.157 0.025 BSC 0.228 0.0099 0.016 20 0 8 0.244 0.0196 0.050 9.81 10.00 3.81 3.98 0.635 BSC 5.80 0.26 0.41 20 0 8 6.19 0.49 1.27 5. 5 6 7 6. 7. 8. 9. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. D E H A A2 B e A1 SEATING PLANE C LEAD COPLANARITY ccc C C L Ordering Information Part Number FAN5182QSCX_NL Temperature Range 0C to +85C Package Type QSOP-20L Packing Method Tape and Reel Quantity per Reel 2500 Note: FAN5182QSCX_NL is a Pb-free part. 17 FAN5182 Rev. 1.0.1 www.fairchildsemi.com FAN5182 Adjustable Output 1, 2, or 3-Phase Synchronous Buck Controller TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM EnSignaTM i-LoTM FACTTM ImpliedDisconnectTM FACT Quiet SeriesTM IntelliMAXTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM Across the board. Around the world.TM OPTOLOGIC OPTOPLANARTM The Power Franchise PACMANTM Programmable Active DroopTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET UniFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I15 18 FAN5182 Rev. 1.0.1 www.fairchildsemi.com |
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