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CDB5504 CS5504 CS5504 Evaluation Board20-Bit A/D Converter Low-power, for CS5504 A/D Converter Low Power, 20-bit A/D Converter
Features Description
The CS5504 is a 2-channel, fully differential 20-bit, serial-output CMOS A/D converter. The CS5504 uses charge-balanced (delta-sigma) techniques to provide a low cost, high-resolution measurement at output word rates up to 200 samples per second. The on-chip digital filter offers superior line rejection at 50 Hz and 60 Hz when the device is operated from a 32.768 kHz clock (output word rate = 20 Sps). The CS5504 has on-chip self-calibration circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. Low power, high-resolution and small package size make the CS5504 an ideal solution for loop-powered transmitters, panel meters, weigh scales and batterypowered instruments. ORDERING INFORMATION See page 23. CS5504-BS -40 to +85 C 20-pin SOIC
I
l Delta-sigma A/D Converter l 2 Differential Inputs
- 20-bit, No Missing Codes - Linearity Error: 0.0007%FS - Pin-selectable Unipolar/Bipolar Ranges - Common Mode Rejection 105 dB @ dc 120 dB @ 50, 60 Hz
l Either 5V or 3.3V Digital Interface l On-chip Self-calibration Circuitry l Output Update Rates up to 200/Sps l Low Power Consumption: 4.4 mW
VREF+ 12
VREF13
VA+ 14
VA15
DGND 16
VD+ 17 2
AIN1+ AIN1AIN2+ AIN2-
8 10 9 11 MUX 4th-Order Delta-Sigma Modulator Serial Interface Logic 18 19
CS SCLK SDATA
Digital Filter
20 DRDY
A0
1
4 Calibration C Calibration SRAM 3 CONV OSC 5 XIN 6 XOUT 7
CAL BP/UP
Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Copyright (c) Cirrus Logic, Inc. 2005Logic, Inc. 1997 (All Rights Reserved) (All Rights Reserved)
AUG `05 MAR `95 AUG `05 DS126F2 DS126F1 1 DS126DB2
CS5504
CS5504
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V 10%; VA- = -5V 10%; VD+ = 3.3V 5%; VREF+ = 2.5V, VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1k with a 10nF to GND at AIN.) (Notes 1, 2)
Parameter* Specified Temperature Range Min Typ -40 to +85 (No Missing Codes) (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 4) 20 Unipolar Bipolar dc 50, 60- Hz (Note 5) 120 (Note 1) ITotal IAnalog IDigital (Note 6) 0.0007 4 8 8 8 4 4 2.6 0 to +2.5 2.5 105 120 15 5 465 425 40 4.4 0.0015 32 32 16 600 6.0 Max Units C %FS Bits LSB LSB LSB LSB LSB LSB LSBrms V V dB dB dB pF nA A A A mW
Accuracy
Linearity Error Differential Nonlinearity Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred to Output)
Analog Input
Analog Input Range: Common Mode Rejection: Off Channel Isolation Input Capacitance DC Bias Current
(Note 2)
Power Supplies
DC Power Supply Currents:
Power Dissipation
Power Supply Rejection 80 dB Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5504's source impedance requirements. Refer to the text section Analog Input Impedance Considerations. 2. Specifications guaranteed by design, characterization and/or test. 3. Applies after calibration at the temperature of interest. 4. Total drift over the specified temperature range since calibration at power-up at 25 C 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and VA- supply voltages. 6. All outputs unloaded. All inputs CMOS levels. * Refer to the Specification Definitions immediately following the Pin Description Section. Specifications are subject to change without notice.
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DS126F1 DS126F2
CS5504
CS5504
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Update Rate (CONV = 1) Filter Corner Frequency Settling Time to 1/2 LSB (FS Step) Symbol fs fout f-3dB ts Ratio fclk/2 fclk/1622 fclk/1928 1/fout Units Hz Sps Hz s
5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V 10%; VA- = -5V 10%;
DGND = 0.) (Notes 2, 7) Parameter High-Level Input Voltage: Low-Level Input Voltage: High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Iout = 1.6 mA XIN All Pins Except XIN XIN All Pins Except XIN (Note 8) Symbol VIH VIH VIL VIL VOH VOL Iin IOZ Min 3.5 2.0 (VD+)-1.0 Typ 1 Max 1.5 0.8 0.4 10 10 Units V V V V V V A A
9 pF Digital Output Pin Capacitance Cout Notes: 7. All measurements are performed under static conditions. 8. Iout = -100 A. This guarantees the ability to drive one TTL load. (V OH = 2.4V @ Iout = -40 A).
3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX;
VA- = -5V 10%; GND = 0V.) (Notes 2, 7) Parameter High-Level Input Voltage: Low-Level Input Voltage: High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance XIN All Pins Except XIN XIN All Pins Except XIN Iout = -400 A Iout = 400 A Symbol VIH VIH VIL VIL VOH VOL Iin IOZ Cout
VA+ = 5V 10%; VD+ = 3.3V 5%; Min 0.7VD+ 0.6VD+ (VD+)-0.3 Typ 1 9 Max 0.3VD+ 0.16VD+ 0.3 10 10 Units V V V V V V A A pF
DS126F1 DS126F2
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CS5504
CS5504
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times: Fall Times: Any Digital Input Any Digital Output Any Digital Input Any Digital Output (Note 9) (Note 9) trise tfall Internal Oscillator External Clock Symbol XIN fclk
VA+, VD+ = 5V 10%; VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Min 30.0 30 40 100 50 100 100 82/fclk 0 Typ 32.768 50 20 10 500 1800/fclk 3246/fclk Max 53.0 330 60 1.0 1.0 2/fclk+200 2/fclk+200 Units kHz kHz % s ns s ns ms ms s ns ns s ns ns ns ns s ns
Start-Up
Power-On Reset Period Oscillator Start-up Time Wake-up Period (Note 10) XTAL = 32.768 kHz (Note 11) (Note 12) (Note 13) tres tosu twup tccw tscl t cal tsac thca tcpw tscn tbus tbuh BP/UP stable prior to DRDY falling BP/UP stable after DRDY falls
Calibration
CONV Pulse Width (CAL=1) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration
Conversion
Set Up Time Hold Time CONV Pulse Width CONV High to Start of Conversion Set Up Time Hold Time A0 to CONV High A0 after CONV High
Start of Conversion to End of Conversion (Note 14) tcon 1624/fclk s Notes: 9. Specified using 10% and 90% points on waveform of interest. 10. An internal power-on-reset is activated whenever power is applied to the device. 11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using an external clock source. 12. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on reset time elapses. 13. Calibration can also be initiated by pulsing CAL high while CONV=1. 14. Conversion time will be 1622/fclk if CONV remains high continuously.
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DS126F1 DS126F2
CS5504
CS5504
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times: Fall Times: Any Digital Input Any Digital Output Any Digital Input Any Digital Output (Note 9) (Note 9) trise tfall Internal Oscillator External Clock Symbol XIN fclk
VA+ = 5V 10%; 5%; VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Min 30.0 30 40 100 50 100 100 82/fclk 0 Typ 32.768 50 20 10 500 1800/fclk 3246/fclk 1624/fclk
VD+ = 3.3V Max 53.0 330 60 1.0 1.0 Units kHz kHz % s ns s ns ms ms s ns ns s ns ns ns ns s ns s
Start-Up
Power-On Reset Period Oscillator Start-up Time Wake-up Period (Note 10) XTAL = 32.768 kHz (Note 11) (Note 12) (Note 13) tres tosu twup tccw tscl t cal tsac thca tcpw tscn tbus tbuh tcon BP/UP stable prior to DRDY falling BP/UP stable after DRDY falls (Note 14)
Calibration
CONV Pulse Width (CAL=1) CONV and CAL High to Start of Calibration Start of Calibration to End of Calibration 2/fclk+200 2/fclk+200 -
Conversion
Set Up Time Hold Time CONV Pulse Widh CONV High to Start of Conversion Set Up Time Hold Time A0 to CONV High A0 after CONV High
Start of Conversion to End of Conversion
DS126F1 DS126F2
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CS5504
CS5504
XIN XIN/2 CAL t ccw CONV t scl STATE Standby t cal Calibration Standby
Figure 1. Calibration Timing (Not to Scale)
XIN XIN/2
A0
t sac CONV DRDY BP/UP t bus t scn STATE Standby t con Conversion t buh Standby t cpw t hca
Figure 2. Conversion Timing (Not to Scale)
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DS126F1 DS126F2
CS5504
CS5504
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
Parameter Serial Clock Serial Clock Access Time: Maximum Delay Time: Output Float Delay: Pulse Width High Pulse Width Low CS Low to data valid (Note 15) (Note 16) SCLK falling to new SDATA bit Symbol fsclk tph tpl tcsd tdd
VA+, VD+ = 5V 10%; VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Min 0 200 200 Typ 60 150 Max 2.5 200 310 Units MHz ns ns ns ns
CS high to output Hi-Z (Note 17) tfd1 60 150 ns tfd2 SCLK falling to Hi-Z 160 300 ns Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high sooner than 2/fclk + 200 ns after CS goes low. 16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized. 17. If CS is returned high before all data bits are output, the SDATA output will complete the current data bit and then go to high impedance.
5%; VA- = -5V 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Serial Clock Serial Clock Access Time: Maximum Delay Time: Output Float Delay: Pulse Width High Pulse Width Low CS Low to data valid (Note 15) (Note 16) SCLK falling to new SDATA bit CS high to output Hi-Z (Note 17) SCLK falling to Hi-Z Symbol fsclk tph tpl tcsd tdd tfd1 tfd2 Min 0 200 200 -
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V 10%; VD+ = 3.3V
Typ 100 400 70 320 Max 1.25 200 600 150 500 Units MHz ns ns ns ns ns ns
DS126F1 DS126F2
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CS5504
CS5504
DRDY
CS t csd SDATA(o) Hi-Z SCLK(i) MSB t dd MSB-1 MSB-2 t fd1
DRDY CS t csd SDATA(o) Hi-Z MSB t dd SCLK(i) t pl
Figure 3. Timing Relationships; Serial Data Read (Not to Scale)
MSB-1
LSB+2 t ph
LSB+1
LSB t fd2
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DS126F1 DS126F2
CS5504
CS5504
RECOMMENDED OPERATING CONDITIONS (DGND = 0V)
Parameter DC Power Supplies: Positive Digital (VA+) - (VA-) Positive Analog Negative Analog Symbol VD+ Vdiff VA+ VAMin 3.15 4.5 4.5 0 1.0 Typ 5.0 10 5.0 -5.0 2.5
(Note 18) Max 5.5 11 11 -5.5 3.6 Units V V V V V
Analog Reference Voltage (VREF+)(Note 19) (VREF-)
Analog Input Voltage: (Note 20) Unipolar VAIN 0 (VREF+)-(VREF-) V VAIN -((VREF+)-(VREF-)) (VREF+)-(VREF-) V Bipolar Notes: 18. All voltages with respect to ground. 19. The CS5504 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-. 20. The CS5504 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode the CS5504 will output all 1's if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0's if the input becomes more negative than 0 Volts. In bipolar mode the CS5504 will output all 1's if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0's if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).
ABSOLUTE MAXIMUM RATINGS*
Parameter DC Power Supplies: Digital Ground Positive Digital Positive Analog Negative Analog Symbol (Note 21) DGND (Note 22) VD+ VA+ VAIin Iout (Note 25) AIN and VREF pins VINA VIND TA Min -0.3 -0.3 -0.3 +0.3 (VA-)-0.3 -0.3 -40 Typ Max (VD+)-0.3 6.0 or VA+ 12 -6.0 10 25 500 (VA+)+0.3 (VD+)+0.3 85 Units V V V V mA mA mW V V C
Input Current, Any Pin Except Supplies Output Current Power Dissipation (Total) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature
(Notes 23, 24)
Storage Temperature Tstg -65 150 C Notes: 21. No pin should go more positive than (VA+)+0.3V. 22. VD+ must always be less than (VA+) +0.3V, and can never exceed +6.0 V. 23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin. 24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 25. Total power dissipation, including all input currents and output currents. * WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
DS126F1 DS126F2
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CS5504
CS5504
GENERAL DESCRIPTION The CS5504 is a low power, 20-bit, monolithic CMOS A/D converter designed specifically for measurement of dc signals. The CS5504 includes a delta-sigma charge-balance converter, a voltage reference, a calibration micro controller with SRAM, a digital filter and a serial interface. The CS5504 is optimized to operate from a 32.768 kHz crystal but can be driven by an external clock whose frequency is between 30 kHz and 330 kHz. When the digital filter is operated with a 32.768 kHz clock, the filter has zeros precisely at 50 and 60 Hz line frequencies and multiples thereof. The CS5504 uses a "start convert" command to latch the input channel selection and to start a convolution cycle on the digital filter. Once the filter cycle is completed, the output port is updated. When operated with a 32.768 kHz clock the ADC converts and updates its output port at 20 samples/sec. The output port operates in a synchronous externally-clocked interface format.
tion of this command will not occur until the complete wake-up period elapses. If no command is given, the device enters the standby state. Calibration After the initial application of power, the CS5504 must enter the calibration state prior to performing accurate conversions. During calibration, the chip executes a two-step process. The device first performs an offset calibration and then follows this with a gain calibration. The two calibration steps determine the zero reference point and the full scale reference point of the converter's transfer function. From these points it calibrates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions. The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at poweron are recognized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. If CAL and CONV become active (high) during the 1800 clock cycle wake-up time, the converter will wait until the wake-up period elapses before executing the calibration. If the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately if CAL and CONV become active. The calibration lasts for 3246 clock cycles. Calibration coefficients are then retained in the SRAM (static RAM) for use during conversion. The states of A0 and BP/UP are ignored during calibration but should remain stable throughout the calibration period to minimize noise. When conversions are performed in unipolar mode or in bipolar mode, the converter uses the same calibration factors to compute the digital
DS126F1 DS126F2
THEORY OF OPERATION Basic Converter Operation The CS5504 A/D converter has three operating states. These are stand-by, calibration, and conversion. When power is first applied, an internal power-on reset delay of about 10 ms resets all of the logic in the device. The oscillator must then begin oscillating before the device can be considered functional. After the power-on reset is applied, the device enters the wake-up period for 1800 clock cycles after clock is present. This allows the delta-sigma modulator and other circuitry (which are operating with very low currents) to reach a stable bias condition prior to entering into either the calibration or conversion states. During the 1800 cycle wake-up period, the device can accept an input command. Execu10
CS5504
CS5504
output code. The only difference is that in bipolar mode the on-chip microcontroller offsets the computed output word by a code value of 8000H. This means that the bipolar measurement range is not calibrated from full scale positive to full scale negative. Instead it is calibrated from the bipolar zero scale point to full scale positive. The slope factor is then extended below bipolar zero to accommodate the negative input signals. The converter can be used to convert both unipolar and bipolar signals by changing the BP/UP pin. Recalibration is not required when switching between unipolar and bipolar modes. At the end of the calibration cycle, the on-chip micro controller checks the logic state of the CONV signal. If the CONV input is low the device will enter the standby mode where it waits for further instruction. If the CONV signal is high at the end of the calibration cycle, the converter will enter the conversion state and perform a conversion on the input channel. The CAL signal can be returned low any time after calibration is initiated. CONV can also be returned low, but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state. If CONV is taken low and then high again with CAL high while the converter is calibrating, the device will interrupt the current calibration cycle and start a new one. If CAL is taken low and CONV is taken low and then high during calibration, the calibration cycle will continue as the conversion command is disregarded. The state of BP/UP is not important during calibrations. If an "end of calibration" signal is desired, pulse the CAL signal high while leaving the CONV signal high continuously. Once the calibration is completed, a conversion will be performed. At the end of the conversion, DRDY will fall to indicate the first valid conversion after the calibration has been completed.
DS126F1 DS126F2
Conversion The conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode. If CONV is taken high to initiate a calibration cycle ( CAL also high), and remains high until the calibration cycle is completed (CAL is taken low after CONV transitions high), the converter will begin a conversion upon completion of the calibration period. The device will perform a conversion on the input channel selected by A0 when CONV transitions high. Table 1 indicates the multiplexer channel selection truth table.
A0 Channel Addressed 0 AIN1 1 AIN2 Table 1. Multiplexer Truth Table
The A0 input is latched internal to the CS5504 when CONV rises. A0 has internal pull-down circuits which default the multiplexer to channel AIN1. The BP/UP pin is not a latched input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 80000H (see Understanding Converter Calibration). BP/UP can be changed after a conversion is started as long as it is stable for 82 clock cycles of the conversion period prior to DRDY falling. If one wishes to intermix measurement of bipolar and unipolar signals on various input channels, it is best to switch the BP/UP pin immediately after DRDY falls and leave BP/UP stable until DRDY falls again. The digital filter in the CS5504 has a Finite Impulse Response and is designed to settle to full accuracy in one conversion time. If CONV is left high, the CS5504 will perform continuous conversions. The conversion time will be 1622 clock cycles. If conversion is initi11
CS5504
CS5504
ated from the standby state, there may be up to two XIN clock cycles of uncertainty as to when conversion actually begins. This is because the internal logic operates at one half the external clock rate and the exact phase of the internal clock may be 180 out of phase relative to the XIN clock. When a new conversion is initiated from the standby state, it will take up to two XIN clock cycles to begin. Actual conversion will use 1624 clock cycles before DRDY goes low to indicate that the serial port has been updated. See the Serial Interface Logic section of the data sheet for information on reading data from the serial port. In the event the A/D conversion command (CONV going positive) is issued during the conversion state, the current conversion will be terminated and a new conversion will be initiated. Voltage Reference The CS5504 uses a differential voltage reference input. The positive input is VREF+ and the negative input is VREF-. The voltage between VREF+ and VREF- can range from 1 volt minimum to 3.6 volts maximum. The gain slope will track changes in the reference without recalibration, accommodating ratiometric applications. Analog Input Range The analog input range is set by the magnitude of the voltage between the VREF+ and VREFpins. In unipolar mode the input range will equal the magnitude of the voltage reference. In bipolar mode the input voltage range will equate to plus and minus the magnitude of the voltage reference. While the voltage reference can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs VREF+ and VREF- stay within the supply voltages for the A/D. The differential input voltage can also have any common mode value as long
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as the maximum signal magnitude stays within the supply voltages. The A/D converter is intended to measure dc or low frequency inputs. It is designed to yield accurate conversions even with noise exceeding the input voltage range as long as the spectral components of this noise will be filtered out by the digital filter. For example, with a 3.0 volt reference in unipolar mode, the converter will accurately convert an input dc signal up to 3.0 volts with up to 15% overrange for 60 Hz noise. A 3.0 volt dc signal could have a 60 Hz component which is 0.5 volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc plus 0.5 volts peak noise) and still accurately convert the input signal (XIN = 32.768 kHz). This assumes that the signal plus noise amplitude stays within the supply voltages. The CS5504 converters output data in binary format when converting unipolar signals and in offset binary format when converting bipolar signals. Table 2 outlines the output coding for both unipolar and bipolar measurement modes.
Unipolar Input Voltage >(VREF - 1.5 LSB) VREF - 1.5 LSB Output Codes FFFFF FFFFF VREF - 1.5 LSB FFFFE 80000 VREF/2 - 0.5 LSB 7FFFF 00001 + 0.5 LSB 00000 <(+ 0.5 LSB) 00000 <(VREF + 0.5 LSB) Note: Table excludes common mode voltage on the signal and reference inputs. Table 2. Output Coding -VREF + 0.5 LSB -0.5 LSB Bipolar Input Voltage >(VREF - 1.5 LSB)
DS126F1 DS126F2
CS5504
CS5504
Converter Performance The CS5504 A/D converter has excellent linearity performance. Calibration minimizes the errors in offset and gain. The CS5504 device has no missing code performance to 20-bits. The converter achieves Common Mode Rejection (CMR) at dc of 105 dB typical, and CMR at 50 and 60 Hz of 120 dB typical. The CS5504 can experience some drift as temperatu re chan ges . Th e CS5 504 uses chopper-stabilized techniques to minimize drift. Measurement errors due to offset or gain drift can be eliminated at any time by recalibrating the converter. Analog Input Impedance Considerations The analog input of the CS5504 can be modeled as illustrated in Figure 4 (the model ignores the multiplexer switch resistance). Capacitors (15 pF each) are used to dynamically sample each of the inputs (AIN+ and AIN-). Every half XIN cycle the switch alternately connects the capacitor to the output of the buffer and then directly to the AIN pin. Whenever the sample capacitor is switched from the output of the buffer to the AIN pin, a small packet of charge (a dynamic demand of current) is required from the input source to settle the voltage of the sample capaci-
tor to its final value. The voltage on the output of the buffer may differ up to 100 mV from the actual input voltage due to the offset voltage of the buffer. Timing allows one half of a XIN clock cycle for the voltage on the sample capacitor to settle to its final value. An equation for the maximum acceptable source resistance is derived.
Rsmax = -1 Ve 2XIN (15pF + CEXT ) ln 15pF(100mv) V + e (15pF + CEXT )
This equation assumes that the offset voltage of the buffer is 100 mV, which is the worst case. The value of Ve is the maximum error voltage which is acceptable. CEXT is the combination of any external or stray capacitance. For a maximum error voltage (Ve) of 600 nV in the CS5504 (1/4LSB at 20-bits), the above equation indicates that when operating from a 32.768 kHz XIN, source resistances up to 84 k in the CS5504 are acceptable in the absence of external capacitance (CEXT = 0). The VREF+ and VREF- inputs have nearly the same structure as the AIN+ and AIN- inputs. Therefore, the discussion on analog input impedance applies to the voltage reference inputs as well. Digital Filter Characteristics The digital filter in the CS5504 is the combination of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interference frequencies (50 and 60 Hz and their multiples) when the CS5504 is clocked at
AIN+ V os 100 mV AINV os 100 mV + -
+ -
15 pF Internal Bias Voltage 15 pF
Figure 4. Analog Input Model DS126F1 DS126F2 13
CS5504
CS5504
0 -20 -40 -60 -80 -100 -120 -140 XIN = 32.768 kHz -160 X1 0 X2 0 40 80 120 160 200 240 402.83 805.66 1208.5 1611.3 2014.2 2416.9 Frequency (Hz) X1 = 32.768kHz X2 = 330.00kHz
Frequency (Hz) 50 60 100 120 150 180 200 240
Notch Depth (dB) 125.6 126.7 145.7 136.0 118.4 132.9 102.5 108.4
Frequency (Hz) 501% 601% 1001% 1201% 1501% 1801% 2001% 2401%
Minimum Attenuation (dB) 55.5 58.4 62.2 68.4 74.9 87.9 94.0 104.4
Attenuation (dB)
Figure 5. Filter Magnitude Plot to 260 Hz
0
-20
Flatness Frequency dB -0.010 1
3 -0.093
Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)
180 135 90 Phase (Degrees) 45 0 -45 -90 XIN = 32.768 kHz -135 -180
Attenuation (dB)
-40 -60
-80
2
4
-0.041
-0.166 -0.259 -0.374 -0.510 -0.667 -0.846 -1.047 -3.093
5 6 7 8 9 10 17
-100 -120
-140 0 5
XIN = 32.768 kHz
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Frequency (Hz)
Frequency (Hz)
Figure 6. Filter Magnitude Plot to 50 Hz
Figure 7. Filter Phase Plot to 50 Hz
32.768 kHz. Figures 5, 6 and 7 illustrate the magnitude and phase characteristics of the filter. Figure 5 illustrates the filter attenuation from dc to 260 Hz. At exactly 50, 60, 100, and 120 Hz the filter provides over 120 dB of rejection. Table 3 indicates the filter attenuation for each of the potential line interference frequencies when the converter is operating with a 32.768 kHz clock. The converter yields excellent attenuation
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of these interference frequencies even if the fundamental line frequency should vary 1% from its specified frequency. The -3dB corner frequency of the filter when operating from a 32.768 kHz clock is 17 Hz. Figure 7 illustrates that the phase characteristics of the filter are precisely linear phase.
DS126F1 DS126F2
CS5504
CS5504
If the CS5504 is operated at a clock rate other than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. Therefore, optimum rejection of line frequency interference will occur with the CS5504 running at 32.768 kHz. Anti-Alias Considerations for Spectral Measurement Applications Input frequencies greater than one half the output word rate (CONV = 1) may be aliased by the converter. To prevent this, input signals should be limited in frequency to no greater than one half the output word rate of the converter (when CONV =1). Frequencies close to the modulator sample rate (XIN/2) and multiples thereof may also be aliased. If the signal source includes spectral components above one half the output word rate (when CONV = 1) these components should be removed by means of low-pass filtering prior to the A/D input to prevent aliasing. Spectral components greater than one half the output word rate on the VREF inputs (VREF+ and VREF-) may also be aliased. Filtering of the reference voltage to remove these spectral components from the reference voltage is desirable. Crystal Oscillator The CS5504 is designed to be operated using a 32.768 kHz "tuning fork" type crystal. One end of the crystal should be connected to the XIN input. The other end should be attached to XOUT. Short lead lengths should be used to minimize stray capacitance. Over the industrial temperature range (-40 to +85 C) the on-chip gate oscillator will oscillate with other crystals in the range of 30 kHz to 53 kHz. The chip will operate with external clock frequencies from 30 kHz to 330 kHz over the industrial temperature range. The 32.768 kHz crystal is normally specified as a time-keeping
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crystal with tight specifications for both initial frequency and for drift over temperature. To maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 C to +60 C) by the manufacturers. Applications of these crystals with the CS5504 does not require tight initial tolerance or low tempco drift. Therefore, a lower cost crystal with looser initial tolerance and tempco will generally be adequate for use with the CS5504. Also check with the manufacturer about wide temperature range application of their standard crystals. Generally, even those crystals specified for limited temperature range will operate over much larger ranges if frequency stability over temperature is not a requirement. The frequency stability can be as bad as 3000 ppm over the operating temperature range and still be typically better than the line frequency (50 Hz or 60 Hz) stability over cycle-to-cycle during the course of a day. Serial Interface Logic The digital filter in the CS5504 takes 1624 clock cycles to compute an output word once a conversion begins. At the end of the conversion cycle, the filter will attempt to update the serial port. Two clock cycles prior to the update DRDY will go high. When DRDY goes high just prior to a port update it checks to see if the port is either empty or unselected (CS = 1). If the port is empty or unselected, the digital filter will update the port with a new output word. When new data is put into the port DRDY will go low. Reading Serial Data SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY goes low), the SDATA pin comes out of Hi-Z with the MSB data bit present. SCLK is the input pin for the serial clock. If the MSB data bit is on the SDATA pin, the
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first rising edge of SCLK enables the shifting mechanism. This allows the falling edges of SCLK to shift subsequent data bits out of the port. Note that if the MSB data bit is output and the SCLK signal is high, the first falling edge of SCLK will be ignored because the shifting mechanism has not become activated. After the first rising edge of SCLK, each subsequent falling edge will shift out the serial data. Once the LSB is present, the falling edge of SCLK will cause the SDATA output to go to Hi-Z and DRDY to return high. The serial port register will be updated with a new data word upon the completion of another conversion if the serial port has been emptied, or if the CS is inactive (high). CS can be operated asynchronously to the DRDY signal. The DRDY signal need not be monitored as long as the CS signal is taken low for at least two XIN clock cycles plus 200 ns prior to SCLK being toggled. This ensures that CS has gained control over the serial port. Power Supplies and Grounding The analog and digital supply pins to the CS5504 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. Note that there is no analog ground pin. No analog ground pin is required because the inputs for measurement and for the voltage reference are differential and require no ground. In the digital section of the chip the supply current flows into the VD+ pin and out of the DGND pin. As a CMOS device, the CS5504 requires that the supply voltage on the VA+ pin always be more positive than the voltage on any other pin of the device. If this requirement is not met, the device can latch-up or be damaged. In all circumstances the VA+ voltage must remain more positive than the VD+ or DGND pins; VD+ must remain more positive than the DGND pin.
The following power supply options are possible:
VA+ = +5V to +10V, VA- = 0V, VA+ = +5V, VA- = -5V, VA+ = +5V, VA- = 0V to -5V, VD+ = +5V VD+ = +5V VD+ = +3.3V
The CS5504 cannot be operated with a 3.3V digital supply if VA+ is greater than +5.5V. Figure 8 illustrates the System Connection Diagram for the CS5504 using a single +5V supply. Note that all supply pins are bypassed with 0.1 F capacitors and that the VD+ digital supply is derived from the VA+ supply. Figure 9 illustrates the CS5504 using dual supplies of +5 and -5V. Figure 10 illustrates the CS5504 using dual supplies of +10V analog and +5V digital. When using separate supplies for VA+ and VD+, VA+ must be established first. VD+ should never become more positive than VA+ under any operating condition. Remember to investigate transient power-up conditions, when one power supply may have a faster rise time.
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CS5504
10 +5V Analog Supply 0.1 F 14 VA+ Calibration Control Bipolar/ Unipolar Input Select 4 CAL
XIN 5
0.1 F 17 VD+
Optional Clock Source 32.768 kHz
7
BP/UP
XOUT
6
CS5504
8 AIN1+ AIN1AIN2+ AIN2SDATA SCLK 18 Serial Data Interface 10 9
11
Analog* Signal Sources
19
DRDY CS
20 2 1 3 16 Unused Logic inputs must be connected to VD+ or DGND Control Logic
*Unused analog inputs should be tied to signal ground + Voltage Reference 12 13 VREF+
VREF-
A0
CONV
VA15
DGND
Figure 8. CS5504 System Connection Diagram Using Single Supply
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CS5504
10 +5V Analog Supply 0.1 F 14 VA+ Calibration Control Bipolar/ Unipolar Input Select 4 CAL
XIN 5
0.1 F 17 VD+
Optional Clock Source 32.768 kHz
7
BP/UP
XOUT
6
CS5504
8 AIN1+ AIN1AIN2+ AIN2SDATA SCLK 18 Serial Data Interface
Analog* Signal Sources
10 9
11
19
DRDY CS
20 2 1 3 16 Unused Logic inputs must be connected to VD+ or DGND Control Logic
*Unused analog inputs should be tied to signal ground + Voltage Reference 12 13 VREF+
VREF-
A0
CONV
-5V Analog Supply
0.1 F
VA15
DGND
Figure 9. CS5504 System Connection Diagram Using Dual Supplies
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CS5504
Note: VD+ should never be more positive than VA+ +10V Analog Supply 0.1 F 14
VA+
0.1 F 17
VD+
+5V Digital Supply
Calibration Control Bipolar/ Unipolar Input Select
4
CAL XIN 5 6
Optional Clock Source 32.768 kHz
7
BP/UP
XOUT
CS5504
8
AIN1+ AIN1AIN2+ AIN2-
SCLK
18
Analog* Signal Sources
10 9 11 *Unused analog inputs should be tied to signal ground
SDATA
19
Serial Data Interface
DRDY
20
CS 12 13
VREF+
2 1 3 16 Unused Logic inputs must be connected to VD+ or DGND Control Logic
+ Voltage Reference -
A0 CONV DGND
VREF-
VA15
Figure 10. CS5504 System Connection Diagram Using Dual Supply, +10V Analog, +5V Digital
Schematic & Layout Review Service
Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering.
Call: (512) 445-7222
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PIN DESCRIPTIONS*
MULTIPLEXER SELECTION INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT A0 CS CONV CAL XIN XOUT BP/UP AIN1+ AIN2+ AIN11 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
DRDY SDATA SCLK VD+ DGND VAVA+ VREFVREF+ AIN2-
DATA READY SERIAL DATA OUTPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND NEGATIVE ANALOG POWER POSITIVE ANALOG POWER VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT
*Pinout applies to both PDIP and SOIC
Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the device into a lower powered state (approximately 70% power reduction). Serial Output I/O CS - Chip Select, Pin 2. This input allows an external device to access the serial port. DRDY - Data Ready, Pin 20. Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. DRDY will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the CS pin is inactive (high). SDATA - Serial Data Output, Pin 19. SDATA is the output pin of the serial output port. Data from this pin will be output at a rate determined by SCLK. Data is output MSB first and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high impedance state when not transmitting data. SCLK - Serial Clock Input, Pin 18. A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin must not be allowed to float.
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Control Input Pins CAL - Calibrate, Pin 4. When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the converter. CONV - Convert, Pin 3. The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If CONV is held high (CAL low) the converter will do continuous conversions. BP/UP - Bipolar/Unipolar, Pin 7. The BP/UP pin selects the conversion mode of the converter. When high the converter will convert bipolar input signals; when low it will convert unipolar input signals. A0 - Multiplexer Selection Input, Pin 1. Selects the input channel for conversion. A0=0=AIN1. A0 is latched when CONV transitions from low to high. This input has a pull-down resistor internal to the chip. Measurement and Reference Inputs AIN1+, AIN2+, AIN1-, AIN2- - Differential Analog Inputs, Pins 8, 9, 10, 11. Analog differential inputs to the delta-sigma modulator. VREF+, VREF- - Differential Voltage Reference Inputs, Pins 12, 13. A differential voltage reference on these pins operates as the voltage reference for the converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts. Power Supply Connections VA+ - Positive Analog Power, Pin 14. Positive analog supply voltage. Nominally +5 volts. VA- - Negative Analog Power, Pin 15. Negative analog supply voltage. Nominally -5volts. VD+ - Positive Digital Power, Pin 17. Positive digital supply voltage. Nominally +5 volts or +3.3 volts. DGND - Digital Ground, Pin 16. Digital Ground.
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SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 32 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (12 LSB above the voltage on the AINpin.) when in unipolar mode (BP/UP low). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (12 LSB below the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs
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CS5504
ORDERING APPENDIX INFORMATION
Model Package Temperature
The following companies provide 32.768 kHz crystals in many package varieties and temperature CS5504-BP 20-pin Plastic DIP ranges.
CS5504-BS CS5504-BSZ (lead Fox Electronics free) 5570 Enterprise Parkway Fort Meyers, FL 33905 (813) 693-0099 ENVIRONMENTAL, MANUFACTURING, &
Model Number Micro Crystal Division / SMH 702 West Algonquin Road CS5504-BP Arlington Heights, IL 60005 CS5504-BS (708) 806-1485 Peak Reflow Temp 260 C
20-pin SOIC
-40 to +85 C
Taiwan X'tal Corp. 5F. No. 16, Sec 2, Chung Yang S. RD. Reitou, Taipei, Taiwan R. O. C. Tel: 02-894-1202 HANDLING INFORMATION Fax: 02-895-6207
MSL Rating* Max Floor Life
Interquip Limited 1 No Limit 24/F Million Fortune Industrial Centre 240 C 2 365 Days 34-36 Chai Wan Kok Street, Tsuen Wan N T 260 C 3 7 Days CS5504-BSZ (lead free) Tel: 4135515 Fax: 4137053 SaRonix * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 4010 Transport Street S& T Enterprises, Ltd. Palo Alto, California 94303 Rm 404 Blk B (415) 856-6900 REVISION HISTORY Sea View Estate Revision Date Changes North Point, Hong Kong Statek F1 First Final Release 512 North MainMAR 1995 Tel: 5784921 F2 California 92668 AUG 2005 Updated device ordering info. Updated legal notice. Added MSL data.. Fax: 8073126 Orange, (714) 639-7810 Mr. Darren Mcleod Hy-Q International Pty. Ltd. IQD Ltd. North Street 12 Rosella Road, Contacting FRANKSON, 3199 Crewkerne Cirrus Logic Support For all product questions Victoria, Australia Somerset TA18 7AK and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com England Tel: 61-3-783 9611 01460 77155 Fax: 61-3-783 9703 IMPORTANT NOTICE Mr. Pierre Hersberger orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale information to verify, before placing supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus Microcrystal/DIV. ETA S.A. this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third for the use of this information, including use of parties. This document is the property of Cirrus and by furnishing any patents, mask Schild-Rust-Strasse 17 or other intellectual propertythis information, Cirrus grants no license, express or implied undercontained herein andwork rights, copyrights, trademarks, trade secrets rights. Cirrus owns the copyrights associated with the information gives consent for copies CH-2540 information only circuits or products of Cirrus. Grenchen totobe made of the such as copying for use within your organization withorrespect to Cirrus integratedfor creatingotherwork for resale. This consent does not extend other copying for general distribution, advertising promotional purposes, or any Switzerland CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY DESIGNED, AUTHORIZED OR WARRANTED FOR 065 OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOTTHE BODY, AUTOMOTIVE SAFETY OR SECURITYUSE 53 05 57 IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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CS5504
- NOTES -
* Notes *
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