View AD837005_1121813.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LF to 750 MHz, Digitally Controlled VGA AD8370
FEATURES
Programmable low and high gain (<2 dB resolution) Low range: -11 dB to +17 dB High range: 6 dB to 34 dB Differential input and output 200 differential input 100 differential output 7 dB noise figure @ maximum gain Two-tone IP3 of 35 dBm @ 70 MHz -3 dB bandwidth of 750 MHz 40 dB precision gain range Serial 8-bit digital interface Wide input dynamic range Power-down feature Single 3 V to 5 V supply
FUNCTIONAL BLOCK DIAGRAM
VCCI
3
VCCO
11
VCCO
6
PWUP ICOM INHI
4 2 1
BIAS CELL
5 7 8
VOCM OCOM OPHI
PRE AMP INLO 16 ICOM 15
TRANSCONDUCTANCE
OUTPUT AMP
9
OPLO
10 OCOM
SHIFT REGISTER AND LATCHES
AD8370
14 13 12
DATA CLCK LTCH
Figure 1.
70 CODE = LAST 7 BITS OF GAIN CODE (NO MSB) 60 HIGH GAIN MODE 50 LOW GAIN MODE HIGH GAIN MODE GAIN 0.409 CODE 30 20 40
APPLICATIONS
Differential ADC drivers IF sampling receivers RF/IF gain stages Cable and video applications SAW filter interfacing Single-ended-to-differential conversion
VOLTAGE GAIN (V/V)
40 30
10 0
GENERAL DESCRIPTION
The AD8370 is a low cost, digitally controlled, variable gain amplifier (VGA) that provides precision gain control, high IP3, and low noise figure. The excellent distortion performance and wide bandwidth make the AD8370 a suitable gain control device for modern receiver designs. For wide input, dynamic range applications, the AD8370 provides two input ranges: high gain mode and low gain mode. A vernier, 7-bit, transconductance (gm) stage provides 28 dB of gain range at better than 2 dB resolution and 22 dB of gain range at better than 1 dB resolution. A second gain range, 17 dB higher than the first, can be selected to provide improved noise performance. The AD8370 is powered on by applying the appropriate logic level to the PWUP pin. When powered down, the AD8370 consumes less than 4 mA and offers excellent input to output isolation. The gain setting is preserved when operating in a power-down mode.
20 10 LOW GAIN MODE 0 0 10 20 30 40 50 60 70 80 GAIN CODE GAIN 0.059 CODE
-10 -20
-30 90 100 110 120 130
Figure 2. Gain vs. Gain Code at 70 MHz
Gain control of the AD8370 is through a serial 8-bit gain control word. The MSB selects between the two gain ranges, and the remaining 7 bits adjust the overall gain in precise linear gain steps. Fabricated on the ADI high speed XFCB process, the high bandwidth of the AD8370 provides high frequency and low distortion. The quiescent current of the AD8370 is 78 mA typically. The AD8370 amplifier comes in a compact, thermally enhanced 16-lead TSSOP package and operates over the temperature range of -40C to +85C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
03692-002
VOLTAGE GAIN (dB)
03692-001
AD8370 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 13 Block Architecture...................................................................... 13 Preamplifier................................................................................. 13 Transconductance Stage ............................................................ 13 Output Amplifier........................................................................ 14 Digital Interface and Timing .................................................... 14 Applications..................................................................................... 15 Basic Connections...................................................................... 15 Gain Codes.................................................................................. 15 Power-Up Feature....................................................................... 15 Choosing Between Gain Ranges .............................................. 16 Layout and Operating Considerations .................................... 16 Package Considerations............................................................. 17 Single-Ended-to-Differential Conversion............................... 17 DC-Coupled Operation............................................................. 18 ADC Interfacing ......................................................................... 19 3 V Operation ............................................................................. 20 Evaluation Board and Software .................................................... 22 Appendix ......................................................................................... 25 Characterization Equipment..................................................... 25 Composite Waveform Assumption.......................................... 25 Definitions of Selected Parameters .......................................... 25 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
7/05--Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Figure 11 and Figure 15............................................... 8 Added Figure 12; Renumbered Sequentially ................................ 8 Added Figure 16; Renumbered Sequentially ................................ 9 Changes to Evaluation Board and Software Section.................. 22 Changes to Figure 60...................................................................... 23 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 1/04--Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8370 SPECIFICATIONS
VS = 5 V, T = 25C, ZS = 200 , ZL = 100 at gain code HG127, 70 MHz, 1 V p-p differential output, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT STAGE Maximum Input Input Resistance Common-Mode Input Range CMRR Input Noise Spectral Density GAIN Maximum Voltage Gain High Gain Mode Low Gain Mode Minimum Voltage Gain High Gain Mode Low Gain Mode Gain Step Size Gain Temperature Sensitivity Step Response OUTPUT INTERFACE Output Voltage Swing Output Resistance Output Differential Offset NOISE/HARMONIC PERFORMANCE 10 MHz Gain Flatness Noise Figure Second Harmonic 1 Third Harmonic1 Output IP3 Output 1 dB Compression Point 70 MHz Gain Flatness Noise Figure Second Harmonic1 Third Harmonic1 Output IP3 Output 1 dB Compression Point Conditions VOUT < 1 V p-p Gain Code HG127, RL = 1 k, AD8370 in compression Gain Code LG127, RL = 1 k, VOUT = 2 V p-p Pins INHI and IHLO Gain Code LG2, 1 dB compression Differential Differential, f = 10 MHz, Gain Code LG127 Min Typ 750 5750 3500 3.2 200 3.2 77 1.9 Max Unit MHz V/ns V/ns V p-p V p-p dB nV/Hz
Gain Code = HG127 Gain Code = LG127
34 52 17 7.4 -8 0.4 -25 0.06 0.408 0.056 -2 20 8.4 95 60
dB V/V dB V/V dB V/V dB V/V (V/V)/Code (V/V)/Code mdB/C ns V p-p mV
Gain Code = HG1 Gain Code = LG1 High Gain Mode Low Gain Mode Gain Code = HG127 For 6 dB gain step, settled to 10% of final value Pins OPHI and OPLO RL 1 k (1 dB compression) Differential VINHI = VINLO, over all gain codes
Within 10 MHz of 10 MHz VOUT = 2 V p-p VOUT = 2 V p-p
0.01 7.2 -77 -77 35 17 0.02 7.2 -65 -62 35 17
dB dB dBc dBc dBm dBm dB dB dBc dBc dBm dBm
Within 10 MHz of 70 MHz VOUT = 2 V p-p VOUT = 2 V p-p
Rev. A | Page 3 of 28
AD8370
Parameter 140 MHz Gain Flatness Noise Figure Second Harmonic1 Third Harmonic1 Output IP3 Output 1 dB Compression Point 190 MHz Gain Flatness Noise Figure Second Harmonic1 Third Harmonic1 Output IP3 Output 1 dB Compression Point 240 MHz Gain Flatness Noise Figure Second Harmonic1 Third Harmonic1 Output IP3 Output 1 dB Compression Point 380 MHz Gain Flatness Noise Figure Output IP3 Output 1 dB Compression Point POWER-INTERFACE Supply Voltage Quiescent Current 3 Conditions Within 10 MHz of 140 MHz VOUT = 2 V p-p VOUT = 2 V p-p Min Typ 0.03 7.2 -54 -50 33 17 0.03 7.2 -43 -43 33 17 0.04 7.4 -28 -33 32 17 0.04 8.1 27 14 3.0 2 72.5 5.5 85.5 Max Unit dB dB dBc dBc dBm dBm dB dB dBc dBc dBm dBm dB dB dBc dBc dBm dBm dB dB dBm dBm V mA
Within 10 MHz of 240 MHz VOUT = 2 V p-p VOUT = 2 V p-p
Within 10 MHz of 240 MHz VOUT = 2 V p-p VOUT = 2 V p-p
Within 10 MHz of 240 MHz
vs. Temperature 4 Total Supply Current Power-Down Current vs. Temperature4 POWER-UP INTERFACE Power-Up Threshold4 Power-Down Threshold4 PWUP Input Bias Current GAIN CONTROL INTERFACE VIH4 VIL4 Input Bias Current
1 2 3
PWUP High, GC = LG127, RL = , 4 seconds after power-on, thermal connection made to exposed paddle under device -40C TA +85C PWUP High, VOUT = 1 V p-p, ZL = 100 reactive, GC = LG127 (includes load current) PWUP low -40C TA +85C Pin PWUP Voltage to enable the device Voltage to disable the device PWUP = 0 V Pins CLCK, DATA, and LTCH Voltage for a logic high Voltage for a logic low
79
105 82 3.7 5 1.8 0.8 400 1.8 0.8 900
mA mA mA mA V V nA V V nA
Refer to Figure 22 for performance into a lighter load. See the 3 V Operation section for more information. Minimum and maximum specified limits for this parameter are guaranteed by production test. 4 Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test.
Rev. A | Page 4 of 28
AD8370 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage, VS PWUP, DATA, CLCK, LTCH Differential Input Voltage, VINHI - VINLO Common-Mode Input Voltage, VINHI or VINLO, with Respect to ICOM or OCOM Internal Power Dissipation JA (Exposed Paddle Soldered Down) JA (Exposed Paddle Not Soldered Down) JC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V VS + 500 mV 2V VS + 500 mV (max), VICOM - 500 mV, VOCOM - 500 mV (min) 575 mW 30C/W 95C/W 9C/W 150C -40C to +85C -65C to +150C 235C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 28
AD8370 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INHI 1 ICOM 2 VCCI 3 PWUP 4
16 INLO 15 ICOM
AD8370
14 DATA
13 CLCK TOP VIEW VOCM 5 (Not to Scale) 12 LTCH
VCCO 6 OCOM 7 OPHI 8
11 VCCO
03692-003
10 OCOM 9
OPLO
Figure 3.16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No. 1 2, 15, PADDLE 3 4 5 Mnemonic INHI ICOM VCCI PWUP VOCM Description Balanced Differential Input. Internally biased. Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the bottom of the device. Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. Power Enable Pin. Device is operational when PWUP is pulled high. Common-Mode Output Voltage Pin. The midsupply ((VVCCO - VOCOM)/2) common-mode voltage is delivered to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a bypass capacitor to ground. This pin is an output only and is not to be driven externally. Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. Output Common. Connect to a low impedance ground. Balanced Differential Output. Biased to midsupply. Balanced Differential Output. Biased to midsupply. Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in shift register is latched on the next high-going edge. Serial Clock Input Pin. Serial Data Input Pin. Balanced Differential Input. Internally biased.
6, 11 7, 10 8 9 12 13 14 16
VCCO OCOM OPHI OPLO LTCH CLCK DATA INLO
Rev. A | Page 6 of 28
AD8370 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, ZS = 200 , ZL = 100 , T = 25C, unless otherwise noted.
70 CODE = LAST 7 BITS OF GAIN CODE (NO MSB) 60 HIGH GAIN MODE 50 LOW GAIN MODE HIGH GAIN MODE GAIN 0.409 CODE 30
30
40
40 35
HIGH GAIN CODES SHOWN WITH DASHED LINES HG127 HG77 HG51 HG102 LG127
VOLTAGE GAIN (V/V)
VOLTAGE GAIN (dB)
VOLTAGE GAIN (dB)
20
25 20 15 10 LG36 5 0 HG3 LG9 LG18 HG25 LG90 HG9 HG18
40 30
10 0
20 10 LOW GAIN MODE 0 0 10 20 30 40 50 60 70 80 GAIN CODE GAIN 0.059 CODE
-10 -20
03692-004
-5 -10 10 100
LOW GAIN CODES SHOWN WITH SOLID LINES
-30 90 100 110 120 130
1000
FREQUENCY (MHz)
Figure 4. Gain vs. Gain Code at 70 MHz
40 HIGH GAIN MODE 35 LOW GAIN MODE 25 20 15
OUTPUT IP3 (dBm) +25C
35
Figure 7. Frequency Response vs. Gain Code
30
40 +25C UNIT CONVERSION NOTE FOR 100 LOAD: dBVrms = dBm-10dB 50
03692-007
OUTPUT IP3 (dBV rms)
30
OUTPUT IP3 (dBm)
30 +85C 25
40
25
35
20
10 5 SHADING INDICATES 3 FROM THE MEAN. DATA BASED ON 30 PARTS FROM TWO BATCH LOTS. 0 20 40 60 80 GAIN CODE 100 120
20 -40C 15 SHADING INDICATES 3 FROM THE MEAN. DATA BASED ON 30 PARTS FROM TWO BATCH LOTS. 0 50 100 150 200 250 300 350
30
15
25
03692-068
5
-5 140
10
20 400
FREQUENCY (MHz)
Figure 5. Output Third-Order Intercept vs. Gain Code at 70 MHz
45 40
Figure 8. Output Third-Order Intercept vs. Frequency at Maximum Gain
25
20 35
NOISE FIGURE (dB) NOISE FIGURE (dB)
LG127 15
30 25 20 15
03692-006
380MHz LOW GAIN MODE 70MHz
10
HG18 HG127
70MHz 5 0 20 40 60 80 100 120 140 GAIN CODE
0 0 100 200 300 400 500 FREQUENCY (MHz)
600
Figure 6. Noise Figure vs. Gain Code at 70 MHz
Figure 9. Noise Figure vs. Frequency at Various Gains
Rev. A | Page 7 of 28
03692-009
10
380MHz
5 HIGH GAIN MODE
03692-069
10
0
OUTPUT IP3 (dBm) -40C, +85C
45
AD8370
20 LOW GAIN MODE 16 HIGH GAIN MODE LOW GAIN MODE HIGH GAIN MODE 8
1.0
GAIN ERROR (dB)
2.0
100 LOAD
1.5
OUTPUT P1dB (dB)
12
1k LOAD
0.5 -40C 0 -0.5 -1.0
03692-012
4 UNIT CONVERSION NOTE: FOR 100 LOAD: dBV rms = dBm-10dB FOR 1k LOAD: dBV rms = dBm
03692-010
+85C
0 -4
-8 0 20 40
SHADING INDICATES 3 FROM THE MEAN. DATA BASED ON 30 PARTS FROM TWO BATCH LOTS. 60 80 100 120 140
-1.5 -2.0 10
ERROR AT -40C AND +85C WITH RESPECT TO +25C. SHADING INDICATES 3 FROM THE MEAN. DATA BASED ON 30 PARTS FROM ONE BATCH LOT. 100 FREQUENCY (MHz) 1000
GAIN CODE
Figure 10. Output P1dB vs. Gain Code at 70 MHz
0 -10 -50 -60
Figure 13. Gain Error over Temperature vs. Frequency, RL = 100
20
HIGH GAIN MODE OUTPUT IMD (dBc)
+25C, 100 LOAD +85C, 100 LOAD
18 16 14
LOW GAIN MODE OUTPUT IMD (dBc)
-20 HIGH GAIN MODE -30 -40 -50 -60 -70 LOW GAIN MODE -80 -90 0 20 40 60 80 GAIN CODE 100 120
-70 -80 -90 -100 -110 -120 -130 -140 140
OUTPUT P1dB (dBm) -40C, +85C
18
16 14 UNIT CONVERSION NOTE: RE 100 LOAD: dBV rms = dBm - 10dB RE 1k LOAD: dBV rms = dBm -40C, 100 LOAD +25C, 1k LOAD
12 10 8
12
10 +85C, 1k LOAD 8 SHADING INDICATES 3 FROM THE MEAN. DATA BASED ON 30 PARTS FROM TWO BATCH LOTS. 6 0 50 100 150 200
03692-011
-40C, 1k LOAD 250 300 350
4 400
FREQUENCY (MHz)
Figure 11. Two-Tone Output IMD3 vs. Gain Code at 70 MHz, RL = 1 k, VOUT = 2 V p-p Composite Differential
35 30 25 25 20 15 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 -82 -84 0
Figure 14. Output P1dB vs. Frequency
OUTPUT IP3 (dBV rms)
OUTPUT IP3 (dBm)
20 15 10 5 0 -5 0 20 40 60 80 GAIN CODE 100 120 LOW GAIN MODE
10 5 0 -5 -10 -15 140
OUTPUT IMD (dBc)
HIGH GAIN MODE
-40C
+25C +85C
03692-005
50
100
150 200 250 FREQUENCY (MHz)
300
350
400
Figure 12. Output Third-Order Intercept vs. Gain Code at 70 MHz, RL = 1 k, VOUT = 2 V p-p Composite Differential
Figure 15. Two-Tone Output IMD3 vs. Frequency at Maximum Gain, RL = 1 k, VOUT = 2 V p-p Composite Differential
Rev. A | Page 8 of 28
03692-014
03692-013
6
OUTPUT P1dB (dBm) +25C
AD8370
34 32 +85C 30 20 18 -40C 26 24 22 20 18 16 14 0 50 100 150 200 250 FREQUENCY (MHz) 300 350 +25C 16 14 12 10 8 6 4 400
03692-008
24 22
120 1GHz
90 60
OUTPUT IP3 (dBm)
28
OUTPUT IP3 (dBV rms)
150
30
S22 180
5MHz
0
210 S11
330
270
Figure 16. Output Third-Order Intercept vs. Frequency at Maximum Gain, RL = 1 k, VOUT = 2 V p-p Composite Differential
2.0 1.5
Figure 19. Input and Output Reflection Coefficients, S11 and S22, ZO = 100 Differential
250 16 DIFFERENT GAIN CODES REPRESENTED R+jX FORMAT 200 50 100
1.0 0.5 -40C 0 -0.5 -1.0
50
03692-015
03692-017
240
300
GAIN ERROR (dB)
150
0
+85C
100
-50
-100
03692-018
-1.5 -2.0
ERROR AT -40C AND +85C WITH RESPECT TO +25C. SHADING INDICATES 3 FROM THE MEAN. DATA BASED ON 30 PARTS FROM ONE BATCH LOT. 10 100 FREQUENCY (MHz) 1000
0 0 100 200 300 400 500 600 FREQUENCY (MHz)
-150 700
Figure 17. Gain Error over Temperature vs. Frequency, RL = 1 k
0 -10
HARMONIC DISTORTION (dBc)
Figure 20. Input Resistance and Reactance vs. Frequency
0 LOW GAIN RL = 1k -10
HARMONIC DISTORTION (dBc)
HIGH GAIN RL = 1k -20 -30 -40 -50 -60 -70 -80 -90 0 20 40 60 80 100 120 140 GAIN CODE
03692-019
-20 -30 -40 LOW GAIN, RL = 100 -50 -60 -70 -80 HIGH GAIN, RL = 1k -90 0 20 40 60 80 100 120 140 GAIN CODE
03692-016
LOW GAIN, RL = 1k HIGH GAIN, RL = 100
HIGH GAIN RL = 100 LOW GAIN RL = 100
Figure 18. Second-Order Harmonic Distortion vs. Gain Code at 70 MHz, VOUT = 2 V p-p Differential
Figure 21. Third-Order Harmonic Distortion vs. Gain Code at 70 MHz, VOUT = 2 V p-p Differential
Rev. A | Page 9 of 28
REACTANCE (j )
RESISTANCE ()
AD8370
0 -10 HD2 RL = 100
HARMONIC DISTORTION (dBc)
120 110 100
HD3 RL = 100
-20 -30 -40 -50 HD3 RL = 1k -60 -70 -80 -90 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz)
03692-020
90
PSRR (dB)
80 70 60 50 40
HD2 RL = 1k
30 20 1 10 100 1000 FREQUENCY (MHz)
Figure 22. Harmonic Distortion vs. Frequency at Maximum Gain, VOUT = 2 V p-p Composite Differential
120 80
Figure 25. Power Supply Rejection Ratio vs. Frequency at Maximum Gain
0 FORWARD TRANSMISSION, HG0
100
60
-20 FORWARD TRANSMISSION, LG0
REACTANCE (j )
RESISTANCE ()
ISOLATION (dB)
80
40
-40
60
20
-60
40 16 DIFFERENT GAIN CODES REPRESENTED R+jX FORMAT
0
-80
03692-021
REVERSE TRANSMISSION, HG127 -120 10 100 FREQUENCY (MHz) 1000
0 0 100 200 300 400 500 600 FREQUENCY (MHz)
-40 700
Figure 23. Output Resistance and Reactance vs. Frequency
860 840 820
GROUP DELAY (ps) GROUP DELAY (ps)
Figure 26. Various Forms of Isolation vs. Frequency
1400 RL = 1k 1300
HIGH GAIN MODE 1200 1100 1000 900 800
03692-025
800 780 760 LOW GAIN MODE 740
03692-022
RL = 100
720 700 0 10 20 30 40 50 60 70 80 90 100 110 120 130 GAIN CODE
700 600 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz)
Figure 24. Group Delay vs. Gain Code at 70 MHz
Figure 27. Group Delay vs. Frequency at Maximum Gain
Rev. A | Page 10 of 28
03692-024
20
-20
-100
FORWARD TRANSMISSION, PWUP LOW
03692-023
AD8370
80
DIFFERENTIAL OUTPUT (50mV/DIV)
70 LG32, LG127 60 HG32, HG127
CMRR (dB)
ZERO
50 40 30
GAIN CODE HG127
PWUP (2V/DIV)
20
03692-026
INPUT = -30dBm, 70MHz 100 AVERAGES
0 10 100 FREQUENCY (MHz) 1000
TIME (40ns/DIV)
Figure 28. Common-Mode Rejection Ratio vs. Frequency
12
Figure 31. PWUP Time Domain Response
DIFFERENTIAL OUTPUT (10mV/DIV)
NOISE SPECTRAL DENSITY (nV/ Hz)
10
ZERO
8 LG127 6
LTCH (2V/DIV) 6dB GAIN STEP (HG36 TO LG127)
4 HG18 2
03692-027
03692-030 03692-031
HG127
GND
0 10 110 210 310 410 510 610 FREQUENCY (MHz)
INPUT = -30dBm, 70MHz NO AVERAGING
TIME (20ns/DIV)
Figure 29. Input Referred Noise Spectral Density vs. Frequency at Various Gains
Figure 32. Gain Step Time Domain Response
VOUT DIFFERENTIAL
VOPHI
VOLTAGE (600mV/DIV)
DIFFERENTIAL VOUT
DIFFERENTIAL VIN
03692-028
VOLTAGE (1V/DIV)
VOPLO
GND
GND
TIME (2ns/DIV)
TIME (2ns/DIV)
Figure 30. DC-Coupled Large Signal Pulse Response
Figure 33. Overdrive Recovery
Rev. A | Page 11 of 28
03692-029
10
GND
AD8370
85 2.75 80 2.70 2.65 +25C LOW GAIN 65 60 HIGH GAIN
+85C
SUPPLY CURRENT (mA)
75
VCM (V)
70
2.60
2.55 2.50 -40C
03692-034
03692-032
55
2.45 LOW GAIN MODE 0 32 64 96
50 0 16 32 48 64 GAIN CODE 80 96 112 128
2.40
HIGH GAIN MODE 0 GAIN CODE 32 64 96 128
Figure 34. Supply Current vs. Gain Code
Figure 36. Common-Mode Output Voltage vs. Gain Code at Various Temperatures
35 MEAN: 51.9 : 0.518 30 25 DATA FROM 136 PARTS FROM ONE BATCH LOT
COUNT
20
15 10
0 50
51
52
53
54
55
GAIN (V/V)
Figure 35. Distribution of Voltage Gain, HG127, 70 MHz, RL = 100
03692-033
5
Rev. A | Page 12 of 28
AD8370 THEORY OF OPERATION
The AD8370 is a low cost, digitally controlled, fine adjustment variable gain amplifier (VGA) that provides both high IP3 and low noise figure. The AD8370 is fabricated on an ADI proprietary high performance 25 GHz silicon bipolar process. The -3 dB bandwidth is approximately 750 MHz throughout the variable gain range. The typical quiescent current of the AD8370 is 78 mA. A power-down feature reduces the current to less than 4 mA. The input impedance is approximately 200 differential, and the output impedance is approximately 100 differential to be compatible with saw filters and matching networks used in intermediate frequency (IF) radio applications. Because there is no feedback between the input and output and stages within the amplifier, the input amplifier is isolated from variations in output loading and from subsequent impedance changes, and excellent input to output isolation is realized. Excellent distortion performance and wide bandwidth make the AD8370 a suitable gain control device for modern differential receiver designs. The AD8370 differential input and output configuration is ideally suited to fully differential signal chain circuit designs, although it can be adapted to single-ended system applications, if required. The input impedance is approximately 200 differential, regardless of which preamplifier is selected. Note that the input impedance is formed by using active circuit elements and is not set by passive components. See Figure 38 for a simplified schematic of the input interface.
1mA
INHI/INLO 2k VCC/2
1mA
Figure 38. INHI/INLO Simplified Schematic
TRANSCONDUCTANCE STAGE
The digitally controlled gm section has 42 dB of controllable gain and makes gain adjustments within each gain range. The step size resolution ranges from a fine ~ 0.07 dB up to a coarse 6 dB per bit, depending on the gain code. As shown in Figure 39, of the 42 dB total range, 28 dB has resolution of better than 2 dB, and 22 dB has resolution of better than 1 dB. Figure 39 shows typical input levels that can be applied to this amplifier at different gain settings. The maximum input was determined by finding the 1 dB compression or expansion point of the VOUT/VSOURCE gain. Note that this is not VOUT/VIN. In this way, the change in the input impedance of the device is also taken into account.
3.2 2.8 <0.5dB RES 34dB GAIN 17dB GAIN 12dB GAIN 6dB GAIN -8dB GAIN 0.1dB GAIN -5dB GAIN 0.4 0 0 0.2 0.4 0.6 0.8 -11dB GAIN -25dB GAIN 1.0 1.2 1.4 1.6 1.8 <1dB RES HIGH GAIN <0.5dB RESOLUTION
BLOCK ARCHITECTURE
The three basic building blocks of the AD8370 are a high/low gain selectable input preamplifier, a digitally controlled transconductance (gm) block, and a fixed gain output stage.
VCCI
3
VCCO
11
VCCO
6
PWUP ICOM INHI
4 2 1
BIAS CELL
5 7 8
VOCM OCOM OPHI
PRE AMP INLO 16 ICOM 15
TRANSCONDUCTANCE
OUTPUT AMP
9
OPLO
10 OCOM
SHIFT REGISTER AND LATCHES
AD8370
14 13 12
03692-035
LOW GAIN
2.4
VOUT [V peak] (V)
DATA CLCK LTCH
2.0 1.6 1.2 0.8
Figure 37. Functional Block Diagram
PREAMPLIFIER
There are two selectable input preamplifiers. Selection is made by the most significant bit (MSB) of the serial gain control dataword. In the high gain mode, the overall device gain is 7.1 V/V (17 dB) above the low gain setting. The two preamplifiers give the AD8370 the ability to accommodate a wide range of input amplitudes. The overlap between the two gain ranges allows the user some flexibility based on noise and distortion demands. See the Choosing Between Gain Ranges section for more information.
<2dB RES
<1dB RES <2dB RES
03692-037
VSOURCE [V peak] (V)
Figure 39. Gain Resolution and Nominal Input and Output Range over the Gain Range
Rev. A | Page 13 of 28
03692-036
AD8370
OUTPUT AMPLIFIER
The output impedance is approximately 100 differential and, like the input preamplifier, this impedance is formed using active circuit elements. See Figure 40 for a simplified schematic of the output interface. Table 4. Serial Programming Timing Parameters
Parameter Clock Pulse Width (TPW) Clock Period (TCK) Setup Time Data vs. Clock (TDS) Setup Time Latch vs. Clock (TES) Hold Time Latch vs. Clock (TEH) Min 25 50 10 20 10 Unit ns ns ns ns ns
OPHI/OPLO 740 VCC/2
10A
CLCK/DATA/LTCH/PWUP
03692-038
Figure 40. OPHI/OPLO Simplified Circuit
Figure 42. Simplified Circuit for Digital Inputs
The gain of the output amplifier, and thus the AD8370 as a whole, is load dependent. The following equation can be used to predict the gain deviation of the AD8370 from that at 100 as the load is varied.
GainDeviation = 1.98 98 1+ RLOAD
VOCM 75 VCC/2
For example, if RLOAD is 1 k, the gain is a factor of 1.80 (5.12 dB) above that at 100 , all other things being equal. If RLOAD is 50 , the gain is a factor of 0.669 (3.49 dB) below that at 100 .
03692-040
Figure 43. Simplified Circuit for VOCM Output
DIGITAL INTERFACE AND TIMING
The digital control port uses a standard TTL interface. The 8-bit control word is read in a serial fashion when the LTCH pin is held low. The levels presented to the DATA pin are read on each rising edge of the CLCK signal. Figure 41 illustrates the timing diagram for the control interface. Minimum values for timing parameters are presented in Table 4. Figure 42 is a simplified schematic of the digital input pins.
TDS DATA (PIN 14) MSB MSB-1 MSB-2 MSB-3 LSB+3 LSB+2 LSB+1 TCK CLCK (PIN 13) TES LTCH (PIN 12) TEH
03692-039
LSB
TPW
Figure 41. Digital Timing Diagram
Rev. A | Page 14 of 28
03692-041
AD8370 APPLICATIONS
BASIC CONNECTIONS
Figure 44 shows the minimum connections required for basic operation of the AD8370. Supply voltages between 3.0 V and 5.5 V are allowed. The supply to the VCCO and VCCI pins should be decoupled with at least one low inductance, surfacemount ceramic capacitor of 0.1 F placed as close as possible to the device.
SERIAL CONTROL INTERFACE 1nF 1nF
GAIN CODES
The AD8370's two gain ranges are referred to as high gain (HG) and low gain (LG). Within each range, there are 128 possible gain codes. Therefore, the minimum gain in the low gain range is given by the nomenclature LG0 whereas the maximum gain in that range is given by LG127. The same is true for the high gain range. Both LG0 and HG0 essentially turn off the variable transconductance stage, and thus no output is available with these codes (see Figure 26). The theoretical linear voltage gain can be expressed with respect to the gain code as AV = GainCode Vernier (1 + (PreGain - 1) MSB)
RL
OCOM PWUP VOCM VCCO OPHI
RS
CLCK DATA ICOM OCOM INLO VCCO LTCH OPLO
2
16
15
14
13
12
11
10
9
BALANCED SOURCE
AD8370
ICOM VCCI INHI
BALANCED LOAD
where: AV is the linear voltage gain. GainCode is the digital gain control word minus the MSB (the final 7 bits). Vernier = 0.055744 V/V PreGain = 7.079458 V/V
RS 2 1nF
1
2
3
4
5
6
7
8
1nF
1nF
100pF
0.1F
0.1F
100pF
03692-042
FERRITE BEAD
FERRITE BEAD +VS (3.0V TO 5.0V)
Figure 44. Basic Connections
The AD8370 is designed to be used in differential signal chains. Differential signaling allows improved even-order harmonic cancellation and better common-mode immunity than can be achieved using a single-ended design. To fully exploit these benefits, it is necessary to drive and load the device in a balanced manner. This requires some care to ensure that the common-mode impedance values presented to each set of inputs and outputs are balanced. Driving the device with an unbalanced source can degrade the common-mode rejection ratio. Loading the device with an unbalanced load can cause degradation to even-order harmonic distortion and premature output compression. In general, optimum designs are fully balanced, although the AD8370 still provides impressive performance when used in an unbalanced environment. The AD8370 is a fine adjustment, VGA. The gain control transfer function is linear in voltage gain. On a decibel scale, this results in the logarithmic transfer functions shown in Figure 4. At the low end of the gain transfer function, the slope is steep, providing a rather coarse control function. At the high end of the gain control range, the decibel step size decreases, allowing precise gain adjustment.
MSB is the most significant bit of the 8-bit gain control word. The MSB sets the device in either high gain mode (MSB = 1) or low gain mode (MSB = 0). For example, a gain control word of HG45 (or 10101101 binary) results in a theoretical linear voltage gain of 17.76 V/V, calculated as 45 x 0.055744 x (1 + (7.079458 - 1) x 1) Increments or decrements in gain within either gain range are simply a matter of operating on the GainCode. Six -dB gain steps, which are equivalent to doubling or halving the linear voltage gain, are accomplished by doubling or halving the GainCode. When power is first applied to the AD8370, the device is programmed to code LG0 to avoid overdriving the circuitry following it.
POWER-UP FEATURE
The power-up feature does not affect the GainCode, and the gain setting is preserved when in power-down mode. Powering down the AD8370 (bringing PWUP low while power is still applied to the device) does not erase or change the GainCode from the AD8370, and the same gain code is in place when the device is powered up, that is, when PWUP is brought high again. Removing power from the device all together and reapplying, however, reprograms to LG0.
Rev. A | Page 15 of 28
AD8370
CHOOSING BETWEEN GAIN RANGES
There is some overlap between the two gain ranges; users can choose which one is most appropriate for their needs. When deciding which preamp to use, consider resolution, noise, linearity, and spurious-free dynamic range (SFDR). The most important points to keep in mind are * * * * The low gain range has better gain resolution. The high gain range has a better noise figure. The high gain range has better linearity and SFDR at higher gains. Conversely, the low gain range has higher SFDR at lower gains. gain is increased beyond this point, which explains the knee in the OIP3 curve. The IIP3 curve has a knee for the same reason; however, as the gain is increased beyond the knee, the IIP3 starts to decrease rather than increase. This is because in this region OIP3 is constant, therefore the higher the gain, the lower the IIP3. The two gain ranges have equal SFDR at approximately 13 dB power gain.
LAYOUT AND OPERATING CONSIDERATIONS
Each input and output pin of the AD8370 presents either a 100 or 50 impedance relative to their respective ac grounds. To ensure that signal integrity is not seriously impaired by the printed circuit board, the relevant connection traces should provide an appropriate characteristic impedance to the ground plane. This can be achieved through proper layout. When laying out an RF trace with a controlled impedance, consider the following: * Space the ground plane to either side of the signal trace at least three line-widths away to ensure that a microstrip (vertical dielectric) line is formed, rather than a coplanar (lateral dielectric) waveguide. Ensure that the width of the microstrip line is constant and that there are as few discontinuities as possible, such as component pads, along the length of the line. Width variations cause impedance discontinuities in the line and may result in unwanted reflections. Do not use silkscreen over the signal line because it alters the line impedance.
Figure 45 provides a summary of noise, OIP3, IIP3, and SFDR as a function of device power gain. SFDR is defined as
SFDR =
2 (IIP3 - NF - N S ) 3
where: IIP3 is the input third-order intercept point, the output intercept point in dBm minus the gain in dB. NF is the noise figure in dB. NS is source resistor noise, -174 dBm for a 1 Hz bandwidth at 300K (27C). In general, NS = 10 log10(kTB), where k = 1.374 x10-23 , T is the temperature in degrees Kelvin, and B is the noise bandwidth in Hertz.
50 180 NF LOW GAIN OIP3 LOW GAIN 30 20 10 NF HIGH GAIN 0 -10 -20 -30 -30 SFDR LOW GAIN SFDR HIGH GAIN 130 120
03692-043
*
*
Keep the length of the input and output connection lines as short as possible. Figure 46 shows the cross section of a PC board, and Table 5 show the dimensions that provide a 100 line impedance for FR-4 board material with r = 4.6. Table 5.
NOISE FIGURE (dB); OIP3 AND IIP3 (dBm)
40
OIP3 HIGH GAIN
170 160
IIP3 LOW GAIN IIP3 HIGH GAIN
150
SFDR (dB)
140
W H T
100 22 mils 53 mils 2 mils
50 13 mils 8 mils 2 mils
110 100
3W
W
3W T
-20
-10
0
10
20
30
40
H ER
03692-044
POWER GAIN (dB)
Figure 45. OIP3, IIP3, NF, and SFDR Variation with Gain
As the gain increases, the input amplitude required to deliver the same output amplitude is reduced. This results in less distortion at the input stage, and therefore the OIP3 increases. At some point, the distortion of the input stage becomes small enough such that the nonlinearity of the output stage becomes dominant. The OIP3 does not improve significantly because the
Figure 46. Cross-Sectional View of a PC Board
It possible to approximate a 100 trace on a board designed with the 50 dimensions above by removing the ground plane within 3 line-widths of the area directly below the trace.
Rev. A | Page 16 of 28
AD8370
The AD8370 contains both digital and analog sections. Care should be taken to ensure that the digital and analog sections are adequately isolated on the PC board. The use of separate ground planes for each section connected at only one point via a ferrite bead inductor ensures that the digital pulses do not adversely affect the analog section of the AD8370. Due to the nature of the AD8370's circuit design, care must be taken to minimize parasitic capacitance on the input and output. The AD8370 could become unstable with more than a few pF of shunt capacitance on each input. Using resistors in series with input pins is recommended under conditions of high source capacitance. High transient and noise levels on the power supply, ground, and digital inputs can, under some circumstances, reprogram the AD8370 to an unintended gain code. This further reinforces the need for proper supply bypassing and decoupling. The user should also be aware that probing the AD8370 and associated circuitry during circuit debug may also induce the same effect. -j1.6 on each input node at 100 MHz. This attenuates the applied input voltage by 0.003 dB. If 10 pF capacitors had been selected, the voltage delivered to the input would be reduced by 2.1 dB when operating with a 200 source impedance.
0.5
DIFFERENTIAL BALANCE (dB)
0
HIGH GAIN MODE (GAIN CODE HG255)
-0.5
-1.0 0 100 200 300 400 500 FREQUENCY (MHz)
Figure 48. Differential Output Balance for a Single-Ended Input Drive at Maximum Gain (RL = 1 k, CAC = 10 nF)
PACKAGE CONSIDERATIONS
The package of the AD8370 is a compact, thermally enhanced TSSOP 16-lead design. A large exposed paddle on the bottom of the device provides both a thermal benefit and a low inductance path to ground for the circuit. To make proper use of this packaging feature, the PCB needs to make contact directly under the device, connected to an ac/dc common ground reference with as many vias as possible to lower the inductance and thermal impedance.
Figure 48 illustrates the differential balance at the output for a single-ended input drive for multiple gain codes. The differential balance is better than 0.5 dB for signal frequencies less than 250 MHz. Figure 49 depicts the differential balance over the entire gain range at 10 MHz. The balance is degraded for lower gain settings because the finite common gain allows some of the input signal applied to INHI to pass directly through to the OPLO pin. At higher gain settings, the differential gain dominates and balance is restored.
0.6 LOW GAIN MODE HIGH GAIN MODE
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
SERIAL CONTROL INTERFACE C
DIFFERENTIAL BALANCE (dB)
AC
CAC
0.5
0.4
RS SINGLEENDED SOURCE
16
15
14
13
12
11
10
9
VCCO
CLCK
DATA
ICOM
OCOM
INLO
OPLO
LTCH
0.3
AD8370
OCOM PWUP VOCM VCCO ICOM OPHI VCCI INHI
RL
0.2
CAC 0.1F 1nF 0.1F
CAC
0
0
32
64
96
0 GAIN CODE
32
64
96
128
+VS
03692-045
Figure 47. Single-Ended-to-Differential Conversion
Figure 49. Differential Output Balance at 10 MHz for a Single-Ended Drive vs. Gain Code (RL = 1 k, CAC = 10 nF)
The AD8370 is primarily designed for differential signal interfacing. The device can be used for single-ended-to-differential conversion simply by terminating the unused input to ground using a capacitor as depicted in Figure 47. The ac coupling capacitors should be selected such that their reactance is negligible at the frequency of operation. For example, using 1 nF capacitors for CAC presents a capacitive reactance of
Even though the amplifier is no longer being driven in a balanced manner, the distortion performance remains adequate for most applications. Figure 50 illustrates the harmonic distortion performance of the circuit in Figure 47 over the entire gain range.
Rev. A | Page 17 of 28
03692-047
1
2
3
4
5
6
7
8
0.1
03692-046
LOW GAIN MODE (GAIN CODE LG127)
AD8370
If the amplifier is driven in single-ended mode, the input impedance varies depending on the value of the resistor used to terminate the other input as RinSE = RinDIFF + RTERM
499 SERIAL CONTROL INTERFACE VOCM
499 +5V
100
16 15 14 13 12 11 10 9
VCCO
CLCK
DATA
ICOM
OCOM
VOCM
PWUP
VCCO
ICOM
where RTERM is the termination resistor connected to the other input.
-40
RS
RT
OCOM
OPLO
INLO
LTCH
AD8138
VOCM
AD8370
OPHI VCCI INHI
RL
499 RT 2
1
2
3
4
5
6
7
8
-50
HARMONIC DISTORTION (dBc)
499
100 1nF 1nF +5V
VOCM
-60 HD2 -70 HD2
SINGLE-ENDED GROUND REFERENCED SOURCE 0.1F
-80
Figure 52. DC Coupling the AD8370. The AD8138 is used as a unity-gain level shifting amplifier to lift the common-mode level of the source to midsupply.
HD3 HD3
-90 LOW GAIN MODE 0 32 64 96 0 GAIN CODE HIGH GAIN MODE 32 64 96 128
03692-048
-100
Figure 50. Harmonic Distortion of the Circuit in Figure 47
DC-COUPLED OPERATION
-2.5V SERIAL CONTROL INTERFACE RT RS SINGLEENDED GROUND REFERENCED SOURCE
16 15 14 13 12 11 10 9
1nF
0V
AD8370
OCOM VOCM PWUP VCCO ICOM OPHI VCCI INHI
RL
1
2
3
4
5
6
7
8
0V -2.5V 0.1F 0.1F 1nF +2.5V
03692-049
The AD8370 is also a dc accurate VGA. The common-mode dc voltage present at the output pins is internally set to midsupply using what is essentially a buffered resistive divider network connected between the positive supply rail and the common (ground) pins. The input pins are at a slightly higher dc potential, typically 250 mV to 550 mV above the output pins, depending on gain setting. In a typical single-supply application, it is necessary to raise the common-mode reference level of the source and load to roughly midsupply to maintain symmetric swing and to avoid sinking or sourcing strong bias currents from the input and output pins. It is possible to use balanced dual supplies to allow ground referenced source and load, as shown in Figure 51. By connecting the VOCM pin and unused input to ground, the input and output common-mode potentials are forced to virtual ground. This allows direct coupling of ground referenced source and loads. The initial differential input offset is typically only a few 100 V. Over temperature, the input offset could be as high as a few tens of mVs. If precise dc accuracy is needed over temperature and time, it may be necessary to periodically measure the input offset and to apply the necessary opposing offset to the unused differential input, canceling the resulting output offset. To address situations where dual supplies are not convenient, a second option is presented in Figure 52. The AD8138 differential amplifier is used to translate the common-mode level of the driving source to midsupply, which allows dc accurate performance with a ground-referenced source without the need for dual supplies. The bandwidth of the solution in Figure 52 is limited by the gain-bandwidth product of the AD8138. The normalized frequency response of both implementations is shown in Figure 53.
ICOM
OCOM
VCCO
INLO
Figure 51. DC Coupling the AD8370. Dual supplies are used to set the input and output common-mode levels to 0 V.
OPLO
DATA
CLCK
LTCH
Rev. A | Page 18 of 28
03692-050
AD8370
10 8
NORMALIZED RESPONSE (dB)
6 4 2 0 -2 -4 -6 -8 -10 1 10 100 1k 10k
AD8370 WITH AD8138 SINGLE +5V SUPPLY
AD8370 USING DUAL 2.5V SUPPLY
03692-051
Often it is wise to include input and output parasitic suppression resistors, RIP and ROP. Parasitic suppressing resistors help to prevent resonant effects that occur as a result of internal bondwire inductance, pad to substrate capacitance, and stray capacitance of the printed circuit board trace artwork. If omitted, undesirable settling characteristics may be observed. Typically, only 10 to 25 of series resistance is all that is needed to help dampen resonant effects. Considering that most ADCs present a relatively high input impedance, very little signal is lost across the RIP and ROP series resistors. Depending on the input impedance presented by the input system of the ADC, it may be desirable to terminate the ADC input down to a lower impedance by using a terminating resistor, RT. The high frequency response of the AD8370 exhibits greater peaking when driving very light loads. In addition, the terminating resistor helps to better define the input impedance at the ADC input. Any part-to-part variability of ADC input impedance is reduced when shunting down the ADC inputs by using a moderate tolerance terminating resistor (typically a 1% value is acceptable). After defining reasonable values for coupling capacitors, suppressing resistors, and the terminating resistor, it is time to design the intermediate filter network. The example in Figure 54 suggests a second-order, low-pass filter network comprised of series inductors and a shunt capacitor. The order and type of filter network used depends on the desired high frequency rejection required for the ADC interface, as well as on pass-band ripple and group delay. In some situations, the signal spectra may already be sufficiently band-limited such that no additional filter network is necessary, in which case ZS would simply be a short and ZP would be an open. In other situations, it may be necessary to have a rather high-order antialiasing filter to help minimize unwanted high frequency spectra from being aliased down into the first Nyquist zone of the ADC. To properly design the filter network, it is necessary to consider the overall source and load impedance presented by the AD8370 and ADC input, including the additional resistive contribution of suppression and terminating resistors. The filter design can then be handled by using a single-ended equivalent circuit, as shown in Figure 55. A variety of references that address filter synthesis are available. Most provide tables for various filter types and orders, indicating the normalized inductor and capacitor values for a 1 Hz cutoff frequency and 1 load. After scaling the normalized prototype element values by the actual desired cut-off frequency and load impedance, it is simply a matter of splitting series element reactances in half to realize the final balanced filter network component values.
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 53. Normalized Frequency Response of the Two Solutions in Figure 51 and Figure 52
ADC INTERFACING
Although the AD8370 is designed to provide a 100 output source impedance, the device is capable of driving a variety of loads while maintaining reasonable gain and distortion performance. A common application for the AD8370 is ADC driving in IF sampling receivers and broadband wide dynamic range digitizers. The wide gain adjustment range allows the use of lower resolution ADCs. Figure 54 illustrates a typical ADC interface network.
ROP CAC ZS RIP VIN 100 ZP RT VIN VOCM ROP CAC ZS RIP ZIN ADC
AD8370
Figure 54. Generic ADC Interface
Many factors need to be considered before defining component values used in the interface network, such as the desired frequency range of operation, the input swing, and input impedance of the ADC. AC coupling capacitors, CAC, should be used to block any potential dc offsets present at the AD8370 outputs, which would otherwise consume the available low-end range of the ADC. The CAC capacitors should be large enough so that they present negligible reactance over the intended frequency range of operation. The VOCM pin may serve as an external reference for ADCs that do not include an on-board reference. In either case, it is suggested that the VOCM pin be decoupled to ground through a moderately large bypassing capacitor (1 nF to 10 nF) to help minimize wideband noise pick-up.
Rev. A | Page 19 of 28
03692-052
AD8370
SOURCE RS LOAD ZS SINGLE-ENDED EQUIVALENT
VS
ZP
RL
RS 2
ZS 2 BALANCED CONFIGURATION RL 2 RL 2
03692-053
A complete design example is shown in Figure 58. The AD8370 is configured for single-ended-to-differential conversion with the input terminated down to present a single-ended 75 input. A sixth-order Chebyshev differential filter is used to interface the output of the AD8370 to the input of the AD9430 170 MSPS, 12-bit ADC. The filter minimizes aliasing effects and improves harmonic distortion performance. The input of the AD9430 is terminated with a 1.5 k resistor so that the overall load presented to the filter network is ~1 k. The variable gain of the AD8370 extends the useable dynamic range of the ADC. The measured intermodulation distortion of the combination is presented in Figure 57 at 42 MHz.
0 -10 -20 -30 -40 -50
VS
ZP
RS 2
ZS 2
Figure 55. Single-Ended-to-Differential Network Conversion
As an example, a second-order, Butterworth, low-pass filter design is presented where the differential load impedance is 1200 , and the padded source impedance of the AD8370 is assumed to be 120 . The normalized series inductor value for the 10-to-1, load-to-source impedance ratio is 0.074 H, and the normalized shunt capacitor is 14.814 F. For a 70 MHz cutoff frequency, the single-ended equivalent circuit consists of a 200 nH series inductor followed by a 27 pF capacitor. To realize the balanced equivalent, simply split the 200 nH inductor in half to realize the network shown in Figure 56.
RS = RS = 0.1 RL LN = 0.074H NORMALIZED SINGLE-ENDED EQUIVALENT
dBFS
-60 -70 -80 -90
-100
03692-055
-110 -120 CN 14.814F RL= 1 -130 0 10 20 30 40 50 60 70 FREQUENCY (MHz)
VS
fC = 1Hz
200nH DE-NORMALIZED SINGLE-ENDED EQUIVALENT
Figure 57. FFT Plot of Two-Tone Intermodulation Distortion at 42 MHz for the Circuit in Figure 58
RS = 120
VS
27pF
RL= 1200
fC = 70MHz
RS = 60 2 VS 100nH BALANCED CONFIGURATION RS = 60 2 100nH RL 2 = 600 RL 2 = 600
03692-054
In Figure 57, the intermodulation products are comparable to the noise floor of the ADC. The spurious-free dynamic range of the combination is better than 66 dB for a 70 MHz measurement bandwidth.
3 V OPERATION
27pF
It is possible to operate the AD8370 at voltages as low as 3 V with only minor performance degradation. Table 6 gives typical specifications for operation at 3 V. Table 6.
Parameter Output IP3 P1dB -3 dB Bandwidth IMD3 Typical (70 MHz, RL = 100 ) +23.5 dBm +12.7 dBm 650 MHz (HG 127) -82 dBc (RL = 1 k)
Figure 56. Second-Order, Butterworth, Low-Pass Filter Design Example
Rev. A | Page 20 of 28
AD8370
SERIAL CONTROL INTERFACE FROM 75 Tx-LINE CAC 100nF RS 120
16 15 14 13 12 11 10 9
CAC 100nF
68nH
180nH
220nH
25 VINA
ICOM
OCOM
INLO
VCCO
AD8370
OCOM VOCM PWUP VCCO ICOM OPHI VCCI INHI
OPLO
DATA
CLCK
LTCH
27pF
39pF
27pF
1.5k
AD9430
1
2
3
4
5
6
7
8
CAC CAC 100nF 0.1F +VS 1nF 0.1F 100nF
68nH
180nH
220nH
25
VINB
Figure 58. ADC Interface Example
Rev. A | Page 21 of 28
03692-056
AD8370 EVALUATION BOARD AND SOFTWARE
The evaluation board allows quick testing of the AD8370 by using standard 50 test equipment. The schematic is shown in Figure 59. Transformers T1 and T2 are used to transform 50 source and load impedances to the desired input and output reference levels. The top and bottom layers are shown in Figure 63 and Figure 64. The ground plane was removed under the traces between T1 and Pins INHI and INLO to approximate a 100 characteristic impedance. The evaluation board comes with the AD8370 control software that allows serial gain control from most computers. The evaluation board is connected via a cable to the parallel port of the computer. Adjusting the appropriate slider bar in the control software automatically updates the gain code of the AD8370 in either a linear or linear-in-dB fashion.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D-SUB 25 PIN MALE L2* C9 C1 TC4-1W 1nF T1
16 15 14 13 12 11 10 9
OPEN C3 1nF T2 JTX-2-10T
R7 R6 R5 1k 1k 1k
IN+
50 Tx LINE
50 Tx LINE
OUT+
INLO
IN-
50 Tx LINE R1 0
1:4
R2 0
OCOM
VCCO
OPLO
ICOM
DATA
CLCK
LTCH
R4 0
2:1 R3 0
50 Tx LINE
OUT-
AD8370
OCOM
7
VOCM
PWUP
VCCO
ICOM
1
2
3
4
5
6
C2 1nF C5 0.1F C8 0.1F
OPHI
8
VCCI
INHI
C4 1nF
SW1 PWUP
C6 1F L1*
VOCM R8 49.9 C10 OPEN P2
1 2 3 4 5
R9 OPEN
+VS C7 0.1F GND
VS
GND *EMI SUPPRESSION FERRITE HZ1206E601R-00
Figure 59. AD8370 Evaluation Board Schematic
Rev. A | Page 22 of 28
03692-057
AD8370
Figure 60. Evaluation Software
Table 7. AD8370 Evaluation Board Configuration Options
Component VS, GND, VOCM Function Power Interface Vector Pins. Apply supply voltage between VS and GND. The VOCM pin allows external monitoring of the common-mode input and output bias levels. Device Enable. Set to Position B to power up the device. When in Position A, the PWUP pin is connected to the PWUP vector pin. The PWUP pin allows external power cycling of the device. R8 and C10 are provided to allow for proper cable termination. Serial Control Interfaces. The evaluation board can be controlled using most PCs. Windows(R)-based control software is shipped with the evaluation kit. A 25-pin, D-sub connector cable is required to connect the PC to the evaluation board. It may be necessary to use a capacitor on the clock line, depending on the quality of the PC port signals. A 1 nF capacitor for C9 is usually sufficient for reducing clock overshoot. Input and Output Signal Connectors. These SMA connectors provide a convenient way to interface the evaluation board with 50 test equipment. Typically, the device is evaluated using a single-ended source and load. The source should connect to J1 (IN+), and the load should connect to J6 (OUT+). AC Coupling Capacitors. Provide ac coupling of the input and output signals. Impedance Transformers. T1 provides a 50 to 200 impedance transformation. T2 provides a 100 to 50 impedance transformation. Single-Ended or Differential. R2 and R4 are used to ground the center tap of the secondary windings on transformers T1 and T2. R1 and R3 should be used to ground J2 and J7 when used in single-ended applications. Power Supply Decoupling. Nominal supply decoupling consists of a ferrite bead series inductor followed by a 1 F capacitor to ground followed by a 0.1 F capacitor to ground positioned as close to the device as possible. C7 provides additional decoupling of the input common-mode voltage. L1 provides high frequency isolation between the input and output power supply. L2 provides high frequency isolation between the analog and digital ground. Default Condition Not applicable
SW1, R8, C10, PWUP P1, R5, R6, R7, C9
03692-058
SW1 = installed R8 = 49.9 (Size 0805) C10 = open (Size 0805) P1 = installed R5, R6, R7 = 1 k (Size 0603) C9 = open (Size 0603)
J1, J2, J6, J7
Not applicable
C1, C2, C3, C4 T1, T2 R1, R2, R3, R4
C1, C2, C3, C4 = 1 nF (Size 0603) T1 = TC4 -1W (Mini-Circuits) T2 = JTX-2-10T (Mini-Circuits) R1, R2, R3, R4 = 0 (Size 0603)
C5, C6, C7, C8 L1, L2
C6 = 1 F (Size 0805) C5, C7, C8 = 0.1 F (Size 0603) L1, L2 = HZ1206E601R-00 (Steward, Size 1206)
Rev. A | Page 23 of 28
AD8370
03692-059
Figure 61. Evaluation Board Top Silkscreen
Figure 63. Evaluation Board Top
03692-060
Figure 62. Evaluation Board Bottom Silkscreen
Figure 64. Evaluation Board Bottom
Rev. A | Page 24 of 28
03692-062
03692-061
AD8370 APPENDIX
CHARACTERIZATION EQUIPMENT
An Agilent N4441A Balanced-Measurement System was used to obtain the gain, phase, group delay, reverse isolation, CMRR, and s-parameter information contained in this data sheet. With the exception of the s-parameter information, T-attenuator pads were used to match the 50 impedance of this instrument's ports to the AD8370. An Agilent 4795A Spectrum Analyzer was used to obtain nonlinear measurements IMD, IP3, and P1dB through matching baluns and/or attenuator networks. Various other measurements were taken with setups shown in this section.
DEFINITIONS OF SELECTED PARAMETERS
Common-mode rejection ratio (Figure 28) has been defined for this characterization effort as
Differential Mode Gain Common Mode Gain
COMPOSITE WAVEFORM ASSUMPTION
The nonlinear two-tone measurements made for this data sheet, that is, IMD and IP3, are based on the assumption of a fixed value composite waveform at the output, generally 1 V p-p. The frequencies of interest dictate the use of RF test equipment, and because this equipment is generally not designed to work in units of volts, but rather watts and dBm, an assumption was made to facilitate equipment setup and operation. Two sinusoidal tones can be represented as V1 = V sin (2f1t) V2 = V sin (2f2t) The RMS average voltage of one tone is
1T 1 (V1 ) dt = 2 T0
2
where the numerator is the gain into a differential load at the output due to a differential source at the input, and the denominator is the gain into a differential-mode load at the output due to a common-mode source at the input. In terms of mixed-mode s-parameters, this equates to
SDD21 SDC 21
More information on mixed-mode s-parameters can be obtained in a reference by Bockelman, D.E. and Eisenstadt, W.R., Combined Differential and Common-Mode Scattering Parameters: Theory and Simulation. IEEE Transactions on Microwave Theory and Techniques, v 43, n 7, 1530 (July 1995). Reverse isolation (Figure 26) is defined as SDD12. Power supply rejection ratio (PSRR) is defined as
Adm As
where T is the period of the waveform. The RMS average voltage of the two-tone composite signal is
1T (V1 + V2 ) dt = 1 T 0
2
where Adm is the differential mode forward gain (SDD21), and As is the gain from the power supply pins (VCCI and VCCO, taken together) to the output (OPLO and OPHI, taken differentially), corrected for impedance mismatch. The following reference provides more information: Gray, P.R., Hurst, P.J., Lewis, S.H. and Meyer, R.G., Analysis and Design of Analog Integrated Circuits, 4th Edition, John Wiley & Sons, Inc., page 422.
It can be shown that the average power of this composite waveform is twice (3 dB) that of the single tone. This also means that the composite peak-to-peak voltage is twice (6 dB) that of a single tone. This principle can be used to set correct input amplitudes from generators scaled in dBm and is correct if the two tones are of equal amplitude and are reasonably close in frequency.
Rev. A | Page 25 of 28
AD8370
-22.5dB SERIAL DATA SOURCE VS 5.0V 1nF T1 MINICIRCUITS TC4-1W
16 15 14 13 12 11 10 9
PORT 1
PORT 1 SERIAL DATA SOURCE BIAS TEE CONNECTION TO PORT 1
1nF T2 MINICIRCUITS TC2-1T PORT 2
1nF
16 15 14 13 12 11 10 9
1nF MINICIRCUITS TC2-1T PORT 2
VCCO
0
OCOM
OPLO
INLO
ICOM
DATA
CLCK
LTCH
VCCO
ICOM
OPHI
VCCI
INHI
200
AD8370
OCOM PWUP VOCM VCCO ICOM OPHI VCCI INHI
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1nF VS 5.0V 1F 1nF 1nF 1nF
1nF VS 5.0V 1F
Figure 65. PSRR Adm Test Setup
03692-063
Figure 66. PSRR As Test Setup
HP8133A 3GHz PULSE GENERATOR TRIG
AUX IN
50 INPUT
50 INPUT
TEKTRONIX TDS5104 DPO OSCILLOSCOPE
50 50 INPUT INPUT
3dB ATTEN 6dB SPLITTER 3dB ATTEN
16 15 14 13 12
OUT
SERIAL DATA SOURCE VS 5.0V 475 52.3
11 10 9
2dB ATTEN
3dB ATTEN 6dB SPLITTER 3dB ATTEN
200
AD8370
OCOM PWUP VOCM VCCO ICOM OPHI VCCI INHI
OUT
1
2
3
4
5
6
OCOM
VCCO
7
OPLO
ICOM
DATA
CLCK
LTCH
INLO
8
475 52.3 VS 5.0V VS 5.0V
2dB ATTEN
Figure 67. DC Pulse Response and Overdrive Recovery Test Setup
Rev. A | Page 26 of 28
03692-065
1F
1nF
1nF
1nF
1F
03692-064
1nF
1nF
1nF
AGILENT 8753D NETWORK ANALYZER
AD8370
OCOM PWUP VOCM VCCO
AGILENT 8753D NETWORK ANALYZER
OCOM
OPLO
INLO
ICOM
DATA
CLCK
LTCH
AD8370
AGILENT 8648D SIGNAL GENERATOR RF OUT
SERIAL DATA SOURCE TEKTRONIX P6205 ACTIVE FET PROBE 1nF 475 T2
TEKTRONIX TDS5104 DPO OSCILLOSCOPE 50 INPUT
VS 5.0V 1nF T1
OCOM VCCO OPLO ICOM DATA CLCK LTCH INLO
MINICIRCUITS TC4-1W
16
15
14
13
12
11
10
9
0
MINICIRCUITS JTX-2-10T 105
50 INPUT
AD8370
OCOM
7
VOCM
PWUP
VCCO
ICOM
1
2
3
4
5
6
OPHI
8
VCCI
INHI
1nF VS 5.0V 1F 1nF 1nF 1nF
1nF 475 VS 5.0V 1F
03692-066
Figure 68. Gain Step Time Domain Response Test Setup
AGILENT 8648D SIGNAL GENERATOR 10MHz REF OUT RF OUT
SERIAL DATA SOURCE
TEKTRONIX TDS5104 DPO OSCILLOSCOPE
VS 5.0V 1nF T1 MINICIRCUITS TC4-1W
16 15 14 13 12 11 10 9
1nF 475 T2 MINICIRCUITS JTX-2-10T 105 50 INPUT
ICOM
OCOM OCOM
7
INLO
VCCO
0
AD8370
VOCM PWUP VCCO ICOM OPHI
8
1
2
VCCI
INHI
3
4
5
6
OPLO
1nF 475 VS 5.0V
DATA
1nF 10MHz IN OUTPUT VS 5.0V 1F 1nF 1nF AGILENT 33250A FUNCTION/ARBITRARY WAVEFORM GENERATOR
CLCK
LTCH
TEKTRONIX P6205 ACTIVE FET PROBE
50 INPUT
1F
03692-067
52.3
1nF
Figure 69. PWUP Response Time Domain Test Setup
Rev. A | Page 27 of 28
AD8370 OUTLINE DIMENSIONS
5.10 5.00 4.90 BOTTOM VIEW
9
16
TOP VIEW
1 8
4.50 4.40 4.30
6.40 BSC
EXPOSED PAD (Pins Up)
3.00 SQ
1.20 MAX 0.15 0.00 SEATING 0.65 BSC PLANE
1.05 1.00 0.80 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 70. 16-Lead Thin Shrink Small Outline Package with Exposed Pad [TSSOP_EP] (RE-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8370ARE AD8370ARE-REEL7 AD8370AREZ 1 AD8370AREZ-RL71 AD8370-EVAL
1
Temperature Range
-40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 16-lead TSSOP, Tube 16-lead TSSOP, 7" Reel 16-lead TSSOP, Tube 16-lead TSSOP, 7" Reel Evaluation Board
Package Option RE-16-2 RE-16-2 RE-16-2 RE-16-2
Z = Pb-free part.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03692-0-7/05(A)
T T
Rev. A | Page 28 of 28

▲Up To Search▲

Price & Availability of AD837005

	To Download AD837005 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .