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| STL100NH3LL N-CHANNEL 30V - 0.0032 - 25A PowerFLATTM (6x5) STripFETTM III MOSFET PRODUCT PREVIEW Table 1: General Features TYPE STL100NH3LL Figure 1: Package RDS(on) ID 25 A (1) VDSS 30 V < 0.0035 TYPICAL R DS(on) = 0.0032 @ 10V IMPROVED DIE-TO-FOOTPRINT RATIO VERY LOW PROFILE PACKAGE (1mm MAX) VERY LOW THERMAL RESISTANCE CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED PowerFLAT (6x5) DESCRIPTION The STL100NH3LL utilizes the latest advanced design rules of ST's proprietary STripFETTM Technology. This process complete to unique metallization technique realised the most advanced low voltage MOSFET in PowerFLAT(6x5). The Chipscaled PowerFLATTM package allows a significant board space saving, still boosting the performance. Figure 2: Internal Schematic Diagram APPLICATIONS HIGH-EFFICIENCY DC-DC CONVERTERS SYNCHRONOUS RECTIFICATION Table 2: Order Codes SALES TYPE STL100NH3LL MARKING L100NH3LL PACKAGE PowerFLATTM( 6x5 ) PACKAGING TAPE & REEL Rev. 4 October 2005 This is a preliminary information on a new product now in development. Details are subjet to change without notice 1/10 STL100NH3LL Table 3: Absolute Maximum ratings Symbol VDS VGS ID (2) ID IDM (3) ID (1) PTOT (2) PTOT(1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Drain Current (continuous) at TC = 25C Total Dissipation at TC = 25C Total Dissipation at TC = 25C Derating Factor Storage Temperature Operating Junction Temperature Range Value 30 16 100 15.6 100 25 80 4 0.03 -55 to 150 Unit V V A A A A W W W/C C Table 4: Thermal Data Rthj-C Rthj-pcb (4) Thermal Resistance Junction-case ( Drain) (Steady State) Thermal Operating Junction-pcb 1.56 31.3 C/W C/W Table 5: Avalanche Characteristics Symbol IAV EAS Parameter Not-Repetitive Avalanche Current (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAV, VDD = 24 V) Max Value 12.5 1.3 Unit A J ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 16V VDS = VGS, ID = 250 A VGS = 10V, ID = 12.5 A VGS = 4.5V, ID =12.5 A 1 0.0032 0.004 0.0035 0.005 Min. 30 1 10 100 Typ. Max. Unit V A A nA V 2/10 STL100NH3LL ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (5) Ciss Coss Crss td(on) tr td(off) tr Qg Qgs Qgd RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Input Resistance Test Conditions VDS = 10 V, ID=12,5 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 30 4450 655 50 18 50 75 8 30 12.5 10 1 2 40 Max. Unit S pF pF pF ns ns ns ns nC nC nC VDD = 15 V, ID = 12.5 A, RG= 4.7 VGS = 10 V (see Figure 15) VDD = 15V, ID = 25 A, VGS = 4.5V (see Figure 17) f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 3 Table 8: Source Drain Diode Symbol ISD ISDM (3) VSD (4) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 25 A, VGS = 0 ISD = 25 A, di/dt = 100A/s VDD = 25 V, Tj = 150C (see test circuit, Figure 16) 32 34 2.1 Test Conditions Min. Typ. Max. 25 100 1.3 Unit A A V ns nC A Note: (1)The value is according Rthj-pcb (2)The value is according Rthj-c (3) Pulse width limited by safe operating area. (4) When mounted on FR-4 board of 1 in2 , 2oz Cu, t < 10 sec (5) Pulsed: Pulse duration = 300s, duty cycle 1.5% 3/10 STL100NH3LL Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STL100NH3LL Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized BVDSS vs Temperature Figure 11: Normalized On Resistance vs Temperature Figure 14: Source-Drain Diode Forward Characteristics 5/10 STL100NH3LL Figure 15: Switching Times Test Circuit For Resistive Load Figure 17: Gate Charge Test Circuit Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/10 STL100NH3LL In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 7/10 STL100NH3LL PowerFLATTM (6x5) MECHANICAL DATA mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch 8/10 STL100NH3LL Table 9: Revision History Date 18-Apr-2005 20-Jun-2005 22-Jun-2005 10-Oct-2005 Revision 1 2 3 4 Description of Changes First release Updated mechanical data New RG value on table 6 Inserted Ecopack indication 9/10 STL100NH3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10 |
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