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STD60NH03L
N-CHANNEL 30V - 0.0075 - 60A DPAK/IPAK STripFETTM III POWER MOSFET
TYPE STD60NH03L
s s s s s s s
VDSS 30 V
RDS(on) < 0.009
ID 60 A
s
TYPICAL RDS(on) = 0.0075 @ 10 V TYPICAL RDS(on) = 0.009 @ 5 V RDS(ON) * Qg INDUSTRY's BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX "-1") SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4")
3 2 1
IPAK TO-251 (Suffix "-1") DPAK TO-252 (Suffix "T4")
3 1
DESCRIPTION
The STD60NH03L utilizes the latest advanced design rules of ST's proprietary STripFETTM technology. This is suitable fot the most demanding DC-DC converter application where high efficiency is to be achieved.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTES
Ordering Information
SALES TYPE STD60NH03LT4 STD60NH03L-1 MARKING D60NH03L D60NH03L PACKAGE TO-252 TO-251 PACKAGING TAPE & REEL TUBE
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM(1) Ptot EAS (2) Tstg Tj October 2003 Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 30 30 20 60 43 240 70 0.47 300 -55 to 175 Unit V V V A A A W W/C mJ C
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THERMAL DATA
Rthj-case Rthj-amb Rthj-pcb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Junction-pcb(#) Maximum Lead Temperature For Soldering Purpose Max Max Max 2.14 100 43 275 C/W C/W C/W C
(#) When Mounted on 1 inch2 FR-4 board, 2 oz of Cu.
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 20V Min. 30 1 10 100 Typ. Max. Unit V A A nA
ON (4)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 5 V ID = 250 A ID = 30 A ID = 30 A Min. 1 0.0075 0.009 0.009 0.017 Typ. Max. Unit V
DYNAMIC
Symbol gfs (4) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance Test Conditions VDS = 15 V ID = 18 A Min. Typ. 25 2200 380 49 Max. Unit S pF pF pF
VDS = 10V f = 1 MHz VGS = 0
f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain
1.5
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ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Qgls (4) Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Third-quadrant Gate Charge Test Conditions ID = 30 A VDD = 15 V RG = 4.7 VGS = 5 V (Resistive Load, Figure 3) VDD= 15 V ID= 60 A VGS= 5 V Min. Typ. 21 95 15.7 8.3 3.4 15 21 Max. Unit ns ns nC nC nC nC
VDS< 0 V
VGS= 10 V
SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 30 A VDD = 15 V RG = 4.7, VGS = 5 V (Resistive Load, Figure 3) Min. Typ. 19 15 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM VSD trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 30 A VGS = 0 32 51 3.2 Test Conditions Min. Typ. Max. 60 240 1.4 Unit A A V ns nC A
A
di/dt = 100A/s ISD = 60 A VDD = 20 V Tj = 150C (see test circuit, Figure 5)
(1) Pulse width limited by safe operating area (2) Starting Tj = 25 oC, ID = 30A, VDD = 20V
(3) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (4) Gate charge for synchronous operation . See Appendix
. .
Safe Operating Area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature
.
.
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-251 (IPAK) MECHANICAL DATA
DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033
H
C A C2
L2
D
B3 B6
A1
L
=
=
3
B5
B
A3
=
B2
=
G
=
E
L1
1
2
=
0068771-E
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STD60NH03L
TO-252 (DPAK) MECHANICAL DATA
mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397
DIM.
H
A
C2
C
DETAIL "A"
A1
L2
D DETAIL "A"
B
=
=
3
B2
=
=
G
E
2
L4
1
=
=
A2
0068772-B
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APPENDIX A Buck Converter: Power Losses Estimation
SW1
SW2
The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performan comparison, of how different pairs of devices ce affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is emoved to allow for a safer working junction r temperature. The low side (SW2) device requires: * * * * * Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires: * Small Rg and Ls to allow higher gate current peak an to limit the voltage d feedback on the gate * Small Qg to have a faster commutation and to reduce gate charge losses * Low RDS(on) to reduce the conduction losses.
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STD60NH03L
High Side Switch (SW1)
Low Side Switch (SW2)
Pconduction
R DS(on)SW1 * I 2 * d L
R DS(on)SW2 * I 2 * (1 - d ) L
Pswitching
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
IL Ig
Zero Voltage Switching
Pdiode
Recovery
Not Applicable
1
Vin * Q rr(SW2) * f
Conduction
Not Applicable
Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f
Pgate(Q G )
Q g(SW1) * Vgg * f
PQoss
Vin * Q oss(SW1) * f 2
Vin * Q oss(SW2) * f 2
Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss
Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses
1
Dissipated by SW1 during turn-on
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (R) 2003 STMicroelectronics - All Rights Reserved
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