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| Active Receive Mixer LF to 500 MHz AD8342 FEATURES Broadband RF port: LF to 500 MHz Conversion gain: 3.7 dB Noise figure: 12.2 dB Input IP3: 22.7 dBm Input P1dB: 8.3 dBm LO drive: 0 dBm Differential high impedance RF input port Single-ended, 50 LO input port Single-supply operation: 5 V @ 98 mA Power-down mode Exposed paddle LFCSP: 3 mm x 3 mm FUNCTIONAL BLOCK DIAGRAM VPDC PWDN EXRB COMM 12 COMM 13 RFCM 14 RFIN 15 VPMX 16 11 BIAS 10 9 8 7 6 5 COMM IFOP IFOM COMM 05352-001 AD8342 1 VPLO 2 LOCM 3 LOIN 4 COMM Figure 1. APPLICATIONS Cellular base station receivers ISM receivers Radio links RF instrumentation GENERAL DESCRIPTION The AD8342 is a high performance, broadband active mixer. It is well suited for demanding receive-channel applications that require wide bandwidth on all ports and very low intermodulation distortion and noise figure. The AD8342 provides a typical conversion gain of 3.7 dB with an RF frequency of 238 MHz. The integrated LO driver presents a 50 input impedance with a low LO drive level, helping to minimize the external component count. The differential high impedance broadband RF port allows for easy interfacing to both active devices and passive filters. The RF input accepts input signals as large as 1.6 V p-p or 8 dBm (relative to 50 ) at P1dB. The open-collector differential outputs provide excellent balance and can be used with a differential filter or IF amplifier, such as the AD8369 or AD8351. These outputs can also be converted to a single-ended signal through the use of a matching network or a transformer (balun). When centered on the VPOS supply voltage, the outputs may swing 2 V differentially. The AD8342 is fabricated on an Analog Devices proprietary, high performance SiGe IC process. The AD8342 is available in a 16-lead LFCSP. It operates over a -40C to +85C temperature range. An evaluation board is also available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD8342 TABLE OF CONTENTS Specifications..................................................................................... 3 AC Performance ............................................................................... 4 Spur Table .......................................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description......................................................................... 14 AC Interfaces................................................................................... 15 IF Port .......................................................................................... 16 LO Considerations ..................................................................... 17 High IF Applications.................................................................. 18 Evaluation Board ............................................................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/05--Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8342 SPECIFICATIONS VS = 5 V, TA = 25C, fRF = 238 MHz, fLO = 286 MHz, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, RF termination = 100 , IF terminated into 100 through a 2:1 ratio balun, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance DC Bias Level OUTPUT INTERFACE Output Impedance DC Bias Voltage Power Range LO INTERFACE Return Loss DC Bias Voltage POWER-DOWN INTERFACE PWDN Threshold PWDN Response Time PWDN Input Bias Current POWER SUPPLY Positive Supply Voltage Quiescent Current VPDC VPMX, IFOP, IFOM VPLO Total Quiescent Current Power-Down Current Conditions Hi-Z input terminated with 100 off-chip resistor Frequency = 238 MHz (measured at RFIN with RFCM acgrounded) Internally generated; port must be ac-coupled Differential impedance, frequency = 48 MHz Supplied externally Via a 2:1 impedance ratio transformer Min Typ 10 1||0.4 2.4 10||0.5 VS Max Unit dB k||pF V k||pF V dBm dB V V s s A A 5.25 V mA mA mA mA A 4.75 5.25 13 Internally generated; port must be ac-coupled 10 VS - 1.6 3.5 0.4 4 -80 +100 4.75 5 5 58 35 98 500 Device enabled, IF output to 90% of its final level Device disabled, supply current <5 mA Device enabled Device disabled Supply current for bias cells Supply current for mixer, RBIAS = 1.82 k Supply current for LO limiting amplifier VS = 5 V Device disabled 85 113 Rev. 0 | Page 3 of 20 AD8342 AC PERFORMANCE VS = 5 V, TA = 25C, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, RF termination 100 , IF terminated into 100 via a 2:1 ratio balun, unless otherwise noted. Table 2. Parameter RF FREQUENCY RANGE1 LO FREQUENCY RANGE1 IF FREQUENCY RANGE1 CONVERSION GAIN SSB NOISE FIGURE INPUT THIRD-ORDER INTERCEPT Conditions High side LO fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz fRF1 = 460 MHz, fRF2 = 461 MHz, fLO = 550 MHz, fIF1 = 90 MHz, fIF2 = 89 MHz each RF tone -10 dBm fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286MHz, fIF1 = 48MHz, fIF2 = 47MHz each RF tone -10 dBm fRF1 = 460 MHz, fRF2 = 410 MHz, fLO = 550 MHz, fIF1 = 90 MHz, fIF2 = 140 MHz fRF1 = 238 MHz, fRF2 = 188 MHz, fLO = 286 MHz, fIF1 = 48MHz, fIF2 = 98 MHz fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz LO power = 0 dBm, fLO = 286 MHz LO power = 0 dBm, fLO = 286 MHz LO power = 0 dBm, fRF = 238 MHz, fLO = 286 MHz IF terminated into 100 and measured with a differential probe RF power = -10 dBm, fRF = 238 MHz, fLO = 286 MHz RF power = -10 dBm, fRF = 238 MHz, fLO = 286 MHz Min 50 60 10 Typ Max 500 850 350 Unit MHz MHz MHz dB dB dB dB dBm dBm dBm dBm dBm dBm dBc dBc dBm dBc dBc 3.2 3.7 12.5 12.2 22.2 22.7 50 44 8.5 8.3 -27 -55 -47 -32 -70 INPUT SECOND-ORDER INTERCEPT INPUT 1 dB COMPRESSION POINT LO TO IF OUTPUT LEAKAGE LO TO RF INPUT LEAKAGE 2x LO TO IF OUTPUT LEAKAGE RF TO IF OUTPUT LEAKAGE IF/2 SPURIOUS 1 Frequency ranges are those that were extensively characterized; this device can operate over a wider range. See the High IF Applications section for details. Rev. 0 | Page 4 of 20 AD8342 SPUR TABLE VS = 5 V, TA = 25C, RF and LO power = 0 dBm, fRF = 238MHz, fLO = 286MHz, ZO = 50 , RBIAS = 1.82 k, RF termination 100 , IF terminated into 100 via a 2:1 ratio balun. Note: Measured using standard test board. Typical noise floor of measurement system = -100 dBm. Table 3. m nfRF - mfLO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 <-100 -39 -52 -81 -78 -98 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 1 -25 3.5 -47 -57 -70 -79 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 2 -54 -42 -51 -79 -80 -95 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 3 -28 -6 -49 -61 -79 -87 -99 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 4 -45 -48 -54 -82 -80 -96 <-100 -96 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 5 -35 -16 -56 -61 -85 -94 -96 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 6 -39 -50 -56 -74 -87 -95 <-100 -98 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 7 -36 -28 -62 -69 -92 -88 <-100 <-100 <-100 <-100 <-100 -96 <-100 <-100 <-100 <-100 8 -42 -57 -62 -94 -93 -98 <-100 <-100 -97 <-100 <-100 <-100 -99 <-100 <-100 <-100 9 -57 -37 -66 -85 -96 -94 <-100 <-100 <-100 <-100 <-100 -97 <-100 -97 <-100 <-100 10 -44 -68 -71 -89 -95 <-100 <-100 <-100 <-100 <-100 -99 <-100 -98 <-100 -98 <-100 11 -42 -45 -80 -86 <-100 <-100 <-100 <-100 <-100 -99 <-100 -96 <-100 -97 -98 <-100 12 -41 -54 -80 -86 -97 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -99 <-100 <-100 13 -46 -37 -67 -90 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 14 -59 -61 -79 -81 -95 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 n Rev. 0 | Page 5 of 20 AD8342 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage, VS RF Input Level LO Input Level PWDN Pin IFOP, IFOM Bias Voltage Minimum Resistor from EXRB to COMM Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 12 dBm 12 dBm VS + 0.5 V 5.5 V 1.8 k 650 mW 77C/W 135C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 AD8342 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 VPMX 15 RFIN 13 COMM 14 RFCM VPLO 1 LOCM 2 LOIN 3 COMM 4 PIN 1 INDICATOR 12 VPDC 11 PWDN 10 EXRB 9 COMM AD8342 TOP VIEW (Not to Scale) COMM 5 COMM 8 IFOM 6 IFOP 7 Figure 2. 16-Lead LFCSP Table 5. Pin Function Descriptions Pin No. 1 2 3 4, 5, 8, 9, 13 6, 7 10 11 12 14 15 16 Mnemonic VPLO LOCM LOIN COMM IFOM, IFOP EXRB PWDN VPDC RFCM RFIN VPMX Function Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V. AC Ground for Limiting LO Amplifier. Internally biased to Vs - 1.6 V. AC-couple to ground. LO Input. Nominal input level 0 dBm. Input level range -10 dBm to +4 dBm (relative to 50 ). Internally biased to Vs - 1.6 V. AC-couple. Device Common (DC Ground). Differential IF Outputs (Open Collectors). Each requires dc bias of 5.00 V (nominal). Mixer Bias Voltage. Connect resistor from EXRB to ground. Typical value of 1.82 k sets mixer current to nominal value. Minimum resistor value from EXRB to ground = 1.8 k. Internally biased to 1.17 V. Connect to Ground for Normal Operation. Connect pin to VS for disable mode. Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V. AC Ground for RF Input. Internally biased to 2.4 V. AC-couple to ground. RF Input. Internally biased to 2.4 V. Must be ac-coupled. Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V. Rev. 0 | Page 7 of 20 05352-002 AD8342 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, RF power = -10 dBm, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, RF termination 100 , IF terminated into 100 via a 2:1 ratio balun, unless otherwise noted. 6 6 5 5 GAIN (dB) GAIN (dB) 4 IF = 48MHz 4 RF = 238MHz RF = 460MHz 3 3 IF = 10MHz IF = 140MHz IF = 90MHz 2 05352-004 2 05352-005 1 50 100 150 200 250 300 350 400 450 500 550 1 10 50 100 150 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 3. Conversion Gain vs. RF Frequency 5 IF = 48MHz 4 IF = 10MHz 5.0 4.5 4.0 3.5 Figure 6. Conversion Gain vs. IF Frequency GAIN (dB) IF = 140MHz 2 IF = 90MHz GAIN (dB) 05352-025 3 3.0 2.5 2.0 1.5 1 1.0 0.5 0 4.75 4.85 4.95 5.05 5.15 05352-026 0 -15 -10 -5 LO LEVEL (dBm) 0 5 5.25 VPOS (V) Figure 4. Gain vs. LO Level, RF Frequency = 238 MHz 5.0 4.5 4.0 3.5 Figure 7. Gain vs. Vpos, fRF = 238 MHz, fLO = 286 MHz 50 45 40 35 NORMAL MEAN = 3.7 STD. DEV. = 0.06 CONVERSION GAIN (238MHz) PERCENTAGE PERCENTAGE GAIN (dB) 3.0 2.5 2.0 1.5 1.0 05352-039 30 25 20 15 10 5 0 3.40 3.45 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85 05352-054 0.5 0 -40 -20 0 20 40 60 80 3.90 TEMPERATURE (C) CONVERSION GAIN (238MHz) Figure 5. Gain vs. Temperature, fRF = 238 MHz, fLO = 286 MHz Figure 8. Conversion Gain Distribution, fRF = 238 MHz, fLO = 286 MHz Rev. 0 | Page 8 of 20 AD8342 27 26 25 IF = 48MHz 24 IF = 90MHz IF = 10MHz 27 26 25 24 INPUT IP3 (dBm) 23 22 21 20 19 05352-007 INPUT IP3 (dBm) 23 22 21 20 19 18 17 10 50 100 150 200 250 RF = 238MHz RF = 460MHz IF = 140MHz 18 17 50 100 150 200 250 300 350 400 450 500 550 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 9. Input IP3 vs. RF Frequency 27 26 25 24 IF = 48MHz IF = 10MHz 27 26 25 24 Figure 12. Input IP3 vs. IF Frequency INPUT IP3 (dBm) 23 22 21 20 19 05352-027 INPUT IP3 (dBm) 23 22 21 20 19 18 17 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 05352-028 IF = 90MHz 140MHz 18 17 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 5.20 5.25 LO LEVEL (dBm) VPOS (V) Figure 10. Input IP3 vs. LO Level, fRF1 = 238 MHz, fRF2 = 239 MHz Figure 13. Input IP3 vs. Vpos, fRF = 238 MHz, fRF2 = 239 MHz LO Frequency = 286 MHz 20 18 16 14 NORMAL MEAN = 22.7 STD. DEV. = 0.41 INPUT IP3 (238MHz) PERCENTAGE 27 26 25 24 INPUT IP3 (dBm) 23 22 21 20 19 05352-032 PERCENTAGE 12 10 8 6 4 2 0 20.6 21.0 21.4 21.8 22.2 22.6 23.0 23.4 23.8 05352-055 18 17 -40 -20 0 20 40 60 80 24.2 TEMPERATURE (C) INPUT IP3 (238MHz) Figure 11. Input IP3 vs. Temperature, fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz Figure 14. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz Rev. 0 | Page 9 of 20 05352-008 AD8342 13 12 11 10 9 8 90MHz 10MHz RF = 460MHz INPUT P1dB (dBm) 9 8 7 6 5 05352-013 INPUT P1dB (dBm) 10 7 6 5 4 3 2 1 0 10 50 100 150 RF = 238MHz 48MHz 140MHz 4 3 50 100 150 200 250 300 350 400 450 500 550 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 15. Input P1dB vs. RF Frequency Figure 18. Input P1dB vs. IF Frequency 10.0 9.5 9.0 IF = 90MHz IF = 10MHz 10 9 8 INPUT P1dB (dBm) 8.0 7.5 7.0 6.5 6.0 05352-038 INPUT P1dB (dBm) 8.5 7 6 5 4 3 2 1 0 4.75 4.85 4.95 5.05 5.15 05352-031 IF = 140MHz IF = 48MHz 5.5 5.0 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 5.25 LO LEVEL (dBm) VPOS (V) Figure 16. Input P1dB vs. LO Level, fRF = 238 MHz 28 26 24 22 20 Figure 19. Input P1dB vs. Vpos, fRF = 238 MHz, fLO = 286 MHz NORMAL MEAN = 8.3 STD. DEV. = 0.07 IP1dB (238MHz) PERCENTAGE 10 9 8 INPUT P1dB (dBm) 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 05352-033 PERCENTAGE 18 16 14 12 10 8 6 05352-056 4 2 0 8.00 8.05 8.10 8.15 8.20 8.25 8.30 8.35 8.40 8.45 8.50 8.55 8.60 IP1dB (238MHz) TEMPERATURE (C) Figure 17. Input P1dB vs. Temperature, fRF = 238 MHz, fLO = 286 MHz Figure 20. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz Rev. 0 | Page 10 of 20 05352-014 AD8342 60 IF = 10MHz 50 IF = 140MHz IF = 90MHz RF = 238MHz 50 RF = 460MHz 60 INPUT IP2 (dBm) IF = 48MHz 30 INPUT IP2 (dBm) 05352-010 40 40 30 20 20 10 10 05352-011 0 100 150 200 250 300 350 400 450 500 550 0 10 50 100 150 200 250 300 350 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 21. Input IP2 vs. RF Frequency (Second RF = R F - 50 MHz) 60 58 56 54 IF = 10MHz IF = 48MHz Figure 24. Input IP2 vs. IF Frequency (Second RF = R F - 50 MHz) 60 58 56 54 INPUT IP2 (dBm) 52 50 48 46 44 42 40 -15 IF = 90MHz IF = 140MHz 05352-029 INPUT IP2 (dBm) 52 50 48 46 44 42 40 4.75 4.85 4.95 5.05 5.15 05352-030 -13 -11 -9 -7 -5 -3 -1 1 3 5 5.25 LO LEVEL (dBm) VPOS (V) Figure 22. Input IP2 vs. LO Level, fRF = 238 MHz, ,fRF2 =188MHz 14.0 16 14 12 Figure 25. Input IP2 vs. Vpos, fRF1 = 238 MHz, fRF2 = 188 MHz, fLO = 286 MHz RF = 460MHz 13.5 NOISE FIGURE (dB) 13.0 NOISE FIGURE (dB) RF = 238MHz 10 8 6 4 12.5 12.0 11.5 05352-016 05352-017 2 0 10 11.0 50 100 150 200 250 300 350 400 450 500 550 60 110 160 210 260 310 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 23. Noise Figure vs. RF Frequency, IF Frequency = 48 MHz Figure 26. Noise Figure vs. IF Frequency Rev. 0 | Page 11 of 20 AD8342 16 30 NORMAL MEAN = 12.25 STD. DEV. = 0.14 NF PERCENTAGE 15 25 NF = 140MHz NF = 90MHz 13 PERCENTAGE 05352-018 14 20 NF (dB) 15 12 NF = 10MHz 11 NF = 48MHz 10 5 05352-023 10 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 0 11.8 11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 LO POWER (dBm) NOISE FIGURE (dB) Figure 27. Noise Figure vs. LO Power, fRF = 238 MHz 5.0 4.5 Figure 30. Noise Figure Distribution, fRF = 238 MHz, fLO = 286 MHz 30 105 NOISE FIGURE AND INPUT IP3 (dBm) 4.0 3.5 25 INPUT IP3 20 100 95 GAIN (dB) 3.0 2.5 2.0 1.5 1.0 0.5 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 05352-024 15 NOISE FIGURE CURRENT 5 90 10 85 80 2.0 2.2 2.4 RBIAS (k) 2.6 2.8 RBIAS (k) Figure 28. Gain vs. RBIAS, RF Frequency = 238 MHz, LO Frequency = 286MHz 61 59 57 55 53 51 49 Figure 31. Noise Figure, Input IP3 and Supply Current vs. RBIAS, fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz 10 9 8 INPUT P1dB (dBm) 7 6 5 4 3 2 INPUT IP2 (dBm) 05352-037 1 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 45 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 RBIAS (k) RBIAS (k) Figure 29. Input IP2 vs. RBIAS, fRF = 238 MHz (Second RF = RF - 50MHz), fLO = 286 MHz Figure 32. Input P1dB vs. RBIAS, fRF = 238 MHz, fLO = 286 MHz Rev. 0 | Page 12 of 20 05352-036 47 05352-015 0 1.8 75 3.0 SUPPLY CURRENT (mA) AD8342 0 -10 100 120 -20 LEAKAGE (dBc) -30 -40 -50 -60 -70 SUPPLY CURRENT (mA) 05352-021 80 60 40 20 -80 -90 50 250 450 LO FREQUENCY (MHz) 650 850 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) Figure 33. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm Figure 36. Supply Current vs. Temperature 0 -5 -10 0 -2 -4 FEEDTHROUGH (dBc) -15 -20 -25 -30 -35 -40 -45 50 05352-035 RETURN LOSS (dB) -6 -8 -10 -12 -14 IF = 10MHz IF = 48MHz 100 150 200 250 300 350 400 450 500 -16 -18 60 550 160 260 360 460 560 660 760 860 RF FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 34. RF to IF Feedthrough, RF Power = -10 dBm 0 -5 -10 VPOS Figure 37. LO Return Loss vs. LO Frequency 100pF 1.82k 0.1F 100pF FEEDTHROUGH (dBc) -15 -20 1nF 13 12 VPDC COMM 11 PWDN 10 EXRB 9 COMM COMM IFOP IFOM COMM 8 7 TC2-1T 6 5 IF OUT (50) -25 100 14 RFCM RF IN VPOS 1nF 16 VPMX 0.1F 100pF VPLO 15 RFIN AD8342 -30 -35 -40 -45 50 05352-020 LOCM LOIN COMM 05352-059 1 2 1nF 3 4 100pF 0.1F VPOS LO FREQUENCY (MHz) LO IN Figure 35. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm Figure 38. Characterization Circuit Used to Measure TPC Data Rev. 0 | Page 13 of 20 05352-058 150 250 350 450 550 650 750 850 0.1F 100pF 1nF 05352-034 AD8342 CIRCUIT DESCRIPTION The AD8342 is an active mixer optimized for operation within the input frequency range of near dc to 500 MHz. It has a differential, high impedance RF input that can be terminated or matched externally. The RF input can be driven either singleended or differentially. The LO input is a single-ended 50 input. The IF outputs are differential open-collectors. The mixer current can be adjusted by the value of an external resistor to optimize performance for gain, compression, and intermodulation, or for low power operation. Figure 39 shows the basic blocks of the mixer, including the LO buffer, RF voltage-tocurrent converter, bias cell, and mixing core. The RF voltage to RF current conversion is done via a resistively degenerated differential pair. To drive this port single-ended, the RFCM pin should be ac-grounded while the RFIN pin is ac-coupled to the signal source. The RF inputs can also be driven differentially. The voltage-to-current converter then drives the emitters of a four-transistor switching core. This switching core is driven by an amplified version of the local oscillator signal connected to the LO input. There are three limiting gain stages between the external LO signal and the switching core. The first stage converts the single-ended LO drive to a well-balanced differential drive. The differential drive then passes through two more gain stages, which ensures a limited signal drives the switching core. This affords the user a lower LO drive requirement, while maintaining excellent distortion and compression performance. The output signal of these three LO gain stages drives the four transistors within the mixer core to commutate at the rate of the local oscillator frequency. The output of the mixer core is taken directly from its open collectors. The open collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the impedance presented to these open collectors. In characterization, a 100 load was presented to the part via a 2:1 impedance transformer. The device also features a power-down function. Application of a logic low at the PWDN pin allows normal operation. A high logic level at the PWDN pin shuts down the AD8342. Power consumption when the part is disabled is less than 10 mW. The bias for the mixer is set with an external resistor (RBIAS) from the EXRB pin to ground. The value of this resistor directly affects the dynamic range of the mixer. The external resistor should not be lower than 1.82 k. Permanent damage to the part could result if values below 1.8 k are used. This resistor sets the dc current through the mixer core. The performance effects of changing this resistor can be seen in the Typical Performance Characteristics section. VPDC EXTERNAL BIAS RESISTOR PWDN BIAS RFIN RFCM IFOP IFOM V TO I LO INPUT VPLO Figure 39. Simplified Schematic Showing the Key Elements of the AD8342 As shown in Figure 40, the IF output pins, IFOP and IFOM, are directly connected to the open collectors of the NPN transistors in the mixer core so the differential and single-ended impedances looking into this port are relatively high--on the order of several k. A connection between the supply voltage and these output pins is required for proper mixer core operation. IFOP IFOM 05352-040 LOIN RFIN RFCM COMM Figure 40. AD8342 Simplified Schematic The AD8342 has three pins for the supply voltage: VPDC, VPMX, and VPLO. These pins are separated to minimize or eliminate possible parasitic coupling paths within the AD8342 that could cause spurious signals or reduced interport isolation. Consequently, each of these pins should be well bypassed and decoupled as close to the AD8342 as possible. Rev. 0 | Page 14 of 20 05352-041 AD8342 AC INTERFACES The AD8342 is designed to downconvert radio frequencies (RF) to lower intermediate frequencies (IF) using a high or low-side local oscillator (LO). The LO is injected into the mixer core at a frequency higher or lower than the desired input RF. The difference between the LO and the RF , fLO - fRF, (high side) or fRF - fLO (low side) is the intermediate frequency, fIF. In addition to the desired RF signal, an RF image is downconverted to the desired IF frequency. The image frequency is at fLO + fIF when driven with a high side LO . When using a broadband load, the conversion gain of the AD8342 is nearly constant over the specified RF input band (see Figure 3). The AD8342 is designed to operate over a broad frequency range. It is essential to ac-couple RF and LO ports to prevent dc offsets from skewing the mixer core in an asymmetrical manner, potentially degrading noise figure and linearity. The RF input of the AD8342 is high impedance, 1 k across the frequency range shown in Figure 41. The input capacitance decreases with frequency due to package parasitics. 2.00 1.75 1.50 RESISTANCE (k) Table 4. Dynamic Performance for Various Input Networks Input Network Gain (dB) IIP3 (dBm) P1dB (dBm) NF (dB) 50 Shunt 0.66 25.4 10.8 14 100 Shunt 3.5 22.9 8.4 12.5 500 Shunt 5.3 20. 6 6.3 10.2 Matched (Fig. 40) 9.3 18.5 2.3 10.5 The RF port can also be matched using an LC circuit, as shown in Figure 42. 50 100nH (1000 + j0) Figure 42. Matching Circuit 1.00 0.75 CAPACITANCE (pF) Impedance transformations of greater than 10:1 result in a higher Q circuit and thus a narrow RF input bandwidth. A 1 k resistor is placed across the RF input of the device in parallel with the device internal input impedance, creating a 500 load. This impedance is matched to as close as possible to 50 for the source, with standard components using a shunt C, series L matching circuit (see Figure 43). 50.0 1.25 1.00 0.75 0.50 0.25 0.25 0.50 25.0 Q = 3.0 100.0 05352-043 3.6pF 1k ZL ZO = 50 fMAIN = 250MHz 200.0 10.0 05352-042 0 0 100M 200M 300M 400M 500M 600M 700M 800M 900M FREQUENCY (Hz) 0 1G 500.0 Figure 41. RF Input Impedance 4 21 500.0 200.0 100.0 50.0 25.0 10.0 3 The matching or termination used at the RF input of the AD8342 has a direct effect on its dynamic range. The characterization circuit, as well as the evaluation board, uses a 100 resistor to terminate the RF port. This termination resistor in shunt with the input stage results in a return loss of better than -10 dBm (relative to 50 ). Table 4 shows gain, IP3, P1dB, and noise figure for four different input networks. This data was measured at an RF frequency of 250 MHz and at an LO frequency of 300 MHz. Point 1(1000.0 + j0.0) Q = 0.0 at 250.000 MHz Point 2(500.0 + j0.0) Q = 0.0 at 250.000 MHz Point 3(55.6 - j157.2) Q = 2.8 at 250.000 MHz Point 4(55.6 - j0.1) Q = 0.0 at 250.000 MHz Figure 43. LC Matching Example Rev. 0 | Page 15 of 20 05352-044 AD8342 IF PORT The IF port comprises open-collector differential outputs. The NPN open collectors can be modeled as current sources that are shunted with resistances of ~10 k in parallel with capacitances of ~1 pF. The specified performance numbers for the AD8342 were measured with 100 differential terminations. However, different load impedances may be used where circumstances dictate. In general, lower load impedances result in lower conversion gain and lower output P1dB. Higher load impedances result in higher conversion gain for small signals, but lower IP3 values for both input and output. If the IF signal is to be delivered to a remote load, more than a few millimeters away at high output frequencies, avoid unintended parasitic effects due to the intervening PCB traces. One approach is to use an impedance transforming network or transformer located close to the AD8342. If very wideband output is desired, a nearby buffer amplifier may be a better choice, especially if IF response to dc is required. An example of such a circuit is presented in Figure 45, in which the AD8351 differential amplifier is used to drive a pair of 75 transmission lines. The gain of the buffer can be independently set by appropriate choice of the value for the gain resistor, RG. 50 45 0.4 40 CAPACITANCE (pF) RESISTANCE (k) The high input impedance of the AD8351 allows for a shunt differential termination to provide the desired 100 load to the AD8342 IF output port. It is necessary to bias the open-collector outputs using one of the schemes presented in Figure 47 and Figure 48. Figure 47 illustrates the application of a center tapped impedance transformer. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a 50 load impedance, a 2-to-1 impedance ratio transformer should be used to transform the 50 load into a 100 differential load at the IF output pins. Figure 48 illustrates a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF operating frequency so it does not load down the output current before reaching the intended load. Additionally, the dc current handling capability of the selected choke inductors needs to be at least 45 mA. The selfresonant frequency of the selected choke should be higher than the intended IF frequency. A variety of suitable choke inductors are commercially available from manufacturers such as Murata and Coilcraft. Figure 46 shows the loading effects when using nonideal inductors. An impedance transforming network may be required to transform the final load impedance to 100 at the IF outputs. There are several good reference books that explain general impedance matching procedures, including: * Chris Bowick, RF Circuit Design, Newnes, Reprint Edition, 1997. * David M. Pozar, Microwave Engineering, Wiley Text Books, Second Edition, 1997. * Guillermo Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, Prentice Hall, Second Edition, 1996. 90 0.5 35 30 25 20 15 10 0.3 0.2 0.1 0 -0.1 5 120 60 0 100M 200M 300M 400M 500M 600M 700M 800M 900M FREQUENCY (Hz) Figure 44. IF Port Impedance +VS 05352-045 0 -0.2 1G 150 50MHz 30 REAL CHOKES AD8342 COMM 8 IFOP 7 100 IFOM 6 COMM 5 RG +VS RFC + AD8351 - Tx LINE ZO = 75 ZL Tx LINE ZO = 75 180 500MHz 210 500MHz 05352-046 0 50MHz IDEAL CHOKES 330 RFC +VS ZL = 100 240 300 270 05352-049 Figure 45. AD8351 Used as Transmission Line Driver and Impedance Buffer Figure 46. IF Port Loading Effects Due to Finite Q Pull-Up Inductors (Murata BLM18HD601SN1D Chokes) Rev. 0 | Page 16 of 20 AD8342 +VS 30 MODELED 25 AD8342 COMM 8 2:1 IFOP 7 IFOM 6 05352-047 VOLTAGE GAIN (dB) IF OUT ZO = 50 20 MEASURED COMM 5 ZL = 100 15 Figure 47. Biasing the IF Port Open-Collector Outputs Using a Center-Tapped Impedance Transformer +VS 10 5 05352-057 AD8342 COMM 8 IFOP 7 RFC IF OUT+ ZL = 100 IMPEDANCE TRANSFORMING NETWORK ZL 0 10 100 IF LOAD () 1000 IFOM 6 IF OUT- COMM 5 Figure 49. Voltage Conversion Gain vs. IF Loading RFC 05352-048 LO CONSIDERATIONS The LOIN port provides a 50 load impedance with commonmode decoupling on LOCM. Again, common-grade ceramic capacitors provide sufficient signal coupling and bypassing of the LO interface. The LO signal needs to have adequate phase noise characteristics and low second-harmonic content to prevent degradation of the noise figure performance of the AD8342. An LO plagued with poor phase noise can result in reciprocal mixing, a mechanism that causes spectral spreading of the downconverted signal, limiting the sensitivity of the mixer at frequencies close-in to any large input signals. The internal LO buffer provides enough gain to hard-limit the input LO and provide fast switching of the mixer core. Odd harmonic content present on the LO drive signal should not impact mixer performance; however, even-order harmonics cause the mixer core to commutate in an unbalanced manner, potentially degrading noise performance. Simple lumped element low-pass filtering can be applied to help reject the harmonic content of a given local oscillator, as shown in Figure 50. The filter depicted is a common 3-pole Chebyshev, designed to maintain a 1-to-1 source-to-load impedance ratio with no more than 0.5 dB of ripple in the pass band. Other filter structures can be effective as long as the second harmonic of the LO is filtered to negligible levels, for example, ~30 dB below the fundamental. AD8342 LOCM LOIN COMM RS LO SOURCE C1 L2 C3 RL 2 3 4 +VS Figure 48. Biasing the IF Port Open-Collector Outputs Using Pull-Up Choke Inductors The AD8342 is optimized for driving a 100 load. Although the device is capable of driving a wide variety of loads, to maintain optimum distortion and noise performance, it is advised that the presented load at the IF outputs is close to 100 . The linear differential voltage conversion gain of the mixer can be modeled as Av = Gm x RLOAD where: Gm = 1 1 + g m Re gm RLOAD is the single-ended load impedance. gm is the transistor transconductance and is equal to 1810/RBIAS. Re is 15 . The external RBIAS resistor is used to control the power dissipation and dynamic range of the AD8342. Because the AD8342 has internal resistive degeneration, the conversion gain is primarily determined by the load impedance and the on-chip degeneration resistors. Figure 49 shows how gain varies with IF load. The external RBIAS resistor has only a small effect. The most direct way to affect conversion gain is by varying the load impedance. Small loads result in lower gains while larger loads increase the conversion gain. If the IF load impedance is too large it causes a decrease in linearity (P1dB, IP3). In order to maintain positive conversion gain and preserve SFDR performance, the differential load presented at the IF port should remain in the range of ~ 100 to 250 . FOR RS = RL C1 = 05352-050 1.864 2fcRL L2 = 1.28RL 2fc C3 = 1.834 2fcRL fC - FILTER CUTOFF FREQUENCY Figure 50. Using a Low-Pass Filter to Reduce LO Second Harmonic Rev. 0 | Page 17 of 20 AD8342 HIGH IF APPLICATIONS In some applications it may be desirable to use the AD8342 as an up-converting mixer. The AD8342 is a broadband mixer capable of both up and down conversion. Unlike other mixers that rely on on-chip reactive circuitry to optimize performance over a specific band, the AD8342 is a versatile general-purpose device that can be used from arbitrarily low frequencies to several GHz. In general, the following considerations help to ensure optimum performance: production concerns due to the sensitivity of the match. For this application, it is advantageous to shunt down the ~1 k input impedance using an external shunt termination resistor to allow for a lower Q reactive matching network. The input is terminated across the RFIN and RFCM pins using a 499 termination. The termination should be as close to the device as possible to minimize standing wave concerns. The RFCM is bypassed to ground using a 1 nF capacitor. A dc blocking capacitor of 1 nF is used to isolate the dc input voltage present on the RFIN pin from the source. A step-up impedance transformation is realized using a series L shunt C reactive network. The actual values used need to accommodate for the series L and stray C parasitics of the connecting transmission line segments. When using the customer evaluation board with the components specified in Figure 51, the return loss over a 5 MHz band centered at 170 MHz was better than 10 dB. External pull-up choke inductors are used to feed dc bias into the open-collector outputs. It is desirable to select pull-up choke inductors that present high loading reactance at the output frequency. Coilcraft 0302CS series inductors were selected due to their very high self-resonant frequency and Q. A 1:1 balun was ac-coupled to the output to convert the differential output to a single-ended signal and present the output with a 50 ac loading impedance. The performance of the circuit is shown in Figure 52. The average ACPR of the adjacent and alternate channels is presented vs. output power. The circuit provides a 65 dBc ACPR at -13 dBm output power. The optimum ACPR power level can be shifted to the right or left by adjusting the output loading and the loss of the input match. -60 * * * * Minimize ac loading impedance of IF port bias network. Maximize power transfer to the desired ac load. For maximum conversion gain and the lowest noise performance reactively match the input as described in the IF Port section. For maximum input compression point and input intercept points resistively terminate the input as described in the IF Port section. As an example, Figure 51 shows the AD8342 as an upconverting mixer for a WCDMA single-carrier transmitter design. For this application, it was desirable to achieve -65 dBc adjacent channel power ratio (ACPR) at a -13 dBm output power level. The ACPR is a measure of both distortion and noise carried into an adjacent frequency channel due to the finite intercept points and noise figure of an active device. 100pF VPOS 1.82k 0.1pF 100pF 12 VPDC 13 1nF 14 RFCM 100nH 170MHz INPUT 4.7pF 1nF 499 15 RFIN VPOS 16 VPMX 0.1F 100pF VPLO COMM 11 PWDN 10 EXRB 9 COMM COMM IFOP IFOM COMM 8 7 VPOS 100pF 34nH ETC1-1-13 AD8342 1nF 6 1nF 5 34nH 100pF VPOS 2140MHz OUT LOCM LOIN COMM 1 2 1nF 3 4 -62 ADJACENT CHANNELS 1nF 100pF 05352-052 ACPR (dBc) 1970MHz OSC -64 Figure 51. WCDMA Tx Up-Conversion Application Circuit -66 ALTERNATE CHANNELS -68 05352-053 Because a WCDMA channel encompasses a bandwidth of almost 5 MHz, it is necessary to keep the Q of the matching circuit low enough so that phase and magnitude variations are below an acceptable level over the 5 MHz band. It is possible to use purely reactive matching to transform a 50 source to match the raw ~1 k input impedance of the AD8342. However, the L and C component variations could present -70 -25 -20 -15 -10 -5 0 OUTPUT POWER (dBm) Figure 52. Single Carrier WCDMA ACPR Performance of Tx Up-Conversion Circuit (Test Model 1_64) Rev. 0 | Page 18 of 20 AD8342 EVALUATION BOARD An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a balun transformer. The schematic for the evaluation board is presented in Figure 53. PWDN PWDN R8 10k W1 GND VPOS VPOS C12 0.1F R7 0 C13 100pF 12 11 10 9 C11 100pF R6 1.82k R9 0 VPDC PWDN EXRB COMM 13 Z2 OPEN R10 0 Z1 OPEN R12 OPEN R11 0 Z4 OPEN R15 0 COMM COMM 8 R3 OPEN T1 3 2 1 4 6 L1 0 RF_IN C14 OPEN 50 TRACE R5 100 C1 1000pF 14 IF_OUT+ 100 TRACES, NO GROUND PLANE RFCM DUT RFIN IFOP 7 Z3 OPEN IFOM 6 C3 1000pF 15 TC2-1T R4 OPEN IF_OUT- R1 VPOS C2 0.1F 16 0 VPMX COMM 5 C4 1000pF VPLO LOCM LOIN COMM 1 2 3 4 R16 0 R2 C5 0.1F 0 C6 1000pF C7 1000pF C8 1000pF INLO VPOS C10 100pF C9 0.1F 05352-003 Figure 53. Evaluation Board Table 6. Evaluation Board Configuration Options Component R1, R2, R7, C2, C4, C5, C6, C10 C12, C13, C14, C9 R3, R4 R15, 16 R6, C11 R8 R9 C3, R5, C16, L1 Function Supply decoupling. Shorts or power supply decoupling resistors and filter capacitors. Default Conditions R1, R2, R7 = 0 C4, C6 = 1000 pF C10, C13 = 100 pF C2, C5, C12, C9 = 0.1 F R3, R4 = Open R15, R16 = 0 R6 = 1.82 k C11 = 100 pF R8 = 10 k R9 = 0 C3 = 1000 pF R5 = 100 C14 = Open L1 = 0 C1 = 1000 pF C7, C8 = 1000 pF Options for single-ended IF output circuit. RBIAS resistor that sets the bias current for the mixer core. The capacitor provides ac bypass for R6. Pull down for the PWDN pin. Link to PWDN pin. RF input. C3 provides dc block for RF input. R5 provides a resistive input termination. C16 and L1 are provided for reactive matching the input. C1 C8 C7 W1 T1, R12, R11, Z3, Z4, Z1, Z2, R10 RF common ac coupling. Provides dc block for RF input common connection. LO input ac coupling. Provides dc block for the LO input. LO common ac coupling. Provides dc block for LO input common connection. Power down. The part is on when the PWDN is connected to ground via a 10 k resistor. The part is disabled when PWDN is connected to the positive supply (VS) via W1. IF output interface. T1 converts a differential high impedance IF output to single-ended. When loaded with 50 , this balun presents a 100 load to the mixers collectors. The center tap of the primary is used to supply the bias voltage (VS) to the IF output pins. T1 = TC2-1T, 2:1 (Mini-Circuits) R12 = Open R10, R11 = 0 Z3, Z4 = Open Z1, Z2 = Open Rev. 0 | Page 19 of 20 AD8342 OUTLINE DIMENSIONS 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.50 0.40 0.30 Preliminary Technical Data 0.60 MAX PIN 1 INDICATOR *1.65 1.50 SQ 1.35 13 12 16 1 EXPOSED PAD 9 (BOTTOM VIEW) 4 8 5 0.25 MIN *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions in millimeters ORDERING GUIDE Models AD8342ACPZ-REEL71 AD8342ACPZ-R21 AD8342ACPZ-WP1 AD8342-EVAL Temperature Package -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Outline CP-16-3 CP-16-3 CP-16-3 Branding Q01 Q01 Q01 Transport Media, Quanity 1,500, Reel 250, Reel 50, Waffle Pack 1 1 Z = Pb-free part. (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05352-0-4/05(0) Rev. 0 | Page 20 of 20 |
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