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| oH V SC AV ER OM AI SIO PL LA N IA BL S NT E Features For use with Texas Instruments' Designed to meet UL1950 and EN60950 5SM53 *R 1 TNET D 4000 C/P chipset Excellent Total Harmonic Distortion (THD) Performance SMT and small size package Designed to meet IEC1950 Operating temperature -40 C to +85 C supplementary insulation requirements for operating voltages up to 250 Vrms Lead free version available (see How to Order) Lead free versions are RoHS compliant* Applications ADSL - TI TNET D4000 C/P SM535-1 ADSL Line Transformers Electrical Specifications @ 25 C Turns Ratio (10-7):(1-4) chip to line......1:1.95 2 % OCL @ 10 kHz, 0.1V (1-4) ..............................1.5 mH 10 % Leakage Inductance @ 10 kHz 0.1 V (1-4) with (10-7) shorted..12.0 H max. Interwinding Capacitance @ 10 kHz, 0.1 V (1-10) ........35 pF max. Isolation Voltage ............1500 Vrms max. DC Resistance ........................2.0 max. Application ..........................................CO Packaging Specifications Tape & Reel* ........................200 pcs./reel *"E" suffix at end of part number designates tape & reel packaging, e.g. SM535-1E. Product Dimensions .711 .050 10 PLCS. (.028 .002) 5 4 13.46 MAX. (.530) 3 2 1 17.65 MAX. (.695) 13.50 MAX. (.531) 6 7 10.00 2.50 (.394) (.098) MAX. Electrical Schematic Chip 10 7 1 : 1.95 Line 1 4 SM535-1 (DATECODE) 8 9 10 How to Order SM535-1E __ Model Termination Blank = Tin-lead L = Tin only (lead free) 12.32 MAX. (.485) 12.07 MAX. (.475) 2.50 (.098) 2.54 (.100) 0.13 (.005) 10 SURFACES 10.00 (.394) 1.30 .050 (.051 .002) 10 PLCS. 15.37 (.605) Recommended PAD layout DIMENSIONS ARE: MM (INCHES) TOLERANCE: 0.25 (.010) 03/05 *RoHS Directive 2002/95/EC Jan 27 2003 including Annex Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. |
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