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CS4954 CS4955 NTSC/PAL Digital Video Encoder
Features Description
The CS4954/5 provides full conversion from digital video Six DACs providing simultaneous composite,S-video, and RGB or Component formats YCbCr or YUV to NTSC and PAL Composite, Y/C (S-video) and RGB, or YUV analog video. Input forYUV outputs mats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU Programmable DAC output currents for low R.BT656 with support for EAV/SAV codes. Video output impedance (37.5 ) and high impedance can be formatted to be compatible with NTSC-M, NTSC(150 ) loads J, PAL-B,D,G,H,I,M,N, and Combination N systems. Closed Caption is supported in NTSC. Teletext is supMulti-standard support for NTSC-M, NTSCported for NTSC and PAL. JAPAN, PAL (B, D, G, H, I, M, N, Combination N) Six 10-bit DACs provide two channels for an S-Video output port, one or two composite video outputs, and ITU R.BT656 input mode supporting EAV/SAV codes and CCIR601 Master/Slave three RGB or YUV outputs. Two-times oversampling reduces the output filter requirements and guarantees no input modes DAC-related modulation components within the speciProgrammable HSYNC and VSYNC timing fied bandwidth of any of the supported video standards. Multistandard Teletext (Europe, NABTS, Parallel or high-speed IC compatible control interfaces are WST) support provided for flexibility in system design. The parallel interface VBI encoding support doubles as a general purpose I/O port when the CS4954/5 is Wide-Screen Signaling (WSS) support, EIA-J in IC mode to help conserve valuable board area. CPX1204 The CS4954 and CS4955 are available in a 48-pin TQFP NTSC closed caption encoder with interrupt and operate in -40 to +85C ambient temperature. The CDB4954/55 Customer Demonstration board is also CS4955 supports Macrovision copy available. Please refer to "Ordering Information" on protection Version 7 page 2. Host interface configurable VAA for parallel or IC(R) compatible CLK Output LPF 10-Bit SCL operation IC Interface C Interpolate DAC SDA On-chip voltage reference 8 Control 10-Bit Chroma Amplifier PDAT[7:0] CVBS Registers DAC Host generator RD Parallel Chroma Modulate WR 10-Bit Interface +3.3 V or +5 V operation, Y DAC PADR Burst Insert CMOS, low-power modes, XTAL_IN 10-Bit Color Sub-carrier Synthesizer R XTAL_OUT DAC three-state DACs Chroma Interpolate
TTXDAT TTXRQ 8 VD[7:0] HSYNC VSYNC FIELD INT RESET Video Formatter Video Timing Generator RGB DGND Teletext Encoder YCbCr to RBG Color Space Converter U,V LPF 10-Bit DAC 10-Bit DAC Y Luma Interpolate Voltage Reference Y RGB TEST Current Reference VREF ISET G B
Luma Amplifier Y Sync Insert
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved) www.cirrus.com
SEPTEMBER '06 DS278F6 1
CS4954 CS4955
ORDERING INFORMATION Product CS4954 CS4955 CDB4954/55 Description NTSC/PAL Digital Video Encoder Package Pb-Free 48-TQFP Yes No Grade Temp Range Container Rail Order# CS4954-CQZ CS4955-CQZ CDB4954A/55A
Commercial -40 to +85C -
CS4954/55 Evaluation Board
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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................................6 AC & DC PARAMETRIC SPECIFICATIONS ............................................................................................6 RECOMMENDED Operating Conditions .......................................................................................................6 THERMAL CHARACTERISTICS ..............................................................................................................6 DC CHARACTERISTICS ..........................................................................................................................6 AC CHARACTERISTICS ..........................................................................................................................8 TIMING CHARACTERISTICS ...................................................................................................................9 ADDITIONAL CS4954/5 FEATURES .....................................................................................................11 CS4954 INTRODUCTION ......................................................................................................................11 FUNCTIONAL DESCRIPTION ...............................................................................................................11 4.1 Video Timing Generator ...............................................................................................................11 4.2 Video Input Formatter ..................................................................................................................12 4.3 Color Subcarrier Synthesizer .......................................................................................................12 4.4 Chroma Path ................................................................................................................................12 4.5 Luma Path ....................................................................................................................................13 4.6 RGB Path and Component YUV Path ..........................................................................................13 4.7 Digital to Analog Converters ........................................................................................................13 4.8 Voltage Reference .......................................................................................................................14 4.9 Current Reference ........................................................................................................................14 4.10 Host Interface ...............................................................................................................................14 4.11 Closed Caption Services ..............................................................................................................14 4.12 Teletext Services ..........................................................................................................................15 4.13 Wide-Screen Signaling Support and CGMS ................................................................................15 4.14 VBI Encoding ...............................................................................................................................15 4.15 Control Registers .........................................................................................................................15 4.16 Testability .....................................................................................................................................15 OPERATIONAL DESCRIPTION ............................................................................................................15 5.1 Reset Hierarchy ...........................................................................................................................15 5.2 Video Timing ................................................................................................................................16 5.2.1 Slave Mode Input Interface ...............................................................................................16 5.2.2 Master Mode Input Interface .............................................................................................16 5.2.3 Vertical Timing ...................................................................................................................17 5.2.4 Horizontal Timing ..............................................................................................................17 5.2.5 NTSC Interlaced ................................................................................................................17 5.2.6 PAL Interlaced ...................................................................................................................17 5.2.7 Progressive Scan ..............................................................................................................18 5.2.8 NTSC Progressive Scan ...................................................................................................18 5.2.9 PAL Progressive Scan ......................................................................................................19 5.3 ITU-R.BT656 ................................................................................................................................19 5.4 Digital Video Input Modes ............................................................................................................21 5.5 Multi-standard Output Format Modes ..........................................................................................21 5.6 Subcarrier Generation ..................................................................................................................22 5.7 Subcarrier Compensation ............................................................................................................23 5.8 Closed Caption Insertion ..............................................................................................................23 5.9 Programmable H-sync and V-sync ..............................................................................................24 5.10 Wide Screen Signaling (WSS) and CGMS ..................................................................................24 5.11 Teletext Support ...........................................................................................................................24 5.12 Color Bar Generator .....................................................................................................................26 5.13 VBI encoding ................................................................................................................................27 5.14 Super White/Super Black support ................................................................................................27 5.15 Interrupts ......................................................................................................................................27 5.16 General Purpose I/O Port .............................................................................................................27 FILTER RESPONSES ............................................................................................................................29 ANALOG ................................................................................................................................................32 7.1 Analog Timing ..............................................................................................................................32 7.2 VREF ............................................................................................................................................32 7.3 ISET .............................................................................................................................................32 7.4 DACs ............................................................................................................................................32 7.4.1 Luminance DAC ................................................................................................................32 7.4.2 Chrominance DAC ............................................................................................................33 7.4.3 CVBS DAC ........................................................................................................................33 7.4.4 Red DAC ...........................................................................................................................33
2. 3. 4.
5.
6. 7.
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7.4.5 Green DAC ....................................................................................................................... 33 7.4.6 Blue DAC .......................................................................................................................... 33 7.4.7 DAC Useage Rules ........................................................................................................... 34 8. PROGRAMMING ................................................................................................................................... 34 8.1 Host Control Interface .................................................................................................................. 34 8.1.1 IC(R) Interface ................................................................................................................... 34 8.1.2 8-bit Parallel Interface ....................................................................................................... 35 8.2 Register Description .................................................................................................................... 36 8.2.1 Control Registers .............................................................................................................. 36 9. BOARD DESIGN AND LAYOUT CONSIDERATIONS ......................................................................... 53 9.1 Power and Ground Planes .......................................................................................................... 53 9.2 Power Supply Decoupling ........................................................................................................... 53 9.3 Digital Interconnect ...................................................................................................................... 53 9.4 Analog Interconnect ..................................................................................................................... 53 9.5 Analog Output Protection ............................................................................................................ 54 9.6 ESD Protection ............................................................................................................................ 54 9.7 External DAC Output Filter .......................................................................................................... 54 10. PIN DESCRIPTION ............................................................................................................................... 56 11. PACKAGE DRAWING ........................................................................................................................... 58 12. REVISION HISTORY ............................................................................................................................. 59
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LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Video Pixel Data and Control Port Timing ..................................................................8 IC Host Port Timing ...................................................................................................9 Reset Timing.............................................................................................................10 ITU R.BT601 Input Slave Mode Horizontal Timing ...................................................16 ITU R.BT601 Input Master Mode Horizontal Timing.................................................16 Vertical Timing ..........................................................................................................18 NTSC Video Interlaced Timing .................................................................................19 PAL Video Interlaced Timing ....................................................................................20 NTSC Video Non-Interlaced Progressive Scan Timing ............................................21 PAL Video Non-Interlaced Progressive Scan Timing .............................................22 CCIR656 Input Mode Timing ..................................................................................22 Teletext Timing (Pulsation Mode) ...........................................................................25 Teletext Timing (Window Mode) .............................................................................25 1.3 MHz Chrominance low-pass filter transfer characteristic..................................29 1.3 MHz Chrominance low-pass filter transfer characterstic (passband) ...............29 650 kHz Chrominance low-pass filter transfer characteristic ..................................29 650 kHz Chrominance low-pass filter transfer characteristic (passband) ...............29 Chrominance output interpolation filter transfer characteristic (passband).............30 Luminance interpolation filter transfer characteristic ..............................................30 Luminance interpolation filter transfer characterstic (passband) ............................30 Chrominance interpolation filter transfer characteristic for RGB datapath..............30 Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) ....31 Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) ....31 Chroma Interpolator for RGB Datapath when rgb_bw=0 -3 dB ..............................31 Chroma Interpolator for RGB Datapath when rgb_bw=0 (Full Scale).....................31 IC Protocol.............................................................................................................35 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle...............................35 8-bit Parallel Host Port Timing: Address Read Cycle .............................................36 8-bit Parallel Host Port Timing: Address Write Cycle .............................................36 External Low Pass Filter .........................................................................................54 Typical Connection Diagram...................................................................................55
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1. CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
AC & DC PARAMETRIC SPECIFICATIONS (AGND,DGND = 0 V, all voltages with respect to 0 V)
Parameter Power Supply Input Current Per Pin (Except Supply Pins) Output Current Per Pin (Except Supply Pins) Analog Input Voltage Digital Input Voltage Ambient Temperature Power Applied Storage Temperature Symbol VAA/VDD Min -0.3 -10 -50 -0.3 -0.3 -55 -65 Max 6.0 10 +50 VAA + 0.3 VDD + 0.3 + 125 + 150 Units V mA mA V V C C
WARNING: Operating beyond these limits can result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED Operating Conditions (AGND,DGND = 0 V, all voltages with respect to 0 V.)
Parameter Power Supplies: Digital Analog Operating Ambient Temperature Note: Operation outside the ranges is not recommended. Symbol VAA/VDD TA Min 3.15 4.75 -40 Typ 3.3 5.0 +25 Max 3.45 5.25 +85 Units V C
THERMAL CHARACTERISTICS
Parameters Allowable Junction Temperature Junction to Ambient Thermal Impedance (Four-layer PCB) TQFP (Two-layer PCB) TQFP Note: Symbol Min Typ 45 65 Max 150 Units C C/W
JA-TM JA-TS
Four-layer PCB recommended for operation in environments where TA > 70 C.
DC CHARACTERISTICS (TA = 25 C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.)
Parameter Digital Inputs High level Input Voltage V [7:0], PDAT [7:0], Hsync/Vsync/CLKIN High Level Input Voltage IC Low level Input Voltage All Inputs Input Leakage Current Digital Outputs High Level Output Voltage lo = -4 mA Low level Output Voltage lo = 4 mA VOH VOL 2.4 VDD 0.4 V V VIH VIH 2.2 0.7 VDD -0.3 -10 VDD+0.3 0.8 +10 V V V A Symbol Min Typ Max Units
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Parameter Low Level Output Voltage SDA pin only, lo = 6mA Output Leakage Current High-Z Digital Outputs Analog Outputs Full Scale Output Current CVBS/Y/C/R/G/B Full Scale Output Current CVBS/Y/C/R/G/B LSB Current CVBS/Y/C/R/G/B LSB Current CVBS/Y/C/R/G/B DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance DAC Output Delay DAC Rise/Fall Time Voltage Reference Reference Voltage Output Reference Input Current Power Supply Supply Voltage Digital Supply Current Analog Supply Analog Supply Power Supply Rejection Ratio Static Performance DAC Resolution Differential Non-Linearity Integral Non-Linearity Dynamic Performance Differential Gain Differential Phase Hue Accuracy Signal to Noise Ratio Saturation Accuracy Notes: 1. Values are by characterization only 2. Output current levels with ISET = 4 k , VREF = 1.232 V. 3. DACs are set to low impedance mode 4. DACs are set to high impedance mode 5. Times for black-to-white-level and white-to-black-level transitions. 6. Low-Z, 3 DACs on 7. High-Z, 6 DACs on (Note 1) (Note 1) (Note 1) (Note 1) DG DP HA SNR SAT 70 2 + 0. 5 1 5 +2 2 2 % dB % (Note 1) (Note 1) (Note 1) DNL INL -1 -2 + 0.5 +1 10 +1 +2 Bits LSB LSB Low-Z High-Z (Note 6) (Note 7) VAA, VDD IAA1 IAA2 IAA3 PSRR 3.15 4.75 3.3 5.0 70 100 60 0.02 3.45 5.25 150 150 100 0.05 V mA mA mA V/V (Note 1) VOV UVC 1.170 1.232 1.294 10 V A (Notes 1, 2, 3) (Notes 1, 2, 4) (Notes 1, 2, 3) (Notes 1, 2, 4) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1, 5) IO IO IB IB MAT VOC ROUT COUT ODEL TRF 32.9 8.22 32.2 8.04 0 34.7 8.68 33.9 8.48 2 15 4 2.5 36.5 9.13 35.7 8.92 4 + 1.4 30 12 5 mA mA A A % V k pF ns ns Symbol VOL Min -10 Typ Max 0.4 +10 Units V A
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AC CHARACTERISTICS
Parameter Pixel Input and Control Port (Figure 1) Clock Pulse High Time Clock Pulse Low Time Clock to Data Set-up Time Clock to Data Hold Time Clock to Data Output Delay Tch Tcl Tisu Tih Toa 14.82 14.82 6 0 18.52 18.52 22.58 22.58 17 ns ns ns ns ns Symbol Min Typ Max Units
CLK Tisu Tch V[7:0] Tcl
Tih HSYNC/VSYNC (Inputs) Toa HSYNC/VSYNC CB/FIELD(1)/INT (Outputs)
Figure 1. Video Pixel Data and Control Port Timing
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TIMING CHARACTERISTICS
Parameter IC Host Port Timing (Figure 2) SCL Frequency Clock Pulse High Time Clock Pulse Low Time Hold Time (Start Cond.) Setup Time (Start Cond.) Data Setup Time Rise Time Fall Time Setup Time (Stop Cond.) Bus Free Time Data Hold Time SCL Low to Data Out Valid Fclk Tsph Tspl Tsh Tssu Tsds Tsr Tsf Tss Tbuf Tdh Tvdo 100 100 0 600 0.1 0.7 100 100 50 1 0.3 1000 kHz s s ns ns ns s s ns ns ns ns Symbol Min Typ Max Units
Tsh Tbu Tdh
Tds Tsh Tss
SDA Tsr SCL Tsph Tvdo
Tspi
Tsi
Tssu
Figure 2. IC Host Port Timing
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TIMING CHARACTERISTICS(Continued)
Parallel Host Port Timing (Figure 27, 28, 29) Read Cycle Time Read Pulse Width Address Setup Time Read Address Hold Time Read Data Access Time Read Data Hold Time Write Recovery Time Write Pulse Width Write Data Setup Time Write Data Hold Time Write-Read/Read-Write Recovery Time Address from Write Hold Time Reset Timing (Figure 3) Reset Pulse Width Tres 100 ns Symbol Trd Trpw Tas Trah Trda Trdh Twr Twpw Twds Twdh Trec Twac Min 60 30 3 10 10 60 40 8 3 50 0 Typ Max 40 50 Units ns ns ns ns ns ns ns ns ns ns ns ns
RESET*
Tres
Figure 3. Reset Timing
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2.
* * * * * * * * * * * *
ADDITIONAL CS4954/5 FEATURES
Five programmable DAC output combinations, including YUV and second composite Optional pseudo-progressive scan @ MPEG2 field rates Stable color subcarrier for MPEG2 systems General purpose input and output pins Individual DAC power-down capability On-chip color bar generator Supports RS170A and ITU R.BT601 composite output timing HSYNC and VSYNC output in ITU R.BT656 mode Teletext encoding selectable on two composite and S-video signals Programmable saturation, SCH Phase, hue, brightness and contrast Device power-down capability Super White and Super Black support
The CS4954/5 is completely configured and controlled via an 8-bit host interface port or an IC compatible serial interface. This host port provides access and control of all CS4954/5 options and features, such as closed caption insertion, interrupts, etc. In order to lower overall system costs, the CS4954/5 provides an internal voltage reference that eliminates the requirement for an external, discrete, three-pin voltage reference. In ISO MPEG-2 system configurations, the CS4954/5 can be augmented with a common colorburst crystal to provide a stable color subcarrier given an unstable 27 MHz clock input. The use of the crystal is optional, but the facility to connect one is provided for MPEG-2 environments in which the system clock frequency variability is too wide for accurate color sub-carrier generation.
4.
FUNCTIONAL DESCRIPTION
3.
CS4954 INTRODUCTION
In the following subsections, the functions of the CS4954/5 will be described. The descriptions refer to the device elements shown in the block diagram on the cover page.
The CS4954/5 is a complete multi-standard digital video encoder implemented in current CMOS technology. The device can operate at 5 V as well as at 3.3 V. ITU R.BT601- or ITU R.BT656-compliant digital video input is converted into NTSC-M, NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I, PAL-M, PAL-N, or PAL-N Argentina-compatible analog video. The CS4954/5 is designed to connect, without glue logic, to MPEG1 and MPEG2 digital video decoders. Two 10-bit DAC outputs provide high quality SVideo analog output while another 10-bit DAC simultaneously generates composite analog video. In addition, there are three more DACs to provide simultaneous analog RGB or analog YUV outputs. The CS4954/5 will accept 8-bit YCbCr or 8-bit YUV input data.
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4.1
Video Timing Generator
All timing generation is accomplished via a 27 MHz input applied to the CLK pin. The CS4954/5 can also accept a signal from an optional color burst crystal on the XTAL_IN & XTAL_OUT pins. See the section, Color Subcarrier Synthesizer, for further details. The Video Timing Generator is responsible for orchestrating most of the other modules in the device. It operates in harmony with external sync input timing, or it can provide external sync timing outputs. It automatically disables color burst on appropriate scan lines and automatically generates serration and equalization pulses on appropriate scan lines.
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The CS4954/5 is designed to function as a video timing master or video timing slave. In both Master and Slave Modes, all timing is sampled and asserted with the rising edge of the CLK pin. In most cases, the CS4954/5 will serve as the video timing master. HSYNC, VSYNC, and FIELD(1) are configured as outputs in Master Mode. HSYNC or FIELD can also be defined as a composite blanking output signal in Master Mode. In Master Mode, the timing of HSYNC, VSYNC, FIELD and Composite Blank (CB) signals is programmable. Exact horizontal and vertical display timing is addressed in the Operational Description section. In Slave Mode, HSYNC and VSYNC are typically configured as input pins and are used to initialize independent vertical and horizontal timing generators upon their respective falling edges. HSYNC and VSYNC timing must conform to the ITUR BT.601 specifications. The CS4954/5 also provides a ITU R.BT656 Slave Mode in which the video input stream contains EAV and SAV codes. In this case, proper HSYNC and VSYNC timing is extracted automatically without any inputs other than the V [7:0]. ITU R.BT656 input data that is sampled with the leading edge of CLK. In addition, it is also possible to output HSYNC and VSYNC signals when in ITU R.BT656 Slave Mode. generates the color burst frequency based on the CLK input (27 MHz). Color burst accuracy and stability are limited by the accuracy of the 27 MHz input. If the frequency varies, then the color burst frequency will also vary accordingly. For environments in which the CLK input varies or jitters unacceptably, a local crystal frequency reference can be used on the XTAL_IN and XTAL_OUT pins. In this instance, the input CLK is continuously compared with the external crystal reference input and the internal timing of the CS4954/5 is automatically adjusted so that the color burst frequency remains within tolerance. Controls are provided for phase adjustment of the burst to permit color adjustment and phase compensation. Chroma hue control is provided by the CS4954/5 via a 10-bit Hue Control Register (HUE_LSB and H_MSB). Burst amplitude control is also made available to the host via the 8-bit burst amplitude register (SC_AMP).
4.4
Chroma Path
The Video Input Formatter delivers 4:2:2 YUV outputs to separate chroma and luma data paths. The chroma output of the Video Input Formatter is directed to a chroma low-pass 19-tap FIR filter. The filter bandwidth is selected (or the filter can be bypassed) via the CONTROL_1 Register. The passband of the filter is either 650 kHz or 1.3 MHz and the passband ripple is less than or equal to 0.05 dB. The stopband for the 1.3 MHz selection begins at 3 MHz with an attenuation of greater than 35 dB. The stopband for the 650 kHz selection begins around 1.1 MHz with an attenuation of greater than 20 dB. The output of the chroma low-pass filter is connected to the chroma interpolation filter in which upsampling from 4:2:2 to 4:4:4 is accomplished. Following the interpolation filter, the U and V chroma signals pass through two independent vari-
4.2
Video Input Formatter
The Video Input Formatter translates YCbCr input data into YUV information, when necessary, and splits the luma and chroma information for filtering, scaling, and modulation.
4.3
Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequency synthesizer that produces the appropriate subcarrier frequency for NTSC or PAL. The CS4954/5
NOTE 1. The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not toggle in SLAVE mode and its output state should be considered random. 12 DS278F6
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able gain amplifiers in which the chroma amplitude can be varied via the U_AMP and V_AMP 8-bit host addressable registers. The U and V chroma signals are fed to a quadrature modulator in which they are combined with the output from the subcarrier synthesizer to produce the proper modulated chrominance signal. The chroma is then interpolated by a factor of two in order to operate the output DACs at twice the pixel rate. The interpolation filters enable running the DACs at twice the pixel rate which helps reduce the sinx/x roll-off for higher frequencies and reduces the complexity of the external analog low pass filters. 4.5 Luma Path Along with the chroma output path, the CS4954/5 Video Input Formatter has a parallel luma data output to a digital delay line. The delay line is a digital FIFO. The FIFO depth matches the clock period delay associated with the more complex chroma path. Brightness adjustment is also provided via the 8-bit BRIGHTNESS_OFFSET Register. Following the luma delay, the data is passed through an interpolation filter that has a programmable bandwidth, followed by a variable gain amplifier. The amplifier DC luma gain can be changed using the the Y_AMP Register. The output of the luma amplifier connects to the sync insertion block. Sync insertion is accomplished by multiplexing, into the luma data path, the different sync DC values at the appropriate times. The digital sync generator takes horizontal sync and vertical sync timing signals and generates the appropriate composite sync timing (including vertical equalization and serration pulses), blanking information, and burst flag. The sync edge rates conform to RS-170A or ITU R.BT601 and ITU R.BT470 specifications. It is also possible to delay the luminance signal, with respect to the chrominance signal, by up to
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three pixel clocks. This variable delay is useful to offset different propagation delays of the luma baseband and modulated chroma signals. This adjustable luma delay is available only on the CVBS_1 output.
4.6
RGB Path and Component YUV Path
The RGB datapath has the same latency as the luma and chroma path. Therefore all six simultaneous analog outputs are synchronized. The 4:2:2 YCbCr data is first interpolated to 4:4:4 and then interpolated to 27 MHz. The color space conversion is performed at 27 MHz. The coefficients for the color space conversion conform to the ITU R.BT601 specifications. After color space conversion, the amplitude of each component can be independently adjusted via the R_AMP, G_AMP, and B_AMP 8-bit host addressable registers. A synchronization signal can be added to either one, two or all of the RGB signals. The synchronization signal conforms to NTSC or PAL specifications. Some applications (e.g., projection TVs) require analog component YUV signals. The chip provides a programmable mode that outputs component YUV data. Sync can be added to the luminance signal. Independent gain adjustment of the three components is provided as well.
4.7
Digital to Analog Converters
The CS4954/5 provides six discrete 27 MHz DACs for analog video. The default configuration is one 10-bit DAC for S-video chrominance, one 10-bit DAC for S-Video luminance, one 10-bit DAC for composite output, and three 10-bit DACs for RGB outputs. All six DACs are designed for driving either low-impedance loads (double terminated 75 ) or high-impedance loads (double terminated 300 ). There are five different DAC configurations to choose from (see Table 1, below). The DACs can be put into high-impedance mode via host-addressable control register bits. Each of
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DAC Y C CVBS R G B Pin # 48 47 44 39 40 43 Mode 1 Y C CVBS_1 R G B Mode 2 Y C CVBS_1 Cr (V) Y Cb (U) Mode 3 Y C CVBS_1 CVBS_2 Mode 4 CVBS_2 CVBS_1 R G B Mode 5 CVBS_2 CVBS_1 Cr (V) Y Cb (U)
Table 1. DAC configuration Modes
the six DACs has its own associated DAC enable bit. In the Disable Mode, the 10-bit DACs source (or sink) zero current. When running the DACs with a low-impedance load, a minimum of three DACs must be powered down. When running the DACs with a high-impedance load, all the DACs can be enabled simultaneously. For lower power standby scenarios, the CS4954/5 also provides power shut-off control for the DACs. Each DAC has an associated DAC shut-off bit.
current modes are software selectable via a register bit.
4.10
Host Interface
4.8
Voltage Reference
The CS4954/5 is equipped with an on-board voltage reference generator (1.232 V) that is used by the DACs. The internal reference voltage is accurate enough to guarantee a maximum of 3% overall gain error on the analog outputs. However, it is possible to override the internal reference voltage by applying an external voltage source to the VREF pin.
The CS4954/5 provides a parallel 8-bit data interface for overall configuration and control. The host interface uses active-low read and write strobes, along with an active-low address enable signal, to provide microprocessor-compatible read and write cycles. Indirect host addressing to the CS4954/5 internal registers is accomplished via an internal address register that is uniquely accessible via bus write cycles for the device when the host address enable signal is asserted. The CS4954/5 also provides an IC-compatible serial interface for device configuration and control. This port can operate in standard (up to 100 kb/sec) or fast (up to 400 kb/sec) modes. When in IC mode, the parallel data interface pins, PDAT [7:0], can be used as a general purpose I/O port controlled by the IC interface.
4.9
Current Reference
4.11
Closed Caption Services
The DAC output current-per-bit is derived in the current reference block. The current step is specified by the size of resistor placed between the ISET current reference pin and electrical ground. A 4 k resistor needs to be connected between ISET pin and GNDA. The DAC output currents are optimized to drive either a doubly terminated 75 W load (low impedence mode) or a double terminated 300 load (high impedence mode). The 2 output
The CS4954/5 supports the generation of NTSC Closed Caption services. Line 21 and Line 284 captioning can be generated and enabled independently via a set of control registers. When enabled, clock run-in, start bit, and data bytes are automatically inserted at the appropriate video lines. A convenient interrupt protocol simplifies the software interface between the host processor and the CS4954/5.
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4.12 Teletext Services
See the Programming section of this data sheet for the individual register bit allocations, bit operational descriptions, and initialization states.
The CS4954/5 encodes the most common teletext formats, such as European Teletext, World Standard Teletext (PAL and NTSC), and North American Teletext (NABTS). Teletext data can be inserted in any of the TV lines (blanking lines as well as active lines). In addition the blanking lines can be individually allocated for Teletext instantiation. The input timing for teletext data is user programmable. See the section Teletext Services for further details. Teletext data can be independently inserted on either one or all of the CVBS_1, CVBS_2, or S-video signals.
4.16
Testability
The digital circuits are completely scanned by an internal scan chain, thus providing close to 100% fault coverage.
5. 5.1
OPERATIONAL DESCRIPTION Reset Hierarchy
4.13
Wide-Screen Signaling Support and CGMS
The CS4954/5 is equipped with an active low asynchronous reset input pin, RESET. RESET is used to initialize the internal registers and the internal state machines for subsequent default operation. See the electrical and timing specification section of this data sheet for specific CS4954/5 device RESET and power-on signal timing requirements and restrictions. While the RESET pin is held low, the host interface in the CS4954/5 is disabled and will not respond to host-initiated bus cycles. All outputs are valid after a time period following RESET pin low. A device RESET initializes the CS4954/5 internal registers to their default values as described by Table 9, Control Registers. In the default state, the CS4954/5 video DACs are disabled and the device is internally configured to provide blue field video data to the DACs (any input data present on the V [7:0] pins is ignored at this time). Otherwise, the CS4954/5 registers are configured for NTSC-M output and ITU R.BT601 output timing operation. At a minimum, the DAC Registers (0x04 and 0x05) must be written (to enable the DACs) and the IN_MODE bit of the CONTROL_0 Register (0x01) must be set (to enable ITU R.BT601 data input on V [7:0]) for the CS4954/5 to become operational after RESET.
Insertion of wide-screen signal encoding for PAL and NTSC standards is supported and CGMS (Copy Generation Management System) for NTSC in Japan. Wide-screen signals are inserted in lines 23 and 336 for PAL, and lines 20 and 283 for NTSC.
4.14
VBI Encoding
This chip supports the transmission of control signals in the vertical blanking time interval according to SMPTE RP 188 recommendations. VBI encoded data can be independently inserted into any or all of CVBS_1, CVBS_2 or S-video signals.
4.15
Control Registers
The control and configuration of the CS4954/5 is accomplished primarily through the control register block. All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during device RESET.
DS278F6
15
CS4954 CS4955
NTSC 27MHz Clock Count PAL 27MHz Clock Count CLK 1682 1683 1684 1685 1686 1702 1703 1704 1705 1706 *** *** 1716 1728 1 1 2 2 3 3 *** *** 128 128 129 129 *** *** 244 264 245 265 246 266 247 267 248 268
HSYNC (input)
V[7:0] (SYNC_DLY=0)
Y ***
Cr
Y horizontal blanking
Cb
Y
Cr
Y
active pixel #720 Y Cr Y
active pixel #1 Cb
active pixel #2 Y Cr active pixel #2
V[7:0] (SYNC_DLY=1)
Cb
active pixel #719
active pixel #720
horizontal blanking
active pixel #1
Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing
5.2
Video Timing
5.2.1 Slave Mode Input Interface
In Slave ITU R.BT601 (not ITU-R.BT656 input) Mode, the CS4954/5 receives signals on VSYNC and HSYNC as inputs. Slave Mode is the default following RESET and is changed to Master Mode via a control register bit (CONTROL_0 [4]). The CS4954/5 is limited to ITU R.BT601 horizontal and vertical input timing. All clocking in the CS4954/5 is generated from the CLK pin. In Slave Mode, the Sync Generator uses externally provided horizontal and vertical sync signals to synchronize the internal timing of the CS4954/5. Video data that is sent to the CS4954/5 must be synchronized to the horizontal and vertical sync signals. Figure 4 illustrates horizontal timing for ITU R.BT601 input in Slave Mode. Note that the CS4954/5 expects to receive the first active pixel data on clock cycle 245
NTSC 27MHz Clock Count PAL 27MHz Clock Count CLK 1682 1683 1684 1685 1686 1702 1703 1704 1705 1706 *** *** 1716 1728 1 1
(NTSC) when CONTROL_2 Register (0x02) bit SYNC_DLY = 0. When SYNC_DLY = 1, it expects the first active pixel data on clock cycle 246 (NTSC).
5.2.2 Master Mode Input Interface
The CS4954/5 defaults to Slave Mode following RESET high but can be switched into Master Mode via the MSTR bit in the CONTROL_0 Register (0x00). In Master Mode, the CS4954/5 uses the VSYNC, HSYNC and FIELD device pins as outputs to schedule the proper external delivery of digital video into the V [7:0] pins. Figure 5 illustrates horizontal timing for the CCIR601 input in Master Mode. The timing of the HSYNC output is selectable in the PROG_HS Registers (0x0D, 0x0E). HSYNC can be delayed by one full line cycle. The timing of the VSYNC output is also selectable in the
2 2
3 3
*** ***
128 128
129 129
*** ***
244 264
245 265
246 266
247 267
248 268
HSYNC (output)
CB (output)
V[7:0]
Y ***
Cr
Y
horizontal blanking
Cb
Y
Cr
Y
active pixel #720
active pixel #1
active pixel #2
Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing 16 DS278F6
CS4954 CS4955
PROG_VS Register (0x0D). VSYNC can be delayed by thirteen lines or advanced by eighteen lines. (falling) edge of HSYNC if the PROG_HS Registers are set to default values.
5.2.3 Vertical Timing
The CS4954/5 can be configured to operate in any of four different timing modes: PAL, which is 625 vertical lines, 25 frames per second interlaced; NTSC, which is 525 vertical lines, 30 frames per second interlaced; and either 625 or 525 line Pseudo-Progressive Scan (See "Progressive Scan" on page 18). These modes are selected in the CONTROL_0 Register (0x00). The CS4954/5 conforms to standard digital decompression dimensions and does not process digital input data for the active analog video half lines as they are typically in the over/underscan region of TV display. 240 active lines total per field are processed for NTSC, and 288 active lines total per field are processed for PAL. Frame vertical dimensions are 480 lines for NTSC and 576 lines for PAL. Table 2 specifies active line numbers for both NTSC and PAL. Refer to Figure 6 for HSYNC, VSYNC and FIELD signal timing.
NTSC Field Active Lines 1, 3; 22-261; 2, 4 285-524 PAL 1, 3, 5, 7; 23-310; 2, 4, 6, 8 336-623 NTSC Progressive-Scan NA 22-261 PAL Progressive-Scan NA 23-310 Table 2. Vertical Timing Mode
5.2.5 NTSC Interlaced
The CS4954/5 supports NTSC-M, NTSC-J and PAL-M modes where there are 525 total lines per frame, two fixed 262.5-line fields per frame and 30 frames occurring per second. NTSC interlaced vertical timing is illustrated in Figure 7. Each field consists of one line for closed caption, 240 active lines of video, plus 21.5 lines of blanking. VSYNC field one transitions low at the beginning of line four and will remain low for three lines or 2574 pixel cycles (858 x 3). The CS4954/5 exclusively reserves line 21 of field one for closed caption insertion. Digital video input is expected to be delivered to the CS4954/5 V [7:0] pins for 240 lines beginning on active video lines 22 and continuing through line 261. VSYNC field two transitions low in the middle of line 266 and stays low for three line-times and transitions high in the middle of line 269. The CS4954/5 exclusively reserves line 284 of field two for closed caption insertion. Video input on the V [7:0] pins is expected between lines 285 through line 525.
5.2.6 PAL Interlaced
The CS4954/5 supports PAL modes B, D, G, H, I, N, and Combination N, in which there are 625 total lines per frame, two fixed 312.5 line fields per frame, and 25 total frames per second. Figure 8 illustrates PAL interlaced vertical timing. Each field consists of 287 active lines of video plus 25.5 lines of blanking. VSYNC will transition low to begin field one and will remain low for 2.5 lines or 2160 pixel cycles (864 x 2.5). Digital video input is expected to be delivered to the CS4954/5 V [7:0] pins for 287 lines beginning on active video line 24 and continuing through line 310. Field two begins with VSYNC transitioning low after 312.5 lines from the beginning of field one.
17
5.2.4 Horizontal Timing
HSYNC is used to synchronize the horizontal-input-to-output timing in order to provide proper horizontal alignment. HSYNC defaults to an input pin following RESET but switches to an output in Master Mode (CONTROL_0 [4] = 1). Horizontal timing is referenced to HSYNC transitioning low. For active video lines, digital video input is to be applied to the V [7:0] inputs for 244 (NTSC) or for 264 (PAL) CLK periods following the leading
DS278F6
CS4954 CS4955
NTSC Vertical Timing (odd field)
Line HSYNC VSYNC
FIELD
3
4
5
6
7
8
9
10
NTSC Vertical Timing (even field)
Line HSYNC
VSYNC
264
265
266
267
268
269
270
271
FIELD
PAL Vertical Timing (odd field) Line
265
1
2
3
4
5
6
7
HSYNC VSYNC FIELD
PAL Vertical Timing (even field)
Line HSYNC VSYNC FIELD
311
312
313
314
315
316
317
318
Figure 6. Vertical Timing
VSYNC stays low for 2.5 line-times and transitions high with the beginning of line 315. Video input on the V [7:0] pins is expected between line 336 through line 622.
5.2.7 Progressive Scan
The CS4954/5 supports a pseudo-progessive scan mode for which "odd" and "even" numbered line information is presented in "odd" numbered line positions by varying the vertical blanking timing. This preserves precise MPEG-2 frame rates of 30 and 25 frames per second. This mode is in contrast to other digital video encoders, which commonly support progressive scan by repetitively displaying
18
a 262 line field (524/525 lines for NTSC). The common method is flawed: over time, the output display rate will overrun a system-clock-locked MPEG-2 decompressor and display a field twice every 8.75 seconds.
5.2.8 NTSC Progressive Scan
VSYNC will transition low at line four to begin field one and will remain low for three lines or 2574 pixel cycles (858 x 3). NTSC interlaced timing is illustrated in Figure 9. In this mode, the CS4954/5 expects digital video input at the V [7:0] pins for 240 lines beginning on active video line 22 and continuing through line 261.
DS278F6
CS4954 CS4955
Analog Field 1
VSYNC Drops
523
524
525
1
2
3
4
5
6
7
8
9
10
22
Analog Field 2
261
262
263
264
265
266
267
268
269
270
271
272
284
285
Analog Field 3
VSYNC Drops
523
524
525
1
2
3
4
5
6
7
8
9
10
22
Analog Field 4
261
262
263
264
265
266
267
268
269
270
271
272
284
285
Burst begins with positive half-cycle
Burst begins with negative half-cycle
Figure 7. NTSC Video Interlaced Timing
Field two begins with VSYNC transitioning low at line 266. VSYNC stays low for 3 line cycles and transitions high during the end of line 268. Video input on the V [7:0] pins is expected between line 284 and line 522. Field two is 263 lines; field one is 262 lines.
335 through line 622. Field two is 313 lines; field one is 312 lines.
5.3
ITU-R.BT656
5.2.9 PAL Progressive Scan
VSYNC will transition low at the beginning of the odd field and will remain low for 2.5 lines or 2160 pixel cycles (864 x 2.5). PAL non-interlaced timing is illustrated in Figure 10. In this mode, the CS4954/5 expects digital video input on the V [7:0] pins for 288 lines, beginning on active video line 23 and continuing through line 309. The second field begins with VSYNC transitioning low after 312 lines from the beginning of the first field. VSYNC stays low for 2.5 line-times and transitions high during the middle of line 315. Video input on the V [7:0] pins is expected between line
The CS4954/5 supports an ITU-R.BT656 slave mode feature that is selectable through the ITUR.BT656 bit of the CONTROL_0 Register. The ITU-R.BT656 slave feature is unique because the horizontal and vertical timing and digital video are combined into a single 8-bit 27 MHz input. With ITU-R.BT656 there are no horizontal and vertical input or output strobes, only 8-bit 27 MHz active CbYCrY data, with start- and end-of-video codes implemented using reserved 00 and FF code sequences within the video feed. As with all modes, V [7:0] are sampled with the rising edge of CLK. The CS4954/5 expects the digital ITU-R.BT656 stream to be error-free. The FIELD(1) output toggles as with non ITU-R.BT656 input. ITUR.BT656 input timing is illustrated in Figure 11.
DS278F6
19
CS4954 CS4955
VSYNC Drops Analog Field 1
620
621
622
623
624
625
1 Analog Field 2
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314 Analog Field 3
315
316
317
318
319
320
336
337
620
621
622
623
624
625
1 Analog Field 4
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 5
620
621
622
623
624
625
1 Analog Field 6
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 7
620
621
622
623
624
625
1 Analog Field 8
2
3
4
5
6
7
23
24
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Burst Phase = 135 degrees relative to U
Burst Phase = 225 degrees relative to U
Figure 8. PAL Video Interlaced Timing
As mentioned above, there are no horizontal and vertical timing signals necessary in ITU-R.BT656 mode. However in some cases it is advantageous to output these timing signals for other purposes. By
setting the 656_SYNC_OUT register bit in CONTROL_6 register, HSYNC and VSYNC are output,so that other devices in the system can synchronize to these timing signals.
20
DS278F6
CS4954 CS4955
Start of VSYNC
Field 1
262
263
1
2
3
4
5 Field 2
6
7
8
9
10
22
261
262
1
2
3
4
5 Field 3
6
7
8
9
10
22
Start of VSYNC
262
263
1
2
3
4
5 Field 4
6
7
8
9
10
22
261
262
1
2
3
4
5
6
7
8
9
10
22
Burst begins with positive half-cycle Burst phase = reference phase = 180 0 relative to B-Y
Burst begins with negative half-cycle Burst phase = reference phase = 180 0 relative to B-Y
Figure 9. NTSC Video Non-Interlaced Progressive Scan Timing
5.4
Digital Video Input Modes
5.5
Multi-standard Output Format Modes
The CS4954/5 provides two different digital video input modes that are selectable through the IN_MODE bit in the CONTROL_0 Register. In Mode 0 and upon RESET, the CS4954/5 defaults to output a solid color (one of a possible of 256 colors). The background color is selected by writing the BKG_COLOR Register (0x08). The colorspace of the register is RGB 3:3:2 and is unaffected by gamma correction. The default color following RESET is blue. In Mode 1 the CS4954/5 supports a single 8-bit 27 MHz CbYCrY source as input on the V [7:0] pins. Input video timing can be ITU-R.BT601 master or slave or ITU-R.BT656.
The CS4954/5 supports a wide range of output formats compatible with worldwide broadcast standards. These formats include NTSC-M, NTSC-J, PAL-B/D/G/H/I, PAL-M, PAL-N, and PAL Combination N (PAL-Nc) which is the broadcast standard used in Argentina. After RESET, the CS4954/5 defaults to NTSC-M operation with ITU-R.BT601 analog timing. NTSC-J can also be supported in the Japanese format by turning off the 7.5 IRE pedestal through the PED bit in the CONTROL_1 Register (0x01). Output formats are configured by writing control registers with the values shown in Table 3.
NOTE 1: The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not toggle in SLAVE mode and its output state should be considered random.
DS278F6
21
CS4954 CS4955
VSYNC Drops Analog Field 1
309
310
311
312
313
1 Analog Field 2
2
3
4
5
6
7
23
24
308
309
310
311
312
1
2
3
4
5
6
7
23
24
Analog Field 3
309
310
311
312
313
1 Analog Field 4
2
3
4
5
6
7
23
24
308
309
310
311
312
1
2
3
4
5
6
7
23
24
Burst Phase = 135 degrees relative to U
Burst Phase = 225 degrees relative to U
Figure 10. PAL Video Non-Interlaced Progressive Scan Timing
Composite Video
ITU R.BT656 V[7:0] DATA
Y
Cr
Y FF 00 00 XY 80 10 80 10 EAV Code 4 Clocks
80
10 80 10 80 10 Ancilliary Data
80 10 80 10 FF 00 00 XY Cb Y Cr Cb Y Cr SAV Code 4 Clocks 1440 Clocks Active Video
268 Clocks (NTSC) 280 Clocks (PAL) Horizontal Blanking
Active Video
Figure 11. CCIR656 Input Mode Timing
5.6
Subcarrier Generation
The CS4954/5 automatically synthesizes NTSC and PAL color subcarrier clocks using the CLK frequency and four control registers (SC_SYNTH0/1/2/3). The NTSC subcarrier synthesizer is reset every four fields (every eight fields for PAL).
22
The SC_SYNTH0/1/2/3 registers used together provide a 32-bit value that defaults to NTSC (43E0F83Eh) following RESET. Table 4 shows the 32-bit value required for each of the different broadcast formats.
DS278F6
CS4954 CS4955
The CS4954/5 is designed to provide automatic compensation for an excessively inaccurate MPEG-2 system clock. Sub-carrier compensation is enabled through the XTAL bit of the CONTROL_2 Register. When enabled, the CS4954/5 will utilize a common quartz color burst crystal (3.579545 MHz 50 ppm for NTSC) attached to the XTAL_IN and XTAL_OUT pins to automatically compare and compensate the color subcarrier synthesis process.
System NTSC-M, NTSC-J PAL-N (Argentina) PAL-M
Fsubcarrier 3.5795455 MHz 3.582056 MHz 3.579611 MHz Table 3.
Value (hex) 43E0F83E 43ED288D 43CDDFC7
PAL-B, D, G, H, I, N 4.43361875 MHz 54131596
5.7
Subcarrier Compensation
Since the subcarrier is synthesized from CLK, the subcarrier frequency error will track the clock frequency error. If the input clock has a tolerance of 200 ppm then the resulting subcarrier will also have a tolerance of 200 ppm. Per the NTSC specification, the final subcarrier tolerance is 10 Hz which is approximately 3 ppm. Care must be taken in selecting a suitable clock source. In MPEG-2 system environments the clock is actually recovered from the data stream. In these cases the recovered clock can be 27 MHz 50 ppm or 1350 Hz. It varies per television, but in many cases given an MPEG-2 system clock of 27 MHz, 1350 Hz, the resultant color subcarrier produced will be outside of the television's ability to compensate and the chrominance information will not be displayed (resulting in a black-and-white picture only).
5.8
Closed Caption Insertion
The CS4954/5 is capable of NTSC Closed Caption insertion on lines 21 and 284 independently. Closed captioning is enabled for either one or both lines via the CC_EN [1:0] Register bits and the data to be inserted is also written into the four Closed Caption Data registers. The CS4954/5, when enabled, automatically generates the seven cycles of clock run-in (32 times the line rate), does start bit insertion (001), and finally does insertion of the two data bytes per line. Data low at the video outputs corresponds to 0 IRE and data high corresponds to 50 IRE. There are two independent 8-bit registers per line (CC_21_1 & CC_21_2 for line 21 and CC_284_1 & CC_284_2 for line 284). Interrupts are also provided to simplify the handshake between the driver software and the device. Typically the host writes
PAL-N Comb. (Argent) 81h 30h 07h 78h 15h 8Ch 28h EDh 43h
Address 0x00 0x01 0x04 0x05 0x10 0x11 0x12 0x13 0x14
Register CONTROL_0 CONTROL_1 CONTROL_4 CONTROL_5 SC_AMP SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3
NTSC-M NTSC-J ITU ITU NTSC-M PALR.BT601 R.BT601 RS170A B,D,G,H,I 01h 12h 07h 78h 1Ch 3Eh F8h E0h 43h 01h 10h 07h 78h 1Ch 3Eh F8h E0h 43h 21h 16h 07h 78h 1Ch 3Eh F8h E0h 43h 41h 30h 07h 78h 15h 96h 15h 13h 54h
PAL-M 61h 12h 07h 78h 15h C7h DFh CDh 43h
PAL-N A1h 30h 07h 78h 15h 96h 15h 13h 54h
Table 4. Multi-standard Format Register Configurations DS278F6 23
CS4954 CS4955
all 4 bytes to be inserted to the registers and then enables closed caption insertion and interrupts. As the closed caption interrupts occur, the host software responds by writing the next two bytes to be inserted to the correct control registers and then clears the interrupt and waits for the next field. enabled by setting WW_23 to "1". Some countries with PAL standard don't use line 336 for wide screen signaling (they use only line 23), therefore we provide another enable bit (WSS_22) for that particular line. There are 3 registers dedicated to contain the transmitted WSS bits (WSS_REG_0, WSS_REG_1, WSS_REG_2). The data insertion into the appropriate lines is performed automatically by this device. The run-in and start code bits do not have to be loaded into this device. It automatically inserts the correct code at the beginning of transfer.
5.9
Programmable H-sync and V-sync
It is possible in master mode to change the H-sync and V-sync times based on register settings. Programmable H-sync and V-sync timing is helpful in systems where control signal latencies are present. The user can then program H-sync and V-sync timing according to their system requirements. The default values are 244, and 264 for NTSC and PAL respectively. H-sync can be delayed by a full line, in 74 nsec intervals. V-sync can be shifted in time in both directions. The default values are 18 and 23 for NTSC and PAL respectively. Since the V-sync register is 5 bits wide (Sync Register 0), the V-sync pulse can be shifted by 31 lines total. V-sync timing can preceed its default timing by a maximum of 18 lines (NTSC) or 23 lines (PAL) and can be delayed from its default timing by a maximum of 13 lines (NTSC) or 8 lines (PAL).
5.11
Teletext Support
This chip supports several teletext standards including European teletext, NABTS (North American teletext), and WST (World Standard Teletext) for NTSC and PAL. All of these teletext standards are defined in the ITU-R BT.653-2 document. The European teletext is defined as "teletext system B" for 625/50 Hz TV systems. NABTS teletext is defined as "teletext system C" for 525/60 Hz TV systems. WST for PAL is defined as "teletext system D" for 624/50 Hz TV systems and WST for NTSC is defined as "teletext system D" for 525/60 Hz TV systems. This chip provides independant teletext encoding into composite 1, composite 2 and s-video signals. The teletext encoding into these various signals is software programmable. In teletext pulsation mode, (TTX_WINDOW=0), register 0x31 bit 3, the pin TTXDAT receives a teletext bitstream sampled at the 27 MHz clock. At each rising edge of the TTXRQ output signal a single teletext bit has to be provided after a programmable input delay at the TTXDAT input pin. Phase variant interpolation of the data in the internal teletext encoder results in minimal phase jitter on the ouput text lines.
5.10
Wide Screen Signaling (WSS) and CGMS
Wide screen signaling support is provided for NTSC and for PAL standards. Wide screen signaling is currently used in most countries with 625 line systems as well as in Japan for EDTV-II applications. For a complete description of the WSS standard, please refer to ITU-R BT.1119 (625 line system) and to EIAJ CPX1204 for the Japanese 525 line system standard. The wide screen signal is transferred in a blanking line of each video field (NTSC: lines 20 and 283, PAL: lines 23 and 336). Wide screen signaling is
24
DS278F6
CS4954 CS4955
TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of the bitstream at independently selectable lines for both TV fields. The internal insertion window for text is set to either 360, 296 or 288 teletext bits, depending on the selected teletext standard. The clock run-in is included in this window. Teletext in enabled by setting the TTX_EN bit to "1". The TTX_WST bit in conjunction with the TV_FORMAT register selects one of the 4 teletext encoding possibilities. The teletext timing is shown in the Figure 12. TTXHS and TTXHD are user programmable and therefore allow the user to have full control over when teletext data is sent to this device. The time tFD is the time needed to interpolate teletext input data and insert it into the CVBS and Y output signals, such that it appears between tTTX = 9.8 s and tTTX = 12 s after the leading edge of the horizontal synchronization pulse. tFD changes with the TV standard and the selected teletext standard. Please refer to ITU-R BT.653-2 for more detailed information. The time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver teletext data. This delay is programmable through the register TTXHD. For every active HIGH transition at output pin TTXRQ, a new teletext bit must be provided by the source. The time between the beginning of the first TTXRQ pulse and the leading edge of H-sync is programmable through the TTXHS register. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable, the TTXDAT data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. The time tTTXWin is the internally used insertion window for TTX data; it has a constant length depending on the selected teletext standard which allows insertion of 360 TTX bits (6.9375 Mbit/sec) (European teletext) or 296 TTX bits (5.6427875 Mbit/sec) (WST PAL) or 288 TTX bits (5.727272 Mbit/sec) (NABTS) or 296 TTX bits (5.727272 Mbit/sec) (WST NTSC) respectively. Using the appropriate programming, all suitable lines of the odd field (TTXOVS through TTXOVE) plus all suitable lines of the even field (TTXEVS through TTXEVE) can be used for teletext insertion. In addition it is possible to selectively disable the teletext insertion on single lines. This can be programmed by setting the TTX_LINE_DIS1, TTX_LINE_DIS2 and TTX_LINE_DIS3 registers appropriately. Note that the TTXDAT signal must be synchronized with the 27 MHz clock. The pulse width of the TTXRQ signal varies between three and four 27 MHz clock cycles. The variation is necessary in
CVBS/Y tTTX TTXRQ textbit #: 1 TTXDAT tPD tFD 2 3 4 5 tTTXWin
CVBS/Y tTTX TTXRQ textbit #: 1 TTXDAT tPD tFD 2 3 4 5 tTTXWin
Figure 12. Teletext Timing (Pulsation Mode) DS278F6
Figure 13. Teletext Timing (Window Mode) 25
CS4954 CS4955
order to maintain the strict timing requirements of the teletext standard. Table 5 shows how to program the TTXHS register for teletext instantiation into the analog signals for the various supported TV formats. TTXHS is the time between the leading edge of the HSYNC signal and the rising edge of the first TTXRQ signal and consists of multiples of 27 MHz clock cycles Note that with increasing values of TTXHS the time tTTX increases as well. The time tFD accounts for the internal pipeline delay due to processing, synchronization and instantiation of the teletext data. The time tPD is dependant on the TTXHD register. Note that the teletext databits are shaped according to the ITU R.BT653-2 specifications. If register 0x31 bit 3 is set, (TTX_WINDOW=1) the teletext is in windows mode. In this mode, the request pulses become a window where the bit provided on the TTXDAT pin is valid (see Figure 13). In pulse mode (where the number of request pulses are determined by the teletext standard chosen), the length of the window must be programmed by the user independent of the teletext standard used. The length of the window is programmed through register 0x29 TTXHS (start of window), register 0x2A (TTXHD) and register 0x31 (end of window). The end-of-window register is a 11 bit value. In teletext window mode, the TTXHS value can be selected using the values in Table 5. Although these values may need to be adjusted to match your system delay, use the following equation to compute the TTXHD value: TTXHS + 1402 = TTXHD (for Europe) TTXHS + 1151 = TTXHD (for WST) TTXHS + 1122 = TTXHD (for NABTS)
Teletext standard NABTS WST-NTSC Europe TTX WST-PAL NABTS WST-NTSC Europe TTX WST-PAL Europe TTX WST-PAL TTXHS (register value) 161 142 204 163 161 142 204 163 204 163
TV standard NTSC-M NTSC-M PAL-B PAL-B PAL-M PAL-M PAL-N (non Arg.) PAL-N (non Arg.) PAL-N (Arg.) PAL-N (Arg.)
tTTX 10.5 s 9.8 s 12.0 s 10.5 s 10.5 s 9.8 s 12.0 s 10.5 s 12.0 s 10.5 s
Table 5. Teletext timing parameters
5.12
Color Bar Generator
The CS4954/5 is equipped with a color bar generator that is enabled through the CBAR bit of the CONTROL_1 Register. The color bar generator works in Master or Slave Mode and has no effect on the video input/output timing. If the CS4954/5 is configured for Slave Mode color bars, proper video timing must be present on the HSYNC and VSYNC pins for the color bars to be displayed. Given proper Slave Mode input timing or Master Mode timing, the color bar generator will override the video input pixel data. The output of the color bar generator is instantiated after the chroma interpolation filter and before the luma delay line. The generated color bar numbers are for 100% amplitude, 100% saturation NTSC EIA color bars or 100% amplitude, 100% saturation PAL EBU color bars. For PAL color bars, the CS4954/5 generates NTSC color bar values, which are very close to standard PAL values. The exact luma and chroma values are listed in Table 6.
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digital input value which is out of this range to conform to the ITU-R BT.601 specifications. However for some applications it is useful to allow a wider input range. By setting the CLIP_OFF bit (CONTROL_6 register), the allowed input range is extended to 0x01 - 0xFE for both luma and chrominance values. Note that 0x00 and 0xFF values are never allowed, since they are reserved for synchronization information.
Color White Yellow Cyan Green Magenta Red Blue Black
Cb 0 - 84 + 28 - 56 + 56 - 28 + 84 0
Cr 0 + 14 - 84 - 70 + 70 + 84 - 14 0
Y + 167 + 156 + 138 + 127 + 110 + 99 + 81 + 70
Table 6. Internal Color Bar Values (8-bit values, Cb/Cr are in twos complement format)
5.15
Interrupts
5.13
VBI encoding
VBI (Vertical Blanking Interval) encoding is performed according to SMPTE RP 188 recommendations. In NTSC mode, lines 10 - 20 and lines 272 283 are used for the transmission of ancillary data. In PAL mode lines 6 - 22 and lines 318 -335 are used. The VBI encoding mode can be set through the CONTROL_3 register. All digital input data is passed through the chip when this mode is enabled. It is therefore the responsibility of the user to ensure appropriate amplitude levels. Table 7 shows the relationship of the digital input signal and the analog output voltage.
Digital Input 0x38 0x3B 0xC4 Analog Output Voltage 286 mV 300 mV 1000 mV
In order to better support precise video mode switches and to establish a software/hardware handshake with the closed caption insertion block, the CS4954/5 is equipped with an interrupt pin named INT. The INT pin is active high. There are three interrupt sources: VSYNC, Line 21, and Line 284. Each interrupt can be individually disabled with the INT_EN Register. Each interrupt is also cleared via writing a one to the corresponding INT_CLR Register bits. The three individual interrupts are OR-ed together to generate an interrupt signal which is presented on the INT output pin. If an interrupt has occurred, it cannot be eliminated with a disable, it must be cleared.
5.16
General Purpose I/O Port
Table 7. VBI Encoding Signal Amplitudes
Each LSB corresponds to a step of 5 mV in the output voltage.
5.14
Super White/Super Black support
The CS4954/5 has a GPIO port and register that is available when the device is configured for IC host interface operation. In IC host interface mode, the PDAT [7:0] pins are unused by the host interface and they can operate as input or output pins for the GPIO_DATA_REG Register (0x0A). The CS4954/5 also contains the GPIO_CTRL_REG Register (0x09) which is used to configure the GPIO pins for input or output operation. The GPIO port PDAT [7:0] pins are configured for input operation when the corresponding GPIO_CTRL_REG [7:0] bits are set to 0. In GPIO input mode, the CS4954/5 will latch the data on the PDAT [7:0] pins into the corresponding bit loca27
The ITU-R BT.601 recommendation limits the allowed range for the digital video data between 0x10 - 0xEB for luma and between 0x10 - 0xF0 for the chrominance values. This chip will clip any
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tions of GPIO_DATA_REG when it detects register address 0x0A through the IC interface. A detection of address 0x0A can happen in two ways. The first and most common way this will happen is when address 0x0A is written to the CS4954/5 via its IC interface. The second method for detecting address 0x0A is implemented by accessing register address 0x09 through IC. In IC host interface operation, the CS4954/5 register address pointer will auto-increment to address 0x0A after an address 0x09 access. The GPIO port PDAT [7:0] pins are configured for output operation when the corresponding GPIO_CTRL_REG [7:0] bits are set. In GPIO output mode, the CS4954/5 will output the data in GPIO_DATA_REG [7:0] bit locations onto the corresponding PDAT [7:0] pins when it detects a register address 0x0A through the IC interface.
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6. FILTER RESPONSES
1.3 Mhz. filter frequency response 0 1.3 Mhz. filter passband response
-10
0
-20 magnitude - dB magnitude - dB
0 1 2 3 4 frequency (Hz) 5 6
-0.1
-30
-0.2
-40
-0.3 -50 -0.4
-60
-70
-0.5 6 x 10
0
2
4 6 frequency (Hz)
8
10
12 x 10 5
Figure 14. 1.3 MHz Chrominance low-pass filter transfer characteristic
Figure 15. 1.3 MHz Chrominance low-pass filter transfer characterstic (passband)
650 Khz. filter frequency response 0 0
650 Khz. filter passband response
-5
-0.5
magnitude - dB
-10
magnitude - dB
-1
-15
-1.5
-2 -20 -2.5 -25 -3 -30
0 1 2 3 4 5 6 0 2 4 6 8 10 12
x 10
6
x 10
5
Figure 16. 650 kHz Chrominance low-pass filter transfer characteristic
Figure 17. 650 kHz Chrominance low-pass filter transfer characteristic (passband)
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Chroma Output Interpolator Pass band
Luma Output Interpolation Filter Response at 27MHz full scale 0 -5 Magnitude Response (dB) -10 -15 -20 -25 -30 -35
1 0.8 0.6 Magnitude Response (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1
-40
0 0.5 1 1.5 2 2.5 3 Frequency (MHz) 3.5 4 4.5 5 0 2 4 6 8 Frequency (MHz) 10 12 14
Figure 18. Chrominance output interpolation filter transfer characteristic (passband)
Figure 19. Luminance interpolation filter transfer characteristic
Luma Output Interpolation Filter Response at 27 MHz (-3 dB) 0.5 0 Magnitude Response (dB) Magnitude Response (dB) -0.5 -1 -1.5 -2 -2.5 -3 -3.5
0 -5 -10 -15 -20 -25 -30 -35 -40 0
RGB datapath filter for rgb_bw = 0 full scale
0
1
2
3 4 5 Frequency (MHz)
6
7
8
2
4
6 8 Frequency (MHz)
10
12
Figure 20. Luminance interpolation filter transfer characterstic (passband)
Figure 21. Chrominance interpolation filter transfer characteristic for RGB datapath
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RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth) (-3 dB) 1 0.5 Magnitude Response (dB) 0 -0.5 -1 -1.5 -2 -2.5 -3 Magnitude Response (dB) 0 -5 -10 -15 -20 -25 -30 -35 -40 -45
0
RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth)
0
2
4
6 8 Frequency (MHz)
10
12
2
4
6 8 Frequency (MHz)
10
12
Figure 22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth)
Figure 23. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth)
RGB datapath filter for rgb_bw = 0 (-3 dB)
Chroma Output Interpolator Full Scale
1 0 0.5 -5 Magnitude Response (dB) Magnitude Response (dB)
0 2 4 6 8 Frequency (MHz) 10 12
0 -0.5 -1 -1.5 -2 -2.5 -3
-10 -15 -20 -25 -30 -35 -40
0
5
10 15 Frequency (MHz)
20
25
Figure 24. Chroma Interpolator for RGB Datapath when rgb_bw=0 -3 dB
Figure 25. Chroma Interpolator for RGB Datapath when rgb_bw=0 (Full Scale)
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7. 7.1 ANALOG Analog Timing
trol register bits that are used to control internal digital amplifiers. The DAC output levels are defined by the following equations:
VREF/RISET = IREF (e.g., 1.232 V/4K = 308 A)
All CS4954/5 analog timing and sequencing is derived from the 27 MHz clock input. The analog outputs are controlled internally by the video timing generator in conjunction with master and slave timing. Since the CS4954/5 is almost entirely a digital circuit, great care has been taken to guarantee analog timing and slew rate performance as specified in the NTSC and PAL analog specifications. Reference the Analog Parameters section of this data sheet for the performance specifications.
CVBS/Y/C/R/G/B outputs in low impedance mode:
VOUT (max) = IREF*(16/145)*1023*37.5 = 1.304V
CVBS/Y/C/R/G/B outputs in high impedance mode:
VOUT (max) = IREF*(4/145)*1023*150 = 1.304 V
7.4
DACs
7.2
VREF
The CS4954/5 can operate with or without the aid of an external voltage reference. The CS4954/5 is designed with an internal voltage reference generator that provides a VREFOUT signal at the VREF pin. The internal voltage reference is utilized by not making a connection to the VREF pin. The VREF pin can also be connected to an external precision 1.232 volt reference, which then overrides the internal reference.
The CS4954/5 is has six independent, video-grade, current-output, digital-to-analog converters (DACs). They are 10-bit DACs operating at a 27 MHz two-times-oversampling rate. All six DACs are disabled and default to low power mode upon RESET. Each DAC can be individually powered down and disabled. The output-current-per-bit of all six DACs is determined by the size of the resistor connected between the ISET pin and ground.
7.4.1 Luminance DAC
The Y output pin is driven from a 10-bit 27 MHz current output DAC that internally receives the Y, or luminance (black and white only) or CVBS data based on its configuration. See Table 1 and "CVBS DAC" on page 33. The Y DAC is designed to drive proper video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact Y digital to analog AC and DC performance data. A EN_L enable control bit in the Control Register 5 (0x05) is provided to enable or disable the luminance DAC. To completely disable or for low power device operation, the luminance DAC can be totally shut down via the SVIDLUM_PD control bit in Control Register 4 (0x04). In this mode, turn-on using the control register will not be instantaneous.
7.3
ISET
All six of the CS4954/5 digital to analog converter DACs are output current normalized with a common ISET device pin. The DAC output current per bit is determined by the size of the resistor connected between ISET and electrical ground. Typically a 4 K, 1% metal film resistor should be used. The ISET resistance can be changed by the user to accommodate varying video output attenuation via post filters and also to suit individual preferred performance needs. In conjunction with the ISET value, the user can also independently vary the chroma, luma and colorburst amplitude levels via host addressable con-
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7.4.2 Chrominance DAC
The C output pin is driven from a 10-bit 27 MHz current output DAC that internally receives the C or chrominance portion of the video signal (color only). The C DAC is designed to drive proper video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact C digital to analog AC and DC performance data. The EN_C enable control register bit in Control Register 1 (0x05) is provided to enable or disable the chrominance DAC. To completely disable or for low power device operation, the chrominance DAC can be totally shut down via the SVIDCHR_PD register bit in Control Register 4 (0x04). In this mode turn-on using the control register will not be instantaneous. electrical section of this data sheet for the exact red digital to analog AC and DC performance data. The EN_R enable control register bit in Control Register 1 (0x05) is provided to enable or disable the output pin. When disabled, there is no current flow from the output. To complete disable or for low power device operation, the red DAC can be totally shut down via the R_PD control register bit in Control Register 4 (0x04). In this mode turn-on using the control register will not be instantaneous.
7.4.5 Green DAC
The Green output pin is driven from a 10-bit 27 MHz current output DAC that internally receives either Green component video data, Y luminance data or CVBS data depending upon its configuration. See Table 1, "CVBS DAC" on page 33 and "Luminance DAC" on page 32. The Green DAC is designed to drive proper composite video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact green digital to analog AC and DC performance data. The EN_G enable control register bit, in Control Register 1 (0x05), is provided to enable or disable the output pin. When disabled, there is no current flow from the output. To completely disable or for low power device operation, the green DAC can be totally shut down via the G_PD control register bit in Control Register 4 (0x04). In this mode turn-on using the control register will not be instantaneous.
7.4.3 CVBS DAC
The CVBS output pin is driven from a 10-bit 27 MHz current output DAC that internally receives a combined luma and chroma signal to provide composite video output. The CVBS DAC is designed to drive proper composite video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact CVBS digital to analog AC and DC performance data. The EN_COM enable control register bit, in Control Register 1 (0x05), is provided to enable or disable the output pin. When disabled, there is no current flow from the output. To completely disable or for low power device operation, the CVBS37 DAC can be totally shut down via the COMDAC_PD control register bit in Control Register 4 (0x04). In this mode turn-on using the control register will not be instantaneous.
7.4.6 Blue DAC
The Blue output pin is driven from a 10-bit 27 MHz current output DAC that internally receives either blue component video data or U (Cb) data. The Blue DAC is designed to drive proper component video levels into a 37.5 load. Reference the detailed electrical section of this data sheet for the exact blue digital to analog AC and DC performance data. The EN_B enable control register bit, in Control Register 5 (0x05), is provided to enable or disable the output pin. When disabled, there is no
33
7.4.4 Red DAC
The Red output pin is driven from a 10-bit 27 MHz current output DAC that internally receives either red component video data or V (Cr) data. The Red DAC is designed to drive proper component video levels into a 37.5 load. Reference the detailed
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current flow from the output. To completely disable or for low power device operation, the blue DAC can be totally shut down via the B_PD control register bit in Control Register 4 (0x04). In this mode turn-on using the control register will not be instantaneous.
Low/High Impedance mode Low Impedance High Impedance Low Impedance High Impedance
Nominal Power supply 3.3V 3.3V 5.0V 5.0V
maximum # of active DACs 3 6 3 6
7.4.7 DAC Useage Rules
If some of the 6 DACs are not used, it is strongly recommended to power them down (see CONTROL_4 register) in order to reduce the power dissipation. Depending on the external resistor connected to the ISET pin the output drive of the DACs can be changed. An external resistor of 4 k must be connected to the ISET pin for normal operation. There are two outpout impedance modes that the DACs can be operated in. The first mode is the high impedance mode (LOW_IMP bit set to 0). In this mode, the DAC output drives a double terminated 300 load and will output a video signal which conforms to the proper analog video specifications. External buffers will be needed if the DAC output load differs from a double terminated 300 load. The second mode is the low impedence mode (LOW_IMP but set to 1). In this mode, the DAC output drives a double terminated 75 load and will output a video signal which conforms to the proper analog video specifications. No external buffers are necessary. The ouputs can directly drive a television input. Note that for power dissipation purposes it is not always possible to have all the 6 DACs active at the same time. Table 8 shows the maximum number of active DACs allowed depending on the power supply and low/high impedance modes. If less than 6 DACs are allowed to be active, the other DACs must be powered down (see CONTROL_4 register).
Table 8. Maximum DAC Numbers
8. 8.1
PROGRAMMING Host Control Interface
The CS4954/5 host control interface can be configured for IC or 8-bit parallel operation. The CS4954/5 will default to IC operation when the RD and WR pins are both tied low at power up. The RD and WR pins are active for 8-bit parallel operation only.
8.1.1 IC(R) Interface
The CS4954/5 provides an IC interface for accessing the internal control and status registers. External pins are a bidirectional data pin (SDA) and a serial input clock (SCL). The protocol follows the IC specifications. A complete data transfer is shown in Figure 26. Note that this IC interface will work in Slave Mode only - it is not a bus master. SDA and SCL are connected via an external pullup resistor to a positive supply voltage. When the bus is free, both lines are high. The output stages of devices connected to the bus must have an opendrain or open-collector in order to perform the wired-AND function. Data on the IC bus can be transferred at a rate of up to 400 Kbits/sec in fast mode. The number of interfaces to the bus is solely dependent on the limiting bus capacitance of 400 pF. When 8-bit parallel interface operation is being used, SDA and SCL can be tied directly to ground. The IC bus address for the CS4954/5 is programmable via the I2C_ADR Register (0x0F). When IC interface operation is being used, RD and WR
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CS4954 CS4955
must be tied to ground. PDAT [7:0] are available to be used for GPIO operation in IC host interface mode. For 3.3 V operation it is necessary to have the appropriate level shifting for IC signals.
SDA
SCL A Start
1-7
8
9
ACK
1-7
8
Data
9
ACK
1-7
8
9
P Stop
Address R/W
Data ACK
Note: IC transfers data always with MSB first, LSB last Figure 26. IC Protocol
8.1.2 8-bit Parallel Interface
The CS4954/5 is equipped with a full 8-bit parallel microprocessor write and read control port. Along with the PDAT [7:0] pins, the control port interface is comprised of host read (RD) and host write (WR) active low strobes and host address enable (ADDR), which, when low, enables unique address register accesses. The control port is used to access internal registers which configure the CS4954/5 for various modes of operation. The internal registers are uniquely addressed via an address register. The
WR Trec RD
address register is accessed during a host write cycle when the WR and ADDR pins set low. Host write cycles with ADDR set high will write 8-bit data to the PDAT [7:0] pins into the register currently selected by the address register. Likewise read cycles occuring with RD set low and ADDR set high will return the register contents selected by the address register. Reference the detailed electrical timing parameter section of this data sheet for exact host parallel interface timing characteristics and specifications.
Trec
Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle
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Trd RD Trpw PADR PDAT[7:0] Tas Trda Trdh Trah
Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle Twpw WR PADR PDAT[7:0] Tas Twds Twdh Twr Twac
Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle
8.2
Register Description
A set of internal registers are available for controlling the operation of the CS4954/5. The registers extend from internal address 0x00 through 0x5A. Table 9 shows a complete list of these registers and their internal addresses. Note that this table and the
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Register Name control_0 control_1 control_2 control_3 control_4 control_5 control_6 RESERVED bkg_color
subsequent register description section describe the full register map for the CS4954 only. A complete CS4955 register set description is available only to MacrovisionTM ACP-PPV Licensed Buyers.
8.2.1 Control Registers
Type r/w r/w r/w r/w r/w r/w r/w r/w Default value 01h 02h 00h 00h 3Fh 00h 00h 03h
Table 9. Control Registers
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Address 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 Register Name gpio_ctrl_reg gpio_data_reg RESERVED RESERVED SYNC_0 SYNC_1 IC_ADR SC_AMP SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3 HUE_LSB HUE_MSB SCH PHASE ADJUST CC_EN CC_21_1 CC_21_2 CC_284_1 CC_284_2 RESERVED WSS_REG_0 WSS_REG_1 WSS_REG_2 RESERVED CB_AMP CR_AMP Y_AMP R_AMP G_AMP B_AMP BRIGHT_OFFSET TTXHS TTXHD TTXOVS TTXOVE TTXEVS TTXEVE TTX_DIS1 TTX_DIS2 TTX_DIS_3 INT_EN INT_CLR Table 9. Control Registers (Continued) DS278F6 37 Type r/w r/w Default value 00h 00h
r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
90h F4h 00h 1Ch 3Eh F8h E0h 43h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 80h 80h 80h 80h 80h 80h 00h A1h 02h 00h 00h 00h 00h 00h 00h 00h 00h 00h
CS4954 CS4955
Address 0x34 0x35 - 0x59 0x5A 0x61 - 0x7F Register Name STATUS_0 RESERVED STATUS_1 RESERVED Table 9. Control Registers (Continued) Type read only read only Default value
04h
Control Register 0
Address Bit Number Bit Name Default Bit 0x00
7 0
CONTROL_0
6 TV_FMT 0 0 5
Read/Write
4 MSTR 0
Default Value = 01h
3 CCIR656 0 2 PROG 0 1 IN_MODE 0 0 CBCR_UV 1
Mnemonic selects the TV display format 000: 001: 010: 011: 100: 101: 110-111:
Function NTSC-M CCIR601 timing (default) NTSC-M RS170A timing PAL-B, D, G, H, I PAL-M PAL-N (Argentina) PAL-N (non Argentina) reserved
7:5
TV_FMT
4 3 2 1 0
MSTR CCIR656 PROG IN_MODE CBCR_UV
1 = Master Mode, 0 = Slave Mode video input is in ITU R.BT656 format with embedded EAV and SAV (0 = off, 1 = on) Progressive scanning enable (enable = 1) Input select (0 = solid background, 1 = use V [7:0] data) enable YCbCr to YUV conversion (1 = enable, 0 = disable)
Control Register 1
Address Bit Number Bit Name Default Bit 0x01
7 LUM DEL 0 0
CONTROL_1
6 5
Read/Write
4 LPF_ON 0
Default Value = 02h
3 RGB_BW 0 2 FLD 0 1 PED 1 0 CBCRSEL 0
CH BW 0
Mnemonic luma delay on the composite1 output 00:
Function no delay (default) 1 pixel clock delay 2 pixel clock delay 3 pixel clock delay
7:6
LUM DEL
01: 10: 11:
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Bit
5 4 3 2 1 0
Mnemonic
CH BW LPF ON RGB_BW FLD_POL PED CBCRSEL
Function chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 MHz) chroma lpf on/off (0 = off, 1 = on) 0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0) Polarity of Field (0: odd field = 0,1: odd field = 1) Pedestal offset (0: 0 IRE, 1: 7.5 IRE) CbCr select (0 = chroma undelayed, 1 = chroma delayed by one clock)
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Control Register 2
Address Bit Number Bit Name Default Bit 0x02
7 0
CONTROL_2
6 OUTPUT FORMAT 0 0 5
Read/Write
4 TTX WST 0
Default Value = 00h
3 TTX EN 0 2 SYNC_DLY 0 1 XTAL 0 0 SC_EN 0
Mnemonic 000 : 001 :
Function selects the output through the DACs rgb, s-video, composite1 (6 DACs) (default) yuv, s-video, composite1 (6 DACs) s-video, composite1, composite2, (4 DACs) rgb, composite1, composite2 (5 DACs) yuv, composite1, composite2 (5 DACs) don't care
7:5
OUTPUT FORMAT
010 : 011 : 100 : 101-111:
To select between world standard (NTSC), world standard (PAL), or north american teletext standard during NTSC or PAL modes (1 = WST TTX) (default is 0) In NTSC-M or PAL-M mode. This bit works in conjunction with the TV FORMAT register. 0: 1: 0: 1:
3 2 1 0 TTX EN SYNC DLY XTAL BU DIS
4
TTX WST
NABTS, if TV FORMAT is NTSC or PAL-M WST (NTSC), if TV FORMAT is NTSC or PAL-M Europe TTX, if TV FORMAT is PAL-B, G..., N WST (PAL), if TV FORMAT is PAL-B, G, ..., N
Enable teletext process (1 = enable) Slave mode 1 pixel sync delay (1 = enable) Crystal oscillator for subcarrier adjustment enable (1 = enable) Chroma burst disable (1 = disable)
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Control Register 3
Address Bit Number Bit Name Default Bit
7:5 4 3 2 1 0
0x03
7 0
CONTROL_3
6 RESERVED 0 0 5
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 0 0 CBAR 0
FD THR C1 FD THR C2 FD THR SV FD THR EN
Mnemonic
FD THR C1 FD THR C2 FD THR SV FD THR_EN CBAR
Function reserved feedthrough enabled for composite 1 output (0 = off, 1 = on) feedthrough enabled for composite 2 output (0 = off, 1 = on) feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on) Enable (1 = enable) input to feed through during inactive lines internal color bar generator (0 = off, 1 = on)
Control Register 4
Address Bit Number Bit Name Default Bit
7 6 5
0x04
7 CB_H_SEL 0
CONTROL_4
6 CB_FLD_SEL(1) 0
Read/Write
5 1
Default Value = 3Fh
4 1 3 1 2 R_PD 1 1 G_PD 1 0 B_PD 1
COMDAC_PD SVIDLUM_PD SVIDCHR_PD
Mnemonic
CB_H_SEL CB_FLD_SEL COMDAC_PD
Function Composite Blank / HSYNC output select (1 = CB select, 0 = HSYNC select) Composite Blank / FIELD output select (1 = CB select, 0 = FIELD select)(1) power down composite DAC 0: power up, 1: power down power down luma s-video DAC 0: power up, 1: power down power down chroma s-video DAC 0: power up, 1: power down power down red rgb video DAC 0: power up, 1: power down power down green rgb video DAC 0: power up, 1: power down power down blue rgb video DAC 0: power up, 1: power down
4
SVIDLUM_PD
3
SVIDCHR_PD
2
R_PD
1
G_PD
0
B_PD
NOTE: 1. The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not toggle in SLAVE mode and its output state should be considered random.
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Control Register 5
Address Bit Number Bit Name Default Bit
7 6 5 4 3 2 1 0
0x05
7 RSVD 0
CONTROL_5
6 LOW IMP 0 5
Read/Write
4 EN L 0
Default Value = 00h
3 EN C 0 2 EN R 0 1 EN G 0 0 EN B 0
EN COM 0
Mnemonic
LOW IMP EN COM EN L EN C EN_R EN_G EN_B
Function reserved selects between tri-state output (0) or output enabled (1) mode of DACs enable composite (CVBS) DAC 0: high-impedance, 1: enable enable S-VIDEO Y DAC for luma output 0: high-impedance, 1: enable enable S-VIDEO C DAC for chroma output 0: high-impedance, 1: enable enable RGB video R DAC for red output 0: high-impedance, 1: enable enable RGB video G DAC for green output 0: high-impedance, 1: enable enable RGB video B DAC for blue output 0: high-impedance, 1: enable
Control Register 6
Address Bit Number Bit Name Default Bit
7 6 5 4 3 2 1 0
0x06
7 656 SYNC OUT 0
CONTROL_6
6 CLIP OFF 0 5 TTXEN COM2 0
Read/Write
4 TTXEN COM1 0
Default Value = 00h
3 TTXEN SVID 0 2 1 0
BSYNC DIS GSYNC DIS RSYNC DIS 0 0 0
Mnemonic
CLIP OFF TTXEN COM2 TTXEN COM1 TTXEN SVID BSYNC DIS GSYNC DIS RSYNC DIS
Function Clipping input signals disable (0: clipping active 1: no clipping) Enable teletext at the composite 2 output (0: disable teletext, 1 : enable teletext) Enable teletext at the composite 1 output ( 0: disable teletext, 1 : enable teletext) Enable teletext at the s-video output ( 0: disable teletext, 1: enable teletext) Disable syncs in the blue or v output (0: enable syncs, 1: disable syncs) Disable syncs in the green or u output ( 0: enable syncs, 1: disable syncs) Disable syncs in the red or y output (0: enable syncs, 1: disable syncs)
656 SYNC OUT Enable (=1) output of hsync and vsync when in ITU R.BT656 mode
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CS4954 CS4955
Background Color Register
Address Bit Number Bit Name Default Bit
7:0
0x08
7 0
BKG_COLOR Read/Write
6 0 5 0 4
Default Value = 03h
3 BG 0 2 0 1 1 0 1
0
Mnemonic
BG
Function Background color (7:5 = R, 4:2 = G, 1:0 = B) (default is 0000 0011 - blue)
GPIO Control Register
Address Bit Number Bit Name Default Bit
7:0
0x09
7 0
GPIO__REG
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 0 0 0
GPR_CNTRL
Mnemonic
GPR CNTRL
Function Input(0)/output(1) control of GPIO registers (bit 0: PDAT(0), bit 7: PDAT(7))
GPIO Data Register
Address Bit Number Bit Name Default Bit
7:0
0x0A
7 0
GPIO_REG
6 0 5 0
Read/Write
4
Default Value = 00h
3 GPIO REG 0 2 0 1 0 0 0
0
Mnemonic
GPIO REG
Function GPIO data register ( data is output on PDAT bus if appropriate bit in address 09 is set to "1", otherwise data is input/output through IC)- This register is only accessible in IC mode.
Sync Register 0
Address Bit Number Bit Name Default Bit
7:3 2:0
0x0D
7 1
Sync_0
6 0 5
Read/Write
4 1 PROG VS[4:0] 0
Default Value = 90h
3 0 2 0 1 PROG HS[10:8] 0 0 0
Mnemonic
PROG VS[4:0]
Function programmable vsync lines
PROG HS[10:8] programmable hsync pixels (3 most significant bits)
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CS4954 CS4955
Sync Register 1
Address Bit Number Bit Name Default Bit
7:0
0x0E
7 1
Sync_1
6 1 5 1
Read/Write
4 1
Default Value = F4h
3 0 2 1 1 0 0 0
PROG HS[7:0]
Mnemonic
PROG HS[7:0]
Function programmable hsync pixels lsb
IC Address Register
Address Bit Number Bit Name Default Bit
7 6:0
0x0F
7 RESERVED 0
IC_ADR
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 IC ADR 0 0 0 0 2 1 0
Mnemonic
IC
Function reserved IC device address (programmable)
Subcarrier Amplitude Register
Address Bit Number Bit Name Default Bit
7:0
0x10
7 0
SC_AMP
6 0 5 0
Read/Write
4
Default Value = 1Ch
3 BU AMP 1 2 1 1 0 0 0
1
Mnemonic
BU AMP
Function Color burst amplitude
Subcarrier Synthesis Register
Address 0x11 0x12 0x13 0x14 Bits
7:0 7:0 7:0 7:0
SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3 Mnemonic
CC 0 CC 1 CC 2 CC 3
Read/Write
Default Value = 3Eh F8h E0h 43h Function
Register
SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3
Subcarrier synthesis bits 7:0 Subcarrier synthesis bits 15:8 Subcarrier synthesis bits 23:16 Subcarrier synthesis bits 31:24
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Hue LSB Adjust Register
Address Bit Number Bit Name Default Bit
7:0
0x15
7 0
HUE_LSB
6 0 5 0
Read/Write
4
Default Value = 00h
3 HUE LSB 0 2 0 1 0 0 0
0
Mnemonic
HUE LSB
Function 8 LSBs for hue phase shift
Hue MSB Adjust Register
Address Bit Number Bit Name Default Bit
7:2 1:0
0x16
7 0
HUE_MSB
6 0 5 0
Read/Write
4 0 RESERVED
Default Value = 00h
3 0 2 0 1 MSB 0 0 0
Mnemonic
HUE MSB
Function reserved 2 MSBs for hue phase shift
SCH Sync Phase Adjust
Address Bit
7:0
0x17 Mnemonic
SCH
SCH
Read/Write
Default Value = 00h Function
Adjust in increments of 1.4 degree per bit up to 360
Closed Caption Enable Register
Address Bit Number Bit Name Default Bit
7:2 1 0
0x18
7 0
CC_EN
6 0 5 0
Read/Write
4 0 RESERVED
Default Value = 00h
3 0 2 0 1 EN_284 0 0 EN_21 0
Mnemonic
CC EN[1] CC EN[0]
Function reserved enable closed caption for line 284 enable closed caption for line 21
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CS4954 CS4955
Closed Caption Data Register
Address 0x19 0x1A 0x1B 0x1C Mnemonic
CC_21_1 CC_21_2 CC_284_1 CC_284_2
CC_21_1 CC_21_2 CC_284_1 CC_284_2
Read/Write
Default Value = 00h 00h 00h 00h Function
Bit
7:0 7:0 7:0 7:0
first closed caption databyte of line 21 second closed caption databyte of line 21 first closed caption databyte of line 284 second closed caption databyte of line 284
Wide Screen Signaling Register 0
Address Bit Number Bit Name Default Bit
7 6 5 4 3 2 1 0
0x1E
7 WSS_23 0
WSS_REG_0
6 WSS_22 0 5
Read/Write
4 WSS_20 0
Default Value = 00h
3 WSS_19 0 2 WSS_18 0 1 WSS_17 0 0 WSS_16 0
WSS_21 0
Mnemonic
WSS_23 WSS_22 WSS_21 WSS_20 WSS_19 WSS_18 WSS_17 WSS_16
Function Enable wide screen signalling (enable =1) PAL: enable WSS (enable = 1) on line 23 of field 2, NTSC: don't care PAL: group 4, bit 13, NTSC: don't care PAL: group 4, bit 12, NTSC: don't care PAL: group 4, bit 11, NTSC: bit 20 PAL: group 3, bit 10, NTSC: bit 19 PAL: group 3, bit 9, NTSC: bit 18 PAL: group 3, bit 8, NTSC: bit 17
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Wide Screen Signalling Register 1
Address Bit Number Bit Name Default Bit
7 6 5 4 3 2 1 0
0x1F
7 WSS_15 0
WSS_REG_1
6 WSS_14 0 5
Read/Write
4 WSS_12 0
Default Value = 00h
3 WSS_11 0 2 WSS_10 0 1 WSS_9 0 0 WSS_8 0
WSS_13 0
Mnemonic
WSS_15 WSS_14 WSS_13 WSS_12 WSS_11 WSS_10 WSS_9 WSS_8
Function PAL: group 2, bit 7, NTSC: bit 16 PAL: group 2, bit 6, NTSC: bit 15 PAL: group 2, bit 5, NTSC: bit 14 PAL: group 2, bit 4, NTSC: bit 13 PAL: group 1, bit 3, NTSC: bit 12 PAL: group 1, bit 2, NTSC: bit 11 PAL: group 1, bit 1, NTSC: bit 10 PAL: group 1, bit 0, NTSC: bit 9
Wide Screen Signalling Register 2
Address Bit Number Bit Name Default Bit
7 6 5 4 3 2 1 0
0x20
7 WSS_7 0
WSS_REG_2
6 WSS_6 0 5
Read/Write
4 WSS_4 0
Default Value = 00h
3 WSS_3 0 2 WSS_2 0 1 WSS_1 0 0 WSS_0 0
WSS_5 0
Mnemonic
WSS_7 WSS_6 WSS_5 WSS_4 WSS_3 WSS_2 WSS_1 WSS_0
Function PAL: don't care, NTSC: bit 8 PAL: don't care, NTSC: bit 7 PAL: don't care, NTSC: bit 6 PAL: don't care, NTSC: bit 5 PAL: don't care, NTSC: bit 4 PAL: don't care, NTSC: bit 3 PAL: don't care, NTSC: bit 2 PAL: don't care, NTSC: bit 1
Filter Register 0
Address Bit Number Bit Name Default Bit
7:0
0x22
7 1
CB_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 U_AMP 0 2 0 1 0 0 0
0
Mnemonic
U_AMP
Function U(Cb) amplitude coefficient
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CS4954 CS4955
Filter Register 1
Address Bit Number Bit Name Default Bit
7:0
0x23
7 1
CR_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 V_AMP 0 2 0 1 0 0 0
0
Mnemonic
V_AMP
Function V(Cr) amplitude coefficient
Filter Register 2
Address Bit Number Bit Name Default Bit
7:0
0x24
7 1
Y_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 Y_AMP 0 2 0 1 0 0 0
0
Mnemonic
Y_AMP
Function Luma amplitude coefficient
Filter Register 3
Address Bit Number Bit Name Default Bit
7:0
0x25
7 1
R_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 R_AMP 0 2 0 1 0 0 0
0
Mnemonic
R_AMP
Function Red amplitude coefficient
Filter Register 4
Address Bit Number Bit Name Default Bit
7:0
0x26
7 1
G_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 G_AMP 0 2 0 1 0 0 0
0
Mnemonic
G_AMP
Function Green amplitude coefficient
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CS4954 CS4955
Filter Register 5
Address Bit Number Bit Name Default Bit
7:0
0x27
7 1
B_AMP
6 0 5 0
Read/Write
4
Default Value = 80h
3 B_AMP 0 2 0 1 0 0 0
0
Mnemonic
B_AMP
Function Blue amplitude coefficient
Filter Register 6
Address Bit Number Bit Name Default Bit
7:0
0x28
7 0
Bright_Offsett
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 0 0 0
BRIGHTNESS_OFFSET
Mnemonic
BRGHT_OFFSET
Function Brightness adjustment ( range: -128 to +127)
Teletext Register 0
Address Bit Number Bit Name Default Bit
7:0
0x29
7 1
TTXHS
6 0 5 1
Read/Write
4
Default Value = A1h
3 TTXHS 0 2 0 1 0 0 1
0
Mnemonic
TTXHS
Function Start of teletext request pulses or start of window
Teletext Register 1
Address Bit Number Bit Name Default Bit 0x2A
7 0
TTXHD
6 0 5 0
Read/Write
4
Default Value = 02h
3 TTXHD 0 2 0 1 1 0 0
0
Mnemonic
Function If TTX_WINDOW = 0 then this register is used as the Pipeline delay between TTXRQ and TTXDAT signals in the teletext source. User programmable delay step of 37 ns per LSB. If TTX_WINDOW = 1 then this register is used as the 8 LSBs of the teletext insertion windows; the 3 MSBs are located in register 0x31. (register 0x31 bit 3)
7:0
TTXHD
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CS4954 CS4955
Teletext Register 2
Address Bit Number Bit Name Default Bit
7:0
0x2B
7 0
TTXOVS
6 0 5 0
Read/Write
4
Default Value = 00h
3 TTXOVS 0 2 0 1 0 0 0
0
Mnemonic
TTXOVS
Function Start of teletext line window in odd field
Teletext Register 3
Address Bit Number Bit Name Default Bit
7:0
0x2C
7 0
TTXOVE
6 0 5 0
Read/Write
4
Default Value = 00h
3 TTXOVE 0 2 0 1 0 0 0
0
Mnemonic
TTXOVE
Function End of teletext line window in odd field
Teletext Register 4
Address Bit Number Bit Name Default Bit
7:0
0x2D
7 0
TTXEVS
6 0 5 0
Read/Write
4
Default Value = 00h
3 TTXEVS 0 2 0 1 0 0 0
0
Mnemonic
TTXEVS
Function Start of teletext line window in even field
Teletext Register 5
Address Bit Number Bit Name Default Bit
7:0
0x2E
7 0
TTXEVE
6 0 5 0
Read/Write
4
Default Value = 00h
3 TTXEVE 0 2 0 1 0 0 0
0
Mnemonic
TTXEVE
Function End of teletext line window in even field
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DS278F6
CS4954 CS4955
Teletext Register 6
Address Bit Number Bit Name Default Bit
7:0
0x2F
7 0
TTX_DIS1
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 0 0 0
TTX_LINE_DIS1
Mnemonic
Function
Teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all TTX_LINE_DIS1 eight lines are disabled), (MSB is for line 5, LSB is for line 12)
Teletext Register 7
Address Bit Number Bit Name Default Bit
7:0
0x30
7 0
TTX_DIS2
6 0 5 0
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 0 0 0
TTX_LINE_DIS2
Mnemonic
Function
Teletext disable bits corresponding to the lines 13-20 respectively, (11111111=all TTX_LINE_DIS2 eight lines are disabled, (MSB is for line 13, LSB is for line 20)
Teletext Register 8
Address Bit Number Bit Name Default Bit
7:5 4 3 2:0
0x31
7 0
TTX_DIS3
6 TTXHD 0 0 5
Read/Write
4 0
Default Value = 00h
3 0 2 0 1 TTX_LINE_DIS3 0 0 0
RESERVED TTX_WINDOW
Mnemonic
TTXHD Reserved TTX_WINDOW TTX_LINE_DIS3
Function If TTX_WINDOW = 0 these 3 bits are unused. If TTX_WINDOW = 1 these 3 bits are the MSBs of the register 0x2A; they are used to specify the length of the teletext insertion window Selects between TTXRQ (= 0) pulsation or TTXRQ (= 1) Window mode Teletext disable bits corresponding to the lines 13-20 respectively, (111=all three lines are disabled), (MSB is for line 21, LSB is for line 23)
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CS4954 CS4955
Interrupt Register 0
Address Bit Number Bit Name Default Bit
7:3 2 1 0 INT_21_EN INT_284_EN INT_V_EN
0x32
7 0
INT_EN
6 0 5
Read/Write
4 0
Default Value = 00h
3 0 2 INT_21_EN 0 1 INT_284_EN 0 0 INT_V_EN 0
RESERVED 0
Mnemonic reserved
Function interrupt enable for closed caption line 21 interrupt enable for closed caption line 284 interrupt enable for new video field
Interrupt Register 1
Address Bit Number Bit Name Default Bit
7:3 2 1 0 CLR_INT_21 CLR_INT_284 CLR_INT_V
0x33
7 0
INT_CLR
6 0 5
Read/Write
4 0 3 0
Default Value = 00h
2 CLR_INT_21 0 1 CLR_INT_284 0 0 CLR_INT_V 0
RESERVED 0
Mnemonic reserved
Function clear interrupt for closed caption line 21 (INT 21) clear interrupt for closed caption line 284 (INT_284) clear interrupt for new video field (INT_V)
Status Register 0
Address Bit Number Bit Name Default Bit
5 4 3 2:0
0x34
5 INT_21 0
STATUS_0
4 INT_284 0
Read Only
3 INT_V 0
Default Value = 00h
2:0 FLD 0
Mnemonic
INT_21 INT_284 INT_V FLD_ST
Function Interrupt flag for line 21 (closed caption) complete Interrupt flag for line 284 (closed caption) complete Interrupt flag for video field change Field Status bits(001 = field 1,000 = field 8)
Status Register 1
Address Bit Number Bit Name Default Bit
7:0
0x5A 7
0
STATUS_1 6
0
Read only 5
0
Default Value = 04h 4
DEVICE_ID 0 0 1 0 0
3
2
1
0
Mnemonic
DEVICE_ID
Function Device identification: CS4954: 0000 0100, CS4955: 0000 0101 DS278F6
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CS4954 CS4955
9. BOARD DESIGN AND LAYOUT CONSIDERATIONS
Place all decoupling caps as close as possible to the device. Surface mount capacitors generally have lower inductance than radial lead or axial lead components. Surface mount caps should be place on the component side of the PCB to minimize inductance caused by board vias. Any vias, especially to ground, should be as large as possible to reduce their inductive effects.
The printed circuit layout should be optimized for lowest noise on the CS4954/5 placed as close to the output connectors as possible. All analog supply traces should be as short as possible to minimize inductive ringing. A well designed power distribution network is essential in eliminating digital switching noise. The ground planes must provide a low-impedance return path for the digital circuits. A PC board with a minimun of four layers is recommended. The ground layer should be used as a shield to isolate noise from the analog traces. The top layer (1) should be reserved for analog traces but digital traces can share this layer if the digital signals have sufficiently slow edges and edge rates and switch little current or if they are separated from the analog traces by a signigicant distance (dependent on their frequency content and current). The PCB layer "stack up" (from top to bottom) should be: analog/digital signal then ground plane followed by the analog power plane and the digital signal layer.
9.3
Digital Interconnect
The digital inputs and outputs of the CS4954/5 should be isolated from the analog outputs as much as possible. Use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. Noise from the digital section is related to the digital edge rates and rise/fall times. Ringing, overshoot, undershoot, and ground bounce are all related to edge rise/fall times. Use lower speed logic such as HCMOS for the host port interface to reduce switching noise. For the video input ports, higher speed logic is required, but use logic that produces the slowest practical edge rise/fall times to reduce noise. It is also important to match the source impedance, line impedance, and load impedance as much as possible. Generally, if the line length is greater than one fourth of the signal wavelength or period (from = /f), a line termination is necessary. Ringing can also be reduced by damping the line with a series resistor (22-150 ). Under extreme cases, it may be advisable to use microstrip techniques to further reduce radiated switching noise if there are very fast (<2 ns) rise/fall times in the system. If microstrip techniques are used, split the analog and digital ground planes and use proper RF decoupling techniques.
9.1
Power and Ground Planes
The power and ground planes need isolation gaps of at least 0.05" to minimize digital switching noise effects on the analog signals and components. A split analog/digital ground plane should be connected at one location as close as possible to the CS4954/5.
9.2
Power Supply Decoupling
Start by reducing power supply ripple and wiring harness inductance by placing a large (33-100 uF) capacitor as close to the power entry point as possible. Use separate power planes or traces for the digital and analog sections even if they use the same supply. If necessary, further isolate the digital and analog power supplies by using ferrite beads on each supply branch followed by a low ESR capacitor.
DS278F6
9.4
Analog Interconnect
The CS4954/5 should be located as close as possible the output connectors to minimize noise pickup and reflections due to impedance mismatch. All unused analog outputs should be placed in shutdown.
53
CS4954 CS4955
This reduces the total power that the CS4954/5 requires, and eliminates the impedance mismatch presented by an unused connector. The analog outputs should not overlay the analog power plane in order to maximize high frequency power supply rejection. on the video out lines. Therefore, it is also a good idea to use output filters that are AC coupled to avoid any problems.
9.6
ESD Protection
9.5
Analog Output Protection
To minimize the possibility of damage to the analog output sections, make sure that all video connectors are well grounded. The connector should have a good DC ground path to the analog and digital power supply grounds. If no DC (and low frequency) path is present, improperly grounded equipment can impose damaging reverse currents
All MOS devices are sensitive to Electro Static Discharge (ESD). When manipulating these devices, proper ESD precautions are recommended to avoid performance degradation or permanent dramage.
9.7
External DAC Output Filter
If an output filter is required, the low pass filter shown in Figure 30 can be used.
NOTE: C2 should be chosen so that C1 = C2 + Ccable
2.2H
IN 330pF 33pF 220pF OUT
C1
C2
Figure 30. External Low Pass Filter
54
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CS4954 CS4955
Vcc
L1 Ferrite Bead 4.7 F 0.1 F
15 NC 14 16
17 XTALIN XTALOUT PADDR VDD
36 41 46 VAA VREF 38
RED 39 30 31 Gpio port Vcc 26-19 27 28 1.5 k 110 32 IC Controller 33 110 27 MHz Clock Pixel Data 29 8 8-1 CLK V[7:0] C 47 TTXDAT TTXRQ PDAT[7:0] RD WR CVBS 44 SDA SCL BLUE 43 GREEN 40
75 or 300 75 or 300 75 or 300 Composite Video Connector 75 or 300 * Identical load resistors are to be used at the receive 75 or 300 device. S-Video Connector
to SCART Connector
1.5 k
CS4954 CS4955
Y
48
9 10 11
FIELD/CB HSYNC /CB INT 12 INT 34 RESET 37 ISET GNDA 35 42 45
75 or 300
VSYNC 13 TEST GNDD 18
4 k1%
Figure 31. Typical Connection Diagram
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CS4954 CS4955
10. PIN DESCRIPTION
B CVBS GNDA VAA C Y V0 V1 V2 V3 V4 V5 V6 V7 FIELD /CB HSYNC/CB VSYNC INT TEST XTAL_OUT XTAL_IN PADR VDD GNDD
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33
CS4954-CQZ CS4955-CQZ 48-Pin TQFP Top View
32 31 30 29 28 27 26 25
GNDA VAA G R VREF ISET VAA GNDA RESET SCL SDA TTXRQ TTXDAT CLKIN WR RD PDAT0 PDAT1 PDAT2 PDAT3 PDAT4 PDAT5 PDAT6 PDAT7
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Pin Name V [7:0] CLK PADDR XTAL_IN XTAL_OUT HSYNC/CB VSYNC FIELD/CB(1) RD WR PDAT [7:0] SDA SCL CVBS Y C R G B VREF ISET TTXDAT TTXRQ INT RESET TEST VAA GNDD VDD GNDA Pin Number 8, 7, 6, 5, 4, 3, 2, 1 29 16 15 14 10 11 9 27 28 19, 20, 21, 22, 23, 24, 25, 26 32 33 44 48 47 39 40 43 38 37 30 31 12 34 13 36, 41, 46 18 17 35, 42, 45 Type IN IN IN IN OUT I/O I/O OUT(1) IN IN I/O I/O IN CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT I/O Description Digital video data inputs 27 MHz input clock Address enable line subcarrier crystal input subcarrier crystal output Active low horizontal sync, or composite blank signal Active low vertical sync. Video field ID. Selectable polarity or composite blank Host parallel port read strobe, active low Host parallel port write strobe, active low
Host parallel port/ general purpose I/O IC data IC clock input Composite video output Luminance analog output Chrominance analog output Red analog output Green analog output Blue analog output Internal voltage reference output or external reference input CURRENT DAC current set IN Teletext data input OUT Teletext request output OUT Interrupt output, active high IN Active low master RESET IN PS PS PS PS TEST pin. Ground for normal operation + 5 V or + 3.3 V supply (must be same as VDD) Ground +5 V or 3.3 V supply (must be same as VAA) Ground
Table 10. Device Pin Descriptions NOTE: 1. The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not toggle in SLAVE mode and its output state should be considered random.
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11. PACKAGE DRAWING
48L TQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm DIM A A1 B D D1 E E1 e* L Controlling dimension is mm. JEDEC Designation: MS026 MILLIMETERS MIN MAX --1.60 0.05 0.15 0.17 0.27 8.70 9.30 6.90 7.10 8.70 9.30 6.90 7.10 0.40 0.60 0.45 0.75 0.00 7.00
MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000
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12. REVISION HISTORY
Revision F1 F2 F3 F4 Date July 1999 April 2004 September 2004 August 2005 Initial release Corrected List of Figures Added lead free package option (CS4955). Updated ordering information. Added lead-free package for CS4954; deleted CQ packages; updated Revision History and Legal notice. - Changed operating temperature range in "Description" on page 1 to -40 to 85 C - Changed operating temperature range in "RECOMMENDED Operating Conditions" on page 6 - Changed operating temperature range in "Ordering Information" on page 2. - Changed Allowable Junction Temperature specification and added note to "Thermal Characteristics" on page 6 - Revised description in "Progressive Scan" on page 18. - Revised descriptions in "Luminance DAC" on page 32, "Chrominance DAC" on page 33, "CVBS DAC" on page 33, "Red DAC" on page 33, "Green DAC" on page 33 and "Blue DAC" on page 33. - Added "DAC Useage Rules" on page 34 and revised text in that section. - Revised bit 3 "Function" description for "Control Register 0" on page 38. - Revised "Function" descriptions for "Control Register 5" on page 42. - Added note to clarify DAC loading to Figure 31 on page 55. - Revised text throughout the document to correct content and grammar. Change
F5
July 2006
F6
Added "This port can operate in standard (up to 100 kb/sec) or fast (up to 400 kb/sec) September 2006 modes" in Section 4.10 on page 14. Updated SCL Frequency values in Timing Characteristics table on page 9.
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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. Macrovision is a trademark of Macrovision Corporation. It is hereby notified that a third-party license from Macrovision Corporation is necessary to distribute software of Macrovision Corporation in any finished end-user or ready-to-use final product.
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Price & Availability of CS4954-CQZ

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