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| FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 1.0 * * * * * * * * * * 2 Features Just-in-time customization of clock frequencies via internal non-volatile 128-bit serial EEPROM I Ca-bus serial interface Three on-chip PLLs with programmable Reference and Feedback Dividers Four independently programmable muxes and post dividers Programmable power-down of all PLLs and output clock drivers Tristate outputs for board testing One PLL and two mux/post-divider combinations can be modified via SEL_CD input 5V to 3.3V operation Accepts 5MHz to 27MHz crystal resonators ROM-based device available for cost reduction migration path - contact your AMI sales representative for more information 2.0 Description The FS6370 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three EEPROM-programmable phaselocked loops (PLLs) driving four programmable muxes and post dividers provide a high degree of flexibility. An internal EEPROM permits just-in-time factory programming of devices for end user requirements. Figure 1: Pin Configuration VSS SEL_CD PD/SCL VSS XIN XOUT OE/SDA VDD 1 2 3 16 15 14 VDD CLK_A VDD CLK_B CLK_C VSS CLK_D MODE FS6370 4 5 6 7 8 13 12 11 10 9 16-pin (0.150") SOIC Figure 2: Block Diagram XIN XOUT Reference Oscillator PLL A Mux A Post Divider A CLK_A MODE PD/SCL Power Down Control PLL B I2C-bus Interface Mux B Post Divider B CLK_B OE/SDA PLL C EEPROM Mux C Post Divider C CLK_C Mux D SEL_CD Post Divider D CLK_D FS6370 I2C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc., reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TYPE P DI DI U NAME VSS SEL_CD PD/SCL VSS XIN XOUT OE/SDA VDD MODE CLK_D VSS CLK_C CLK_B VDD CLK_A VDD Ground DESCRIPTION Selects one of two programmed PLL C, Mux C/D, and Post Divider C/D combinations Power-Down Input (Run Mode) or Serial Interface Clock Input (Program Mode) Ground Crystal Oscillator Feedback Crystal Oscillator Drive Output Enable Input (Run Mode) or Serial Interface Data Input/Output (Program Mode) Power Supply (5V to 3.3V) Selects either Program Mode (low) or Run Mode (high) D Clock Output Ground C Clock Output B Clock Output Power Supply (5V to 3.3V) A Clock Output Power Supply (5V to 3.3V) U P AI AO DI O P DIU DO P DO DO P DO P U 3.0 3.1 Functional Block Description Phase Locked Loops Each of the three on-chip phase-locked loops (PLLs) is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a Reference Divider, a Phase-Frequency Detector (PFD), a charge pump, an internal loop filter, a Voltage-Controlled Oscillator (VCO), and a Feedback Divider. During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the Reference Divider. The divider value is often referred to as the modulus, and is denoted as NR for the Reference Divider. The divided reference is fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the Feedback Divider (the modulus is denoted by NF) to close the loop. Figure 3: PLL Block Diagram LFTC REFDIV[7:0] CP Loop Filter fREF Reference Divider (NR) PhaseFrequency Detector fPD UP Charge Pump DOWN FBKDIV[10:0] Voltage Controlled Oscillator fVCO Feedback Divider (NF) 2 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is Figure 4: Feedback Divider fVCO Dual Modulus Prescaler FBKDIV[2:0] M Counter fPD aeN f VCO = f REF c F cN eR o /. / o FBKDIV[10:3] 3.1.1 Reference Divider The Reference Divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The Reference Divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h. 3.1.2 Feedback Divider The Feedback Divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable Feedback Divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight prescaler could have been used in the Feedback Divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input-frequency-to-output-frequency ratio without making both the Reference and Feedback Divider values comparatively large. Generally, very large values are undesirable as they degrade the bandwidth of the PLL, increasing phase jitter and acquisition time. To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-modulus prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A-counter, and the cycle begins again. Note that N=8, and A and M are binary numbers. A Counter Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of the feedback divider becomes MxN. Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-byN+1 for its first divide cycle and then revert to a divide-byN. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the Feedback Divider. The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the Feedback Divider modulus is equal to MxN+A, where AM. 3.1.3 Feedback Divider Programming For proper operation of the Feedback Divider, the Acounter must be programmed only for values that are less than or equal to the M-counter. Therefore, not all divider moduli below 56 are available for use. This is shown in Table 2. Above a modulus of 56, the Feedback Divider can be programmed to any value up to 2047. Table 2: Feedback Divider Modulus Under 56 M-COUNTER: FBKDIV[10:3] 00000001 00000010 00000011 00000100 00000101 00000110 00000111 A-COUNTER: FBKDIV[2:0] 000 8 16 24 32 40 48 56 001 9 17 25 33 41 49 57 010 18 26 34 42 50 58 011 27 35 43 51 59 100 36 44 52 60 101 45 53 61 110 54 62 111 63 FEEDBACK DIVIDER MODULUS 3 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 3.2 Post Divider Muxes 4.1 MODE Pin As shown in Figure 2, a mux in front of each post divider stage can select from any one of the three PLL frequencies or the reference frequency. The mux selection is controlled by bits in the EEPROM or the control registers. The input frequency on two of the four multiplexers (Muxes C and D in Figure 2) can be altered without reprogramming by a logic-level input on the SEL_CD pin. 3.3 Post Dividers A post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to aeN f CLK = f REF c F cN eR oae 1 /c /c N oe P o / / o The MODE pin controls the mode of operation. A logiclow places the FS6370 in Program Mode. A logic-high puts the device in Run Mode. A pull-up on this pin defaults the device into Run Mode. Reprogramming of either the control registers or the EEPROM is permitted at any time if the MODE pin is a logic-low. Note, however, that a logic-high state on the MODE pin is latched so that only one transfer of EEPROM data to the FS6370 control registers can occur. If a second transfer of EEPROM data into the FS6370 is desired, power (VDD) must be removed and reapplied to the device. The MODE pin also controls the function of the PD/SCL and OE/SDA pins. In Run Mode, these two pins function as power-down (PD) and output enable (OE) controls. In 2 Program Mode, the pins function as the I C interface for clock (SCL) and data (SDA). where NP is the post divider modulus. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. The modulus on two of the four post dividers (Post Dividers C and D in Figure 2) can be altered without reprogramming by a logic level on the SEL_CD pin. 4.2 SEL_CD Pin 4.0 Device Operation The FS6370 has two modes of operation: Program Mode, during which either the EEPROM or the FS6370 control registers can be programmed directly with the desired PLL settings, and Run Mode, where the PLL settings stored the EEPROM are transferred to the FS6370 control registers on power-up, and the device then operates based on those settings. Note that the EEPROM locations are not physically the same registers used to control the FS6370. Direct access to either the EEPROM or the FS6370 control registers is achieved in Program Mode. The EEPROM register contents are automatically transferred to the FS6370 control registers in normal device operation (Run Mode). The SEL_CD pin provides a way to alter the operation of PLL C, Muxes C and D, and Post Dividers C and D without having to reprogram the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3. Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-divider(s) is/are altered. 4.3 Oscillator Overdrive For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN must be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times, and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01F or 0.1F capacitor. A minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer. 4 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 5.0 Run Mode 6.1 EEPROM Programming If the MODE pin is set to a logic-high, the device enters the Run Mode. The high state is latched (see MODE Pin). The FS6370 then copies the stored EEPROM data into its control registers and begins normal operation based on that data when the self-load is complete. The self-load process takes about 89,000 clocks of the crystal oscillator. During the self-load time, all clock outputs are held low. At a reference frequency of 27MHz, the self-load takes about 3.3ms to complete. If the EEPROM is empty (all zeros), the crystal reference frequency provides the clock for all four outputs. No external programming access to the FS6370 is possible in Run Mode. The dual-function PD/SCL and OE/SDA pins become a power-down (PD) and output enable (OE) control, respectively. Data must be loaded into the EEPROM in a mostsignificant-bit (MSB) to least-significant-bit (LSB) order. The register map of the EEPROM is noted in Table 3. The device address of the EEPROM is: A6 1 A5 0 A4 1 A3 0 A2 X A1 X A0 X 5.1 Power-Down and Output Enable A logic-high on the PD/SCL pin powers down only those portions of the FS6370 which have their respective power-down control bits enabled. Note that the PD/SCL pin has an internal pull-up. When a Post Divider is powered down, the associated output driver is forced low. When all PLLs and Post Dividers are powered down the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high. A logic-low on the OE/SDA pin tristates all output clocks. Note that this pin has an internal pull-up. 6.1.1 Write Operation The EEPROM can only be written to with the Random Register Write Procedure (see Page 8). The procedure consists of the device address, the register address, a R/W bit, and one byte of data. Following the STOP condition, the EEPROM initiates its internally timed 4ms write cycle, and commits the data byte to memory. No acknowledge signals are generated during the EEPROM internal write cycle. If a stop bit is transmitted before the entire write command sequence is complete, then the command is aborted and no data is written to memory. If more than eight bits are transmitted before the stop bit is sent, then the EEPROM will clear the previously loaded data byte and will begin loading the data buffer again. 6.1.2 Acknowledge Polling The EEPROM does not acknowledge while it internally commits data to memory. This feature can be used to increase data throughput by determining when the internal write cycle is complete. The process is to initiate the Random Register Write Procedure with a START condition, the EEPROM device address, and the write command bit (R/W=0). If the EEPROM has completed its internal 4ms write cycle, the EEPROM will acknowledge on the next clock, and the write command can continue. If the EEPROM has not completed the internal 4ms write cycle, the Random Register Write Procedure must be restarted by sending the START condition, device address, and R/W bit. This sequence must be repeated until the EEPROM acknowledges. 6.1.3 Read Operation The EEPROM supports both the Random Register Read Procedure and the Sequential Register Read Procedure (both are outlined on Page 8). 6.0 Program Mode If the MODE pin is logic-low, the device enters the Program Mode. All internal registers are cleared to zero, delivering the crystal frequency to all outputs. The device allows programming of either the internal 128-bit 2 EEPROM or the on-chip control registers via I C control over the PD/SCL and OE/SDA pins. The EEPROM and the FS6370 act as two separate parallel devices on the 2 same on-chip I C-bus. Choosing either the EEPROM or 2 the device control registers is done via the I C device address. The dual-function PD/SCL and OE/SDA pins become the serial data I/O (SDA) and serial clock input (SCL) for 2 normal I C communications. Note that power-down and output enable control via the PD/SCL and OE/SDA pins is not available. 5 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC For sequential read operations, the EEPROM has an internal address pointer that increments by one at the end of each read operation. The pointer directs the EEPROM to transmit the next sequentially addressed data byte, allowing the entire memory contents to be read in one operation. 7.0 Cost Reduction Migration Path The FS6370 is compatible with the programmable register-based FS6377 or a fixed-frequency ROM-based clock generator. Attention should be paid to the board layout if a migration path to either of these devices is desired. 6.2 Direct Register Programming The FS6370 control registers may be directly accessed by simply using the FS6370 device address in the read or write operations. The operation of the device will follow the register values. The register map of the FS6370 is identical to that of the EEPROM shown in Table 3. The FS6370 supports the Random Read and Write procedures, as well as the Sequential Read and Write procedures described on Page 7. The device address for the FS6370 is: A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 0 7.1 Programming Migration Path 2 If the design can support I C programming overhead, a cost reduction from the EEPROM-based FS6370 to the register-based FS6377 is possible. Figure 5 shows the five pins that may not be compatible between the various devices if programming of the FS6370 or the FS6377 is desired. Figure 5: FS6370 to FS6377 (FS6370) VSS SDA (FS6377) 1 (FS6370) 16 15 VDD SCL (FS6377) PD/SCL (FS6370) SEL_CD VSS XIN 2 CLK_A VDD CLK_B CLK_C VSS CLK_D MODE ADDR (FS6370) FS6370 / FS6377 3 14 13 12 11 10 9 (FS6377) PD 4 5 6 7 OE/SDA OE (FS6370) XOUT (FS6377) VDD 8 (FS6377) 7.2 Non-Programming Migration Path If the design has solidified on a particular EEPROM programming pattern, the EEPROM pattern can be hardcoded into a ROM-based device. For high-volume requirements, a ROM-based device offers significant cost savings over the FS6370. Contact an AMI Sales representative for more detail. 6 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion. 8.1.5 Acknowledge When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. 8.0 I C-bus Control Interface 2 This device is a read/write slave device 2 meeting all Philips I C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. 2 I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-low corresponds to ground (VSS). 8.1 Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined 2 by the I C-bus protocol. 8.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 8.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 8.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 8.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data 7 8.2 I2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital inter2 face. The device accepts the following I C-bus commands. 8.2.1 Device Address After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W bit. The device address of the FS6370 is: A6 1 A5 0 A4 1 A3 1 A2 1 A1 0 A0 0 Any one of eight possible addresses are available for the EEPROM. The least significant three bits are don't care's. A6 1 A5 0 A4 1 A3 0 A2 X A1 X A0 X FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a Sequential Register Write. 8.2.5 Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the Random Register Read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all sixteen bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. 8.2.2 Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a Register Write, the data that has been transferred is ignored. 8.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition. 8.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the Random Register Write if several registers must be written. 8 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Figure 6: Random Register Write Procedure S DEVICE ADDRESS WA REGISTER ADDRESS A DATA AP 7-bit Receive Device Address START Command Register Address Acknowledge WRITE Command From bus host to device Data Acknowledge STOP Condition Acknowledge From device to bus host Figure 7: Random Register Read Procedure S DEVICE ADDRESS WA REGISTER ADDRESS AS DEVICE ADDRESS RA DATA AP 7-bit Receive Device Address START Command Register Address Acknowledge WRITE Command From bus host to device 7-bit Receive Device Address Repeat START Acknowledge From device to bus host Data Acknowledge READ Command STOP Condition NO Acknowledge Figure 8: Sequential Register Write Procedure S DEVICE ADDRESS WA REGISTER ADDRESS A DATA A DATA A DATA AP 7-bit Receive Device Address START Command Register Address Acknowledge WRITE Command From bus host to device Data Acknowledge Data Acknowledge Acknowledge Data Acknowledge STOP Command From device to bus host Figure 9: Sequential Register Read Procedure S DEVICE ADDRESS WA REGISTER ADDRESS AS DEVICE ADDRESS RA DATA A DATA AP 7-bit Receive Device Address START Command Register Address Acknowledge WRITE Command From bus host to device 7-bit Receive Device Address Repeat START Acknowledge From device to bus host Data Acknowledge READ Command Acknowledge Data NO Acknowledge STOP Command 9 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 9.0 Programming Information Table 3: Register Map (Note: All Register Bits are cleared to zero on power-up.) ADDRESS BYTE 15 BYTE 14 BYTE 13 BYTE 12 BYTE 11 BYTE 10 BYTE 9 BYTE 8 BYTE 7 BYTE 6 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE 0 MUX_A[1:0] PDPLL_A FBKDIV_A[7:3] M-Counter REFDIV_A[7:0] MUX_B[1:0] PDPLL_B MUX_C1[1:0] (selected via SEL_CD = 0) PDPLL_C BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 PDPOST_D BIT 2 PDPOST_C BIT 1 PDPOST_B BIT 0 PDPOST_A MUX_D2[1:0] (selected via SEL_CD = 1) MUX_C2[1:0] (selected via SEL_CD = 1) POST_D2[3:0] (selected via SEL_CD = 1) POST_D1[3:0] (selected via SEL_CD = 0) POST_B[3:0] MUX_D1[1:0] (selected via SEL_CD = 0) Reserved (0) LFTC_C2 (SEL_CD=1) CP_C2 (SEL_CD=1) POST_C2[3:0] (selected via SEL_CD = 1) POST_C1[3:0] (selected via SEL_CD = 0) POST_A[3:0] FBKDIV_C2[10:8] M-Counter (selected via SEL_CD pin = 1) FBKDIV_C2[2:0] A-Counter (selected via SEL_CD pin = 1) FBKDIV_C2[7:3] M-Counter (selected via SEL_CD pin = 1) REFDIV_C2[7:0] (selected via SEL_CD pin = 1) LFTC_C1 (SEL_CD=0) CP_C1 (SEL_CD=0) FBKDIV_C1[10:8] M-Counter (selected via SEL_CD = 0) FBKDIV_C1[2:0] A-Counter (selected via SEL_CD = 1) FBKDIV_C1[7:3] M-Counter (selected via SEL_CD = 0) REFDIV_C1[7:0] (selected via SEL_CD = 0) LFTC_B CP_B FBKDIV_B[10:8] M-Counter FBKDIV_B[2:0] A-Counter FBKDIV_B[7:3] M-Counter REFDIV_B[7:0] LFTC_A CP_A FBKDIV_A[10:8] M-Counter FBKDIV_A[2:0] A-Counter 9.1 Control Bit Assignments If the power-down bit contains a zero, the related circuit will continue to function regardless of the PD pin state. If any PLL control bit is altered during device operation, including those bits controlling the Reference and Feedback Dividers, the output frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time constant. However, any programming changes to any Mux or Post Divider control bits will cause a glitch on an operating clock output. 9.1.1 Power Down All power-down functions are controlled by enable bits. That is, the bits select which portions of the FS6370 to power-down when the PD input is asserted. If the powerdown bit contains a one, the related circuit will shut down if the PD pin is high (Run Mode only). When the PD pin is low, power is enabled to all circuits. 10 Table 4: Power-Down Bits NAME PDPLL_A (Bit 21) DESCRIPTION Power-Down PLL A Bit = 0 Bit = 1 PDPLL_B (Bit 45) Bit = 0 Bit = 1 PDPLL_C (Bit 69) Reserved (0) (Bit 69) Bit = 0 Bit = 1 Power On Power Off Power On Power Off Power On Power Off Power-Down PLL B Power-Down PLL C Set these reserved bits to zero (0) FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 5: Power-Down Bits, continued NAME PDPOST_A (Bit 120) DESCRIPTION Power-Down POST divider A Bit = 0 Bit = 1 Bit = 0 Bit = 1 PDPOSTC (Bit 122) Bit = 0 Bit = 1 PDPOSTD (Bit 123) Bit = 0 Bit = 1 Power On Power Off Power On Power Off Power On Power Off Power On Power Off Table 7: Post Divider Control Bits NAME POST_A[3:0] (Bits 99-96) POST_B[3:0] (Bits 103-100) POST_C1[3:0] (Bits 107-104) POST_C2[3:0] (Bits 115-112) POST_D1[3:0] (Bits 111-108) POST_D2[3:0] (Bits 119-116) DESCRIPTION POST divider A (see Table 8) POST divider B (see Table 8) POST divider C1 (see Table 8) selected when the SEL_CD pin = 0 POST divider C2 (see Table 8) selected when the SEL_CD pin = 1 POST divider D1 (see Table 8) selected when the SEL_CD pin = 0 POST divider D2 (see Table 8) selected when the SEL_CD pin = 1 Power-Down POST divider B PDPOST_B (Bit 121) Power-Down POST divider C Power-Down POST divider D Table 8: Post Divider Modulus Table 6: Divider Control Bits NAME REFDIV_A[7:0] (Bits 7-0) REFDIV_B[7:0] (Bits 31-24) REFDIV_C1[7:0] (Bits 55-48) REFDIV_C2[7:0] (Bits 79-72) FBKDIV_A[10:0] (Bits 18-8) DESCRIPTION REFerence DIVider A (NR) REFerence DIVider B (NR) REFerence DIVider C1 (NR) selected when the SEL_CD pin = 0 REFerence DIVider C2 (NR) selected when the SEL_CD pin = 1 FeedBacK DIVider A (NF) FBKDIV_A[2:0] FBKDIV_A[10:3] FBKDIV_B[10:0] (Bits 42-32) A-Counter Value M-Counter Value BIT [3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT [2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT [1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT [0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DIVIDE BY 1 2 3 4 5 6 8 9 10 12 15 16 18 20 25 50 FeedBacK DIVider B (NF) FBKDIV_B[2:0] FBKDIV_B[10:3] A-Counter Value M-Counter Value FBKDIV_C1[10:0] (Bits 66-56) FeedBacK DIVider C1 (NF) selected when the SEL_CD pin = 0 FBKDIV_C1[2:0] FBKDIV_C1[10:3] A-Counter Value M-Counter Value FBKDIV_C2[10:0] (Bits 90-80) FeedBacK DIVider C2 (NF) selected when the SEL_CD pin = 1 FBKDIV_C2[2:0] FBKDIV_C2[10:3] A-Counter Value M-Counter Value 11 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 9: PLL Tuning Bits NAME DESCRIPTION Loop Filter Time Constant A LFTC_A (Bit 20) Bit = 0 Bit = 1 LFTC_B (Bit 44) Short Time Constant: 7s Long Time Constant: 20s Table 10: Mux Select Bits NAME DESCRIPTION MUX A frequency select Bit 23 MUX_A[1:0] (Bits 23-22) 0 0 1 1 Bit 47 MUX_B[1:0] (Bits 47-46) 0 0 1 1 Bit 22 0 1 0 1 Bit 46 0 1 0 1 Reference Frequency PLL A Frequency PLL B Frequency PLL C Frequency Reference Frequency PLL A Frequency PLL B Frequency PLL C Frequency Loop Filter Time Constant B Bit = 0 Bit = 1 Short Time Constant: 7s Long Time Constant: 20s MUX B frequency select LFTC_C1 (Bit 68) Loop Filter Time Constant C1 selected when the SEL_CD pin = 0 Bit = 0 Bit = 1 Short Time Constant: 7s Long Time Constant: 20s LFTC_C2 (Bit 92) Loop Filter Time Constant C2 selected when the SEL_CD pin = 1 Bit = 0 Bit = 1 Charge Pump A Short Time Constant: 7s Long Time Constant: 20s MUX_C1[1:0] (Bits 71-70) MUX C1 frequency select selected when the SEL_CD pin = 0 Bit 71 0 0 1 1 Bit 70 0 1 0 1 Reference Frequency PLL A Frequency PLL B Frequency PLL C Frequency CP_A (Bit 19) Bit = 0 Bit = 1 Charge Pump B Current = 2A Current = 10A MUX C2 frequency select selected when the SEL_CD pin = 1 Current = 2A Current = 10A MUX_C2[1:0] (Bits 125-124) Bit 125 0 0 1 1 Bit 124 0 1 0 1 Reference Frequency PLL A Frequency PLL B Frequency PLL C Frequency CP_B (Bit 43) Bit = 0 Bit = 1 CP_C1 (Bit 67) Charge Pump C1 selected when the SEL_CD pin = 0 Bit = 0 Bit = 1 Current = 2A Current = 10A MUX D1 frequency select selected when the SEL_CD pin = 0 Bit 95 MUX_D1[1:0] (Bits 95-94) 0 0 1 1 Bit 94 0 1 0 1 Reference Frequency PLL A Frequency PLL B Frequency PLL C Frequency CP_C2 (Bit 91) Charge Pump C2 selected when the SEL_CD pin = 1 Bit = 0 Bit = 1 Current = 2A Current = 10A MUX D2 frequency select selected when the SEL_CD pin = 1 Bit 127 MUX_D2[1:0] (Bits 127-126) 0 0 1 1 Bit 126 0 1 0 1 Reference Frequency PLL A Frequency PLL B Frequency PLL C Frequency 12 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 10.0 Electrical Specifications Table 11: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage, dc (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) SYMBOL VDD VI VO IIK IOK TS TA TJ MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 150 260 2 UNITS V V V mA mA C C C C kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 12: Operating Conditions PARAMETER Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Serial Data Transfer Rate Output Driver Load Capacitance CL SYMBOL VDD TA fXIN CXL Parallel resonant, AT cut Standard mode 10 CONDITIONS/DESCRIPTION 5V 10% 3.3V 10% MIN. 4.5 3 0 5 18 100 15 TYP. 5 3.3 MAX. 5.5 3.6 70 27 UNITS V C MHz pF kb/s pF 13 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 13: DC Electrical Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER Overall Supply Current, Dynamic Supply Current, Write Supply Current, Read Supply Current, Static Dual Function I/O (PD/SCL, OE/SDA) SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS IDD IDD(write) IDD(read) IDDL VDD = 5.5V, fCLK = 50MHz, CL = 15pF See Figure 11 for more information Additional operating current demand, EEPROM Program Mode, VDD = 5.5V Additional operating current demand EEPROM Program Mode, VDD = 5.5V VDD = 5.5V, powered down via PD pin VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V -1 -1 -20 3.85 2.52 3.85 2.52 3.85 2.52 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 43 2 1 0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 1.65 1.08 1.65 1.08 1.65 1.08 2.20 1.44 2.20 1.44 0.275 0.18 1 1 -36 26 3.0 2.4 2.0 VSS-0.3 VSS-0.3 -1 -20 -36 VDD+0.3 VDD+0.3 0.8 0.8 1 -80 -80 mA mA mA mA Run Mode (PD, OE) High-Level Input Voltage VIH Register Program Mode (SDA, SCL) EEPROM Program Mode (SDA, SCL) Run Mode (PD, OE) Low-Level Input Voltage VIL Register Program Mode (SDA, SCL) EEPROM Program Mode (SDA, SCL) Run Mode (PD, OE) Hysteresis Voltage Vhys Register Program Mode (SDA, SCL) EEPROM Program Mode (SDA, SCL) High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) IIH IIL IOL EEPROM Program Mode VIL = 0V V V V Run / Register Program Mode A A mA Run / Register Program Mode, VOL = 0.4V EEPROM Program Mode, VOL = 0.4V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V Mode and Frequency Select Inputs (MODE, SEL_CD) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) VIH VIL IIH IIL V V A A 14 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 14: DC Electrical Specifications, continued Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Drive (XOUT) High-Level Output Source Current Low-Level Output Sink Current High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current * Short Circuit Sink Current * SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS VTH IIH IIL CL(xtal) CL(XIN) VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 5.5V, oscillator powered down As seen by an external crystal connected to XIN and XOUT As seen by an external clock driver on XOUT; XIN unconnected 2.9 1.7 54 5 -25 -54 18 36 15 -75 V A mA A pF pF IOH IOL IOH IOL zOH zOL IZ ISCH ISCL VDD = V(XIN) = 5.5V, VO = 0V VDD = 5.5V, V(XIN) = VO = 5.5V VO = 2.4V VO = 0.4V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low 10 -10 21 -21 -125 23 29 27 30 -30 mA mA mA mA Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) -10 VDD = 5.5V, VO = 0V; shorted for 30s, max. VDD = VO = 5.5V, shorted for 30s, max. -150 123 10 A mA mA Figure 10: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs Voltage (V) 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 Low Drive Current (mA) MIN. 0 9 22 29 39 44 51 55 60 62 65 65 66 67 68 69 TYP. 0 11 25 34 46 52 61 66 73 77 81 83 85 87 88 89 91 MAX. 0 12 29 40 55 64 76 83 92 97 104 108 112 117 119 120 121 123 Voltage (V) 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5 High Drive Current (mA) MIN. -87 -85 -83 -80 -74 -65 -61 -53 -48 -39 -32 -21 -13 0 TYP. -112 -110 -108 -104 -97 -88 -84 -77 -71 -62 -55 -44 -36 -24 -15 0 MAX. -150 -147 -144 -139 -131 -121 -116 -108 -102 -92 -85 -74 -65 -52 -43 -28 -11 0 150 100 50 Output Current (mA) 0 -50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -100 -150 M IN -200 O utpu t V o ltag e (V ) T YP M AX The data in this table represents nominal characterization data only. 15 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Figure 11: Dynamic Current vs. Output Frequency VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz, CL = 17pF except where noted 110 100 90 Dynamic Current (mA) 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Output Frequency (MHz) All outputs off except output under test, CL = 0pF All outputs off except output under test All outputs at 200MHz except output under test All outputs at the same frequency All outputs at the same frequency, CL = 0pF All outputs at 4MHz except output under test VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, CL = 17pF except where noted 45 40 35 Dynamic Current (mA) 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Output Frequency (MHz) All outputs off except output under test All outputs off except output under test, CL = 0pF All outputs at 100MHz except output under test All outputs at the same frequency All outputs at the same frequency, CL = 0pF All outputs at 2MHz except output under test 16 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 15: AC Timing Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER Overall EEPROM Write Cycle Time Output Frequency * VCO Frequency * VCO Gain * Loop Filter Time Constant * Rise Time * Fall Time * Tristate Enable Delay * Tristate Disable Delay * Clock Stabilization Time * Divider Modulus Feedback Divider Reference Divider Post Divider SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS tWC fO fVCO AVCO LFTC bit = 0 LFTC bit = 1 tr tf tPZL, tPZH tPLZ, tPHZ tSTB Output active from power-up, RUN Mode via PD pin After last register is written, Register Program Mode See also Table 2 See also Table 8 Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 4 VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V 0.8 0.8 40 40 400 7 20 2.0 2.1 1.8 1.9 1 1 100 1 8 1 1 2047 255 50 8 8 150 100 230 170 ms MHz MHz MHz/V s ns ns ns ns s ms VO = 0.5V to 4.5V; CL = 15pF VO = 0.3V to 3.0V; CL = 15pF VO = 4.5V to 0.5V; CL = 15pF VO = 3.0V to 0.3V; CL = 15pF NF NR NP Clock Outputs (PLL A clock via CLK_A pin) Duty Cycle * 100 100 50 100 50 45 45 ps 165 110 ps 390 55 % Jitter, Long Term (y()) * tj(LT) Jitter, Period (peak-peak) * tj(P) 17 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 16: AC Timing Specifications, continued Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS Clock Outputs (PLL B clock via CLK_B pin) Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active 100 100 60 100 60 45 45 55 % Jitter, Long Term (y()) * tj(LT) On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) ps 75 120 ps 400 Jitter, Period (peak-peak) * tj(P) Clock Outputs (PLL_C clock via CLK_C pin) Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active 100 100 40 100 40 45 45 55 % Jitter, Long Term (y()) * tj(LT) On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) ps 105 120 ps 440 Jitter, Period (peak-peak) * tj(P) Clock Outputs (Crystal Oscillator via CLK_D pin) Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, No other PLLs active 14.318 14.318 14.318 14.318 14.318 45 20 55 % Jitter, Long Term (y()) * tj(LT) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, C=40MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, No other PLLs active ps 40 90 ps 450 Jitter, Period (peak-peak) * tj(P) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, C=40MHz) 18 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 17: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 5.0V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER Clock frequency Bus free time between STOP and START Set up time, START (repeated) Hold time, START Set up time, data input Hold time, data input Output data valid from clock Rise time, data and clock Fall time, data and clock High time, clock Low time, clock Set up time, STOP SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tAA tR tF tHI tLO tsu:STO SDA SDA SCL CONDITIONS/DESCRIPTION STANDARD MODE MIN. 0 4.7 4.7 4.0 250 0 3.5 1000 300 4.0 4.7 4.0 MAX. 100 UNITS kHz s s s ns s s ns ns s s s Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP SDA, SCL SDA, SCL SCL SCL Figure 12: Bus Timing Data ~ ~ SCL tsu:STA thd:STA tsu:STO ~ ~ SDA ~ ~ START ADDRESS OR DATA VALID DATA CAN CHANGE STOP Figure 13: Data Transfer Sequence tF tHI tR ~ ~ SCL tLO tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO ~ ~ SDA IN tAA tAA tBUF ~ ~ SDA OUT 19 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 11.0 Package Information Table 18: 16-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 8 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 0 MAX. 1.73 0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89 8 BASE PLANE 1 ALL RADII: 0.005" TO 0.01" R 16 E H AMERICAN MICROSYSTEMS, INC. B e A2 D A1 SEATING PLANE h x 45 7 typ. 0.050 BSC 1.27 BSC A C L Table 19: 16-pin SOIC (0.150") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air 16-pin 0.150" SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL JA L11 L12 C11 CONDITIONS/DESCRIPTION Air flow = 0 m/s Corner lead Center lead Any lead to any adjacent lead Any lead to VSS TYP. 109 4.0 3.0 0.4 0.5 UNITS C/W nH nH pF 20 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 12.0 Ordering Information 12.1 Device Ordering Codes DEVICE NUMBER FS6370 FS6370 FONT PACKAGE TYPE 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 0C to 70C (Commercial) 0C to 70C (Commercial) SHIPPING CONFIGURATION Tape-and-Reel Tubes ORDERING CODE 11575-801 11575-811 -01 -01 12.2 Demo Kit Ordering Codes KIT FOR DEVICE NUMBER: DESCRIPTION Kit includes: * Populated board with example device * Interface Cable * Demonstration Software Kit includes: * Populated board with single programming socket * Interface Cable * Demonstration Software ORDERING CODE 11575-301 FS6370-01 11575-201 FS6370-01 Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Compa2 2 nies conveys a license under Philips I C Patent Rights to use these components in an I C system, provided 2 that the system conforms to the I C Standard Specification as defined by Philips. Copyright (c) 1998, 1999 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com 21 2 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC The board schematic is shown below. Components listed with an asterisk (*) are not required in an actual application, and are used here to preserve signal integrity with the cabling associated with the board. A cabled interface between a computer parallel port (DB25 connector) and the board (J1) is provided. Components shown in dashed lines are optional, depending on the application. Contact your local sales representative for more information. 13.0 Demonstration Board and Software A simple demonstration board and Windows 3.1x/95/98based software is available from American Microsystems that illustrates the capabilities of the FS6370. The software can operate under Windows NT but cannot communicate with the board. Figure 14: Board Schematic +V +V +5V/3.3V RED TP1 +V +V +V R13 4.7k R12 4.7k R14 4.7k R11 10 +V R5 10 +V R11 4.7k J1* 1 SCL SDA ADDR/ MODE SEL +5V GND 2 3 R2 100 R3 100 R1 100 C5 2.2F U1 1 R10 100 C11 100pF C13 100pF 2 3 4 C12 100pF +V C14 100pF Y1 5 6 7 8 C1 2.2F C3 0.1F C6 0.1F C4 0.1F C2 2.2F VSS SEL_CD PD/SCL VSS XIN XOUT OE/SDA VDD VDD CLK_A VDD CLK_B 16 15 14 13 12 11 10 R7* 47 C8 10pF TP4 +V R6* 47 C7 10pF +V D2 CLK_B TP3 4 5 6 D1 CLK_A FS6370 CLK_C VSS CLK_D MODE GND BLK R4 10 TP2 +V 9 R8* 47 C9 10pF +V TP5 D3 CLK_C AMERICAN MICROSYSTEMS, INC. FS6370 BOARD R9* 47 C10 10pF TP6 D4 CLK_D 22 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC 2. Connect a power supply to the board: RED = power, BLACK = ground. 3. Connect the supplied interface cable to the parallel port (DB25 connector) and to the demo board (6-pin connector). Make sure the cable is facing away from the board. Pin 1 is the red wire per Table 20. 4. Connect the clock outputs to the target application board with a twisted-pair cable. 13.1 * * * * Demo Kit Contents Demonstration board Interface cable (DB25 to 6-pin connector) Data sheet Demonstration software, totaling 24 compressed files which will expand to 1.8MB, including fs6370.exe after installation. 13.4 13.2 * Demo Program Operation Requirements PC running MS Windows 3.1x or 95/98 with an accessible parallel (LPT1) port. Software also runs on Windows NT in a calculation mode only. 1.8MB available space on hard drive C. * 13.3 Board Setup and Software Installation Instructions 1. At the appropriate disk drive prompt (A:\) unzip the compressed demo files to a directory of your choice. Run setup.exe to install the software. Launch the fs6370.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear stating: "This version of the demo program cannot communicate with the FS6370 hardware when running on a Windows NT operating system. Do you want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only. The opening screen is shown in Figure 15. Figure 15: Opening Screen 23 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both Mux C and Mux D are also affected by the logic level on the SEL_CD pin, as are the Post Dividers C and D (see Section 4.2 for more detail). 13.4.1 Example Programming Type a value for the crystal resonator frequency in MHz in the Reference Crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 16 should appear. Type in a desired Output Clock frequency in MHz, set the operating voltage (3.3V or 5V), and the desired maximum output frequency error. Pressing Calculate Solutions generates several possible divider and VCO-speed combinations. Figure 17: Post Divider Menu Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the Post Divider B as the output divider. Notice the Post Divider box has split in two (as shown in Figure 17). The Post Divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as Mux B is the PLL C output. Clicking on Post Divider A reveals a pull-down menu provided to permit adjustment of the Post Divider value independently of the PLL screen. A typical menu is shown in Figure 17. The range of possible post divider values is also given in Table 8. Once all of the PLLs, switches, and post dividers have been set, the information can be downloaded out the PC parallel port to the FS6370 (not available on Windows NT). The EEPROM settings are shown to the left in the screen shown in Figure 15. Clicking on a register location displays a screen shown in Figure 18. Individual bits can be poked, or the entire register value can be changed. Figure 16: PLL Screen For a 100MHz output, the VCO should ideally operate at a higher frequency, and the Reference and Feedback Dividers should be as small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a Post Divider of 2 to obtain an optimal 50% duty cycle. Now choose which Mux and Post Divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv value in Solution #7 into Post Divider A and switches Mux A to take the output of PLL A. The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Note that Mux A has been switched to PLL A and the Post Divider A has the chosen 100MHz output displayed. Repeat the steps for PLL B. Figure 18: Register Screen 24 FS6370-01 EEPROM Programmable 3-PLL Clock Generator IC Table 20: Cable Interface Color Red White Green Blue Brown Black J1 1 2 3 4 5 6 DB25 2, 13 3, 12 8 5 4 25 Signal SCL SDA MODE SEL +5V GND Figure 20: Board Layout Figure 19: Cable Diagram PIN 2 3 8 5 4 13 12 25 100 PIN RED WHT GRN BLU BRN BLK 1 2 3 4 5 6 Figure 21: Board Layout with Socket J1 100 DB-25 25 |
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