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HD74LS165A
Parallel-Load 8-bit Shift Register
REJ03D0449-0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift / load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift / load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the clock, clock inhibit, or serial inputs.
Features
* Ordering Information
Part Name HD74LS165AP HD74LS165AFPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Shift/ Load Clock E Parallel Inputs F G H Output QH GND
1 2 3 4 5 6 7 8
Shift/Load Clock CK Inhibit E F G H QH D C B A Serial QH Input
16 15 14 13 12 11 10 9
VCC Clock Inhibit D C B A Serial Input Output QH Parallel Inputs
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7
HD74LS165A
Function Table
Inputs Shift / Load L H H H H Clock Inhibit X L L L H Clock X X Serial X X H L X Parallel A...H a...h X X X X Internal outputs QA a QA0 H L QA0 QB b QB0 QAn QAn QB0 Output QH h QH0 QGn QGn QH0
Notes: 1. H; high level, L; low level, X; irrelevant 2. ; transition from low to high level 3. a to h; the level of steady-state input at inputs A to H respectively 4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were established. 5. QAn to QGn; the level of QA to QG, respectively, before the most recent transition of the clock.
Block Diagram
A B C D
E
F
G
H
PR S QA CK
PR S QB CK R QB Clear
PR S QC CK R QC Clear
PR S QD CK R QD Clear
PR S QE CK R QE Clear
PR S QF CK R QF Clear
PR S QG CK R QG Clear
PR S QH CK R QH Clear QH QH
Serial Input Shift / Load
R QA Clear
Clock Clock Inhibit
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.3.00, Jul.15.2005, page 2 of 7
HD74LS165A
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Load pulse width Clock enable setup time Parallel input setup time Serial input setup time Shift setup time Hold time Symbol VCC IOH IOL Topr clock tw (clock) tw (load) tsu tsu tsu tsu th Min 4.75 -- -- -20 0 25 15 30 10 20 45 0 Typ 5.00 -- -- 25 -- -- -- -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL Shift / Load Other inputs Shift / Load High level input current Other inputs Low level input Shift / Load current Other inputs Short-circuit output current Supply current** Input clamp voltage Input current II IIH IIL IOS ICC VIK min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- -- -- -- 21 -- max. -- 0.8 -- 0.4 0.5 0.3 0.1 60 20 -1.2 -0.4 -100 36 -1.5 Unit V V V V mA mA A A mA mA mA mA V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Note: * VCC = 5 V, Ta = 25C **. With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift / load, ICC is measured with the parallel inputs at 4.5 V, than with the parallel inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Symbol max tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Inputs Outputs min. 25 -- -- -- -- -- -- -- -- typ. 35 21 26 14 16 13 24 19 17 max. -- 35 35 25 25 25 30 30 25 Unit MHz ns ns ns ns ns ns ns ns Condition
Load Clock H H
Any Any QH QH
Propagation delay time
CL = 15 pF, RL = 2 k
Rev.3.00, Jul.15.2005, page 3 of 7
HD74LS165A
Testing Method
Test Circuit
4.5V VCC
Serial Input Shift/Load
Output RL QH CL
Load circuit 1
Input
See Testing Table
A B C D E F G H Clock Clock Inhibit
P.G. Zout = 50
QH
Same as Load Circuit 1.
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Waveforms 1
3V Shift/ Load 1.3V 0V tsu Serial Input 1.3V tsu Clock Inhibit 1.3V 1.3V tsu 1.3V 3V 0V 3V 0V
Notes:
A. The eight data inputs and the clock-inhibit input are low. Results are monitored at output QH at Tn + 7. B. The input pulse generators have the following characteristics: PRR < 1 MHz, duty cycle < 50%, Zout 50 , tTLH 15 ns, tTHL 6 ns.
Rev.3.00, Jul.15.2005, page 4 of 7
HD74LS165A Waveforms 2
3V Clock Inhibit Input
1.3V tsu (Disable while clock is high)
0V 3V
Clock Input
tsu
1.3V tw (clock)
1.3V
1.3V
0V 3V
F and H 1.3V Inputs (See Notes A and B)
1.3V
1.3V tw (load)
1.3V tsu tw (load)
0V 3V
Shift/ Load
tPHL tPLH
1.3V
1.3V
1.3V
1.3V
0V
tPHL tPLH tPHL tPLH
VOH Output QH
tPLH 1.3V tPHL 1.3V tPLH 1.3V tPHL 1.3V tPLH 1.3V
VOL
tPHL
VOH Output QH
1.3V 1.3V 1.3V 1.3V 1.3V 1.3V
VOL
Notes:
A. The remaining six data inputs and the serial input are low. B. Prior to test, high-level data is loaded into H input. C. The input pulse Generators have the following characteristics: PRR 1 MHz, duty cycle 50%, Zout 50 , tTLH 15 ns, tTHL 6 ns.
Rev.3.00, Jul.15.2005, page 5 of 7
HD74LS165A
Typical Shift, Load and Inhibit Sequences
Clock Clock Inhibit Serial Input Shift / Load A B C D Data E F G H Output QH Output QH Inhibit Load H L H H H L H L L H H L L H H L L H H L H L H L
Serial Shift
Rev.3.00, Jul.15.2005, page 6 of 7
HD74LS165A
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jul.15.2005, page 7 of 7
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