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U6808B
Special Fail-Safe IC
Description
The U6808B is designed to support the fail-safe function of a safety critical system e.g. ABS. It includes a relay driver, a watchdog controlled by an external R/C-network and a reset circuit initiated by an over- and undervoltage condition of the 5-V supply providing a positive and a negative reset signal.
Features
D Digital self-supervising watchdog with hysteresis D One 250-mA output driver for relay D Enable output open collector 10 mA D Over-/undervoltage detection D ENABLE- and RELAY outputs protected against standard transients and 40 V load dump D ESD protection according to MIL-STD-883 D test method 3015.7 - Human body model:" 2 kV (100 pF, 1.5 kW) - Machine model: " 200 V (200 pF, 0 W)
Block Diagram
VS VS Bandgap reference 2.44 V Power-on reset RESET Reset debounce + - RELAY Reset delay
+ -
Under/ overvoltage detection
ENABLE RIN - + + - Watchdog
Internal oscillator RC oscillator
Current limitation
WDI
GND
WDC
14523
Figure 1. Block diagram
Ordering Information
Extended Type Number U6808B Package SO8 Remarks
Rev. A2, 18-Jan-01
1 (12)
U6808B
Pin Description
RELAY 1 8 VS RIN WDI
GND ENABLE
2
7
3
6
WDC
4
5
RESET
14019
Figure 2. Pinning U6808B Table 1 Pin description
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2 3 4 5 6 7 8 GND ENABLE WDC RESET WDI RIN VS Standard ground Negative reset signal External RC for watchdog timer Negative reset signal Watchdog trigger signal Activation of relay driver 5-V supply Reset: L Reset: L Pulse sequence H: driver on L: driver off Supply
Pin 1
Name RELAY
Type Open collector driver output Supply Digital output Analog input Digital output Digital input Digital input
Function Fail-safe relay driver
Logic Driver off:--- driver on: L
Fail-Safe Functions
A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the pins (e.g. short circuit). This ensures that a microcontroller system would not be brought into a critical status. A critical status
Table 2 Table of fault conditions
is reached if the system is not able to switch off the relay and to give a signal to the mC via ENABLE- and RESET outputs. The following table shows the fault conditions for the pins.
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WDI OSC Watchdog reset Watchdog reset Watchdog reset Watchdog reset Watchdog reset Watchdog reset RELAY Relay on Relay off 2 (12) Rev. A2, 18-Jan-01
Pin RIN
Function Short to Vs Digital input to Relay on activate the failsafe relay Watchdog trigger Watchdog reset input Capacitor and Watchdog reset resistor of watchdog Driver of the failsafe relay
Short to VBat Relay on
Short to GND Relay off
Open Circuit Relay off
U6808B
Truth Tables
Table 3 Truth table the over- and under voltage conditions
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Too slow Too fast
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Table 4 Truth table for watchdog failures (RESET output don`t care)
Inputs Supply Voltage Relay Input (RIN) (VS) Normal Low High Too low Low High Too high Low High Inputs
Relay Output Driver (RELAY) Off On Off Off Off Off
Outputs RESET Output (RESET) High High Low Low Low Low
Enable Output Driver (ENABLE) Off Off On On On On
Watchdog Input (WDI) Normal
Relay Input (RIN) Low High Low High Low High
Relay Output Driver (RELAY) Off On Off Off Off Off
Outputs Enable Output Driver (ENABLE) Off Off On On On On
Description of the Watchdog
RCOSC
Binary counter
Dual MUX
WDI RESET OSCERR
Slope detector
Up/down counter
RS-FF
WD-OK
13949
Figure 3. Watchdog block diagram
Abstract
The microcontroller is monitored by a digital window watchdog which accepts an incomming trigger signal of a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog`s time window is determined by external R/C components. The following description refers to the block diagram (Fig. 3)
Rev. A2, 18-Jan-01
3 (12)
U6808B
WDI Input (Pin 6)
The microcontroller has to provide a trigger signal with the frequency fWDI which is fed to the WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and clocks the up/down counter additionally.The latter one counts only from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches status 3 the RS flip-flop is set; see Fig. 4 (WD state diagram). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see WD OK output) and resets the up/down counter directly.
Watchdog State Diagram
Initial status bad bad O/F bad good 1/F good Figure 4. Watchdog state diagram bad 2/F good good 1/NF bad bad 3/NF 2/NF good good
RCOSC Input
With an external R/C circuitry the IC generates a time base (frequency fWDC) independent from the microcontroller. The watchdog`s time window refers to a frequency of fWDC = 100 fWDI
Explanation
In each block, the first character represents the state of the counter. The second notation indicates the fault status of the counter. A fault status is indicated by an "F" and a no fault status is indicated by an "NF". When the watchdog is powered up initially, the counter starts out at the 0/F block (initial state). "Good" indicates that a pulse has been received whose width resides within the timing window. "Bad" indicates that a pulse has been received whose width is either too short or too long.
OSCERR Input
A smart watchdog has to ensure that internal problems with its own time base are detected and do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating a signal is fed to the OSCERR input after a timeout delay. It resets the up/down counter and disables the WD-OK output. Without this reset function the watchdog would freeze its current status when fRC stops.
Watchdog-Window Calculation
Example with recommended values Cosc = 3.3 nF (should be preferably 10%, NPO) Rosc= 39 kW (may be 5%, Rosc <100 kW due to leakage current and humidity)
RESET Input
During power-on and under-/ overvoltage detection a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state.
WD-OK Output
After the up/down counter is incremented to status 3 (see Fig. 4, WD state diagram) the RS flip-flop is set and the WD-OK output becomes logic "1". This information is available for the microcontroller at the open-collector output ENABLE. If on the other hand the up/down counter is decremented to 0 the RS flip-flop is reset, the WD-OK output and the ENABLE output are disabled. The WD-OK output also controls a dual MUX stage which shifts the time window by one clock after a successful trigger thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal `good' or `false'. The WD-OK signal is also reset in the case the watchdog counter is not reset after 250 clocks (missing trigger signal). RC Oscillator tWDC (s) = 10-3 [Cosc (nF) 0.0005]] fWDC (Hz) = 1 / (tWDC) Watchdog WDI fWDI (Hz) =0.01 tWDC = 100 ms fWDI = 100 Hz fWDC -> fWDC = 10 kHz -> tWDI = 10 ms [(0.00078 Rosc (kW)) +
4 (12)
Rev. A2, 18-Jan-01
U6808B
WDI pulse width for fault detection after 3 pulses: Upper watchdog window Minimum: 169/ fWDC = 16.9 ms -> fWDC / 169 = 59.1 Hz Maximum: 170/ fWDC = 17.0 ms -> fWDC / 170 = 58.8 Hz Lower watchdog window Minimum: 79/ fWDC = 7.9 ms -> fWDC / 79 = 126.6 Hz Maximum: 80/ fWDC = 8.0 ms -> fWDC / 80 = 125.0 Hz WDI dropouts for immediate fault detection: Minimum: Maximum: 250/ fWDC = 25 ms 251/ fWDC = 25.1 ms
Time/s
79/ fWDC
80/ fWDC
169/ fWDC
170/ fWDC
250/ fWDC
251/ fWDC
Watchdog window update rate is good
Update rate is too fast Update rate is either too fast or good Update rate is ei- Update rate ther too slow or is too slow good Update rate is Pulse has either too dropped out slow or pulse has dropped out
Figure 5. Watchdog timing diagram with tolerances
Remark to Reset Delay The duration of the over- or undervoltage pulses determines the enable- and reset output. A pulse duration shorter than the debounce time has no effect on the
outputs. A pulse longer than the debounce time results in the first reset delay. If a pulse appears during this delay, a 2nd delay time is triggered. Therefore, the total reset delay time can be longer than specified in the data sheet.
Absolute Maximum Ratings
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Supply-voltage range Power dissipation VS - 0.2 to 16 250 150 160 150 V VS = 5 V; Tamb = -40C VS = 5 V; Tamb = 125C Thermal resistance Ptot Ptot Rthja Tj mW mW K/W C C C Junction temperature Ambient temperature range Storage temperature range Tamb Tstg -40 to 125 -55 to 155 Rev. A2, 18-Jan-01 5 (12)
Parameters
Symbol
Value
Unit
U6808B
Electrical Characteristics
VS = 5 V, Tamb = -40 to + 125C; reference pin is GND; fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz "10%; fWDI = 100 Hz Parameter Supply voltage Operation range general Operation range reset Supply current Relay off Relay on Digital input WDI Detection low Detection high Resistance to VS Input current low Input current high Zener clamping voltage Digital input RIN Detection low Detection high Resistance to GND Input current low Input current high Zener clamping voltage Voltage high Voltage low Zener clamping voltage Reset debounce time Reset delay time Input voltage = 0 V Input voltage = VS VZRIN Input voltage = 0 V Input voltage = VS VZWDI -0.2 0.7 10 100 -5 20 VS 0.2 VS V V kW mA mA V V V kW mA mA V V
VS+0.5 V
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
VS VS Tamb = - 40C Tamb = 125C Tamb = - 40C Tamb = 125C
4.5 1.2
5.5 16.0
V V mA mA mA mA
6 15
40 550 5 24
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-0.2 0.2 VS 0.7 10 -5 100 20 VS
VS+0.5 V
40 +5 550 24
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Digital output RESET with internal pull-up Pull-up = 6 kW 0.7 VS+0.1 0 VS I v 1 mA 1.2 VtVSt16 V 0.3 30 V V VZRESE
T
26
Switch to `low`
tdeb tdel
120
320 50
500
ms
Switch back to `high` I v 10 mA
ms V V
Digital output ENABLE with open collector Saturation voltage low Zener clamping voltage
0.01 26
0.5 30
VZEN
6 (12)
Rev. A2, 18-Jan-01
U6808B
Electrical Characteristics (continued)
VS = 5 V, Tamb = -40 to + 125C; reference pin is GND; fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz "10%; fWDI = 100 Hz Parameter Test Conditions / Pins Symbol Ilim IEN5 IEN16 IEN26 tdeb tdel Min. 10 Typ. Max. 20 100 200 Unit mA mA mA mA ms ms V V
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Current limitation Leakage current VEN = 5 V VEN = 16 V VEN = 26 V Reset debounce time Reset delay time Switch to `low` 120 320 85 500 Switch back to `high` I v 250 mA I v 130 mA Relay driver output RELAY Saturation voltage
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Maximum load current Tamb -40 to 90C Tamb u 90C IR IR 250 200 26 30 mA mA V mJ Zener clamping voltage Turn-off enegy Leakage current VZR IR16 IR26 VS VS 30 VR = 16 V VR = 26 V 20 200 4.7 5.6 mA mA V V Reset and VS control Lower reset level Upper reset level Hysteresis Reset debounce time Reset delay RC oscillator WDC Oscillator frequency Watchdog timing Power-on-reset prolongation time Detection time for RC-oscillator fault Time interval for over-/ under voltage detection Reaction time of RESET output over/ under voltage Nominal frequency for WDI Minimum pulse duration for a securely WDI input pulse detection fRC = 100 fWDI fWDC Nominal frequency for WDC fWDI = 1/100 VRC = const. tPOR tRCerror tD,OUV tR,OUV fWDI fWDC tP,WDI 34 .3 81.9 0.16 .187 10 1 182 103.1 246 0.64 0.72 130 13 ms ms ms ms Hz kHz s ROSC = 39 kW, COSC = 3.3 nF fWDC 9 10 11 kHz 4.5 25 120 20 320 50 5.35 100 500 80 mV ms ms Rev. A2, 18-Jan-01 7 (12)
VRsat VRsat
0.5 0.3
U6808B
Electrical Characteristics (continued)
VS = 5 V, Tamb = -40 to + 125C; reference pin is GND; fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz "10%; fWDI = 100 Hz Parameter Frequency range for a correct WDI signal Number of incorrect WDI trigger counts for locking the outputs Number of correct WDI trigger counts for releasing the outputs Detection time for a stucked WDI signal Minimum pulse duration for a securely WDI input pulse detection Frequency range for a correct WDI signal Hysteresis range at the WDI ok margins Detection time for a dropped out WDI signal VWDI = const. 250 80 1 251 VWDI = const. Test Conditions / Pins Symbol fWDI nlock Min. 64.7 3 Typ. Max. 112.5 Unit Hz
nrelease
3
tWDIerror
24.5
25.5
ms
Watchdog timing relative to fWDC 2 cycles
169
cycles cycle cycles
Protection against transient voltages according to ISO TR 7637-3 level 4 (except pulse 5)
Pulse 1 2 3a 3b 5 Voltage - 110 V + 110 V - 160 V + 150 V 40 V
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100 V/s 100 V/s 30 V/ns 20 V/ns 10 V/ms 2 ms 0.05 ms 0.1 s 0.1 s 250 ms 15.000 15.000 1h 1h 20 * Relay driver: relay coil with Rmin = 70 W to be added to the source resistance. 8 (12) Rev. A2, 18-Jan-01
Source Resistance * 10 10 50 50 2
Rise Time
Duration
Amount
U6808B
Timing Diagrams
Normal operation 5V WDI 0V VBatt RELAY 0V 5V ENABLE 0V Don't care
14525
WDI too fast
Normal operation
Figure 6. Watchdog in too-fast condition
Normal operation 5V WDI 0V VBatt RELAY 0V 5V ENABLE 0V
WDI too slow
Normal operation
Don't care
14526
Figure 7. Watchdog in too-slow condition
Rev. A2, 18-Jan-01
9 (12)
U6808B
Overvoltage condition > 120 s u5.6 V t 120s u5.6 V
5V VS 0V VBatt RELAY 0V 5V ENABLE 0V 5V RESET 0V
Reset debounce time 1st Reset delay
3 good WDI pulses
Don't care
2nd Reset delay Figure 8. Overvoltage condition Undervoltage condition > 120 s 5V VS 0V VBatt RELAY 0V 5V ENABLE 0V 5V RESET 0V Reset debounce time 1st Reset delay 2nd Reset delay Figure 9. Undervoltage condition 3 good WDI pulses t4.5 V t 120 s t4.5 V
14527
Don't care
14528
10 (12)
Rev. A2, 18-Jan-01
U6808B
Application Circuit VS =5 V C 100 Hz C C
8 0.01F
7
6
5
U6808B
1 Relay 2 3 4 Cosc 3.3 nF
Rosc 39 k
C VBatt
14524
Figure 10. Application circuit
Package Information
Package SO8
Dimensions in mm
5.00 4.85 1.4 0.4 1.27 3.81 8 5 0.25 0.10 0.2 3.8 6.15 5.85 5.2 4.8 3.7
technical drawings according to DIN specifications 13034
1
4
Rev. A2, 18-Jan-01
11 (12)
U6808B
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com 11. Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
12 (12)
Rev. A2, 18-Jan-01

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