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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
D D D D D D D
Qualification in Accordance With AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (CL = 200 pF, RL = 0) 2.7-V Operation Two Differential Microphone Inputs, One Differential Earphone Output, and One Single-Ended Earphone Output Programmable Gain Amplifiers for Transmit, Receive, Sidetone, and Volume Control
D D D D D D D
Earphone Mute and Microphone Mute On-Chip I2C Bus, Which Provides a Simple, Standard, Two-Wire Serial Interface With Digital ICs Programmable for 15-Bit Linear Data or 8-Bit Companded (-Law or A-Law) Data Available in a 32-Pin Thin Quad Flatpack (TQFP) Package Designed for Analog and Digital Wireless Handsets and Telecommunications Applications Dual-Tone Multifrequency (DTMF) and Single Tone Generator Pulse Density Modulated (PDM) Buzzer Output
PBS PACKAGE (TOP VIEW)
description
The voice-band audio processor (VBAP) is designed to perform transmit encoding analog/ digital (A/D) conversion, receive decoding digital/analog (D/A) conversion, and transmit and receive filtering for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded (-law or A-Law) mode, which is selectable through the I2C interface. The VBAP generates its own internal clocks from a 2.048-MHz master clock input.
AVAILABLE OPTIONS TA - 40C to 105C TQFP PBS PACKAGE Tube Tape and Reel PART NO. TWL1103TPBSQ1 TWL1103TPBSRQ1 TOP-SIDE MARKING TWL1103T TWL1103T
24 23 22 21 20 19 18 17
PLLVSS VSS MCLK RESET PWRUPSEL BUZZCON PCMSYN PCMCLK PLLVDD EARVSS EAR1ON EARVDD EAR1OP EARVSS EAR2O AVDD
25 26 27 28 29 30 31 32 1 2 3 4567 8
Contact factory for details. Q100 qualification data available on request.
PCMO PCMI DVSS DVDD 12 SCL 11 SDA 10 NC 9 NC
15 14 13
16
NC - No internal connection
VBAP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
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MBIAS MIC1P MIC1N MIC2P MIC2N REXT NC AVSS
Copyright 2002, Texas Instruments Incorporated
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
functional block diagram
PCMO (16)
EAR1OP (29) EAR1ON (27) EAR2O (31)
BUZZCON (19)
Ear Amp1
Ear Amp2 PWRUPSEL (20) V SS AV DD AV SS Power and RESET DV DD DV SS (23) (32) (8) (13) (14)
Digital Modulator and Filter
Buzzer Control
PLLV DD (25) PLLV SS (24)
RX Filter and PGA g = -6 dB to +6 dB
EARV DD (28) EARV SS (30, 26) RESET (21)
RX Volume Control g = -18 dB to 0 dB PLL PCM Interface Sidetone g = -24 dB to -12 dB DTMF Generator TX Filter and PGA g = -10 dB to 0 dB REXT (6) MBIAS (1) MCLK (22)
REF
Analog Modulator
Control Bus MIC Amplifier 2 g = 12 dB or 0 dB I 2C I/F SDA SCL (11) (12)
MIC Amplifier 1g = 23.5 dB
PCMCLK (17) PCMI (15) PCMSYN (18) MIC1P (2) MIC1N (3) MIC2P (4) MIC2N (5)
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
functional description
power on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low RESET terminal to guarantee reset upon power on. After the initial power-on sequence the TWL1103 can be functionally powered up and down by writing to the power control register through the I2C interface. There is a hardwired selectable power-up terminal in default mode option. The PWRUPSEL function allows the VBAP to power up in the default mode and allows use without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. control interface The I2C interface is a two-wire bidirectional serial interface that controls the VBAP by writing data to the six control registers:
D D D D D D D D
Power control Mode control Transmit PGA and sidetone control Receive PGA gain and volume control DTMF high tone DTMF low tone
There are two power-up modes which may be selected at the PWRUPSEL terminal: The PWRUPSEL state (VDD at terminal 20) causes the device to power up in the default mode when power is applied. In the default mode, the I2C interface is not required, and the device may be used without an I2C interface. The programmable functions are fixed in the default modes. The PWRUPSEL state (ground at terminal 20) causes the device to go to a power-down state when power is applied. In this mode an I2C interface is required to power up the device.
phase-locked loop The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the 2.048-MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a lownoise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of 0 dB or 12 dB.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
functional description (continued)
analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either the 15-bit linear or 8-bit companded -law or A-law mode that is selectable through the I2C interface. The transmit PGA defaults to 0 dB. sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to -12 dB. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of -18 dB to 0 dB in 2 dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates in either the 15-bit linear or 8-bit -law or A-law companded mode, which is selectable through the I2C interface. The gain defaults to -1 dB representing a 3-dBm0 level for a 32- load impedance and the corresponding digital full scale PCMI code. The gain may be set to -2 dB for the respective 3-dBm0 level for a 16- load impedance. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones and single tone frequencies which are output to the following devices: 1) The buzzer driver, as a pulse density modulation (PDM) signal 2) The receive path digital/analog converter (DAC) for outputting through the earphone. There are 255 possible single tones. The tone integer value is determined by the following formula: Round (Tone Freq (Hz)/7.8135 Hz) The value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05). The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the high DTMF tone must be applied to the high-tone register and the low frequency tone to the low-tone register.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
Terminal Functions
TERMINAL NAME AVDD AVSS BUZZCON DVDD DVSS EAR1ON EAR1OP EAR2O EARVDD EARVSS MBIAS MCLK MIC1P MIC1N MIC2P MIC2N PCMI PCMO PCMSYN PCMCLK PLLVSS PLLVDD PWRUPSEL REXT RESET SCL SDA NO. BGA A1 J1 F9 J6 J7 A6 A4 A2 A5 A3, A7 B1 C9 C1 D1 E1 F1 J8 J9 G9 H9 A9 A8 E9 G1 D9 J5 J4 PBS 32 8 19 13 14 27 29 31 28 30, 26 1 22 2 3 4 5 15 16 18 17 24 25 20 6 21 12 11 I I O I I O O O I I O I I I I I I O I I I I I I/O I I I/O Analog positive power supply Analog negative power supply Buzzer output, a pulse-density modulated signal to apply to external buzzer driver Digital positive power supply Digital negative power supply Earphone 1 amplifier output (-) Earphone 1 amplifier output (+) Earphone 2 amplifier output Analog positive power supply for the earphone amplifiers Analog negative power supply for the earphone amplifiers Microphone bias supply output, no decoupling capacitors Master system clock input (2.048 MHz) (digital) MIC1 input (+) MIC1 input (-) MIC2 input (+) MIC2 input (-) Receive PCM input Transmit PCM output PCM frame synchronization PCM data clock PLL negative power supply PLL digital power supply Selects the power-up default mode Internal reference current setting terminal--use precision 100-k resistor and no filtering capacitors Active low reset I2C-bus serial clock--this input is used to synchronize the data transfer from and to the VBAP I2C-bus serial address/data input/output--this is a bidirectional terminal used to transfer register control addresses and data into and out of the CODEC. It is an open-drain terminal and therefore requires a pullup resistor to VDD (typical 10 k for 100 kHz) Ground return for bandgap internal reference I/O DESCRIPTION
VSS
B9
23
I
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, AVDD, DVDD, PLLVDD, EARVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4 V Input voltage range, VF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature range, TA (extended temperature) . . . . . . . . . . . . . . . . . . . . . . . - 40C to 105C Storage temperature range, testing, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE PBS TA 25C POWER RATING 680 mW DERATING FACTOR ABOVE TA = 25C 6.8 mW/C TA = 85C POWER RATING 270 mW TA = 105C POWER RATING 134 mW
recommended operating conditions (see Notes 1 and 2)
MIN Supply voltage, AVDD, DVDD, PLLVDD, EARVDD High-level input voltage (VIH) Low-level input voltage (VIL) Load impedance between EAR1OP and EAR1ON-RL Load impedance for EAR2OP-RL Operating free-air temperature, TA - 40 16 32 105 2.7 0.7 x VDD 0.3 x VDD 32 NOM MAX 3.3 UNIT V V V
_C
NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, the power-on initialization paragraph must be followed, described in the Principles of Operations. 2. Voltages are with respect to AVSS, DVSS, PLLVSS, and EARVSS.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
electrical characteristics, VDD = 2.7 V, TA = -40C to 105C (unless otherwise noted) supply current
PARAMETER TEST CONDITIONS Operating, EAR1 selected, MicBias disabled Operating, EAR2 selected, MicBias disabled IDD Supply current from VDD Power down, Reg 2 bit 7 = 1, MClk not present (see Note 3) Power down, Reg 2 bit 7 = 0, MClk not present (see Note 3) ton(i) Power-up time from power down NOTE 3: VIH = VDD, VIL = VSS MIN TYP 6 5.4 0.5 25 5 MAX 7 6 18 40 10 UNIT mA mA A A ms
digital interface
PARAMETER VOH VOL IIH IIL CI Co RL High-level output voltage, PCMO and BuzzCon Low-level output voltage, PCMO and BuzzCon High-level input current, any digital input Low-level input current, any digital input Input capacitance Output capacitance Load impedance (BuzzCon) TEST CONDITIONS IOH = - 3.2 mA, IOL = 3.2 mA, VI = VDD VI = VSS VDD = 3 V VDD = 3 V MIN 2 0.8 10 10 10 20 5 TYP MAX UNIT V V A A pF pF k
microphone interface
PARAMETER VIO IIB Ci Vn IOmax V(mbias) Input offset voltage at MIC1N, MIC2N Input bias current at MIC1N, MIC2N Input capacitance at MIC1N, MIC2N Microphone input referred noise, psophometric weighted (C-message weighted is similar) Output source current MBIAS Microphone bias supply voltage (see Note 5) MICMUTE Input impedance Fully differential 35 60 Micamp 1 gain = 23.5 dB Micamp 2 gain = 0 dB 1 2.35 2.5 TEST CONDITIONS See Note 4 MIN -5 -600 5 3.0 7.7 1.2 2.6 -80 100 TYP MAX 5 600 UNIT mV nA pF Vrms mA V dB k
NOTES: 4. Measured while MIC1P and MIC1N are connected together. Less than 5 mV offset results in 0 value code on PCMOUT. 5. Not a JEDEC symbol.
speaker interface
PARAMETER TEST CONDITIONS VDD = 2.7 V, fully differential, 16- load, 3-dBm0 output, RGXPA = - 2 dB VDD = 2.7 V, fully differential, 32- load, 3-dBm0 output, RGXPA = -1 dB VDD = 2.7 V, single ended, 32- load, 3-dBm0 output Fully differential 3-dBm0 input, 16- load 3-dBm0 input, 32- load 3-dBm0 input MIN TYP 120.9 76.1 10 5 86.9 48.7 17.7 MAX 151.1 95.1 12.5 30 108.6 60.8 22.1 -80 dB mA UNIT mW mW mW mV
Earphone AMP1 output power (See Note 6)
Earphone AMP2 output power (See Note 6) VOO IOmax Output offset voltage at EAR1 Maximum output current for EAR1(rms) Maximum output current for EAR2 (rms) EARMUTE
NOTE 6: Maximum power is with a load impedance of approximately 12 .
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
electrical characteristics, VDD = 2.7 V, TA = -40C to 105C (unless otherwise noted) (continued) transmit gain and dynamic range, companded mode (-law or A-law) or linear mode selected, transmit slope filter bypassed (see Notes 7 and 8)
PARAMETER Transmit reference-signal level (0 dB) Overload-signal Overload signal level (3 dBm0) Absolute gain error Linear mode gain error with in ut level input relative to gain at - 10 dBm0 MIC1N, MIC1P to PCMO Differential Differential, normal mode Differential, extended mode 0 dBm0 input signal, VDD = 2.7 V (minimum) MIC1N, MIC1P to PCMO at 3 dBm0 to -30 dBm0 MIC1N, MIC1P to PCMO at - 31 dBm0 to - 45 dBm0 MIC1N, MIC1P to PCMO at - 46 dBm0 to - 55 dBm0 -1 - 0.5 -1 - 1.2 TEST CONDITIONS MIN TYP MAX 175 248 63 1 0.5 1 1.2 dB UNIT mVpp mVpp mVpp dB
NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms.
transmit gain and dynamic range, companded mode (-law or A-law) or linear mode selected, transmit slope filter enabled (see Notes 7 and 8)
PARAMETER Transmit reference-signal level (0dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error Linear mode gain error with in ut level input relative to gain at - 10-dBm0 MIC1N, MIC1P to PCMO Differential Differential, normal mode Differential, extended mode 0-dBm0 input signal, VDD = 2.7 V (minimum) MIC1N, MIC1P to PCMO at 3 dBm0 to -30 dBm0 MIC1N, MIC1P to PCMO at - 31 dBm0 to - 45 dBm0 MIC1N, MIC1P to PCMO at - 46 dBm0 to - 55 dBm0 -1 - 0.5 -1 - 1.2 TEST CONDITIONS MIN TYP MAX 175 248 63 1 0.5 1 1.2 dB UNIT mVpp mVpp mVpp dB
NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms.
transmit filter transfer, linear mode selected, transmit slope filter bypassed, external high pass filter bypassed (MCLK = 2.048 MHz)
PARAMETER TEST CONDITIONS fMIC1 or fMIC2 <100 Hz fMIC1 or fMIC2 = 200 Hz G i relative t i ti lit l high-pass Gain l ti to input signal gain at 1020 H i t Hz, internal hi h filter disabled fMIC1 or fMIC2 > 700 Hz to 3 kHz fMIC1 or fMIC2 = 3.4 kHz fMIC1 or fMIC2 = 4 kHz fMIC1 or fMIC2 = 4.6 kHz Gain relative to input signal g gain at 1020 Hz, internal high-pass g , g filter enabled fMIC1 or fMIC2 = 8 k Hz fMIC1 or fMIC2 <100 Hz fMIC1 or fMIC2 = 200 Hz MIN - 8.5 - 4.5 - 0.5 - 1.5 TYP MAX -6 -3 0.5 0 - 14 - 35 - 47 - 15 -5 dB dB UNIT
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
electrical characteristics, VDD = 2.7 V, TA = -40C to 105C (unless otherwise noted) (continued) transmit filter transfer, linear mode selected, transmit slope filter selected (MCLK = 2.048 MHz) (see Note 9)
PARAMETER TEST CONDITIONS fMIC1 or f MIC2 =100 Hz fMIC1 or fMIC2 = 200 Hz fMIC1 or fMIC2 = 250 Hz fMIC1 or fMIC2 = 300 Hz fMIC1 or fMIC2 = 400 Hz fMIC1 or fMIC2 = 500 Hz fMIC1 or fMIC2 = 600 Hz fMIC1 or fMIC2 = 700 Hz fMIC1 or fMIC2 = 800 Hz fMIC1 or fMIC2 = 900 Hz Gain relative to input signal gain at 1000 Hz, with slope filter selected Hz fMIC1 or fMIC2 = 1000 Hz fMIC1 or fMIC2 = 1500 Hz fMIC1 or fMIC2 = 2000 Hz fMIC1 or fMIC2 = 2500 Hz fMIC1 or fMIC2 = 3000 Hz fMIC1 or fMIC2 = 3100 Hz fMIC1 or fMIC2 = 3300 Hz fMIC1 or fMIC2 = 3500 Hz fMIC1 or fMIC2 = 4000 Hz fMIC1 or fMIC2 = 4500 Hz fMIC1 or fMIC2 = 5000 Hz fMIC1 or fMIC2 = 8000 Hz NOTE 9: The pass-band tolerance is 0.25 dB from 300 Hz to 3500 Hz. - 1.80 - 1.50 - 1.30 - 1.1 - 0.8 - 0.57 - 0.25 0 1.8 4.0 6.5 7.6 7.7 8.0 6.48 - 13 - 35 - 45 - 50 MIN TYP MAX -27 -8 -4 UNIT dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
transmit idle channel noise and distortion, linear mode selected, slope filter bypassed
PARAMETER Transmit idle channel noise TEST CONDITIONS TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0.0 dB MIC1N, MIC1P to PCMO at 3 dBm0 MIC1N, MIC1P to PCMO at 0 dBm0 MIC1N, MIC1P to PCMO at - 5 dBm0 Transmit signal-to-total distortion ratio with 1020-Hz g sine-wave input MIC1N, MIC1P to PCMO at - 10 dBm0 MIC1N, MIC1P to PCMO at - 20 dBm0 MIC1N, MIC1P to PCMO at - 30 dBm0 MIC1N, MIC1P to PCMO at - 40 dBm0 MIC1N, MIC1P to PCMO at - 45 dBm0 40 50 60 55 58 50 38 30 MIN TYP - 86.6 50 65 68 70 65 60 50 45 dB MAX - 78 UNIT dBm0p
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9
TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
electrical characteristics, VDD = 2.7 V, TA = -40C to 105C (unless otherwise noted) (continued) transmit idle channel noise and distortion, linear mode selected, slope filter enabled
PARAMETER Transmit idle channel noise TEST CONDITIONS TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0.0 dB MIC1N, MIC1P to PCMO at 3 dBm0 MIC1N, MIC1P to PCMO at 0 dBm0 MIC1N, MIC1P to PCMO at - 5 dBm0 Transmit signal-to-total distortion ratio with 1020-Hz g sine-wave input MIC1N, MIC1P to PCMO at - 10 dBm0 MIC1N, MIC1P to PCMO at - 20 dBm0 MIC1N, MIC1P to PCMO at - 30 dBm0 MIC1N, MIC1P to PCMO at - 40 dBm0 MIC1N, MIC1P to PCMO at - 45 dBm0 40 50 55 55 58 48 38 30 MIN TYP - 86.6 50 65 68 70 65 60 50 45 dB MAX - 78 UNIT dBm0p
receive gain and dynamic range, EAR1 selected, linear or companded (-law or A-law) mode selected (see Note 10)
PARAMETER Overload signal level (3.0 dB) (3 0 Overload-signal Absolute gain error Linear mode gain error with output l Li d i ith t t level l relative to gain at -10 dBm0 TEST CONDITIONS 16- load RXPGA = - 2.0 dB 32- load RXPGA = - 1.0 dB (default gain) 0-dBm0 input signal, VDD = 2.7 V (minimum) PCMIN to EAR1ON, EAR1OP at 3 dBm0 to - 40 dBm0 PCMIN to EAR1ON, EAR1OP at - 41 dBm0 to - 50 dBm0 PCMIN to EAR1ON, EAR1OP at - 51 dBm0 to - 55 dBm0 -1 - 0.5 -1 - 1.2 MIN TYP 3.93 4.41 1 0.5 1 1.2 dB MAX UNIT Vpp dB
NOTE 10: RXPGA = -1 dB for 32 default mode or RXPGA = -2 dB for 16 , RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP
receive gain and dynamic range, EAR2 selected, linear or companded (-law or A-law) mode selected (see Note 11)
PARAMETER Receive reference-signal level (0 dB) Overload-signal level (3 dB) Absolute gain error Linear mode gain error with output l Li d i ith t t level relative t l l ti to gain at -10 dBm0 NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB 0-dBm0 input signal, VDD = 2.7 V (minimum) PCMIN to EAR2O at 3 dBm0 to - 40 dBm0 PCMIN to EAR2O at - 41 dBm0 to - 50 dBm0 PCMIN to EAR2O at - 51 dBm0 to - 55 dBm0 -1 - 0.5 -1 - 1.2 TEST CONDITIONS 0-dBm0 PCM input signal MIN TYP 1.1 1.6 1 0.5 1 1.2 dB MAX UNIT Vpp Vpp dB
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
electrical characteristics, VDD = 2.7 V, TA = -40C to 105C (unless otherwise noted) (continued) receive filter transfer, linear mode selected (MCLK = 2.048 MHz) (see Note 11)
PARAMETER TEST CONDITIONS fEAR1 or fEAR2 < 100 Hz fEAR1 or fEAR2 = 200 Hz Gain l ti to input signal gain at 1020 H i t G i relative t i ti lit Hz, internal l high- ass high-pass filter disabled fEAR1 or fEAR2 = 300 Hz to 3 kHz fEAR1 or fEAR2 = 3.4 kHz fEAR1 or fEAR2 = 4 kHz fEAR1 or fEAR2 = 4.6 kHz Gain relative to input signal g g gain at 1020 Hz, internal high-pass filter enabled NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB fEAR1 or fEAR2 = 8 kHz fEAR1 or fEAR2 < 100 Hz fEAR1 or fEAR2 = 200 Hz MIN - 0.5 - 0.5 - 0.5 -1.5 TYP MAX 0.5 0.5 0.5 0 - 14 - 35 - 47 -15 -5 dB dB UNIT
receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 12)
PARAMETER Receive noise, (20 Hz to 20 kHz brickwall window) TEST CONDITIONS PCMIN = 0000000000000 PCMIN to EAR1ON, EAR1OP at 3 dBm0 PCMIN to EAR1ON, EAR1OP at 0 dBm0 PCMIN to EAR1ON, EAR1OP at - 5 dBm0 Receive signal-to-distortion ratio with 1020 Hz g sine-wave input PCMIN to EAR1ON, EAR1OP at -10 dBm0 PCMIN to EAR1ON, EAR1OP at - 20 dBm0 PCMIN to EAR1ON, EAR1OP at - 30 dBm0 PCMIN to EAR1ON, EAR1OP at - 40 dBm0 PCMIN to EAR1ON, EAR1OP at - 45 dBm0 Intermodulation distortion, 2-tone CCITT method, , , composite power level, - 13 dBm0 CCITT G.712 (7.1), R2 CCITT G.712 (7.2), R2 65 73 72 70 60 50 40 33 50 54 MIN TYP - 86 78 80 78 78 76 67 60 55 dB dB MAX - 83 UNIT dBm0
NOTE 12: RXPGA = -1 dB for 32 default mode or RXPGA = -2 dB for 16 , RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP.
receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 11)
PARAMETER Receive noise, (20 Hz to 20 kHz brickwall window) TEST CONDITIONS PCMIN = 0000000000000 PCMIN to EAR2O at 3 dBm0 PCMIN to EAR2O at 0 dBm0 PCMIN to EAR2O at - 5 dBm0 Receive signal-to-distortion ratio with 1020-Hz sine-wave input g PCMIN to EAR2O at - 10 dBm0 PCMIN to EAR2O at - 20 dBm0 PCMIN to EAR2O at - 30 dBm0 PCMIN to EAR2O at - 40 dBm0 PCMIN to EAR2O at - 45 dBm0 Intermodulation distortion, 2-tone CCITT method, composite , , power level, - 13 dBm0 NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB CCITT G.712 (7.1), R2 CCITT G.712 (7.2), R2 45 60 58 55 53 52 44 33 50 54 MIN TYP - 86 60 65 62 60 60 58 57 52 dB dB MAX - 82 UNIT dBm0
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11
TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
electrical characteristics, VDD = 2.7 V, TA = -40C to 105C (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation
PARAMETER Supply voltage rejection, transmit channel Supply voltage rejection, receive channel, EAR1 selected (differential) Crosstalk attenuation, transmit-to-receive (differential) Crosstalk attenuation, receive-to-transmit TEST CONDITIONS MIC1N, MIC1P =0 V, VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz PCM code = positive zero, VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured differentially between EAR1ON and EAR1OP PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at PCMO, EAR1 amplifier 70 70 MIN TYP - 80 - 90 MAX - 45 - 45 UNIT dB dB dB dB
DTMF generator
PARAMETER DTMF high to low tone relative amplitude (preemphasis) TEST CONDITIONS MIN 1.5 TYP 2 MAX 2.5 UNIT dB
MICBIAS
PARAMETER Load impedance TEST CONDITIONS MIN 2.0 TYP MAX 2.5 UNIT k
timing requirements
clock
MIN tt Transition time, MCLK MCLK frequency MCLK jitter Number of PCMCLK clock cycles per PCMSYN frame tc(PCMCLK) PCMCLK clock period Duty cycle, PCMCLK 256 156 45% 488 50% 2.048 NOM MAX 10 2.048 37% 256 512 68% ns UNIT ns MHz
transmit (see Figure 6)
MIN tsu(PCMSYN) th(PCMSYN) Setup time, PCMSYN high before PCMCLK Hold time, PCMSYN high after PCMCLK 20 20 MAX tc(PCMCLK)- 20 tc(PCMCLK)- 20 UNIT ns
receive (see Figure 5)
MIN tsu(PCSYN) th(PCSYN) tsu(PCMI) th(PCMI) Setup time, PCMSYN high before PCMCLK Hold time, PCMSYN high after PCMCLK Setup time, PCMI high or low before PCMCLK Hold time, PCMI high or low after PCMCLK 20 20 20 20 MAX tc(PCMCLK)- 20 tc(PCMCLK)- 20 UNIT ns ns ns ns
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
timing requirements (continued)
I2C bus (see Figure 6)
MIN SCL tHIGH tLOW tR tF thD:STA tsu:STA thD:DAT tsu:DAT tsu:STO tBUF Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Hold time (repeated) START condition. After this period the first clock pulse is generated. Setup time for repeated START condition Data input hold time Data input setup time STOP condition setup time Bus free time 600 600 0 100 600 1300 600 1300 300 300 MAX 400 UNIT kHz ns ns ns ns ns ns ns ns ns ns
switching characteristics
propagation delay times, CLmax = 10 pF (see Figure 5)
MIN tpd1 tpd2 tpd3 From PCMCLK bit 1 high to PCMO bit 1 valid From PCMCLK high to PCMO valid, bits 2 to n From PCMCLK bit n low to PCMO bit n Hi-Z 30 MAX 35 35 UNIT ns ns ns
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
SCL
SDA
A6
A5
A4
A0 R/W 0
ACK 0
R7
R6
R5
R0 ACK 0
D7
D6
D5
D0
ACK 0
Start
Slave Address
Register Address
Data
Stop
NOTE: SLAVE = VBAP
Figure 1. I2C Bus Write to VBAP
SCL
SDA Start
A6
A5
A0 R/W ACK 0 0
R7
R6
R0 ACK
A6
A0
R/W ACK 1 0
D7
D6
D0 ACK Stop Master Drives ACK and Stop
Slave Address
Register Address Repeated Start
Slave Address
Slave Drives The Data
NOTE: SLAVE = VBAP
Figure 2. I2C Read From VBAP: Protocol A
SCL
SDA Start
A6 A5
A0 R/W ACK 0 0
R7
R6
R0 ACK Stop Start
A6 A5
A0 R/W ACK D7
D0 ACK Stop Master Drives ACK and Stop
Slave Address
Register Address
Slave Address
Slave Drives The Data
NOTE: SLAVE = VBAP
Figure 3. I2C Read From VBAP: Protocol B
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION register map addressing
REG Power control Mode control TXPGA RXPGA High DTMF Low DTMF 00 01 02 03 04 05 07 Sidetone En Comp Sel PD0 RP3 HIFREQ Sel7 LOFREQ Sel7 06 TXEn TMEn TP3 RP2 HIFREQ Sel6 LOFREQ Sel6 05 RXEn PCMLB TP2 RP1 HIFREQ Sel5 LOFREQ Sel5 04 MICSEL Comp En TP1 RP0 HIFREQ Sel4 LOFREQ Sel4 03 BIASEn BUZZEn TP0 RV3 HIFREQ Sel3 LOFREQ Sel3 02 RXEn RXFLTR En ST2 RV2 HIFREQ Sel2 LOFREQ Sel2 01 EAROUT Sel TXFLTR En ST1 RV1 HIFREQ Sel1 LOFREQ Sel1 00 PWRUP TXSLOPE En ST0 RV0 HIFREQ Sel0 LOFREQ Sel0
register power-up defaults
REG Power control Power control Mode control TXPGA RXPGA High DTMF 00 00 01 02 03 04 07 1 1 0 0 0 0 0 06 1 0 0 1 1 0 0 05 1 0 0 0 1 0 0 04 1 1 0 0 1 0 0 03 0 1 0 0 0 0 0 02 1 0 0 0 0 0 0 01 1 1 1 0 0 0 0 00 0 1 0 0 0 0 0
Low DTMF 05 Value when PWRUPSEL = 0 Value when PWRUPSEL = 1
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION register map
Table 1. Power Control Register: Address {00} HEX
BIT NUMBER 7 1 1 X X X X X X X X X X X X X X 0 1 6 1 0 X X X X X X X X X X X 0 1 1 X X 5 1 0 X X X X X 0 1 X X X X X 0 1 X X 4 1 1 X X X X X X X X X 1 0 X X X X X 3 0 1 X X X X X X X 1 0 X X X X X X X 2 1 0 X X X X 0 1 1 X X X X X X X X X 1 1 1 X X 1 0 X X X X X X X X X X X X 0 0 1 0 1 X X X X 0 X X X X X X X X X Default setting PWRUPSEL = 0 Default setting PWRUPSEL = 1 Reference system, power down Reference system, power up EAR AMP1 selected, EAR AMP2 power down EAR AMP2 selected, EAR AMP1 power down Receive channel enabled Receive channel muted Receive channel, power down MICBIAS selected MICBIAS power down MIC1 selected MIC2 selected Transmit channel enabled Transmit channel muted Transmit channel power down Sidetone enabled Sidetone muted DEFINITIONS
Table 2. Mode Control Register: Address {01} HEX
BIT NUMBER 7 0 X X X X X X X X X 1 0 X X X X 6 0 X X X X X X X X X X X X X 0 1 5 0 X X X X X X X X X X X 0 1 X X 4 0 X X X X X X X X 0 1 1 X X X X 3 0 X X X X X X 0 1 X X X X X X X 2 0 X X X X 0 1 X X X X X X X X X 1 1 0 0 1 1 X X X X X X X X X X X 0 0 0 1 0 1 X X X X X X X X X X X Default setting TX channel high-pass filter enabled and slope filter enabled TX channel high-pass filter enabled and slope filter disabled TX channel high-pass filter disabled and slope filter enabled TX channel high-pass filter disabled and slope filter disabled RX channel high-pass filter disabled (low pass only) RX channel high-pass filter enabled BUZZCON disabled BUZZCON enabled Linear mode selected A-law companding mode selected -law companding mode selected TX and RX channels normal mode PCM loopback mode Tone mode disabled Tone mode enabled DEFINITIONS
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
Transmit PGA and sidetone control register: Address {02}HEX Bit definitions:
7 PDO 0 6 TP3 1 5 TP2 0 4 TP1 0 3 TP0 0 2 ST2 0 1 ST1 0 0 ST0 0 DEFINITION See Table 2 and Table 4 Default setting
Receive volume control register: Address {03}HEX Bit definitions :
7 RP3 0 6 RP2 1 5 RP1 1 4 RP0 1 3 RV3 0 2 RV2 0 1 RV1 0 0 RV0 0 DEFINITION See Table 3 and Table 5 Default setting
High tone selection control register: Address {04}HEX Bit definitions:
7 X 0 6 X 0 5 X 0 4 X 0 3 X 0 2 X 0 1 X 0 0 X 0 DEFINITION DTMF (see Table 7) Default setting
Low tone selection control register: Address {05}HEX Bit definitions:
7 X 0 6 X 0 5 X 0 4 X 0 3 X 0 2 X 0 1 X 0 0 X 0
Transmit Time Slot 0 80% PCMCLK tsu(PCMSYN) th(PCMSYN) 20% 20% 1 2 3 4 N-2 N-1 N 80% N+1
DEFINITION DTMF (see Table 7) Default setting
PCMSYN
See Note A PCMO
NOTES: A. B. C. D.
This window is allowed for PCMSYN high. This window is allowed for PCMSYN low (th(PCMSYN)max determined by data collision considerations). Transitions are measured at 50%. Bit 1 = MSB, Bit N = LSB
IIIIIIII I II I IIIIIIII I II I IIIIIIII I II I
1 See Note C tpd1
tpd2 2 See Note D 3
See Note B tpd3 4 N-2 N-1 N
tsu(PCMO)
Figure 4. Transmit Timing Diagram
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
Receive Time Slot 0 80% PCMCLK tsu(PCMSYN) PCMSYN 20% th(PCMSYN) 20% 1 2 3 4 N -2 N -1 N 80% N +1
PCMI
A. B. C. D.
SDA tBUF tLOW SCL thd(STA) thd(DAT) tHIGH tsu(DAT) tsu(STA) STA tsu(STO) STO tr tf thd(STA)
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IIIIIIIII II IIIIIIIII II
See Note A See Note C 1 STO STA
See Note B th(PCMI) 3 4 N -2 N -1 tsu(PCMI) N
See Note D 2
This window is allowed for PCMSYN high. This window is allowed for PCMSYN low. Transitions are measured at 50%. Bit 1 = MSB, Bit N = LSB
Figure 5. Receive Timing Diagram
Figure 6. I2C Bus Timing Diagram
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PRINCIPLES OF OPERATION power-on initialization
An external reset with a minimum pulse width of 500 ns must be applied to the active low RESET terminal to guarantee reset upon power on. All registers are set with default values upon external reset initialization. The desired selection for all programmable functions can be initialized prior to a power-up command using the I2C interface. Table 3. Power-Up and Power-Down Procedures (VDD = 2.7 V, Earphone amplifier unloaded)
DEVICE STATUS Power up Power down PROCEDURE Set bit 1 = 1 in power control register, EAR1 enabled Set bit 1 = 0 in power control register, EAR2 enabled Set bit 7 = 1 in TXPGA control register and bit 0 = 0 Set bit 7 = 0 in TXPGA control register and bit 0 = 0 MAXIMUM POWER CONSUMPTION 16.2 mW 14.6 mW 1.35 W 67.5 W
In addition to resetting the power-down bit in the power control register, loss of MCLK (no transition detected) automatically enters the device into a power-down state with PCMO in the high impedance state. If during a pulse code modulation (PCM) data transmit cycle an asynchronous power down occurs, the PCM interface remains powered up until the PCM data is completely transferred. An additional power-down mode overrides the MCLK detection function. This allows the device to enter the power-down state without regard to MCLK. Setting bit 7 of the TX filter and PGA sidetone register to logic high enables this function.
conversion laws
The device can be programmed either for a 15-bit linear or 8-bit (-law or A-law) companding mode. The companding operation approximates the CCITT G.711 recommendation. The linear mode operation uses a 15-bit twos-complement format.
transmit operation
microphone input The microphone input stage is a low noise differential amplifier that provides a preamplifier gain of 23.5 dB. A microphone can be capacitively connected to the MIC1N and MIC1P inputs, while the MIC2N and MIC2P inputs can be used to capacitively connect a second microphone or an auxiliary audio circuit.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PRINCIPLES OF OPERATION transmit operation (continued)
MBIAS
_ + Vref
Rmic Ci MIC1N
M I C
510 k 34 k _ + Ci MIC1P 34 k 510 k
Rmic
Figure 7. Typical Microphone Interface microphone mute function Transmit channel muting provides 80-dB attenuation of input microphone signal. The MICMUTE function can be selected by setting bit 6 of the power control register through the I2C interface. transmit channel gain control The values in the transmit PGA control registers control the gain in the transmit path. The total TX channel gain can vary from 35.5 dB to 13.5 dB. The default total TX channel gain is 23.5 dB Table 4. Transmit Gain Control
BIT NAME TP3 0 0 0 0 0 0 1 1 1 1 1 1 TP2 0 0 0 0 1 1 0 0 0 0 1 1 TP1 0 0 1 1 0 0 0 0 1 1 0 0 TP0 0 1 0 1 0 1 0 1 0 1 0 1 MIC AMP1 GAIN 23.5 23.5 23.5 23.5 23.5 23.5 23.5 23.5 23.5 23.5 23.5 23.5 MIC AMP2 GAIN 12 12 12 12 12 12 0 0 0 0 0 0 TX PGA GAIN 0 -2 -4 -6 -8 -10 0 -2 -4 -6 -8 -10 Extended Extended Extended Extended Extended Extended Normal Normal Normal Normal Normal Normal GAIN MODE MIN 35.3 33.3 31.3 29.3 27.3 25.3 23.3 21.3 19.3 17.3 15.3 13.3 TOTAL TX GAIN TYP 35.5 33.5 31.5 29.5 27.5 25.5 23.5 21.5 19.5 17.5 17.5 13.5 MAX 35.7 33.7 31.7 29.7 27.7 25.7 23.7 21.7 19.7 17.7 17.7 13.7 UNIT dB dB dB dB dB dB dB dB dB dB dB dB
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PRINCIPLES OF OPERATION receive operation
receive channel gain control The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from - 6 dB to 6 dB in 1-dB steps through the I2C interface. The default receive channel gain is -1 dB. Table 5. Receive PGA Gain Control
BIT NAME RP3 0 0 0 0 0 0 0 0 1 1 1 1 1 RP2 0 0 0 0 1 1 1 1 0 0 0 0 1 RP1 0 0 1 1 0 0 1 1 0 0 1 1 0 RP0 0 1 0 1 0 1 0 1 0 1 0 1 0 MIN 5.8 4.8 3.8 2.8 1.8 0.8 - 0.2 -1.2 - 2.2 - 3.2 - 4.2 - 5.2 - 6.2 RELATIVE GAIN TYP 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 MAX 6.2 5.2 4.2 3.2 2.2 1.2 0.2 - 0.8 -1.8 - 2.8 - 3.8 - 4.8 - 5.8 UNIT dB dB dB dB dB dB dB dB dB dB dB dB dB
sidetone gain control The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from -12 dB to - 24 dB in 2-dB steps through the I2C interface. Sidetone can be muted by setting bit 7 of the power control register. The default sidetone gain is -12 dB. Table 6. Sidetone Gain Control
BIT NAME ST2 0 0 0 0 1 1 1 ST1 0 0 1 1 0 0 1 ST0 0 1 0 1 0 1 0 MIN -12.2 -14.2 -16.2 -18.2 - 20.2 - 22.2 - 24.2 RELATIVE GAIN TYP -12 -14 -16 -18 - 20 - 22 - 24 MAX -11.8 -13.8 -15.8 -17.8 -19.8 - 21.8 - 23.8 UNIT dB dB dB dB dB dB dB
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PRINCIPLES OF OPERATION receive operation (continued)
receive volume control The values in the volume control PGA control registers provide volume control into the earphone. Volume control gain is set from 0 dB to -18 dB in 2-dB steps through the I2C interface. The default RX volume control gain is 0 dB. Table 7. rx Volume Control
BIT NAME RV3 0 0 0 0 0 0 0 0 1 1 RV2 0 0 0 0 1 1 1 1 0 0 RV1 0 0 1 1 0 0 1 1 0 0 RV0 0 1 0 1 0 1 0 1 0 1 MIN - 0.2 - 2.2 - 4.2 - 6.2 - 8.2 -10.2 -12.2 -14.2 -16.2 -18.2 RELATIVE GAIN TYP 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 MAX 0.2 -1.8 - 3.8 - 5.8 -7.8 - 9.8 -11.8 -13.8 -15.8 -17.8 UNIT dB dB dB dB dB dB dB dB dB dB
earphone amplifier The analog signal can be routed to one of two earphone amplifiers: one with differential output (EAR1ON and EAR1OP) capable of driving a 16- load or one with single-ended output (EAR2O) capable of driving a 32- load. earphone mute function Muting can be selected by setting bit 3 of the power control register through the I2C interface. receive PCM data format
D D
Companded mode: eight bits are received, the most significant (MSB) first. Linear mode: 15 bits are received, MSB first.
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PRINCIPLES OF OPERATION receive operation (continued)
Table 8. Receive-Data Bit Definitions
BIT NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 COMPANDED MODE CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 - - - - - - - - LINEAR MODE LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 --
Transmit channel gain control bits always follow the PCM data in time: CD7- CD0 = data word in companded mode LD14- LD0 = data word in linear mode
DTMF generator operation and interface
The dual-tone multifrequency generator (DTMF) circuit generates the summed DTMF tones for push button dialing and provides the PDM output for the BUZZCON user-alert tone. There are 255 possible single tones. The tone integer value is determined by the formula: Round (tone frequency (Hz)/7.8125 Hz) The integer value is loaded into either one of two 8-bit registers, high-tone register (04), or low-tone register (05). The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the high frequency value must be applied to the high-tone register (04) and the low DTMF value to the low-tone register.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PRINCIPLES OF OPERATION DTMF generator operation and interface (continued)
Table 9. Typical DTMF and Single Tone Control
DT7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 DT6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 DT5 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 DT4 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 1 DT3 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 DT2 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 DT1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 DT0 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 INTEGER VALUE 0 45 47 50 53 56 60 63 67 71 75 80 84 89 95 100 106 113 119 126 134 142 150 159 169 179 189 201 213 225 239 253 89 99 109 120 155 171 189 209 TONE FUNCTION OFF F F# G G# A A# B C C# D D# E F F# G G# A A# B C C# D D# E F F# G G# A A# B DTMF Low DTMF Low DTMF Low DTMF Low DTMF HIgh DTMF HIgh DTMF HIgh DTMF HIgh TONE/HZ 0 349 370 392 415 440 466 494 523 554 587 622 659 698 740 784 831 880 932 988 1047 1109 1175 1245 1319 1397 1480 1568 1661 1760 1865 1976 697 770 852 941 1209 1336 1477 1633
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SGLS120A - APRIL 2002 - REVISED MAY 2002
PRINCIPLES OF OPERATION DTMF generator operation and interface (continued)
Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the individual output ports. The values that determine the tone frequency are loaded into the tone registers (high and lo) as two separate values. The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in twos complement value into the the tone registers. There is a 2 dB difference in the resulting output of the two registers, the high-tone register having the greater result. The resulting range of a tone set into the low register value is +31 {1F}HEX to -32 {20}HEX for a range of six bits and is in twos complement format. The resulting range of a tone set into the high register value is +39 {27}HEX to -40 {D8}HEX in twos-complement format, as well. The maximum range is six bits having a maximum value of {31}HEX. The value {31} is represented as 011111. Two zeros are added to the leading side of the value and then the value is padded with seven LSB zeros to create a value of 000 1111 1000 0000. Because the maximum full scale value is 000 1111 1000 0000, the resulting output magnitude is 20 log (input value/maximum value) or 20 log (3968/16783) or -12.31 dB below full scale. This is the result when all gains are set at default. buzzer logic section The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver transistor. The PDM begins as a selected tone, is generated and passed through the receive D/A channel, and is fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the BUZZCON output. support section The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive internal counters, filters, and converters. Register control data is written into and read back from the VBAP registers via the control interface. I2C- bus protocols The VBAP serial interface is designed to be I2C bus-compatible and operates in the slave mode. This interface consists of the following terminals: SCL: I2C bus serial clock--This input synchronizes the control data transfer from and to the CODEC. SDA: I2C bus serial address/data input/output--This is a bidirectional terminal that transfers register control addresses and data into and out of the codec. It is an open drain terminal and therefore requires a pullup resistor to VCC (typical 10 k for 100 kHz). TWL1103 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode. For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are reserved for indicating the start and stop conditions. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted as a start or stop condition.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
PRINCIPLES OF OPERATION
Table 10. I2C Bus Conditions
CONDITION A B C D STATUS Bus not busy Start data transfer Stop data transfer Data valid DESCRIPTION Both data and clock lines remain at high. A high to low transition of the SDA line while the clock (SCL) is high determines a start condition. All commands must proceed from a start condition. A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition. All operations must end with a stop condition. The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal.
I2C bus protocols The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the VBAP generates an acknowledge after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit. The VBAP must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (VBAP) must leave the data line high to enable the master to generate the stop condition. clock frequencies and sample rates A fixed PCMSYN rate of 8 kHz determines the sampling rate.
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TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP)
SGLS120A - APRIL 2002 - REVISED MAY 2002
MECHANICAL DATA
PBS (S-PQFP-G32)
0,23 0,17 24 17
PLASTIC QUAD FLATPACK
0,50
0,08 M
25
16
32
9 0,13 NOM
1 3,50 TYP 5,05 SQ 4,95 7,10 SQ 6,90 1,05 0,95
8 Gage Plane
0,25 0,10 MIN 0,70 0,40 0- 7
Seating Plane 1,20 MAX 0,08 4087735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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