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TSC 80251G1
TSC 80251G1 Extended 8-bit Microcontroller with Serial Communication Interfaces
Design Guide - 1996
MATRA MHS
TSC 80251G1
TEMIC reserves the right to make changes in the products or specifications contained in this document in order to improve design or performance and to supply the best possible products. TEMIC also assumes no responsibility for the use of any circuits described herein, conveys no license under any patents or other rights, and makes no representations that the circuits are free from patent infringement. Applications for any integrated circuits contained in this publication are for illustration purposes only and TEMIC makes no representation or warranty that such applications will be suitable for the use specified without further testing or modification. Reproduction of any portion hereof without the prior written consent of TEMIC is prohibited. ETEMIC Semiconductors 1996.
On line information
World Wide Web: http://www.temic.de
Publisher MATRA MHS S.A. La Chantrerie Route de Gachet, BP 70602 44306 NANTES Cedex 03 France Fax: +33 2 40 18 19 60
Copyright INTEL Corporation 1994. Portions reprinted by permission of INTEL Corporation. "Quick Pulse Algorithm" is a trademark of INTEL. "I2C" is a trademark of PHILIPS. "SPI" is a trademark of MOTOROLA. "mWire" is a trademark of NATIONAL SEMICONDUCTOR.
MATRA MHS
TSC 80251G1
Table of Contents
General Introduction
Extended 8-bit Microcontroller with Analog Interfaces . . . . . . . . . . . . . . . . . 1.
Section I: Introduction to TSC80251G1
Chapter 1: Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 1.1 Chapter 2: Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 2.1 Chapter 3: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 3.1 Chapter 4: Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 4.1
Section II: Design Information
Chapter 1: Configuration and Memory Mapping . . . . . . . . . . . . . . . . . . II. 1.1
1.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.1 1.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.1
1.2.1. Page Mode and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.1 1.2.2. Real-time Wait States Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.4 1.2.3. External Memory Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.4 1.2.3.1. How to Address 256 Kbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.4 1.2.3.2. How to Address 128 Kbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.5 1.2.3.3. How to Address 64 Kbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.5 1.2.3.4. How to Keep C51 Memory Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.6
1.3. Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.7
1.3.1. Configuration Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.7 1.3.2. Program/Code Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.7 1.3.3. Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.9
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
1.3.4. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.10
Chapter 2: Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.1
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.1 2.2. I/O Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.3 2.3. Port 1 and Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.3 2.4. Port 0 and Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.4 2.5. Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.6 2.6. Quasi-Bidirectional Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.6 2.7. Port Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.7 2.8. External Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.8
Chapter 3: Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.1
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.1 3.2. Timer/Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.3 3.3. Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.3
3.3.1. Mode 0 (13-bit Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2. Mode 1 (16-bit Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3. Mode 2 (8-bit Timer with Auto-Reload) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4. Mode 3 (Two 8-bit Timers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1. Mode 0 (13-bit Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2. Mode 1 (16-bit Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3. Mode 2 (8-bit Timer with Auto-Reload) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4. Mode 3 (Halt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.3 II. 3.4 II. 3.5 II. 3.6 II. 3.7 II. 3.7 II. 3.7 II. 3.7
3.4. Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.6
3.5. Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.7
3.5.1. Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.8 3.5.2. Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.9 3.5.3. Baud Rate Generator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.10 3.5.4. Clock-Out Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.10
3.6. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.12
Chapter 4: Serial I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.1
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.1 4.2. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.3
4.2.1. Synchronous Mode (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.3 4.2.1.1. Transmission (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.4 4.2.1.2. Receptionion (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.4 4.2.2. Asynchronous Modes (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
4.2.2.1. Transmission (Mode 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.5 4.2.2.2. Receptionion (Mode 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.5
4.3. Framing Bit Error Detection (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.5 4.4. Overrun Error Detection (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.5 4.5. Multiprocessor Communication (Modes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.6 4.6. Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.6
4.6.1. Given Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.7 4.6.2. Broadcast Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.8 4.6.3. Reset Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.8
4.7. Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.8
4.7.1. Baud Rate for Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.8 4.7.2. Baud Rate for Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.9 4.7.3. Baud Rate for Modes 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.10 4.7.3.1. Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.10 4.7.3.2. Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.10 4.7.3.3. Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.11 4.7.3.4. Internal Baud Rate Generator (BRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.14
4.8. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.16
Chapter 5: Event and Waveform Controller . . . . . . . . . . . . . . . . . . . . . . . II. 5.1
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.1 5.2. PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.1
5.2.1. Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.1 5.2.2. Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.2 5.2.2.1. 16-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.4 5.2.2.2. 16-bit Software Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.5 5.2.2.3. High-Speed Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.6 5.2.2.4. Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.6 5.2.2.5. Pulse Width Modulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.8
5.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.11
Chapter 6: SSLC / Inter-Integrated Circuit (I2C) Interface . . . . . . . . . . II. 6.1
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.1
6.1.1. Interface and Bit rate source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.3 6.1.2. Master transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.3 6.1.3. Master receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.4
6.2. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.10
Chapter 7: SSLC / Synchronous Peripheral Interface (mwire/SPI) . . . . . II. 7.1
7.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.1
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
7.2. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.2
7.2.1. Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.3 7.2.2. Data Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.5
7.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.7
Chapter 8: Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 8.1
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 8.1 8.2. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 8.1 8.3. Using the Hardware WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 8.1 8.4. Hardware WDT during Idle and Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . II. 8.1 8.5. Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 8.2
Chapter 9: Power Monitoring and Management . . . . . . . . . . . . . . . . . . . II. 9.1
9.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.1 9.2. Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.1 9.3. Power-Fail Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.2 9.4. Power-Off Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.2 9.5. Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.2 9.6. Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.3
9.6.1. Entering Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.3 9.6.2. Exiting Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.4 9.6.3. Recovering from Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.4
9.7. Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.4
9.7.1. Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.5 9.7.2. Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.5 9.7.3. Recovering from Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.6
9.8. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.7
Chapter 10: Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.1
10.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.1 10.2. Interrupt System Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.2 10.3. External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.4 10.4. Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.4 10.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.5
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Section III: Electrical and Mechanical Information
Chapter 1: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.1 Chapter 2: AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.1 Chapter 3: IC Interface AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . III. 3.1 Chapter 4: EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.1
4.1. Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.1 4.2. Verify algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.3
Chapter 5: TSC80C251G1: Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.1
5.1. List of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.1 5.2. PDIL 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.2
5.2.1. Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.2 5.2.2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.3
5.3. PLCC 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.4
5.3.1. Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.4 5.3.2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.5
5.4. CQPJ 44 with Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.6
5.4.1. Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.6 5.4.2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.7
5.5. PQFP 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.8
5.5.1. Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.8 5.5.2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.9
5.6. VQFP 44 (1010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.10
5.6.1. Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.10 5.6.2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.11
5.7. VQFP 44 (1414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.12
5.7.1. Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.12 5.7.2. Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.13
Section IV: Application Notes
How to Plug a TSC80251G1 Step A in a C51 Board ? . . . . . . . . . . . . . . . IV. 1.1
1.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.1
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
1.2. Pin-to-Pin Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.1 1.3. Configuration Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.1 1.4. Speed Increase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.5
Section V: Ordering Information
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V. 1.1
Section VI: TEMIC Addresses
Sales Offices Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VI. so.1 Representatives Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VI. rep.1 Distributors Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VI. dist.1
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
List of Figures
Section I: Introduction to TSC80251G1
Chapter 3: Block Diagram
Figure 3.1. TSC80251G1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 3.1
Chapter 4: Pin Description
Figure 4.1. TSC80251G1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 4.1
Section II: Design Information
Chapter 1: Configuration and Memory Mapping
Figure 1.1. Bus Structure in Non-Page Mode and Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.2 Figure 1.2. External Bus Cycle: Code Fetch, Non-Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.2 Figure 1.3. External Bus Cycle: Code Fetch, Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.3 Figure 1.4. External Bus Cycle: Code Fetch with One RD#/PSEN# Wait State in Non-Page Mode . . . . . . . . . . II. 1.3 Figure 1.5. Internal/External Memory Segments (RD1:0 = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.4 Figure 1.6. Internal/External Memory Segments (RD1:0 = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.5 Figure 1.7. Internal/External Memory Segments (RD1:0 = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.6 Figure 1.8. Internal/External Memory Segments (RD1:0 = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.6 Figure 1.9. Programmable Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.8 Figure 1.10. Data Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.9 Figure 1.11. Configuration Byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.12 Figure 1.12. Configuration Byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.13
Chapter 2: Parallel I/O Ports
Figure 2.1. Port 1 and Port 3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.4 Figure 2.2. Port 0 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.5 Figure 2.3. Port 2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.5 Figure 2.4. Internal Pull-Up Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.7
Chapter 3: Timers/Counters
Figure 3.1. Timer/Counter x (x = 0 or 1) in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.4 Figure 3.2. Timer/Counter x (x = 0 or 1) in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.4 Figure 3.3. Timer/Counter x (x = 0 or 1) in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.5 Figure 3.4. Timer/Counter 0 in Mode 3 : Two 8-bit Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Figure 3.5. Timer 2: Auto Reload Mode Up Counter (DCEN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.8 Figure 3.6. Timer 2: Auto Reload Mode Up/Down Counter (DCEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.9 Figure 3.7. Timer 2: Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.10 Figure 3.8. Timer 2: Clock Out Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.11 Figure 3.9. TCON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.12 Figure 3.10. TMOD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.13 Figure 3.11. T2CON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.14 Figure 3.12. T2MOD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.15
Chapter 4: Serial I/O Port
Figure 4.1. Serial Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.1 Figure 4.2. Mode 0 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.3 Figure 4.3. Data Frames (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.5 Figure 4.4. Overrun Error (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.6 Figure 4.5. Clock Transmission Sources in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.9 Figure 4.6. UART in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.9 Figure 4.7. Baud Rate Generator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.10 Figure 4.8. Timer 1 as Baud Rate Generator in Modes 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.10 Figure 4.9. Timer 2 in Baud Rate Generator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.12 Figure 4.10. Internal Baud Rate Generator in Modes 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.14 Figure 4.11. BDRCON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.16 Figure 4.12. BRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.17 Figure 4.13. SADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.17 Figure 4.14. SADEN Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.17 Figure 4.15. SBUF Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.17 Figure 4.16. SCON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.18
Chapter 5: Event and Waveform Controller
Figure 5.1. EWC Counter in PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.2 Figure 5.2. PCA 16-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.5 Figure 5.3. PCA Software Timer and High-Speed Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.6 Figure 5.4. PCA Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.8 Figure 5.5. PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.9 Figure 5.6. PWM Variable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.10
Chapter 6: SSLC / Inter-Integrated Circuit (I2C) Interface
Figure 6.1. Typical I2C Bus Configuration using the TSC80251G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.1 Figure 6.2. Complete data transfer on I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.2 Figure 6.3. Format and States in the Master Transmitter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Figure 6.4. Format and state in the master receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.7 Figure 6.5. SSBR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.10 Figure 6.6. SSCON register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.10 Figure 6.7. SSCS register: read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.11 Figure 6.8. SSDAT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.11 Figure 6.9. SSCS register: write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.12
Chapter 7: SSLC / Synchronous Peripheral Interface
Figure 7.1. Typical SPI Bus Configuration using TSC80251G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.1 Figure 7.2. Wire and Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.2 Figure 7.3. Data Transmission (a/ SSCPHA = 0, b/ SSCPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.4 Figure 7.4. SSBR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.7 Figure 7.5. SSCON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.7 Figure 7.6. SSCS Register: write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.8 Figure 7.7. SSDAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 7.8
Chapter 8: Hardware Watchdog Timer
Figure 8.1. WDTRST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 8.2
Chapter 9: Power Monitoring and Management
Figure 9.1. Block Diagram of the On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.3 Figure 9.2. Symbolic of the On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.3 Figure 9.3. CKRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.7 Figure 9.4. PCON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.7 Figure 9.5. PFILT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.8 Figure 9.6. POWM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.8
Chapter 10: Interrupt System
Figure 10.1. Minimum Pulse Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.4 Figure 10.2. Keyboard Interface Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.5 Figure 10.3. IE0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.6 Figure 10.4. IE1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.7 Figure 10.5. IPH0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.8 Figure 10.6. IPH1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.9 Figure 10.7. IPL0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.10 Figure 10.8. IPL1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.11 Figure 10.9. P1F Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.12 Figure 10.10. P1IE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.13 Figure 10.11. PILS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.14
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Section III: Electrical and Mechanical Information
Chapter 1: DC Characteristics
Figure 1.1. IPD Test Condition, Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.3 Figure 1.2. IDL Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.4 Figure 1.3. IDD Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.4 Figure 1.4. Wait Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.4
Chapter 2: AC Characteristics
Figure 2.1. External Instruction Bus Cycle in Non-Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.3 Figure 2.2. External Data Read Cycle in Non-Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.3 Figure 2.3. External Write Data Bus Cycle in Non-Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.4 Figure 2.4. External Instruction Bus Cycle in Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.4 Figure 2.5. External Read Data Bus Cycle in Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.5 Figure 2.6. External Write Data Bus Cycle in Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.5 Figure 2.7. Serial Port Waveform - Shift Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.6
Chapter 3: IC Interface AC/DC Characteristics
Figure 3.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 3.2
Chapter 4: EPROM Programming
Figure 4.1. Setup for EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.1 Figure 4.2. Timings for EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.2 Figure 4.3. Setup for EPROM Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.3 Figure 4.4. Timings for EPROM Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.4
Chapter 5: Packages
Figure 5.1. Plastic Dual In Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.2 Figure 5.2. Plastic Lead Chip Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.4 Figure 5.3. Ceramic Quad Pack J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.6 Figure 5.4. Plastic Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.8 Figure 5.5. Shrink Quad Flat Pack (Plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.10 Figure 5.6. Shrink Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.12
Section IV: Application Notes
Chapter 1: How to Plug a TSC80251G1 Step A in a C51 Board ?
Figure 1.1. Configuration Byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.3 Figure 1.2. Configuration Byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
List of Tables
Section I: Introduction to TSC80251G1
Chapter 4: TSC80251G1 Pin Description
Table 4.1. TSC80251G1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I. 4.2
Section II: Design Information
Chapter 1: Configuration and Memory Mapping
Table 1.1. SFR addresses and Reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 1.11
Chapter 2: Parallel I/O Ports
Table 2.1. Port 0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.1 Table 2.2. Port 1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.2 Table 2.3. Port 2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.2 Table 2.4. Port 3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.3 Table 2.5. Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.6 Table 2.6. Instructions for External Data Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 2.8
Chapter 3: Timers/Counters
Table 3.1. Timer/Counter SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.1 Table 3.2. External signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.2 Table 3.3. Timer 2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 3.8
Chapter 4: Serial I/O Port
Table 4.1. Serial Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.2 Table 4.2. Serial Port SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.2 Table 4.3. Timer 1 Generated Baud Rates at 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.11 Table 4.4. Timer 1 Generated Baud Rates at 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.11 Table 4.5. Timer 2 Generated Baud Rates at 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.13 Table 4.6. Timer 2 Generated Baud Rates at 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.13 Table 4.7. Internal Baud Rate Generator at 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.15 Table 4.8. Internal Baud Rate Generator at 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 4.15
Chapter : Event and Waveform Controller
Table 5.1. PCA Module Modes (x = 0, 1, 2, 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 5.4
Chapter 6: SSLC / Inter Integrated Circuit Interface
Table 6.1. PCA module modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 6.4
Chapter 9: Power Monitoring and Management
Table 9.1. Pin Conditions in Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 9.1
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Chapter 10: Interrupt System
Table 10.1. Interrupt System Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.1 Table 10.2. Interrupt System SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.2 Table 10.3. Level of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.3 Table 10.4. Interrupt Priority within Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II. 10.3
Section III: Electrical and Mechanical Information
Chapter 1: DC Characteristics
Table 1.1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.1 Table 1.2. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.1 Table 1.3. Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 1.5
Chapter 2: AC Characteristics
Table 2.1. AC Characteristics (Capacitive Loading = 50 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 2.1
Chapter 4: EPROM Programming
Table 4.1. EPROM Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.1 Table 4.2. EPROM Verifying Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.3 Table 4.3. EPROM Programming & Verification Characteristics ( TA = 21 to 275C ; VCC = 5V +/- 0.25V ; VSS= 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 4.4
Chapter 5: Packages
Table 5.1. PDIL Package Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.2 Table 5.2. PDIL Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.3 Table 5.3. PLCC Package Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.4 Table 5.4. PLCC Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.5 Table 5.5. CQPJ Package Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.6 Table 5.6. CQPJ Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.7 Table 5.7. PQFP Package Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.8 Table 5.8. PQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.9 Table 5.9. VQFP Package Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.10 Table 5.10. VQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.11 Table 5.11. VQFP Package Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.12 Table 5.12. VQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III. 5.13
Section IV: How to Plug a TSC80251G1 Step A in a C51 Board ?
Table 1.1. Configuration Bytes Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.2 Listing 1.1. Loop Executed at 12 MHz on 80C51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV. 1.5 Listing 1.2. Loop Executed at 12 MHz on TSC80251G1 Without Code Modification . . . . . . . . . . . . . . . . . . . . IV. 1.6 Listing 1.3. Loop Executed at 12 MHz on TSC80251G1 With Code Modification . . . . . . . . . . . . . . . . . . . . . . . IV. 1.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
General Introduction
TSC 80251G1
Extended 8-bit Microcontroller with Serial Communication Interfaces
The TSC80251G1 products are derivatives of the TEMIC Application Specific Microcontroller family based on the extended 8-bit C251 architecture described below. This family of products are tailored to microcontroller applications requiring highly increased instruction throughput and addressable memory space combined with an optimized internal power management. Three major features have been implemented to provide optimized performance to the designer: E Serial Communication Interfaces: I2C/Wire/SPI and RS232 protocols E Power Monitoring and Management Unit: Power-Fail reset Internal clock prescaler Power-Down mode (current < 20A) E 256 Kbytes of external addressable memory for code and data
1.1. Application Focus
Typical applications for these products are ISDN-terminals, digital and analog subscriber linecards, PABX systems, networking applications, high speed modems, computer peripherals or similar systems in other segments. With the high instruction throughput, the TSC80251G1 products are focusing on all high-end 8-bit to 16-bit applications. They are also well suited to systems where a lower operating frequency is needed to reduce power consumption or Radio Frequency Interference (RFI), while maintaining a high level of CPU power.
1.2. C251 Architecture
The C251 architecture at its lowest performance level, is binary code compatible with the 80C51 architecture. Due to a 3-stage instruction pipeline, the average CPU performance is increased by 5 times, using existing 80C51 code without any modification. Using the new C251 instruction set, the performance is increased by up to 15 times, at the same clock rate. This performance enhancement is based on a new 16-bit and even partly 32-bit oriented powerful instruction set, and additional internal 8 and 16-bit data busses. A 24-bit address bus will allow an extension of the address space up to 16 Mbytes for future derivatives. Programming flexibility and C-code efficiency are both increased by the register-based architecture, the 64-Kbyte extended stack space and the new instruction set. Combining the above features of the C251 core, the final code size could be reduced by a factor of 3, compared to an 80C51 implementation. The TSC80251G1 derivatives implement Intel's core revision A and all technical information in this document relates to this revision. The latest Intel's core revision is presently being integrated by TEMIC.
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TSC 80251G1
Both revisions are upward compatible, so that no problem will appear if a revision A product is replaced by a new one. The major differences are some additional features in the configuration bytes and a modified emulator interface which is not impacting your application. This document will be released as soon as the first TSC80251G1 product will be available in the new revision.
1.3. TSC80251G1 Products
The TSC80251G1 is available as a ROMless version (TSC80251G1) or with on-chip Mask Programmable ROM (TSC83251G1). The TSC87251G1 is an EPROM version compatible to the Mask ROM version. The standard production packages are 44 pins PLCC or QFP, 40 pins PDIL. All products can be delivered as 12 or 16 MHz versions at 5 Volts and in all major temperature ranges. ROMless and Mask ROM versions are also available in 3 Volts.
1.4. TSC80251G1 Documentation and Tools
The following documentation and Starter tools are available to use of the TEMIC TSC80251G1 derivatives: E "TSC80251G1 Extended 8-bit Microcontroller with Serial Communication Interfaces Design Guide" Contains all information about the G1 derivatives (block diagram, memory mapping, peripheral description, electrical mechanical and ordering information) and application notes. E "TSC80251 Extended 8-bit Microcontrollers Programmer`s Guide" Contains all information for the programmer (architecture, instruction set, programming, software tools). E "TSC80251G1 Starter Kits" These kits enable the TSC80251G1 to be evaluated by the designer. Their contents is: C-Compiler (limited to 2 Kbytes of code) Assembler Linker TSC80251G1 Simulator TSC80251G1 Evaluation Board with ROM-Monitor (Evaluation Kit only) Please visit our WWW for updated versions in ZIP format. E "TSC80251G1 Development Tools" See chapter "Tool Vendors" in the Programmer's Guide (Keil, Tasking, Hitex, Metalink, Nohau). E World Wide Web Please contact our WWW for possible updated information at http://www.temic.de E TSC80251 e-mail hotline: C251@temic.fr
2.
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1
Section I
Introduction to TSC80251G1
TSC 80251G1
Core Features
Based on the extended 8-bit C251 architecture, the TSC80251G1 includes a complete set of new or improved C51 compatible peripherals as well as multiple protocol serial interfaces.
The key features of the new C251 architecture are: E Intel's MCS 251 compliance E Register-based architecture: 40-byte register file Registers accessible as bytes, words, and double word E 3-stage instruction pipeline E Enriched instruction set 16-bit and 32-bit arithmetic and logic instructions Compare and conditional jump instructions Expanded set of move instructions E Reduced instruction set 189 generic instructions Free space for additional instructions in the future Additionally all 80C51 instructions are usable in binary mode E 16-bit internal code fetch E 64 Kbytes extended stack space E Maximum addressable memory of 16 Mbytes The benefits of this new architecture are: E 5 times 80C51 performances in binary mode (80C51 binary code compatibility) E 15 times 80C51 performances in source mode (full architecture performance) E Efficient C language support: up to a factor 3 of code size reduction (when a C program for 80C51 is recompiled in C251 language) E Complete system development support Compatible with existing tools New tools available: C-Compiler, Assembler, Debugger, ICE E Reduction of RFI and power consumption (reduced operating frequency)
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Product Features
E E E E E E E E E E E C251 core based (MCS 251Intel compliance) Pin-Out compatibility with 80C51 standard products 1 Kbyte of internal RAM TSC83251G1: 16 Kbytes of on-chip masked ROM TSC87251G1: 16 Kbytes of internal programmable ROM (OTP or UV erasable in window package) TSC80251G1: ROMless version External memory space (Code/Data) programmable from 64 Kbytes to 256 Kbytes Four 8-bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the standard 80C51) Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the standard 80C51) Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator EWC: Event and Waveform Controller Compatible with PCA: Programmable Counter Array (5 16-bit modules) High-speed output Compare/Capture I/O 8-bit Pulse Width Modulator (PWM) Watchdog Timer capabilities SSLC: Synchronous Serial Link Controller I2C protocol Wire and SPI protocols Hardware Watchdog Timer Power Monitoring and Management Power-Fail reset Power-On reset (integrated on the chip) Power-Off flag (cold and warm resets) Software programmable system clock Idle and Power-Down modes Keyboard interrupt on Port 1 Non Maskable Interrupt input (NMI) Real-time Wait states input (WAIT#) Power Supply: 5 V +/- 10% and 3 V +/- 10% (*) Up to 16 MHz operation and three temperature ranges: Commercial (0 to +70C) Industrial (-40 to +85C) Automotive (-40 to +125C) Packages : PLCC44, CQPJ44 (window), QFP44 and PDIL40 (**)
1
E E E
E E E E E
E
* Please contact your sales office for availability of 3 V option ** Please contact your sales office for QFP and PDIL availability
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Block Diagram
P3(A16) P2(A15-8) P1(A17)
P0(AD7-0)
PSEN# OTPROM EPROM ROM 16 Kbytes RAM 1 Kbyte UART 16-bit Memory Code EA#/VPP Peripheral Interface Unit 16-bit Memory Address Event and Waveform Controller Timers 0, 1 and 2
PORTS 0-3 ALE/PROG#
1
WAIT#
I2C/SPI/mWire Controller
Bus Interface Unit
Watchdog Timer 24-bit Prog. Counter Bus
24-bit Data Address Bus
16-bit Inst. Bus
RST 8-bit Internal Bus Power Monitoring XTAL2 Clock Unit Clock System Prescaler XTAL1
8-bit Data Bus
Keyboard Interface
CPU
Interrupt Handler Unit
NMI
VDD
VSS
VSS1
VSS2
Figure 3.1. TSC80251G1 Block Diagram
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Pin Description
P1.4/CEX1
P1.3/CEX0
P1.1/T2EX
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.3/AD3
P1.2/ECI
P1.0/T2
VSS1
VDD
1
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA#/VPP
P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK A17/P1.7/CEX4/SDA/MOSI RST P3.0/RXD WAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1
TSC80251G1
NMI ALE/PROG# PSEN# P2.7/A15 P2.6/A14 P2.5/A13
P3.6/WR#
VSS
XTAL2
XTAL1
VSS2
P2.2/A10
P2.3/A11
P2.0/A8
P2.1/A9
Figure 4.1. TSC80251G1 Pin Description
Caution: See "Packages" chapter in section III for position of pin #1.
P3.7/RD#/A16
P2.4/A12
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Table 4.1. TSC80251G1 Pin Description
Pin P0.0:7 Type I/O Description Port 0 This is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. It is also Address/Data lines AD0:7, which are multiplexed lower address lines and data lines for external memory. External pull-ups are required during program verification. Port 1 This is an 8-bit bidirectional I/O port. It receives the low-order address byte during EPROM programming and verification. It serves also the functions of various special features: P1.0 T2 : Timer 2 external clock input/output P1.1 T2EX : Timer 2 external input P1.2 ECI : EWC external clock input P1.3 CEX0 : EWC module 0 Capture input/PWM output P1.4 CEX1 : EWC module 1 Capture input/PWM output P1.5 CEX2 : EWC module 2 Capture input/PWM output MISO : Wire/SPI master input slave output P1.6 CEX3 : EWC module 3 Capture input/PWM output SCL : I2C clock SCK : Wire/SPI serial clock P1.7 A17 : Address line for the 256-Kbyte memory space depending on the byte CONFIG0 CEX4 : EWC module 4 Capture input/PWM output SDA : I2C synchronous serial link data MOSI : Wire/SPI master output slave input Port 1 is also used as a keyboard interface. Port 2 This is an 8-bit bidirectional I/O port with internal pull-ups. It receives data during EPROM programming and verification. It is also Address lines A8:15, which are upper address lines for external memory. Port 3 This is an 8-bit bidirectional I/O port with internal pull-ups. It receives the high-order address bits during EPROM programming and verification. It serves also the functions of various special features: P3.0 RXD : Serial Port Receive Data input P3.1 TXD : Serial Port Transmit Data output P3.2 INT0# : External Interrupt 0 P3.3 INT1# : External Interrupt 1 P3.4 T0 : Timer 0 external clock input P3.5 T1 : Timer 1 external clock input P3.6 WR# : Write signal for external access P3.7 A16 : Address line for 128-Kbyte and 256-Kbyte memory space depending on the byte CONFIG0, RD# : Read signal for external access, depending CONFIG0 byte.
P1.0:7
I/O
P2.0:7
I/O
P3.0:7
I/O
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Pin ALE/PROG# Type I/O Description Address Latch Enable/Program Pulse It signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from address/data bus. It is also used as the Program Pulse input PROG#, during EPROM programming. Program Store Enable/Read signal output This output is asserted for a memory address range that depends on bits RD0 and RD1 in CONFIG0 byte. External Access Enable/Programming Supply Voltage This input directs program memory accesses to on-chip or off-chip code memory. For EA# = 0, all program memory accesses are off-chip. For EA# = 1, an access is on-chip OTPROM/EPROM/ROM if the address is within the range of the on-chip OTPROM/EPROM/ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without ROM on-chip, EA# must be strapped to ground. It receives also the Programming Supply Voltage VPP during EPROM programming operation. Real-time Wait States Input When this pin is active (low level), the memory cycle is stretched until it becomes high. Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. Digital Supply Voltage Digital Ground Digital Ground Digital Ground Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.
PSEN#
O
EA#/VPP
I
1
WAIT#
I
NMI VDD VSS VSS1 VSS2 RST
I PWR GND GND GND I
XTAL1
I
XTAL2
O
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Section II
2 Design Information
TSC 80251G1
Configuration and Memory Mapping
1.1. Introduction
The C251 architecture provides generic configuration and memory addressing capabilities. However, the products based on this architecture may provide various derivative features. The configuration and memory mapping features of the TSC80251G1 derivatives are detailed in this chapter.
1.2. Configuration
The TSC80251G1 derivatives provide design flexibility by configuring some operating features during the device reset. These features fall into the following categories: D external/internal memory access operation, D external memory interface, D source/binary mode opcodes, D selection of the bytes pushed on the stack by an interrupt. The choice of internal ROM or external memory access is made through the External Access pin (EA#, see paragraph 1.3.2.). The internal memories of the TSC80251G1 derivatives are detailed in "Memory Mapping" paragraph. The choice of external memory interface is detailed in this chapter. The choice of source or binary mode and the interrupt processing are discussed in the TSC80251 Programmers' Guide. These settings are made based on two configuration bytes (CONFIG0 and CONFIG1, see Figure 1.11. and Figure 1.12. at the end of this chapter).
2
1.2.1. Page Mode and Wait States
This part deals with the choice of external bus cycle speed configuration. All the external bus cycles are based on states which are made of two cycles of the internal oscillator. The external XTAL1 frequency can be internally divided by the prescaler to reduce the power consumption (See "Power Monitoring and Management" chapter) and the speed of the external cycles is then reduced accordingly. TSC80251G1 derivatives use two 8-bit Ports (P0, P2) to multiplex a 16-bit address bus and an 8-bit data bus. The first configuration is multiplexing the lower 8-bit address bus and the 8-bit data bus on Port 0; this is the non-page mode which is compatible with the 80C51 derivatives. The second configuration is multiplexing the upper 8-bit address bus and the 8-bit data bus on Port 2; this is the page mode which improves performance. This bus structure is shown on Figure 1.1 and is configured by the PAGE bit of CONFIG0 byte (See Figure 1.11. ).
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TSC80251G1 P2 A15:8 A15:8 AD7:0 P0 Latch A7:0 D7:0 D7:0 Non-page Mode RAM/ EPROM/ Flash P0 Page Mode A7:0 P2 Latch A15:8/D7:0 A15:8 A7:0 A7:0 RAM/ EPROM/ Flash A15:8 TSC80251G1 D7:0
Figure 1.1. Bus Structure in Non-Page Mode and Page Mode Figure 1.2. highlights the non-page mode configuration with a code fetch cycle. One state is used to latch A7:0 on Port 0, then the data are transferred during the second state.
State 1 OSC*
State 2
ALE RD#/PSEN#
P0 A17/A16/P2
A7:0 A17/A16/A15:8
D7:0
* The OSC signal is the internal clock signal. It has no link with XTAL1/XTAL2 signals.
Figure 1.2. External Bus Cycle: Code Fetch, Non-Page Mode
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State 1 OSC* State 2 State 3
ALE RD#/PSEN#
A17/A16/P0 P2
A17/A16/A7:0 A15:8 D7:0
A17/A16/A7:0 D7:0
* The OSC signal is the internal clock signal. It has no link with XTAL1/XTAL2 signals.
Figure 1.3. External Bus Cycle: Code Fetch, Page Mode Three configuration bits are provided to introduce wait states and modulate the access time depending on the external devices. One wait state can be added to extend the address latch time using the XALE bit in CONFIG0 byte. Another wait state can also be added to extend the data access time once the multiplexed addresses have been latched. Figure 1.4. shows a code fetch in non-page mode with one such wait state. The Wait State A bit (WSA bit in CONFIG0 byte) adds one state for external program/code and data accesses (See segments FF:, FE:, 00: in paragraph 1.2.3.). The Wait State B bit (WSB bit in CONFIG1 byte) adds one state for external data accesses only (See segment 01: in paragraph 1.2.3.).
State 1 OSC* State 2 State 3
2
ALE RD#/PSEN#
P0 A17/A16/P2
A7:0 A17/A16/A15:8
D7:0
* The OSC signal is the internal clock signal. It has no link with XTAL1/XTAL2 signals.
Figure 1.4. External Bus Cycle: Code Fetch with One RD#/PSEN# Wait State in Non-Page Mode
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1.2.2. Real-time Wait States Input
A WAIT# pin is available on TSC80251G1 to extend the width of the RD#,WR# and PSEN# pulses in order to allow access of slow memories/peripherals. If the WAIT# input is low by the specified time after falls, the TSC80251G1 will hold the bus lines to their values. When the WAIT# input rises the bus cycle continues (See "AC/DC Characteristics" chapter in section III, for timings).
1.2.3. External Memory Signals
For easy reference to the C51 architecture, it is convenient to consider the 24-bit linear address space of the C251 architecture as 256 segments of 64 Kbytes (from segment 00: to segment FF:). Some of these segments are reserved to map the internal registers and, in this section, we only consider the segments which allows to access to the external memory. In the TSC80251G1 derivatives only four segments of the 24-bit internal address space (00:, 01:, FE:, FF:) are implemented to address the external memory. This allows a maximum program or data memory space of 256 Kbytes. Various configurations are possible, depending on the Read configuration bits (RD1:0) which are set in CONFIG0 byte (See Figure 1.11. ). 1.2.3.1. How to Address 256 Kbytes The maximum external memory is provided when RD1:0 = 00, as shown on Figure 1.5. PSEN# is used as a read signal and WR# is used as a write signal. Eighteen address bits are provided externally (A17, A16, P2, P0) to control 256 Kbytes in four segments. In this configuration, the program/code and data spaces share the same external memory segments.
Internal Spaces Read/Write Signals Segments A17:A16 11 FF: FE: Program/Code PSEN# 01: 00: FF: Data PSEN#/WR# FE: 01: 00: 10 01 00 11 10 01 00 FF: FE: 01: 00: Addresses A17, A16, P2, P0 External Memory
256 Kbytes
Figure 1.5. Internal/External Memory Segments (RD1:0 = 00)
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1.2.3.2. How to Address 128 Kbytes One I/O pin (P1.7/A17) is saved if 128 Kbytes of external memory are enough, as shown on Figure 1.6. (RD1:0 = 01). PSEN# is used as a read signal and WR# is used as a write signal. Seventeen address bits are provided externally (P0, P2, A16) to control 128 Kbytes in two segments. In this configuration, the program/code and data spaces share the same external memory segments which are replicated twice in each internal space.
Internal Spaces Read/Write Signals Segments A16 FF: Program/Code PSEN# FE: 01: 00: FF: Data PSEN#/WR# FE: 01: 00: 1 0 1 0 1 0 1 0 128 Kbytes 01:, FF: 00:, FE: Addresses A16, P2, P0 External Memory
2
Figure 1.6. Internal/External Memory Segments (RD1:0 = 01) 1.2.3.3. How to Address 64 Kbytes Two I/O pins (P1.7/A17 and P3.7/A16/RD#) are saved if 64 Kbytes of external memory are enough, as shown on Figure 1.7. (RD1:0 = 10). PSEN# is used as a read signal and WR# is used as a write signal. Sixteen address bits are provided externally (P0, P2) to control 64 Kbytes in one segment. In this configuration, the program/code and data share the same external memory segment which is replicated four times in each internal space.
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Internal Spaces Read/Write Signals Segments Addresses P2, P0 FF: Program/Code FE: PSEN# 01: 00: FF: Data PSEN#/WR# FE: 01: 00: 64 Kbytes 00:, 01:, FE:, FF: External Memory
Figure 1.7. Internal/External Memory Segments (RD1:0 = 10) 1.2.3.4. How to Keep C51 Memory Compatibility The last configuration provides a full compatibility with the C51 architecture, as shown on Figure 1.8. (RD1:0 = 11). PSEN# is used as a read signal for program/code memory while RD# is used as a read signal and WR# is used as a write signal for data memory accesses. 16 address bits are provided externally (P0, P2). In this configuration, the program/code fits in one read-only external memory segment and the data fits in another read-write external memory segment. Each segment is replicated four times in each internal space.
Internal Spaces Read/Write Signals Segments FF: FE: Program/Code PSEN# 01: 00: FF: Data RD#/WR# FE: 01: 00: 264 Kbytes 00:, 01:, FE:, FF: 00:, 01:, FE:, FF: Addresses P2, P0 External Memory
Figure 1.8. Internal/External Memory Segments (RD1:0 = 11)
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1.3. Memory Mapping
The specific internal memories of the TSC80251G1 derivatives fall into the following categories: D 2 Configuration bytes D 16 Kbytes on-chip ROM or EPROM/OTP program/code memory D 1 Kbyte on-chip RAM data memory D Special Function Registers (SFRs)
1.3.1. Configuration Bytes
The configuration bytes, CONFIG0 and CONFIG1, are detailed in Figure 1.11. and Figure 1.12. During reset they are read from a specific ROM area. For the TSC87251G1 EPROM and OTPROM versions, these bytes are programmable in an EPROM area (See "EPROM Programming" chapter). For the TSC83251G1 masked ROM versions, these bytes are additional information provided in a masked ROM area. For the TSC80251G1 ROMless versions, these bytes are configured in factory according to the part number (See "Ordering Information"). These bytes are not accessible by the user during operation and they do not appear in the Memory Mapping of the TSC80251G1 derivatives.
2
1.3.2. Program/Code Memory
The split of the internal and external program/code memory space is shown on Figure 1.9. If EA# is tied to a high level, the 16-Kbyte internal program memory are mapped in the lower part of segment FF: where the C251 core jumps after reset. The rest of the program/code memory space is mapped to the external memory (See paragraph 1.2.2. to determine to which external memory location each segment actually maps). If EA# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. For the TSC87251G1 EPROM and OTPROM versions, the internal program/code is programmable in EPROM (See "EPROM programming" chapter). For the TSC83251G1 masked ROM versions, the internal program/code is provided in a masked ROM. For the TSC80251G1 ROMless versions, there is no possible internal program/code and EA# must be tied to a low level.
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Program/code Program/code External Memory Space Segments FF:FFFFh 48 Kbytes 16 Kbytes 64 Kbytes FE:0000h FD:FFFFh Reserved 02:0000h 01:FFFFh 128 Kbytes 01:0000h 00:FFFFh EA#=1 EA#=0 FF:4000h FF:3FFFh FF:0000h FE:FFFFh 8 Kbytes Internal Memory ROM Program
8 Kbytes
00:0000h
Figure 1.9. Programmable Memory Mapping
Note: Special care should be taken when the Program Counter (PC) increments: D If your program executes exclusively from on-chip ROM/OTPROM/EPROM (not from external memory), beware of executing code from the upper eight bytes of the on-chip ROM/OTPROM/EPROM (FF:3FF8h-FF:3FFFF). Because of its pipeline capability, the 80C251G1 may attempt to prefetch code from external memory (at an address above FF:3FF8h/FF:3FFFF) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does not affect Ports 0 and 2. D When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC increments beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents from it going into the reserved area).
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1.3.3. Data Memory
Data External Memory Space 48 Kbytes 16 Kbytes EA#=0 FF:4000h FF:3FFFh FF:0000h FE:FFFFh 64 Kbytes FE:0000h FD:FFFFh Reserved 02:0000h 01:FFFFh 64 Kbytes 01:0000h 8 Kbytes 55 Kbytes EMAP=1 00:FFFFh 00:E000h 00:DFFFh 00:0420h RAM Data EMAP=0 1 Kbyte 32 bytes reg. EA#=1 8 Kbytes Data Segments FF:FFFFh Internal Memory ROM Code
8 Kbytes
2
Figure 1.10. Data Memory Mapping The split of the internal and external data memory space is shown on Figure 1.10. All the TSC80251G1 derivatives feature an internal 1 Kbyte RAM. This memory is mapped in the data space just over the 32 bytes of registers area (See TSC80251 Programmers' Guide). Hence, the lowermost 96 bytes of the internal RAM are bit addressable. This internal RAM is not accessible through the program/code memory space. For computation with the internal ROM code of the TSC83251G1 and TSC87251G1 versions, its upper 8 Kbytes are also mapped in the segment 00: if the EPROM Map configuration bit is cleared (EMAP bit in CONFIG1 byte, see Figure 1.2. ). However, if EA# is tied to a low level, the TSC80251G1 derivative is running as a ROMless and the code is actually fetched in the corresponding external memory (i.e. the upper 8 Kbytes of the lower 16 Kbytes of segment FF:). If EMAP bit is set, the internal ROM is not accessible through the segment 00:. All the accesses to the portion of the data space with no internal memory mapped onto are redirected to the external memory, see paragraph 1.2.3. to determine to which external memory location each segment actually maps.
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1.3.4. Special Function Registers
The Special Function Registers (SFRs) of the TSC80251G1 derivatives fall into the following categories: D C251 core registers (SP, SPH, DPL, DPH, DPXL, PSW, PSW1, ACC, B) D Port registers (P0, P1, P2, P3) D Timer registers (TCON, TMOD, TL0, TL1, TH0, TH1, T2CON, T2MOD, RCAP2L, RCAP2H, T2L, T2H) D Serial Port and Baud Rate Generator registers (SCON, SBUF, SADDR, SADEN, BDRCON, BRL) D Event and Waveform Controller registers: G Counters (CCON, CMOD) G Compare/Capture (CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H, CCAP4H) D Synchronous Serial Link Controller registers (SSBR, SSCON, SSCS, SSDAT) D Power monitoring/management and clock control registers (PCON, PFILT, POWM, CKRL) D Hardware Watchdog Timer register (WDTRST) D Keyboard interrupt registers (P1F, P1E, P1LS) D Interrupt system registers (IE0, IE1, IPL0, IPL1, IPH0, IPH1) SFRs are placed in a reserved internal memory segment S: which is not represented in the internal memory mapping. The relative addresses within S of these SFRs: are provided together with their reset values in Table 1.2. All the SFRs are bit-addressable using the C251 instruction set. The C251 core registers are in italics in this table and they are described in the TSC80251 Programmers' Guide. The other registers are detailed in the following sections which fully describe each peripheral unit.
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TSC 80251G1
Table 1.1. SFR Addresses and Reset Values
0/8 F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h
IPL0 0000 0000 P3 1111 1111 IE0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 TMOD 0000 0000 SP 0000 0111 SBUF XXXX XXXX BRL 0000 0000 SSBR 0000 0000 TL0 0000 0000 DPL 0000 0000 BDRCON XXX0 0000 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 P1LS 0000 0000 SSCS 0XXX XXX0 TH0 0000 0000 DPXL 0000 0001 P1E 0000 0000 SSDAT 0000 0000 TH1 0000 0000 CKRL 0000 0000 PFILT XXXX XXXX POWM 0XXX 0XXX PCON 0000 0000 SADEN 0000 0000 IE1 XX0X XXX0 SADDR 0000 0000 WDTRST 1111 1111 P1F 0000 0000 IPL1 XX0X XXX0 IPH1 XX0X XXX0 SPH 0000 0000 IPH0 X000 0000 ACC 0000 0000 CCON 0010 0000 PSW 0000 0000 T2CON 0000 0000 CMOD 0011 1000 PSW1 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CCAPM0 1000 0000 CCAPM1 1000 0000 CCAPM2 1000 0000 CCAPM3 1000 0000 CCAPM4 1000 0000 B** 0000 0000 CL 0000 0000 CCAP0L 0000 0000 CCAP1L 0000 0000 CCAP2L 0000 0000 CCAP3L 0000 0000 CCAP4L 0000 0000
1/9
CH 0000 0000
2/A
CCAP0H 0000 0000
3/B
CCAP1H 0000 0000
4/C
CCAP2H 0000 0000
5/D
CCAP3H 0000 0000
6/E
CCAP4H 0000 0000
7/F F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h
2
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Italicized registers are described in the TSC80251 Programmer's Guide (C251 core registers). reserved S:00h - S:7Fh unimplemented S:100h - S:1FFh unimplemented
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TSC 80251G1
CONFIG0 Configuration byte 0
- 7 Bit Number 7 6 5 - 6 Bit Mnemonic - - WSA WSA 5 XALE 4 RD1 3 Description Reserved Set this bit when writing to CONFIG0. Reserved Set this bit when writing to CONFIG0. Wait State A bit Clear to generate one external wait state for memory regions 00:, FE:, and FF:. Set for no wait states for these regions. Extend ALE bit Clear to extend the time of the ALE pulse from TOSC to 3.TOSC, which adds one external wait state. Set the time of the ALE pulse to TOSC. RD# and PSEN# Function Select bits RD1 RD0 RD# P1.7 PSEN# Range 0 0 A16 A17 PSEN# is the read signal for both external data and program address space (256 Kbytes). 0 1 A16 I/O pin PSEN# is the read signal for both external data and program address space (128 Kbytes). 1 0 I/O pin I/O pin PSEN# is the read signal for both external data and program address space (64 Kbytes). 1 1 RD# I/O pin 64-Kbyte code memory space 64-Kbyte data memory space Page Mode Select bit Clear for page mode with A15:8/D7:0 on Port 2 and A7:0 on Port0. Set for non-page mode with A15:8 on Port 2 and A7:0/D7:0 on Port 0 (compatible with 80C51 microcontrollers). Source Mode/Binary Mode Select bit Clear for Binary Mode (Binary Code compatible with 80C51 Microcontrollers). Set for Source Mode. RD0 2 PAGE 1 SRC 0
4
XALE
3
RD1
2
RD0
1
PAGE
0
SRC
Figure 1.11. Configuration Byte 0
Notes: D To configure the TSC80251G1 in C51 binary mode, use the following bit values in CONFIG0 byte: 1101 1110b. This configuration is already programmed in -B option microcontroller (See "Ordering Information"). D To configure the TSC80251G1 in C251 default mode, use the following bit values in CONFIG0 byte: 1111 1111b. This configuration is already programmed in -A option microcontroller (See "Ordering Information").
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TSC 80251G1
CONFIG1 Configuration byte 1
- 7 Bit Number 7 6 5 4 - 6 Bit Mnemonic - - - INTR - 5 INTR 4 WSB 3 Description Reserved Set this bit when writing to CONFIG1. Reserved Set this bit when writing to CONFIG1. Reserved Set this bit when writing to CONFIG1. Interrupt Mode bit Clear so that the interrupts push 2 bytes onto the stack (the 2 lower bytes of the PC register). Set so that the interrupts push 4 bytes onto the stack (the 3 bytes of the PC register and the PSW1 register). Wait State B bit Clear to generate one external wait state for memory region 01:. Set for no wait states for region 01:. Reserved Set this bit when writing to CONFIG1. Reserved Set this bit when writing to CONFIG1. EPROM Map bit Clear to map the upper 8 Kbytes of on-chip code memory (FF:2000h-FF:3FFFh) to 00:C000h-00:FFFFh. Set not to map the upper 8 Kbytes of on-chip code memory (FF:2000h-FF:3FFFh). - 2 - 1 EMAP 0
2
3
WSB
2 1 0
- - EMAP
Figure 1.12. Configuration Byte 1
Notes: D To configure the TSC80251G1 in C51 binary mode, use the following bit values in CONFIG1 byte: 1110 0111b. This configuration is already programmed in -B option microcontroller (See "Ordering Information"). D To configure the TSC80251G1 in C251 default mode, use the following bit values in CONFIG1 byte: 1111 1111b. This configuration is already programmed in -A option microcontroller (See "Ordering Information").
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TSC 80251G1
Parallel I/O Ports
2.1. Introduction
The TSC80251G1 uses input/output (I/O) Ports to exchange data with external devices. In addition to performing general-purpose I/O, some Ports are capable of external memory operations; others allow for alternate functions. All four TSC80251G1 I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Port 0 drives the lower address byte onto the parallel address bus and Port 2 drives the upper address byte onto the bus. In non-page mode, the data is multiplexed with the lower address byte on Port 0. In page mode, the data is multiplexed with the upper address byte on Port 2. All Port 1 and Port 3 pins serve for both general-purpose I/O and alternate functions (See Table 2.1. , Table 2.2. , Table 2.3. and Table 2.4. ). Table 2.1. Port 0 Pin Descriptions
Pin Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Type I/O I/O I/O I/O I/O I/O I/O I/O Alternate Pin Name AD0 A0 AD1 A1 AD2 A2 AD3 A3 AD4 A4 AD5 A5 AD6 A6 AD7 A7 Alternate Description Address/Data line 0 (Non-page mode) Address line 0 (Page mode) Address/Data line 1 (Non-page mode) Address line 1 (Page mode) Address/Data line 2 (Non-page mode) Address line 2 (Page mode) Address/Data line 3 (Non-page mode) Address line 3 (Page mode) Address/Data line 4 (Non-page mode) Address line 4 (Page mode) Address/Data line 5 (Non-page mode) Address line 5 (Page mode) Address/Data line 6 (Non-page mode) Address line 6 (Page mode) Address/Data line 7 (Non-page mode) Address line 7 (Page mode) Alternate Type I/O I/O I/O I/O I/O I/O I/O I/O
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Table 2.2. Port 1 Pin Descriptions
Pin Name P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 Type I/O I/O I/O I/O I/O I/O Alternate Pin Name T2 P1.0 Alternate Description Timer 2 external clock input/output Keyboard input 0 Timer 2 external input Keyboard input 1 Alternate Type I/O I I I I I
A A A A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAAAAAA A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
T2EX P1.1 ECI P1.2 EWC external clock input Keyboard input 2 CEX0 P1.3 CEX1 P1.4 EWC module 0 Capture input/PWM output Keyboard input 3 EWC module 1 Capture input/PWM output Keyboard input 4 EWC module 2 Capture input/PWM output Wire/SPI master input slave output Keyboard input 5 EWC module 3 Capture input/PWM output I2C serial clock Wire/SPI serial clock Keyboard input 6 Address line 17 EWC module 4 Capture input/PWM output I2C serial data Wire/SPI master output slave input Keyboard input 7 I/O I I/O I I/O I/O I I/O O O I I/O I/O I/O I/O I CEX2 MISO P1.5 CEX3 SCL SCK P1.6 P1.6 I/O P1.7 I/O A17 CEX4 SDA MOSI P1.7
Table 2.3. Port 2 Pin Descriptions
Pin Name P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
Type I/O I/O I/O I/O I/O I/O I/O I/O
Alternate Pin Name A8 A8/D0 A9 A9/D1 A10 A10/D2 A11 A11/D3 A12 A12/D4 A13 A13/D5 A14 A14/D6 A15 A15/D7
Alternate Description Address line 8 (Non-page mode) Address line 8/Data line 0 (Page mode) Address line 9 (Non-page mode) Address line 9/Data line 1 (Page mode) Address line 10 (Non-page mode) Address line 10/Data line 2 (Page mode) Address line 11 (Non-page mode) Address line 11/Data line 3 (Page mode) Address line 12 (Non-page mode) Address line 12/Data line 4 (Page mode) Address line 13 (Non-page mode) Address line 13/Data line 5 (Page mode) Address line 14 (Non-page mode) Address line 14/Data line 6 (Page mode) Address line 15 (Non-page mode) Address line 15/Data line 7 (Page mode)
Alternate Type O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O
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TSC 80251G1
Table 2.4. Port 3 Pin Descriptions
Pin Name P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Type I/O I/O I/O I/O I/O I/O I/O I/O Alternate Pin Name RXD TXD INT0# INT1# T0 T1 WR# RD# A16 Alternate Description Serial Port Receive Data input Serial Port Transmit Data output External Interrupt 0 External Interrupt 1 Timer 0 input Timer 1 input Write signal to external memory Read signal to external memory Address line 16 Alternate Type I O I I I I O O O
Notes: D EWC = Event Waveform Controller D I2C = Inter-Integrated Circuit D PWM = Pulse Width Modulation D SPI = Serial Peripheral Interface D Refer to Table 9.1. for Pin conditions in Special Operating Modes.
2
2.2. I/O Configurations
Each Port SFR operates via type-D latches, as illustrated in Figure 2.1. for Ports 1 and 3. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions (See "Read-Modify-Write Instructions" paragraph). Each I/O line may be independently programmed as input or output.
2.3. Port 1 and Port 3
Figure 2.1. shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input or output function (See Table 2.2. and Table 2.4. ). To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1 or 3). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive. To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (See Figure 2.1. ). The operation of Ports 1 and 3 is discussed further in "Quasi-Bidirectional Port Operation" paragraph.
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TSC 80251G1
Note: To allow proper operation of alternate functions on one pin, the corresponding latch must be set to logical one. Otherwise a logical zero is forced on the pin. VDD Read Latch Internal Bus Write to Latch Alternate Output Function Internal pull-up P3.x P1.x
D P1.x Q P3.x Latch CL Q#
Read Pin
Alternate Input Function
Figure 2.1. Port 1 and Port 3 Structure
2.4. Port 0 and Port 2
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 2.2. , differs from the other Ports in not having internal pull-ups. Figure 2.3. shows the structure of Port 2. An external source can pull a Port 2 pin low. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 0 or 2). To use a pin for general-purpose input set the bit in the Px register to turn off the output driver FET.
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TSC 80251G1
Read Latch Internal Bus Write to Latch Address/ Data Control VDD
D CL
P0.x Latch
Q P0.x Q# 1 0
Read Pin
Figure 2.2. Port 0 Structure
Address Read Latch Internal Bus Write to Latch 1 0 P2.x Control VDD
2
D CL
P2.x Latch
Q Q#
Read Pin
Figure 2.3. Port 2 Structure When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line. "External Memory Access" paragraph discusses the operation of Port 0 and Port 2 as the external address/data bus.
Notes: D Port 0 and Port 2 are precluded from use as general purpose I/O Ports when used as address/data bus drivers. D Port 0 internal pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off. All other Port 0 outputs are open-drain.
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TSC 80251G1
2.5. Read-Modify-Write Instructions
Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "Read-Modify-Write" instructions. Below is a complete list of these special instructions (See Table 2.5. ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: Table 2.5. Read-Modify-Write Instructions
Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y, C CLR Px.y SET Px.y logical AND logical OR logical EX-OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit y of Port x clear bit y of Port x set bit y of Port x Description ANL P1,A ORL P2,A XRL P3,A JBC P1.1, LABEL CPL P3.0 INC P2 DEC P2 DJNZ P3, LABEL MOV P1.5, C CLR P2.4 SET P3.3 Example
It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the Port (all 8 bits), modify the specifical addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor's base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pin returns the correct logic-one value.
2.6. Quasi-Bidirectional Port Operation
Port 1, Port 2 and Port 3 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pin floats when configured as input. Resets write logical one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch.
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TSC 80251G1
VDD 2 Osc. Periods p1 p2 p3 VDD VDD
Q# from Port Latch
n
Input data Read Port Pin
2
Figure 2.4. Internal Pull-Up Configurations
Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output buffers (and therefore the pin state) update early in the instruction after the Read-Modify-Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 2 and Port 3 use an additional pull-up to aid this logic transition (See Figure 2.4. ). This increases switch speed. The extra pull-up briefly sources 100 times normal internal circuit current. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3.
2.7. Port Loading
Output buffers of Port 1, Port 2 and Port 3 can each sink 1.6 mA at logic zero (See VOL specification in "Electrical and Mechanical Information" section). These Port pins can be driven by open-collector and open-drain devices. Logic zero-to-one transitions occur slowly as limited current pulls the pin to a logic-one condition (See Figure 2.4. ). A logic zero input turns off pFET #3. This leaves only pFET #2 weakly in support of the transition. In external bus mode, Port 0 output buffers each sink 3.2 mA at logic zero (See VOL1 specification in "Electrical and Mechanical Information" section). However, the Port 0 pins require external pull-ups to drive external gate inputs. External circuits must be designed to limit current requirements to these conditions.
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TSC 80251G1
2.8. External Memory Access
The external bus structure is different for page mode and non-page mode. In non-page mode (used by 80C51 microcontrollers), Port 2 outputs the upper address byte; the lower address byte and the data are multiplexed on Port 0. In page mode, the upper address byte and the data are multiplexed on Port 2, while Port 0 outputs the lower address byte. The TSC80251G1 CPU writes FFh to the P0 register for all external memory bus cycles. This overwrites previous information in Port 0. In contrast, the P2 register is unmodified for external bus cycles. When address bits or data bits are not on the P2 pins, the bit values in Port 2 appear on the Port 2 pins. In non-page mode, Port 0 uses a strong internal pull-up FET to output ones or a strong internal pull-down FET to output zeros for the lower address byte and the data. Port 0 is in a high-impedance state for data input. In page mode, Port 0 uses a strong internal pull-up FET to output ones or a strong internal pull-down FET to output zeros for the lower address byte or a strong internal pull-down FET to output zeros for the upper address byte. In non-page mode, Port 2 uses a strong internal pull-up FET to output ones or a strong internal pull-down FET to output zeros for the upper address byte. In page mode, Port 2 uses a strong internal pull-up FET to output ones or a strong internal pull-down FET to output zeros for the upper address byte and data. Port 2 is in a high-impedance state for data input.
Note: In external bus mode, Port 0 outputs do not require external pull-ups.
There are two types of external memory accesses: external program memory and external data memory. External program memories use signal PSEN# as a read strobe. 80C51 microcontrollers use RD# (read) or WR# (write) to strobe memory for data accesses. Depending on its RD0 and RD1 configuration bits, the TSC80251G1 uses PSEN# or RD# for data reads (See "Configuration and Memory Mapping" chapter). During instruction fetches, external program memory can transfer instructions with 16-bit addresses for binary compatible code or with the external bus configured for extended memory addressing (17-bit or 18-bit). External data memory transfers use an 8-bit, 16-bit, 17-bit or 18-bit address bus, depending on the instruction and the configuration of the external bus. Table 2.6. lists the instructions that can be used for the these bus widths. Table 2.6. Instructions for External Data Moves
Bus Width 8 MOVX @Ri MOV @Rm MOV dir8 MOVX @DPTR MOV @WRj MOV @WRj+dis MOV dir16 Instructions
16
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TSC 80251G1
Table 2.6. Instructions for External Data Moves
Bus Width 17 18 MOV @DRk MOV @DRk+dis MOV @DRk MOV @DRk+dis Instructions
Note: Avoid MOV P0 instructions for external memory accesses. These instructions can corrupt input code bytes at Port 0.
External signal ALE (address latch enable) facilitates external address latch capture. The address byte is valid after the ALE pin drives VOL . For write cycles, valid data is written to Port 0 just prior to the write pin (WR#) asserting VOL . Data remains valid until WR# is undriven. For read cycles, data returned from external memory must appear at Port 0 before the read pin (RD#) is undriven. Waits states, by definition, affect bus-timing.
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TSC 80251G1
Timers/Counters
3.1. Introduction
The TSC80251G1 contains three general-purpose, 16-bit Timers/Counters. Although they are identified as Timer 0, Timer 1, and Timer 2, you can independently configure each to operate in a variety of modes as a Timer or as an Event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. Each Timer/Counter employs two 8-bit Timer registers, used separately or in cascade, to maintain the count. The Timer registers and associated control and capture registers are implemented as addressable Special Function Registers (SFRs). Table 3.1. briefly describes the SFRs referred to in this chapter. Four of the SFRs provide programmable control of the Timers as follows: D Timer/Counter mode control register (TMOD) and Timer/Counter control register (TCON) control Timer 0 and Timer 1. D Timer/Counter 2 mode control register (T2MOD) and Timer/Counter 2 control register (T2CON) control Timer 2. These registers are described in Table 3.1. and at the end of this chapter. Table 3.1. Timer/Counter SFRs
Mnemonic TL0 TH0 Description Timer 0 registers Used separately as two 8-bit Counters or in cascade as one 16-bit Counter. Counts an internal clock signal with frequency FOSC /12 (Timer operation) or an external input (event Counter operation). Timer 1 registers Used separately as two 8-bit Counters or in cascade as one 16-bit Counter. Counts an internal clock signal with frequency FOSC /12 (Timer operation) or an external input (event Counter operation). Timer 2 registers. Used in cascade as one 16-bit Counter. Counts an internal clock signal with frequency FOSC /12 (Timer operation) or an external input (event Counter operation) Timer 0/1 Control register Contains the run control bits, overflow flags, interrupt flags and interrupt type control bits for Timer 0 and Timer 1. Timer 2 Control register Contains the receive clock, transmit clock and capture/reload bits used to configure Timer 2. Also contains the run control bit, Counter/Timer select bit, overflow flag, external flag and external enable for Timer 2. Address S:8Ah S:8Ch
2
TL1 TH1
S:8Bh S:8Dh
TL2 TH2
S:CCh S:CDh
TCON
S:88h
T2CON
S:C8h
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TSC 80251G1
Table 3.1. Timer/Counter SFRs
Mnemonic TMOD Description Timer 0/1 Mode Control register Contains the mode select bits, Counter/Timer select bits and external control gate bits for Timer 0 and Timer 1. Timer 2 Mode Control Register. Contains the Timer 2 output enable and down count enable bits. Timer 2 Reload/Capture registers Provide values to and receive values from the Timer registers (TL2,TH2). Address S:89h
T2MOD RCAP2L RCAP2H
S:C9h S:CAh S:CBh
Table 3.2. describes the external signals referred to in this chapter. Table 3.2. External Signals
Mnemonic INT0# Type I Description External Interrupt 0 This input sets the IE0 interrupt flag in TCON register. IT0 selects the triggering method: IT0 = 1 selects edge-triggered (high-to-low); IT0 = 0 selects level-triggered (active low). INT0# also serves as external run control for Timer 0, when selected by GATE0 bit in TCON register. External Interrupt 1 This input sets the IE1 interrupt flag in TCON register. IT1 selects the triggering method: IT1 = 1 selects edge-triggered (high-to-low); IT1 =0 selects level-triggered (active low). INT1# also serves as external run control for Timer 1, when selected by GATE1 bit in TCON register. Timer 0 External Clock Input When Timer 0 operates as a Counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When Timer 1 operates as a Counter, a falling edge on the T1 pin increments the count. Timer 2 Clock Input/Output This signal is the external clock input for the Timer 2 capture mode and it is the Timer 2 clock output for the clock-out mode. Timer 2 External Input In Timer 2 capture mode, a falling edge initiates a capture of the Timer 2 registers. In auto-reload mode, a falling edge causes the Timer 2 registers to be reloaded. In the up-down Counter mode, this signal determines the count direction: high = up, low = down. Multiplexed With P3.2
INT1#
I
P3.3
T0
I
P3.4
T1
I
P3.5
T2
I/O
P1.0
T2EX
I
P1.1
The various operating modes of each Timer/Counter are described below
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TSC 80251G1
3.2. Timer/Counter Operations
For instance, a basic operation is Timer registers THx and TLx (x = 0, 1 or 2) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON or T2CON register (See Figure 3.10. or Figure 3.11. ) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON or T2CON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C\Tx# control bit selects Timer operation or Counter operation by selecting the divided-down system clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down system clock. The Timer register is incremented once every peripheral cycle, i.e. once every six states. Since six states equals 12 oscillator periods (clock cycles), the Timer clock rate is FOSC /12. Exceptions are the Timer 2 Baud Rate and Clock-out modes, where the Timer register is incremented by the system clock divided by two. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled during every S5P2 state. Programmer's Guide describes the notation for the states in a peripheral cycle. When the sample is high in one cycle and low in the next one, the Counter is incremented. The new count value appears in the register during the next S3P1 state after the transition was detected. Since it takes 12 states (24 oscillator periods) to recognize a negative transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
2
3.3. Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 3.1. , Figure 3.3. ,Figure 3.3. and Figure 3.4. show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (See Figure 3.5. ) and bits 0, 1, 4 and 5 of TCON register (See Figure 3.4. ). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request.
3.3.1. Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (See Figure 3.1. ). The
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upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register.
OSC
B12
C/Tx = 0 Tx C/Tx = 1
TLx THx (5 bits) (8 bits)
TFx
Timer x Interrupt Request
OVERFLOW
TRx GATEx INTx#
Figure 3.1. Timer/Counter x (x = 0 or 1) in Mode 0
3.3.2. Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (See Figure 3.3. ). The selected input increments TL0 register.
OSC
B12
C/Tx = 0 Tx C/Tx = 1
THx TLx (8 bits) (8 bits)
TFx
Timer x Interrupt Request
OVERFLOW
TRx GATEx INTx#
Figure 3.2. Timer/Counter x (x = 0 or 1) in Mode 1
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3.3.3. Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (See Figure 3.3. ). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. the next reload value may be changed at any time by writing it to TH0 register.
OSC
B12
C/Tx = 0 Tx C/Tx = 1
TLx (8 bits) CONTROL RELOAD
TFx
Timer x Interrupt Request
TRx GATEx INTx# THx (8 bits)
2
Figure 3.3. Timer/Counter x (x = 0 or 1) in Mode 2
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3.3.4. Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (See Figure 3.3. ). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FOSC /12) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
OSC
B12 C/T0 = 0 C/T0 = 1 TL0 (8 bits) CONTROL TF0 Timer 0 Interrupt Request
T0
TR0 GATE0 INT0# B12 TH0 (8 bits) CONTROL TR1 Timer 1 Interrupt Request
OSC
TF1
Figure 3.4. Timer/Counter 0 in Mode 3 : Two 8-bit Counters
3.4. Timer 1
Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 3.1. and Figure 3.3. show the logical configuration for modes 0, 1, and 2. Timer 1's mode 3 is a hold-count mode. Timer 1 is controlled by the four high-order bits of TMOD register (See Figure 3.5. ) and bits 2, 3, 6 and 7 of TCON register (See Figure 3.4. ). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). Timer 1 operation in modes 0, 1 and 2 is identical to Timer 0. Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.
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When Timer 0 is in mode 3, it uses Timer 1's overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
3.4.1. Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (See Figure 3.1. ). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register.
3.4.2. Mode 1 (16-bit Timer)
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (See Figure 3.2. ). The selected input increments TL1 register.
3.4.3. Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (See Figure 3.3. ). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
2
3.4.4. Mode 3 (Halt)
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available, i.e. when Timer 0 is in mode 3.
3.5. Timer 2
Timer 2 is a 16-bit Timer/Counter. The count is maintained by two eight-bit Timer registers, TH2 and TL2, connected in cascade. Timer 2 is controlled by T2MOD register (See Figure 3.10. ) and T2CON register (See Figure 3.12. ). Timer 2 provides the following operating modes: capture mode, auto-reload mode, Baud Rate Generator mode, and programmable clock-out mode. Select the operating mode with T2MOD and T2CON register bits as shown in Table 3.3. Auto-reload is the default mode. Setting RCLK and/or TCLK selects the Baud Rate Generator mode. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2# selects FOSC /12 (Timer operation) or external pin T2 (Counter operation) as the Timer register input. Setting TF2 allows TL2 to be incremented by the selected input. The operating modes are described in the following paragraphs. Block diagrams in Figure 3.7. through Figure 3.8. show the Timer 2 configuration for each mode.
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Table 3.3. Timer 2 Modes of Operation
Mode Auto-reload Capture Baud Rate Generator Programmable Clock-Out RCLK or TCLK (in T2CON) 0 0 1 X CP/RL2# (in T2CON) 0 1 X 0 T2OE (in T2MOD) 0 0 X 1
3.5.1. Auto-Reload Mode
The auto-reload mode configures Timer 2 as a 16-bit Timer or event Counter with automatic reload. The Timer operates an as an up Counter or as an up/down Counter, as determined by the down Counter enable bit DCEN in T2MOD register (See Figure 3.12. ). At device reset, DCEN is cleared, so in the auto-reload mode, Timer 2 defaults to operation as an up Counter. 3.5.1.1. Up Counter Operation When DCEN = 0, Timer 2 operates as an up Counter (Figure 3.6. ). The external enable bit EXEN2 in T2CON register provides two options. If EXEN2 = 0, Timer 2 counts up to FFFFh and sets TF2 overflow flag. The overflow condition loads the 16-bit value of the reload/capture registers (RCAP2H, RCAP2L) into the Timer registers (TH2, TL2). The values in RCAP2H and RCAP2L are preset by software. In this case, T2EX is not used. If EXEN2 = 1, the Timer registers are reloaded by either a Timer overflow or a high-to- low transition at external input T2EX. This transition also sets EXF2 bit in T2CON register. Either TF2 or EXF2 bit can generate an interrupt request.
OSC B12 0 1 TL2 Overflow TH2 (8 Bits) (8 Bits)
T2 C/T2# TR2 RCAP2HRCAP2L
TF2 Timer 2 Interrupt Request
T2EX
EXF2
EXEN2
Figure 3.5. Timer 2: Auto Reload Mode Up Counter (DCEN = 0)
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3.5.1.2. Up/Down Counter Operation When DCEN = 1, Timer 2 operates as an up/down Counter (See Figure 3.8. ). External pin T2EX controls the direction of the count. When T2EX is high, Timer 2 counts up. The Timer overflow occurs at FFFFh which sets the TF2 overflow flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L to be loaded into the Timer registers (TH2, TL2). When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the Timer registers (TH2, TL2) equals the value stored in RCAP2H and RCAP2L. The underflow sets TF2 bit and reloads FFFFh into the Timer registers. The EXF2 bit toggles when Timer 2 overflows or underflows changing the direction of the count. When Timer 2 operates as an up/down Counter, EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.
(Down Counting Reload Value) FFh FFh Toggle EXF2
2
OSC
B12 0 1 TL2 Overflow TH2 (8 Bits) (8 Bits) TF2 Timer 2 Interrupt Request
T2 C/T2# TR2 RCAP2H RCAP2L T2EX Count Direction 1 = Up 0 = Down
Figure 3.6. Timer 2: Auto Reload Mode Up/Down Counter (DCEN = 1)
3.5.2. Capture Mode
In the capture mode, Timer 2 functions as a 16-bit Timer or Counter (See Figure 3.5. ). An overflow condition sets TF2 bit, which you can use to request an interrupt. Setting the external enable bit EXEN2 allows RCAP2H and RCAP2L registers to capture the current value in Timer registers TH2
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and TL2 in response to a 1-to-0 transition at external input T2EX. The transition at T2EX also sets bit EXF2 in T2CON register. EXF2 bit, like TF2, can generate an interrupt.
OSC B12 0 1 T2 C/T2# TR2 RCAP2H RCAP2L Timer 2 Interrupt Request TH2 TL2 (8 bits) (8 bits) Overflow TF2
T2EX
EXF2
EXEN2
Figure 3.7. Timer 2: Capture Mode
3.5.3. Baud Rate Generator Mode
This mode configures Timer 2 as a Baud Rate Generator for use with the Serial Port. Select this mode by setting the RCLK and/or TCLK bits in T2CON register. See paragraph 4.7.3.3. for more information on this mode.
3.5.4. Clock-Out Mode
In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 3.9. ). The input clock increments TL0 at frequency FOSC/2. The Timer repeatedly counts to overflow from a preloaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers:
Clock-Out Frequency + F OSC 65535 * RCAP2H RCAP2L
4
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz to 4 MHz. The generated clock signal is brought out to T2 pin. Timer 2 is programmed for the clock-out mode as follows: D Set T2OE bit in T2MOD. This gates the Timer register overflow to the 2 Counter. D Clear C/T2# bit in T2CON register to select FOSC /2 as the Timer input signal. This also enables the clock output (T2 pin).
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D Determine the 16-bit reload value from the formula and enter it in the RCAP2H/RCAP2L registers. D Enter a 16-bit initial value in Timer register TH2/TL2. It can be the same as the reload value or a different one depending on the application. D To start the Timer, set TR2 run control bit in T2CON register. Operation is similar to Timer 2 operation as a Baud Rate Generator. It is possible to use Timer 2 as a Baud Rate Generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
OSC B12 0 1 TH2 TL2 (8 Bits) (8 Bits)
T2 TR2 C/T2# RCAP2H RCAP2L
2
2
T2OE T2EX EXF2 Timer 2 Interrupt Request
EXEN2
Figure 3.8. Timer 2: Clock Out Mode
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3.6. Registers
TCON (S:88h) Timer/Counter Control register
TF1 7 Bit Number 7 TR1 6 Bit Mnemonic TF1 TF0 5 TR0 4 IE1 3 Description Timer 1 Overflow flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. Timer 1 Run Control bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Timer 0 Overflow flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. Timer 0 Run Control bit Clear to turn off Timer 0. Set to turn on Timer 0. Interrupt 1 Edge flag Cleared by hardware when interrupt is processed if edge-triggered (See IT1). Set by hardware when external interrupt is detected out INT1# pin. Interrupt 1 Type Control bit Clear to select low level active (level triggered) for external interrupt 1. Set to select falling edge active (edge triggered) for external interrupt 1. Interrupt 0 Edge flag Cleared by hardware when interrupt is processed if edge-triggered (See IT0). Set by hardware when external interrupt is detected out INT0# pin. Interrupt 0 Type Control bit Clear to select low level active (level triggered) for external interrupt 0. Set to select falling edge active (edge triggered) for external interrupt 0. IT1 2 IE0 1 IT0 0
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Reset value = 0000 0000b
Figure 3.9. TCON Register
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TMOD (S:89h) Timer/Counter Mode register
GATE1 7 Bit Number 7 C/T1# 6 Bit Mnemonic GATE1 M11 5 M01 4 GATE0 3 Description Timer 1 Gating Control bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Timer 1 Counter/Timer Select bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. Timer 1 Mode Select bits M11 M01 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescalar (TL1) 0 1 Mode 1: 16-bit Timer/Counter 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1). Reloaded from TH1 at overflow 1 1 Mode 3: Timer 1 halted. Retains count. Timer 0 Gating Control bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Timer 0 Counter/Timer Select bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. Timer 0 Mode Select bit M10 M00 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescalar (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0). Reloaded from TH0 at overflow. 1 1 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1's TR0 and TF0 bits. C/T0# 2 M10 1 M00 0
6
C/T1#
5
M11
4
M01
2
3
GATE0
2
C/T0#
1
M10
0
M00
Reset value = 0000 0000b
Figure 3.10. TMOD Register
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T2CON (S:C8h) Timer/Counter 2 Control register
TF2 7 Bit Number 7 EXF2 6 Bit Mnemonic TF2 RCLK 5 TCLK 4 EXEN2 3 Description Timer 2 Overflow flag TF2 is not set if RCLK=1 or TCLK=1. Set by hardware when Timer 2 overflows. Must be cleared by software. Timer 2 External flag EXF2 does not cause an interrupt in up/down counter mode (DCEN=1). Set by hardware if EXEN2=1 when a negative transition on T2EX pin is detected. Receive Clock bit Clear to select Timer 1 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3. Set to select Timer 2 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3. Transmit Clock bit Clear to select Timer 1 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3. Set to select Timer 2 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for Timer 2. Set to cause a capture or reload when a negative transition on T2EX pin is detected unless Timer 2 is being used as the Baud Rate Generator for the Serial Port. Timer 2 Run Control bit Clear to turn off Timer 2. Set to to turn on Timer 2. Timer 2 Counter/Timer Select bit Clear for Timer operation: Timer 2 counts the divided-down system clock. Set for Counter operation: Timer 2 counts negative transitions on external pin T2. Capture/Reload bit CP/RL2# is ignored and Timer 2 is forced to auto-reload on Timer 2 overflow if RCLK=1 or TCLK=1. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. TR2 2 C/T2# 1 CP/RL2# 0
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset value = 0000 0000b
Figure 3.11. T2CON Register
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T2MOD (S:C9h) Timer/Counter 2 Control register
- 7 Bit Number 7 - 6 Bit Mnemonic - - 5 - 4 - 3 Description Reserved Must be set by software. Do not clear this bit. The value read from this bit is indeterminate. Reserved Must be set by software. Do not clear this bit. The value read from this bit is indeterminate. Reserved Must be set by software. Do not clear this bit. The value read from this bit is indeterminate. Reserved Must be set by software. Do not clear this bit. The value read from this bit is indeterminate. Reserved Must be set by software. Do not clear this bit. The value read from this bit is indeterminate. Reserved Must be set by software. Do not clear this bit. The value read from this bit is indeterminate. Timer 2 Output Enable bit Clear to disable the programmable clock output to external pin T2 in the Timer 2 clock-out mode . Set to enable the programmable clock output to external pin T2 in the Timer 2 clock-out mode. Down Count Enable bit Clear to configure Timer 2 as an up Counter. Set to configure Timer 2 as an up/down Counter. - 2 T2OE 1 DCEN 0
6
-
5
-
4
-
2
3
-
2
-
1
T2OE
0
DCEN
Reset value = XXXX XX00b
Figure 3.12. T2MOD Register
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Serial I/O Port
4.1. Introduction
This chapter provides instructions on programming the Serial Port and generating the Serial I/0 Baud Rates with Timer 1, Timer 2 and the internal Baud Rate Generator. The Serial Input/Output Port supports communication with modems and other external peripheral devices. The Serial Port provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different Baud Rates. The UART supports framing-bit error detection, overrun error detection, multiprocessor communication, and automatic address recognition. The Serial Port also operates in a single synchronous mode (Mode 0). The synchronous mode (Mode 0) operates either at a single Baud Rate (80C51 compatibility) or at a variable Baud Rate with an independent and internal Baud Rate Generator. Mode 2 can operate at two Baud Rates. Modes 1 and 3 operate over a wide range of Baud Rates, which are generated by Timer 1, Timer 2 and internal Baud Rate Generator. The Serial Port signals are defined in Table 4.1. and the Serial Port special function registers are described in Table 4.2. and detailed at the end of this chapter. Figure 4.1. is the Serial Port block diagram.
2
IB Bus Write SBUF TXD SBUF Transmitter Mode 0 Transmit Receive Shift register Serial Port Interrupt Request RI TI SBUF Receiver Load SBUF Read SBUF
RXD
SCON reg
Figure 4.1. Serial Port Block Diagram
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Table 4.1. Serial Port Signals
Name TXD Type O Description Transmit Data In mode 0, TXD transmits the clock signal. In modes 1, 2 and 3, TXD transmits serial data. Receive Data In mode 0, RXD transmits and receives serial data. In mode 1,2 and 3, RXD receives serial data. Multiplexed with P3.1
RXD
I/O
P3.0
For the three asynchronous modes, the UART transmits on the TXD pin and receives on the RXD pin. For the synchronous mode (Mode 0), the UART outputs a clock signal on the TXD pin and sends and receives messages on the RXD pin (See Figure 4.1. ). SBUF register, which holds received bytes and bytes to be transmitted, actually consists of two physically different registers. To send, software writes a byte to SBUF; to receive, software reads SBUF. The receive shift register allows reception of a second byte before the first byte has been read from SBUF. However, if software has not read the first byte by the time the second byte is received, the second byte will overwrite the first. The UART sets interrupt bits TI and RI on transmission and reception, respectively. These two bits share a single interrupt request and interrupt vector. Table 4.2. Serial Port SFRs
Mnemonic BDRCON BRL SADDR SADEN Description Baud Rate Control register Enables and configures the internal Baud Rate register. Baud Rate Reload register Contains the auto-reload value of the Baud Rate Generator. Serial Address register Defines the individual address for a slave device connected on the serial lines. Serial Address Enable register Specifies the mask byte that is used to define the given address for a slave device. Serial Buffer Two separate registers comprise the SBUF register. Writing to SBUF loads the transmit buffer and reading SBUF accesses the receive buffer. Serial Port Control register Selects the Serial Port operating mode. SCON enables and disables the receiver, framing bit error detection, overrun error detection, multiprocessor communication, automatic address recognition and the Serial Port interrupt bits. Address S:9Bh S:9Ah S:A9h S:B9h
SBUF
S:99h
SCON
S:98h
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4.2. Modes of Operation
The Serial Port can operate in one synchronous and three asynchronous modes.
4.2.1. Synchronous Mode (Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data. The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur in the last phase (S6P2) of every peripheral cycle, which corresponds to a Baud Rate of FOSC/12. Figure 4.2. shows the timing for transmission and reception in mode 0.
Transmit TXD Write to SBUF S6P2 Shift S6P2 RXD S6P2 TI S1P1 D0 D1 S6P2 D2 S6P2 D6 D7 S6P2 S3P1 S6P1
2
Receive TXD S3P1 S6P1 Write to SCON Shift S6P2 D0 S6P2 D1 S6P2 D6 S6P2 D7 Set REN, Clear RI
RXD
RI
S5P2 S1P1
Figure 4.2. Mode 0 Timings
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4.2.1.1. Transmission (Mode 0) Follow these steps to begin a transmission: E Write to SCON register clearing bits SM0, SM1 and REN. E Write the byte to be transmitted to the SBUF register. This write starts the transmission. Hardware executes the write to SBUF in the last phase (S6P2) of a peripheral cycle. At S6P2 of the following cycle, hardware shifts the LSB (D0) onto the RXD pin. At S3P1 of the next cycle, the TXD pin goes low for the first clock-signal pulse. Shifts continue every peripheral cycle. In the ninth cycle after the write to SBUF, the MSB (D7) is on the RXD pin. At the beginning of the 10th cycle, hardware drives the RXD pin high and asserts TI to indicate the end of the transmission. 4.2.1.2. Reception (Mode 0) To start a reception in mode 0, write to the SCON register. Clear SM0, SM1 and RI bits and set the REN bit. Hardware executes the write to SCON in the last phase (S6P2) of a peripheral cycle (See Figure 4.2. ). In the second peripheral cycle clock-signal pulse, and the LSB (D0) is sampled on the RXD pin at S5P2. The D0 bit is then shifted into the shift register. After eight shifts at S6P2 of every peripheral cycle, the LSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate acompleted reception. Software can then read the received byte from SBUF register.
4.2.2. Asynchronous Modes (Modes 1, 2 and 3)
The Serial Port has three asynchronous modes of operation: E Mode 1 Mode 1 is a full-duplex, asynchronous mode. The data frame (See Figure 4.3. ) consists of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. When a message is received, the stop bit is read in the RB8 bit in SCON register. The Baud Rate is generated either by overflow of Timer 1 or by overflow of Timer 2, or by overflow of the internal Baud Rate Generator (see "Baud Rate Generator" paragraph). E Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (See Figure 4.3. ) consists of 11-bit: one start bit, 8-bit data (transmitted and received LSB first), one programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On transmit, the ninth data bit is written to TB8 bit in SCON register. (Alternatively, you can use the ninth bit as a command/data flag.) In mode 2, the Baud Rate is programmable to 1/32 or 1/64 of the oscillator frequency. In mode 3, the Baud Rate is generated either by overflow of Timer 1 or by overflow of Timer 2, or by overflow of internal Baud Rate Generator.
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Mode 1 D0 D1 D2 D3 D4 D5 D5 D6 D7 Start 8-bit data Stop
Modes 2 and 3 D0 D1 D2 D3 D4 D5 D5 D6 D7 D8 Start 9-bit data Stop
Figure 4.3. Data Frames (Modes 1, 2 and 3) 4.2.2.1. Transmission (Modes 1, 2 and 3) Follow these steps to initiate a transmission: E Write to SCON register. Select the mode with SM0 and SM1 bits and clear REN bit. For modes 2 and 3, also write the ninth bit to TB8 bit. E Write the byte to be transmitted to SBUF register. This write starts the transmission. 4.2.2.2. Reception (Modes 1, 2 and 3) To prepare for a reception, set REN bit in SCON register. The actual reception is then initiated by a detected high-to-low transition on the RXD pin.
2
4.3. Framing Bit Error Detection (Modes 1, 2 and 3)
Framing bit error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the software sets FE bit in SCON register. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit.
4.4. Overrun Error Detection (Modes 1, 2 and 3)
Overrun error detection is provided for the three asynchronous modes. To enable the overrun error detection feature, set SMOD0 bit in PCON register.
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This error occurs when a data received and not read by the CPU is overwritten by a new one. Figure 4.4. shows an example of Overrun Error.
RXD Data 1 Data 2
RI
OVR Data 1 is overwritten by Data 2
Figure 4.4. Overrun Error (Modes 1, 2 and 3) In this example Data 1 is received and RI is set. Then a Data 2 is sent before the CPU has read the first one. Data 1 is overwritten by Data 2 and the Overrun Error bit (OVR) is set in SCON register to indicate the error.
4.5. Multiprocessor Communication (Modes 2 and 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the Serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set). This allows the TSC80251G1 to function as a slave processor in an environment where multiple slave processors share a single serial line. When the multiprocessor communication feature is enabled, the receiver ignores frames with the ninth bit clear. The receiver examines frames with the ninth bit set for an address match. If the received address matches the slaves address, the receiver hardware sets RB8 and RI bits in SCON register, generating an interrupt. The addressed slave's software then clears SM2 bit in SCON register and prepares to receive the data bytes. The other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses.
Note: ES bit must be set in IE register to allow RI bit to generate an interrupt.
4.6. Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the Serial Port to examine the address of each incoming
II. 4.6
MATRA MHS Rev.A (18 Dec. 96)
TSC 80251G1
command frame. Only when the Serial Port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect).
4.6.1. Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or mores slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111B. For example: SADDR = 0101 0110B SADEN = 1111 1100B Given = 0101 01XXB The following is an example of how to use given addresses to address different slaves: Slave A: SADDR = 1111 0001B SADEN = 1111 1010B Given = 1111 0X0XB Slave B: SADDR = 1111 0011B SADEN = 1111 1001B Given = 1111 0XX1B Slave C: SADDR = 1111 0010B SADEN = 1111 1101B Given = 1111 00X1B The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000B). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011B). To communicate with slaves A, B and C, the master must send an address with bit 0 set , bit 1 clear, and bit 2 clear (e.g. 1111 0001B).
2
MATRA MHS Rev.A (18 Dec. 96)
II. 4.7
TSC 80251G1
4.6.2. Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.: SADDR = 0101 0110B SADEN = 1111 1100B (SADDR) or (SADEN) = 1111 111XB The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR = 1111 0001B SADEN = 1111 1010B Given = 1111 1X11B, Slave B: SADDR = 1111 0011B SADEN = 1111 1001B Given = 1111 1X11B, Slave C: SADDR = 1111 0010B SADEN = 1111 1101B Given = 1111 1111B, For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
4.6.3. Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXB (all don't-care bits). This ensures that the Serial Port is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.
4.7. Baud Rates
The Baud Rate Control register (BDRCON, see Figure 4.9. ) is added to the TSC80251G1 derivatives in order to manage the new functionality of the UART. Three Baud Rate Generators can supply the transmission clock to the UART: Timer 1, Timer 2 and the internal Baud Rate Generator as detailed below.
4.7.1. Baud Rate for Mode 0
The transmission clock is provided by either the internal Baud Rate Generator or the internal fixed prescaler. This selection is done by setting SRC bit in BDRCON register. The transmission clock selection is shown in Figure 4.5. E When SRC = 0, the Baud Rate is fully compatible with 80C51 microcontrollers: Baud_Rate = FOSC/12
II. 4.8
MATRA MHS Rev.A (18 Dec. 96)
TSC 80251G1
E When SRC = 1, the Internal Baud Rate Generator (BRG) is selected and the Baud Rate is variable in two ranges: When SPD = 1, the Fast mode is selected: Baud_Rate = Fosc/[4(256-BRL)] When SPD = 0, the Slow mode is selected: Baud_Rate = Fosc/[24(256-BRL)].
OSC
2
6
SRC=0 SRC=1 2 BRG UART
SPD=0 SPD=1 SPD BRR SRC
BRL
Figure 4.5. Clock Transmission Sources in Mode 0 By default, after a reset, the bit SRC is cleared and the transmission clock is compatible with 80C51 microcontrollers. Setting this bit to one, selects the internal Baud Rate Generator. The 8-bit register BRL is the reload register of the Baud Rate Generator.
2
4.7.2. Baud Rate for Mode 2
The Baud Rate in mode 2 depends on the value of SMOD1 bit in PCON register. If SMOD1 = 0 (default value on reset), the Baud Rate is 1/64 the oscillator frequency. If SMOD1 = 1, the Baud Rate is 1/32 the oscillator frequency: Baud_Rate + The configuration is shown in Figure 4.6.
OSC 2 2 SMOD1 = 0 16 SMOD1 = 1 SMOD1 UART
2 SMOD1 F OSC 64
Figure 4.6. UART in Mode 2
MATRA MHS Rev.A (18 Dec. 96)
II. 4.9
TSC 80251G1
4.7.3. Baud Rate for Modes 1 and 3
Three Baud Rate Generators can supply the Baud Rate to the UART: Timer 1, Timer 2 and the internal Baud Rate Generator. It is possible to have different clocks for the transmission and reception. 4.7.3.1. Baud Rate Selection The Baud Rate Generator for transmit and receive clocks can be selected separately via the BDRCON register (See Figure 4.11. ).
INT_BRG TIMER1_BRG TIMER2_BRG RCLK RBCK INT_BRG TIMER1_BRG TIMER2_BRG TCLK TBCK 0 1 TBCK = 1 16 TIMER_BRG TBCK = 0 TX Clock 0 1 RBCK = 1 16 TIMER_BRG RBCK = 0 RX Clock
Figure 4.7. Baud Rate Generator Selection 4.7.3.2. Timer 1 When Timer 1 is used as Baud Rate Generator, the Baud Rates in Modes 1 and 3 are determined by the Timer 1 overflow and the value of SMOD1 bit in PCON register: 2 SMOD1 F OSC Baud_Rate + 12 32 [256 * (TH1)] TH1 + 256 * The configuration is shown in Figure 4.8.
OSC 12 C/T1#=0 TL1 T1 C/T1# INT1# GATE1 TR1 C/T1#=1 TH1 Control SMOD1 2 SMOD1=1 TIMER1_BRG SMOD1=0
2 SMOD1 F OSC 384 Baud_Rate
Figure 4.8. Timer 1 as Baud Rate Generator in Modes 1 and 3
II. 4.10
MATRA MHS Rev.A (18 Dec. 96)
A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAA AAA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAA AA A A AA A AAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA AA A A AAAAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAA A AAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Baud Rates Baud Rates 19200 28800 38400 57600 19200 28800 38400 57600 1200 2400 4800 9600 1200 2400 4800 9600 600 150 300 600 SMOD1 SMOD1 0 0 0 0 0 0 - 0 - 0 0 0 0 0 0 0 1 0 - 1
MATRA MHS Rev.A (18 Dec. 96) Note: Turn the timer off (clear the TR2 bit in T2CON register) before accessing registers. TH2, TL2 RCAP2H and RCAP2L. 150 300 0 0
4.7.3.3. Timer 2 In this mode, a rollover in TH2 register does not set the TF2 bit in T2CON register. Also, a high-to-low transition at T2EX pin sets the EXF2 bit in T2CON register but does not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). You can use the T2EX pin as an additional external interrupt by setting the EXEN2 bit in T2CON.
Table 4.4. Timer 1 Generated Baud Rates at 16 MHz
Table 4.3. Timer 1 Generated Baud Rates at 12 MHz
FOSC = 14.7456 MHz
FOSC = 11.0592 MHz
TH1
TH1
128
192
224
240
248
252
254
255
160
208
232
244
250
253
253
255
255
64
0
-
-
-
Error (%)
Error (%)
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
-
0
SMOD1
SMOD1
-
0
1
1
1
1
1
-
-
-
-
0
0
0
0
0
1
-
-
-
-
-
TSC 80251G1
FOSC = 16 MHz
FOSC = 12 MHz
TH1
TH1
187
221
239
247
152
204
230
243
243
117
117
48
-
-
-
-
-
-
-
-
-
-
Error (%)
Error (%)
0.08
0.08
0.64
0.79
2.12
3.55
0.16
0.16
0.16
0.16
0.16
0.16
-
-
-
-
-
-
-
-
-
-
II. 4.11
2
TSC 80251G1
You may configure Timer 2 as a timer or a counter. In most applications, it is configured for timer operation (the C/T2# bit is clear in T2CON register).
OSC
2 TH2 TL2 (8 bits) (8 bits) TIMER2_BRG
T2 C/T2# TR2
RCAP2H RCAP2L
T2 EXEN2 Note availability of additional external interrupt.
EXF2
Interrupt Request
Figure 4.9. Timer 2 in Baud Rate Generator Mode Note that Timer 2 increments every state time (2TOSC) when it is in the Baud Rate Generator mode. In the Baud Rate formula that follows, "RCAP2H, RCAP2L" denotes the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned integer: F OSC Baud_Rate + 32 [65536 * (RCAP2H, RCAP2L)] (RCAP2H, RCAP2L) + 65536 * 32 F OSC Baud_Rate
Note: When Timer 2 is configured as a timer and is in Baud Rate Generator mode, do not read or write the TH2 or TL2 registers. The timer is being incremented every state time, and the results of a read or write may not be accurate. In addition, you may read, but not write to RCAP2 registers; a write may overlap a reload and cause write and/or reload errors.
II. 4.12
MATRA MHS Rev.A (18 Dec. 96)
AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Baud Rates Baud Rate 115200 115200 19200 28800 38400 57600 19200 28800 38400 57600 1200 2400 4800 9600 1200 2400 4800 9600 150 300 600 150 300 600 RCAP2H, RCAP2L RCAP2H, RCAP2L
MATRA MHS Rev.A (18 Dec. 96)
Table 4.6. Timer 2 Generated Baud Rates at 16 MHz
Table 4.5. Timer 2 Generated Baud Rates at 12 MHz
62464
64000
64768
65152
65344
65440
65488
65512
65520
65524
65528
65532
63232
64384
64960
65248
65392
65464
65500
65518
65524
65527
65530
65533
FOSC = 14.7456 MHz
FOSC = 11.0592 MHz
Error (%)
Error (%)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RCAP2H, RCAP2L
RCAP2H, RCAP2L
62203
63869
64703
65428
65432
65484
65510
65519
65523
65527
63036
64286
65224
65380
65458
65467
65516
65526
65119
64911
6552
TSC 80251G1
-
-
-
FOSC = 16 MHz
FOSC = 12 MHz
Error (%)
Error (%)
0.01
0.02
0.04
0.08
0.16
0.16
0.16
0.16
2.12
0.16
3.55
0.16
0.16
0.16
0.16
2.34
0.16
2.34
-
0
0
0
-
-
II. 4.13
2
TSC 80251G1
4.7.3.4. Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow, the value of SPD bit (Speed Mode) in BRCON register and the value of the SMOD1 bit in PCON register: E SPD = 1 2 SMOD1 F OSC Baud_Rate + 2 32 [256 * (BRL)] BRL + 256 * E SPD = 0 (Default Mode) Baud_Rate + 12 2 SMOD1 F OSC 32 [256 * (BRL)] 2 SMOD1 F OSC 64 Baud_Rate
BRL + 256 *
2 SMOD1 F OSC 384 Baud_Rate
The configuration is shown in the Figure 4.10.
OSC 2 6 SMOD1=1 SPD=0 BRG SPD BRR SMOD1 SPD=1 BRL 2 INT_BRG SMOD1=0
Figure 4.10. Internal Baud Rate Generator in Modes 1 and 3
II. 4.14
MATRA MHS Rev.A (18 Dec. 96)
A AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAA AAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAA AAA AA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAA AAAA AAA AA AAAAA A A AAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Baud Rates 115200 19200 28800 38400 57600 1200 2400 4800 9600 1200 600 150 300 600 SPD 0 0 0 0 0 0 1 0 1 1 0 0 0 0
AAAAAAAAAAAAAAA A AA AA AA A AA AAAAA A A A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAA AAA AAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AAAAAAAAAAAAAAA AAAAAAAA AAAAA AAA AAA AA AAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAA A AAAA A AAA AAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Baud Rate 115200 19200 28800 38400 57600 2400 4800 9600 SPD 0 0 0 0 0 1 0 1
MATRA MHS Rev.A (18 Dec. 96) 150 300 - 0
Table 4.8. Internal Baud Rate Generator at 16 MHz
Table 4.7. Internal Baud Rate Generator at 12 MHz
FOSC = 14.7456 MHz
FOSC = 11.0592 MHz
SMOD
SMOD
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
BRL
BRL
128
192
224
240
248
252
254
248
255
252
254
160
208
232
244
250
253
253
255
247
255
253
64
-
Error (%)
Error (%)
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPD
SPD
-
0
0
1
1
1
1
1
1
1
1
-
0
0
0
0
0
0
1
1
1
1
-
-
TSC 80251G1
SMOD
SMOD
FOSC = 16 MHz
FOSC = 12 MHz
-
0
1
0
0
0
0
0
1
1
1
-
0
0
0
0
0
1
0
0
0
0
-
-
BRL
BRL
152
204
230
243
239
243
247
152
204
230
243
243
217
236
243
246
117
117
48
48
-
-
-
-
Error (%)
Error (%)
0.08
0.08
0.16
0.16
0.16
0.16
0.16
2.12
0.16
3.55
0.16
0.16
0.16
0.16
0.16
0.16
0.16
2.34
0.16
2.34
II. 4.15 - - - -
2
TSC 80251G1
4.8. Registers
BDRCON (S:9Bh) Baud Rate Control register
- 7 Bit Number 7 6 5 4 - 6 Bit Mnemonic - - - BRR - 5 BRR 4 TBCK 3 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run control bit Clear to stop the Baud Rate Set to start the Baud Rate Transmission Baud Rate Generator Selection bit Clear to select Timer 1 for the Baud Rate Generator Set to select Internal Baud Rate Generator Reception Baud Rate Generator Selection bit Clear to select Timer 1 for the Baud Rate Generator Set to select internal Baud Rate Generator Baud Rate Speed control bit Clear to select the SLOW Baud Rate Generator when SRC = 0 Set to select the FAST Baud Rate Generator when SRC = 1 Baud Rate Source select bit in Mode 0 Clear to select FOSC/12 as the Baud Rate Generator (fixed transmission clock). Set to select the internal Baud Rate Generator. RBCK 2 SPD 1 SRC 0
3
TBCK
2
RBCK
1
SPD
0
SRC
Reset value = XXX0 0000b
Figure 4.11. BDRCON Register
II. 4.16
MATRA MHS Rev.A (18 Dec. 96)
TSC 80251G1
BRL (S:9Ah) Baud Rate Reload register
7 6 Reset value = 0000 0000b
5
4
3
2
1
0
Figure 4.12. BRL Register SADDR (S:A9h) Serial Address register
7 6 Reset value = 0000 0000b
5
4
3
2
1
0
Figure 4.13. SADDR Register SADEN (S:B9h) Serial Address Enable register
2
4 3 2 1 0
7 6 Reset value = 0000 0000b
5
Figure 4.14. SADEN Register SBUF (S:99h) Serial Buffer register
7 6 Reset value = XXXX XXXXb
5
4
3
2
1
0
Figure 4.15. SBUF Register
MATRA MHS Rev.A (18 Dec. 96)
II. 4.17
TSC 80251G1
SCON (S:98h) Serial Control register
FE/SM0 OVR/SM1 SM2 REN TB8 RB8 TI RI 7 6 5 4 3 2 1 0 Bit Bit Description Number Mnemonic 7 FE Framing Error bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. Serial Port Mode bit 0 SM0 To select this function, clear SMOD0 bit in PCON register. Software writes to bits SM0 and SM1 to select the Serial Port operating mode. Refer to SM1 bit for the mode selections. 6 OVR Overrun error bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an overwrite of the receive buffer. Must be cleared by software SM1 Serial Port Mode bit 1 To select this function, clear SMOD0 bit in PCON register. Software writes to bits SM1 and SMO to select the Serial Port operating mode. SMO SM1 Mode Description Baud Rate 0 0 0 Shift register FOSC/12 or variable if SRC bit BDRCON register is set 0 1 1 8-bit UART Variable 1 0 2 9-bit UART FOSC/32 or FOSC/64 1 1 3 9-bit UART Variable 5 SM2 Serial Port Mode bit 2 Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features. This allows the Serial Port to differentiate between data and command frames and to recognize slave and broadcast addresses. 4 REN Receiver Enable bit Clear to enable transmission. Set to enable reception. 3 TB8 Transmit bit 8 Modes 0 and 1: Not used. Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8. 2 RB8 Receiver bit 8 Mode 0: Not used. Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received. Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received. 1 TI Transmit Interrupt flag Set by the transmitter after the last data bit is transmitted. Must be cleared by software. 0 RI Receive Interrupt flag Set by the receiver after the stop bit of a frame has been received. Must be cleared by software. Reset value = 0000 0000b
Figure 4.16. SCON Register
II. 4.18
MATRA MHS Rev.A (18 Dec. 96)
TSC 80251G1
Event and Waveform Controller
5.1. Introduction
The Event and Waveform Controller (EWC) is an on-chip peripheral that performs a variety of timing and counting operations, including Pulse Width Modulation (PWM). The EWC provides also the capability for a software Watchdog Timer. On TSC80251G1 derivatives the EWC is configured in Programmable Counter Array (PCA) mode. This mode has up to five Compare/Capture modules using the same Counter as time base. E Each module may use four clock sources: FOSC/12 FOSC/4 Timer 0 overflow (Modes 1, 2 and 3) External input on P1.2 (ECI pin) E Each module may be programmed in any of the following modes: Rising and/or falling edge Capture Software Timer High-speed output Pulse Width Modulation (PWM)
2
5.2. PCA Mode
5.2.1. Timers/Counters
Figure 5.1. depicts the basic logic of the Counter portion of the PCA. The CH/CL special function register pair operates as a 16-bit Counter. The selected input increments CL (low byte) register. When CL overflows, CH (high byte) register increments after two oscillator periods; when CH overflows, it sets the PCA overflow flag (CF in CCON register) generating a PCA interrupt request if ECF bit in CMOD register is set.
MATRA MHS Rev. A (18 Dec. 96)
II. 5.1
TSC 80251G1
Module 0 Module 1 CMOD reg CPS1 CPS0 FOSC/12 FOSC/4 Timer 0 P1.2/ECI CMOD reg CIDL Processor in Idle Mode 00 01 10 11 CCON reg CR ECF CMOD reg CH (8 bits) Module 2 Module 3 Module 4 CL (8 bits) EWC Interrupt Request
CF CCON reg
Counter
Figure 5.1. EWC Counter in PCA Mode CPS1 and CPS0 bits in CMOD register select one of four signals as the input to the Counter (See Figure 5.1. ): E FOSC /12 Provides a clock pulse at S5P2 of every peripheral cycle. With FOSC = 16 MHz, the Counter increments every 750 ns. E FOSC /4 Provides clock pulses at S1P2, S3P2, and S5P2 of every peripheral cycle. With FOSC = 16 MHz, the Counter increments every 250 ns. E Timer 0 overflow The CL register is incremented at S5P2 of the peripheral cycle when Timer 0 overflows. This selection provides the PCA with a programmable frequency input. E External signal on Port 1.2/ECI The CPU samples the ECI pin at S1P2, S3P2 and S5P2 of every peripheral cycle. The first clock pulse (S1P2, S3P2 or S5P2) that occurs following a high-to-low transition at the ECI pin increments the CL register. The maximum input frequency for this input selection is FOSC /8. Setting the run control bit (CR in CCON register) turns the PCA Counter on, if the output of the NAND gate (See Figure 5.1. ) equals logic one. The PCA Counter continues to operate during idle mode unless CIDL bit of CMOD register is set. CPU can read the contents of CH and CL registers at any time. However, writing to them is inhibited while they are counting i.e., when CR bit is set.
5.2.2. Compare/Capture Modules
Each Compare/Capture module is made up of a Compare/Capture register pair (CHx/CLx; x = 0, 1, 2, 3 or 4), a 16-bit comparator and various logic gates and signal transition selectors. The registers store the time or count at which an external event occurred (capture) or at which an action should occur
II. 5.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
(comparison). For example, in the PWM mode, the low-byte register controls the duty cycle of the output waveform. The logical configuration of a Compare/Capture module depends on its mode of operation. Each module can be independently programmed for operation in any of the following modes: E 16-bit Capture mode with triggering on the positive edge, negative edge or either edge E Compare modes: 16-bit software Timer 16-bit high-speed output 16-bit Watchdog Timer (module 4 only) 8-bit Pulse Width Modulation The Compare function provides the capability for operating the five modules as Timers, event Counters or Pulse Width Modulators. Four modes employ the Compare function: 16-bit software Timer mode, high-speed output mode, WDT mode and PWM mode. In the first three of these, the Compare/Capture module continuously compares the 16-bit PCA Counter value with the 16-bit value pre-loaded into the module's CCAPxH/CCAPxL register pair. In the PWM mode, the module continuously compares the value in the low-byte PCA Counter register (CL) with an 8-bit value in the CCAPxL module register. Comparisons are made three times per peripheral cycle to match the fastest PCA Counter clocking rate (FOSC/4). Setting ECOMx bit in a module's mode register (CCAPMx) selects the Compare function for that module. To use the modules in the Compare modes, observe the following general procedure: Select the module's mode of operation. Select the input signal for the PCA Counter. Load the comparison value into the module's Compare/Capture register pair. Set the PCA Counter run Counter bit. After a match causes an interrupt, clear the module's Compare/Capture flag. E No operation Bit combinations programmed into a Compare/Capture module's mode register (CCAPMx) determine the operation mode. NO TAGprovides bit definition and Table 5.1. lists the bit combinations of the available modes. Other bit combinations are invalid and produce undefined results. The Compare/Capture modules perform their programmed functions when their common time base, the PCA Counter, runs. The Counter is turned on and off with CR bit in CCON register. To disable any given module, program it for the "no operation" mode. The occurrence of a Capture, software Timer, or high-speed output event in a Compare/Capture module sets the module's Compare/Capture flag (CCFx) in CCON register and generates a PCA interrupt request if the corresponding enable bit in CCAPMx register is set. The CPU can read or write CCAPxH and CCAPxL registers at any time.
2
MATRA MHS Rev. A (18 Dec. 96)
II. 5.3
TSC 80251G1
Table 5.1. PCA Module Modes (x = 0, 1, 2, 3, 4)
ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx 0 X (2) X (2) X (2) 1 1 1 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 X (2) 0 0 0 0 0 0 1 0 0 X (2) X (2) X (2) X (2) X (2) 0 X (2) No operation 16-bit Capture on positive-edge trigger at CEXx 16-bit Capture on negative-edge trigger at CEXx 16-bit Capture on positive/negative-edge trigger at CEXx Compare: software Timer Compare: high-speed output Compare: 8-bit PWM Compare: PCA WDT (3) Module Mode
Notes: 1. This table shows the CCAPMx register bit combinations for selecting the operating modes of the PCA Compare/Capture modules. Other bit combinations are invalid. 2. X = indetermined. 3. For the PCA WDT mode, set also WDTE bit in CMOD register to enable the reset output signal (Module 4 only).
5.2.2.1. 16-bit Capture Mode The Capture mode (See Figure 5.2. ) provides the PCA with the ability to measure periods, pulse widths, duty cycles and phase differences at up to five separate inputs. External I/0 pins CEX0 through CEX4 are sampled for signal transitions (positive and/or negative as specified). When a Compare/Capture module programmed for the Capture mode detects the specified transition, it captures the PCA Counter value. This records the time at which an external event is detected, with a resolution equal to the Counter clock period. To program a Compare/Capture module for the 16-bit Capture mode, program the CAPPx and CAPNx bits in the module's CCAPMx register as follows: E To trigger the Capture on a positive transition, set CAPPx and clear CAPNx E To trigger the Capture on a negative transition, set CAPNx and clear CAPPx E To trigger the Capture on a positive or negative transition, set both CAPPx and CAPNx Table 5.1. lists the bit combinations for selecting module modes. For modules in the Capture mode, detection of a valid signal transition at the I/O pin (CEXx) causes hardware to load the current PCA Counter value into the Compare/Capture registers (CCAPxH/CCAPxL) and to set the module's Compare/Capture flag (CCFx) in the CCON register. If the corresponding interrupt enable bit (ECCFx) in the CCAPMx register is set, the PCA sends an interrupt request to the EWC interrupt handler. Since hardware does not clear the event flag when the interrupt is processed, the user must clear the flag by software. A subsequent Capture by the same module overwrites the existing captured value.
II. 5.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
To preserve a captured value, save it in RAM with the interrupt service routine before the next Capture event occurs.
PCA Counter Count Input Capture CEX x = 0, 1, 2, 3, 4
CCAPxH CCAPxL CH (8bits) CL (8bits)
CCFx CCON Reg - 7 0 CAPPx CAPNx 0 0 0 ECCFx 0
EWC Interrupt Request
CCAPMx Mode Register (x = 0, 1, 2, 3, 4)
2
Figure 5.2. PCA 16-bit Capture Mode 5.2.2.2. 16-bit Software Timer Mode To program a Compare/Capture module for the 16-bit software Timer mode (See Figure 5.3. ), set the ECOMx and MATx bits in the module's CCAPMx register. Table 5.1. lists the bit combinations for selecting module modes. A match between the PCA Counter and the Compare/Capture registers (CCAPxH/CCAPxL) sets the module's Compare/Capture flag (CCFx in CCON register). This generates an interrupt request if the corresponding interrupt enable bit (ECCFx in CCAPMx register) is set. Since hardware does not clear the Compare/Capture flag when the interrupt is processed, the user must clear the flag in software. During the interrupt routine, a new 16-bit Compare value can be written to the Compare/Capture registers (CCAPxH/CCAPxL).
MATRA MHS Rev. A (18 Dec. 96)
II. 5.5
TSC 80251G1
Count PCA Counter CH CL (8 bits) (8 bits) Compare/Capture Module CCAPxH CCAPxL (8 bits) (8 bits) Match Toggle CEXx CCFx CCON reg - 7 "0" Reset Write to CCAPxL For software Timer mode, set ECOMx and MATx. For high speed output mode, set ECOMx, MATx and TOGx. ECOMx 0 0 MATx TOGx 0 ECCFx 0 EWC Interrupt Request
16-Bit Comparator Enable
CCAPMx Mode Register (x = 0, 1, 2, 3, 4)
"1"
Write to CCAPxH
Figure 5.3. PCA Software Timer and High-Speed Output Modes
Note: To prevent an invalid match while updating these registers, user software should write to CCAPxL first, then CCAPxH. A write to CCAPxL clears the ECOMx bit disabling the Compare-function, while a write to CCAPxH sets the ECOMx bit enabling the Compare function again.
5.2.2.3. High-Speed Output Mode The high-speed output mode (See Figure 5.3. ) generates an output signal by toggling the module's I/0 pin (CEXx) when a match occurs. This provides greater accuracy than toggling pins in software because the toggle occurs before the interrupt request is serviced. Thus, interrupt response time does not affect the accuracy of the output. To program a Compare/Capture module for the high-speed output mode, set the ECOMx, MATx, TOGx bits in the module's CCAPMx register. Table 5.1. lists the bit combinations for selecting module modes. A match between the PCA Counter and the Compare/Capture registers (CCAPxH/CCAPxL) toggles the CEXx pin and sets the module's Compare/Capture flag (CCFx in CCON register). This generates an interrupt if the corresponding enable bit (CCFx in CCON register) is set. By setting or clearing the CEXx pin in software, the user selects whether the match toggles the pin from low to high or vice versa. 5.2.2.4. Watchdog Timer Mode A Watchdog Timer (WDT) provides the means to recover from routines that do not complete successfully. A WDT automatically invokes a device reset if it does not regularly receive hold-off signals. Watchdog Timers are used in applications that are subject to electrical noise, power glitches, electrostatic discharges, etc., or where high reliability is required. The PCA provides a 16-bit programmable frequency WDT as a mode option on Compare/Capture module 4. This mode generates a device reset when the count in the PCA Counter matches the value
II. 5.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
stored in the module 4 Compare/Capture registers. A PCA WDT reset has the same effect as an external reset. Module 4 is the only PCA module that has the WDT mode (See Figure 5.4. ). When not programmed as a WDT, it can be used in the other modes. To program module 4 for the PCA WDT mode: E Set ECOM4 and MAT4 bits in CCAPM4 register and WDTE bit in CMOD register. Table 5.1. lists the bit combinations for selecting module modes. E Select the desired input for the PCA Counter by programming CPS0 and CPS1 bits in CMOD register (See Figure 5.13. ). E Enter a 16-bit comparison value in the Compare/Capture registers (CCAP4H/CCAP4L). E Enter a 16-bit initial value in the PCA Counter (CH/CL) or use the reset value (0000h). E The difference between these values multiplied by the PCA input pulse rate determines the running time to "expiration." E Set the Counter run Counter bit (CR in CCON register) to start the PCA WDT. E The PCA WDT generates a reset signal each time a match occurs. E To hold off a PCA WDT reset, the user has three options: Periodically change the comparison value in CCAP4H/CCAP4L so a match never occurs. Periodically change the PCA Counter value so a match never occurs. Disable the module 4 reset output signal by clearing WDTE bit before a match occurs, then later enable it again. The first two options are more reliable because the Watchdog Timer is not disabled as in the third option. The second option is not recommended if other PCA modules are in use, since the five modules share a common time base. Thus, in most applications the first option is the best one.
2
MATRA MHS Rev. A (18 Dec. 96)
II. 5.7
TSC 80251G1
Count PCA Counter CL CH (8 bits) (8 bits) Compare/Capture Module CCAPxH CCAPxL (8 bits) (8 bits)
16-Bit Comparator Enable - 7 "0" Reset Write to CCAP4L ECOM4 0 0
Match PCA WDT Reset WDTE CMOD.6 1 - 0 - 0
CCAPM4 Mode Register
"1" Write to CCAP4H
Figure 5.4. PCA Watchdog Timer Mode 5.2.2.5. Pulse Width Modulation Mode The five PCA Compare/Capture modules can be independently programmed to function as Pulse Width Modulators (PWM). The modulated output, which has an 8-bit pulse width resolution is available on CEXx pin. The PWM output can be used to convert digital data to an analog signal with simple external circuitry. In this mode, the value in the low byte of the PCA Timer/Counter (CL) is continuously compared with the value in the low byte of the Compare/Capture register (CCAPxL; x = 0, 1, 2, 3, 4). When CL < CCAPxL, the output waveform is low (See Figure 5.6. ). When a match occurs (CL = CCAPxL), the output waveform goes high and remains high until CL register rolls over from FFh to 00h, ending the period. At roll-over the output returns to low, the value in CCAPxH register is loaded into CCAPxL register, and a new period begins. The value in CCAPxL register determines the duty cycle of the current period. The value in CCAPxH register determines the duty cycle of the following period. Changing the value in CCAPxL over time modulates the pulse width. As depicted in Figure 5.6. , the 8-bit value in CCAPxL can vary from 0 (100% duty cycle) to 255 (0.4% duty cycle).
II. 5.8
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
To program a Compare/Capture module for the PWM mode: E Set ECOMx and PWMx bits in the module's CCAPMx register. Table 5.1. lists the bit combinations for selecting module modes. E Select the desired input for the PCA Counter by programming CPS0 and CPS1 bits in CMOD register. E Enter an 8-bit value in CCAPxL to specify the duty cycle of the first period of the PWM output waveform. E Enter an 8-bit value in CCAPxH to specify the duty cycle of the second period. E Set the Counter run Counter bit (CR in CCON register) to start the PCA Counter.
Note: To change the value in CCAPxL without glitches, write the new value to the high byte register (CCAPxH). This value is shifted by hardware into CCAPxL when CL rolls over from FFh to 00h.
The frequency of the PWM output equals the frequency of the PCA Counter input signal divided by 256. The highest frequency occurs when the FOSC/4 input is selected for the PCA Counter. For FOSC = 16 MHz, this is 15.6 KHz.
CCAPxH CL rolls over from FFh TO 00h loads CCAPxH contents into CCAPxL CCAPxL "0" CL < CCAPxL CL (8 bits) x = 0, 1, 2 or 4 8-Bit Comparator CL >= CCAPxL "1" CEX
2
- 7
ECOMx
0
0
0
0
PWMx
CCAPMx reg
0 0
Figure 5.5. PWM Mode
MATRA MHS Rev. A (18 Dec. 96)
II. 5.9
TSC 80251G1
CCAPxL 255 Duty Cycle 0.4%
1
Output Waveform
0 1
230 10%
0 1
128 50%
0 1
25 90%
0 1
0
100%
0
Figure 5.6. PWM Variable Duty Cycle
II. 5.10
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
5.3. Registers
CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) Compare/Capture Module x High registers (x = 0, 1, 2, 3, 4)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Figure 5.7. EWC CCAPxH Registers (x = 0, 1, 2, 3, 4) CCAP0L (S:EAh) CCAP1L (S:EBh) CCAP2L (S:ECh) CCAP3L (S:EDh) CCAP4L (S:EEh) Compare/Capture Module x Low registers (x = 0, 1, 2, 3, 4)
2
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Figure 5.8. EWC CCAPxL Registers (x = 0, 1, 2, 3, 4)
MATRA MHS Rev. A (18 Dec. 96)
II. 5.11
TSC 80251G1
CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) Compare/Capture Module x Mode registers (x = 0, 1, 2, 3, 4)
- 7 Bit Number 7 6 ECOMx 6 Bit Mnemonic - ECOMx CAPPx 5 CAPNx 4 MATx 3 TOGx 2 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and Watchdog Timer (WDT). Capture Mode (Positive) Module x bit Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin. Capture Mode (Negative) Module x bit Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. Match Module x bit Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt. Must be cleared by software. Toggle Module x bit The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. Must be cleared by software. Pulse Width Modulation Module x Mode bit Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. Must be cleared by software. Enable CCFx Interrupt bit Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request. PWMx 1 ECCFx 0
5
CAPPx
4
CAPNx
3
MATx
2
TOGx
1
PWMx
0
ECCFx
Reset Value = 1000 0000b
Figure 5.9. EWC CCAPMx Registers (x = 0, 1, 2, 3, 4)
II. 5.12
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
CCON (S:D8h) Timer/Counter Control register
CF 7 Bit Number 7 CR 6 Bit Mnemonic CF - 5 CCF4 4 CCF3 3 CCF2 2 Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software. PCA Module 3 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software. PCA Module 2 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software. PCA Module 1 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. PCA Module 0 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software. CCF1 1 CCF0 0
6
CR
5 4
- CCF4
2
3
CCF3
2
CCF2
1
CCF1
0
CCF0
Reset Value = 0010 0000b
Figure 5.10. EWC CCON Register
MATRA MHS Rev. A (18 Dec. 96)
II. 5.13
TSC 80251G1
CH (S:F9h) Timer/Counter High register
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Figure 5.11. EWC CH Register CL (S:E9h) Timer/Counter Low register
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Figure 5.12. EWC CL Register
II. 5.14
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
CMOD (S:D9h) Counter Mode register
CIDL 7 Bit Number 7 WDTE 6 Bit Mnemonic CIDL - 5 - 4 - 3 Description PCA Counter Idle Control bit Clear to let the PCA running during Idle mode. Set to stop the PCA when Idle mode is invoked. Watchdog Timer Enable bit Clear to disable the Watchdog Timer function on EWC module 4. Set to enable the Watchdog Timer function on EWC module 4. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, Fosc/12 0 1 Internal Clock, Fosc/4 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = Fosc/8) Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. CPS1 2 CPS0 1 ECF 0
6
WDTE
5 4 3 2
- - - CPS1
2
1
CPS0
0
ECF
Reset Value = 0011 1000b
Figure 5.13. EWC CMOD Register
MATRA MHS Rev. A (18 Dec. 96)
II. 5.15
TSC 80251G1
SSLC / Inter-Integrated Circuit (I2C) Interface
6.1. Introduction
The Synchronous Serial Link Controller (SSLC) provides the selection of one synchronous serial interface among the three most popular ones: D Inter-Integrated Circuit (I2C) interface. D Wire and Serial Peripheral Interface (SPI). When I2C interface is selected, SPI is no longer available. This section describes the I2C interface. The I2C bus is a bi-directional two-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (I2C) control. The bus is made of two lines: oneSerial Clock (SCL) and one Serial Data (SDA) that carry information between the ICs connected to them. The serial data transfer is limited to 100kbit/s in basic mode. Various communication configuration can be designed using this bus; however, the TSC80251G1 implements only the two basic Master transfer modes without multimaster capability. Figure 6.1. shows a typical I2C bus configuration.
2
TSC80251G1 (Master) SCL/P1.6 SDA/P1.7 Rp Rp
Slave 1
Slave 2
Slave N
Figure 6.1. Typical I2C Bus Configuration using the TSC80251G1 The CPU interfaces to the I2C logic via the following three 8-bit Special Function Registers (SFR): the Synchronous Serial Control register (SSCON, see Figure 6.6. ), the Synchronous Serial Data register (SSDAT, see Figure 6.8. ) and the Synchronous Serial Control and Status register (SSCS, see Figure 6.9. ). SSCON is used to enable the I2C interface, to program the bit rate (See Table 6.1. ), to acknowledge or not a received data, to send a START or a STOP condition on the I2C bus, and to acknowledge a SSLC interrupt. An hardware reset disables the I2C interface. In write mode, SSCS is used to select the I2C interface and to select the bit rate source. In read mode, SSCS contains a status code which reflects the status of the I2C logic and the I2C bus. The three least significant bits are always zero. The five most significant bits contains the status code. There are 11 possible status code. When SSCS contains F8h, no relevant state information is available and no SSLC interrupt is requested. A valid status code is available in SSCS one machine cycle after the Synchronous Serial Interrupt flag (SSI) is set by hardware and is still present one machine cycle after SSI has been reset by software. Table 6.2. to Table 6.4. give the status for the master modes and miscellaneous states. SSDAT contains a serial data byte to be transmitted or a byte which has just been received. It is addressable while it is not in process of shifting a byte. This occurs when I2C logic is in a defined
MATRA MHS Rev. A (18 Dec. 96)
II. 6.1
TSC 80251G1
state and SSI is set. Data in SSDAT remains stable as long as SSI is set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always contains the last byte present on the bus. Figure 6.2. shows how a data transfer is accomplished on the I2C bus.
SDA MSB Slave Address Acknowledgment R/W direction signal from receiver bit 8 9 1 Nth data byte Acknowledgment signal from receiver 8 9 P/S
SCL S
1
2
2
Clock line held low while serial interrupts are serviced
Figure 6.2. Complete data transfer on I2C bus The two operating modes are: D Master Transmitter D Master Receiver Data transfer in each mode of operation are shown in Figure 6.3. and Figure 6.4. These figures contain the following abbreviations: A Acknowledge bit (low level on SDA) Not acknowledge bit (high level on SDA) A Data 8-bit data byte P Stop condition MR Master Reveive MT Master Transmit S Start condition SLA Slave Address R Read bit (high level on SDA) W Write bit (low level on SDA) In Figure 6.3. and Figure 6.4. , circles are used to indicate when SSI is set. The numbers in the circles show the status code held in SSCS. At each point, a proper service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until SSI is cleared by software. When the SSLC interrupt routine is entered, the status code in SSCS is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table 6.2. and Table 6.3.
II. 6.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
6.1.1. Interface and Bit rate source selection
Before the I2C interface can be enabled, SSCS must be initialised as follows:
SSBRS Bit Rate Source - - - - - - - - - - - - SSM0D 0
SSMOD selects the I2C interface. The bit rate can be derived from a programmable bit rate generator or from the internal bit rate controller. The Synchronous Serial Bit Rate Selection bit (SSBRS) selects the programmable or predefined bit rates (See Figure 6.9. ). When in the programmable bit rate generator configuration, the bit rate depends on the content of the Synchronous Serial Bit Rate register (SSBR, see Figure 6.5. ). It is given by the following formula:
Br= FOSC 4(SSBR value+3)
2
6.1.2. Master transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 6.3. ). Before the master transmitter mode can be entered, SSCON must be initialized as follows:
SSCR2 bit rate SSPE 1 SSSTA 0 SSSTO 0 SSI 0 SSAA X SSCR1 bit rate SSCR0 bit rate
SSCR0, SSCR1 and SSCR2 select one predefined serial bit rate if the programmable bit rate generator is not used. SSPE must be set to enable I2C interface. SSSTA, SSSTO and SSI must be cleared. The master transmitter mode may now be entered by setting the SSSTA bit. The I2C logic will now test the I2C bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SSI) is set, and the status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that loads SSDAT with the slave address and the data direction bit (SLA+W). The serial interrupt flag (SSI bit in SSCON) must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, SSI is set again and two status code in SSCS are possible: 18h and 20h. The appropriate action to be taken for each of these status code is detailed in Table 6.2. This scheme is repeated until a STOP condition is transmitted. SSPE, SSCR2, SSCR1 and SSCR0 are not affected by the serial transfer and are not referred to in Table 6.2. After a repeated START condition (state 10h) I2C logic may switch to the master receiver mode by loading SSDAT with SLA+R.
MATRA MHS Rev. A (18 Dec. 96)
II. 6.3
TSC 80251G1
6.1.3. Master receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter (See Figure 6.4. ). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the service routine must load SSDAT with the 7-bit slave address and the data direction bit (SLA+R). Then SSI must be cleared in SSCON before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, SSI is set again and two status code in SSCS are possible: 40h, and 48h. The appropriate action to be taken for each of these status code is detailed in Table 6.3. This scheme is repeated until a STOP condition is transmitted. SSPE, SSCR2, SSCR1 and SSCR0 are not affected by the serial transfer and are not referred to in Table 6.3. After a repeated START condition (state 10h) I2C logic may switch to the master transmitter mode by loading SSDAT with SLA+W. The I2C logic interfaces to the external I2C bus via two port pins: P1.6/SCL and P1.7/SDA. To allow proper operation of the I2C interface, the output latches of P1.6 and P1.7 must be set to logic 1 (See section 2.6).
II. 6.4
MATRA MHS Rev. A (18 Dec. 96)
A A A A AAAAAAAAAAA A A A A AA AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A AA AA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A AA AA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AA AA
SSBRS SSCR2 SSCR1 SSCR0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 X X 1 1 0 0 1 1 0 0 X X 1 0 1 0 1 0 1 0
MATRA MHS Rev. A (18 Dec. 96)
Table 6.1. Serial Clock Rates
11.6< <100 min SSBR value: 27
FOSC= 12MHz
0.5 < . < 62.5
12.5
62.5
53.5
100
75
47
-
-
Bit frequency (kHz)
15.5< <100 min SSBR value: 37
FOSC= 16MHz
0.67 < . < 83
16.5
71.5
62.5
100
83
-
-
-
TSC 80251G1
96 (256 - reload value Timer 1) (reload value range: 0-254 in mode 2)
4 (SSBR value + 3)
FOSC divided by
Reserved
120
960
160
192
224
256
60
II. 6.5
2
TSC 80251G1
MT
Successful transmission to a slave receiver
S
SLA
W
A
Data
A
P
08h Next transfer started with a repeated start condition
18h
28h
S
SLA
W
10h Not acknowledge received after the slave address R A P
20h Not acknowledge received after a data byte A P
MR
30h From master to slave From slave to master Data A Any number of data bytes and their associated acknowledge bits
n
This number (contained in STAT) corresponds to a defined state of the I2C bus
Figure 6.3. Format and States in the Master Transmitter Mode
II. 6.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
MR
Successful transmission to a slave receiver
S
SLA
R
A
Data
A
Data
A
P
08h
40h
50h
58h
Next transfer started with a repeated start condition
S
SLA
R
10h Not acknowledge received after the slave address W A P
2
48h MT
From master to slave From slave to master Data A Any number of data bytes and their associated acknowledge bits
n
This number (contained in SSCS) corresponds to a defined state of the I2C bus
Figure 6.4. Format and state in the master receiver mode
MATRA MHS Rev. A (18 Dec. 96)
II. 6.7
TSC 80251G1
Table 6.2. Status for Master Transmitter Mode
Status Code
(SSCS) 08h
Status of the I2C bus and
I2C hardware
Application software response To/From
SSDAT SSSTA X
To SSCON
SSSTO 0 SSI 0 SSAA X
Next action taken I2C hardware
AAAAAAAAAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAA A AA A AAA AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A AAA AAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA AA AA AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
10h 18h A START condition has been transmitted. A repeated START condition has been transmitted SLA+W has been transmitted; ACK has been received. Write SLA+W SLA+W will be transmitted then ACK will be transmitted Write SLA+W Write SLA+R X X 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 X X X X X X Write data byte No SSDAT action No SSDAT action No SSDAT action 20h SLA+W has been transmitted; NOT ACK has been received. Write data byte 0 1 0 1 0 0 1 1 0 0 0 0 X X X X No SSDAT action No SSDAT action No SSDAT action 28h Data byte has been transmitted; ACK has been received. Write data byte 0 1 0 1 0 0 1 1 0 0 0 0 X X X X No SSDAT action No SSDAT action No SSDAT action 30hAAAAAA Data byte has Write data byte been transmitted; NOT ACK has No SSDAT action been received. No SSDAT action No SSDAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X SLA+W will be transmitted then ACK will be transmitted SLA+R will be transmitted then logic will switched to master receiver mode. Data byte will be transmitted then ACK will be received. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be transmitted then ACK will be received. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be transmitted then ACK will be received. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be transmitted then ACK will be received. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset.
II. 6.8
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Table 6.3. Status for Master Receiver Mode.
Status Code
(SSCS) 08h
Status of the I2C bus and
I2C hardware
Application software response To/From
SSDAT SSSTA X
To SSCON
SSSTO 0 SSI 0 SSAA X
Next action taken I2C hardware
AAAAAAAAAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAA A A A AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAA A A A A AAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A AAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A
10h A START condition Write SLA+R has been transmitted. A repeated START Write SLA+R condition has been transmitted Write SLA+W SLA+R will be transmitted then ACK will be transmitted X X 0 0 0 0 X X 40h SLA+R has been transmitted; ACK has been received. SLA+R has been transmitted; NOT ACK has been received. No SSDAT action No SSDAT action No SSDAT action No SSDAT action No SSDAT action 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 48h X X X 50h Data byte has been received; ACK has been returned. Data byte has been received; NOT ACK has been returned. Read data byte 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 Read data byte Read data byte Read data byte Read data byte 58h X X X SLA+R will be transmitted then ACK will be transmitted SLA+W will be transmitted then logic will switched to master transmitter mode. Data byte will be received then NOT ACK will be returned. Data byte will be received then ACK will be returned. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data byte will be received then NOT ACK will be returned. Data byte will be received then ACK will be returned. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset.
2
Table 6.4. Status for Miscellaneous States
Application software response
To SSCON SSSTA SSSTO SSI SSAA
Status
Code
Status of the
I2C bus and
To/From SSDAT No SSDAT action No SSDAT action 0
Next action taken I2C hardware
(SSCS) F8h
I2C hardware No relevant state information available; SSI= 0. Bus error due to an illegal START or STOP condition. State 00h can also occur when interference causes I2C logic to enter an undefined state.
No SSCON action
Wait or proceed current transfer.
00h
1
0
X
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and SSSTO is reset.
MATRA MHS Rev. A (18 Dec. 96)
II. 6.9
TSC 80251G1
6.2. Registers
SSBR (S:92h) Synchronous Serial Bit Rate register
7 Bit Number 7-0 Reset value = 00h
6 Bit Mnemonic
5
4
3 Description
2
1
0
Synchronous Serial Bit Rate data Bit rate is given by the formula: Br= FOSC/(4(SSBR value+3)).
Figure 6.5. SSBR register SSCON (S:93h) Synchronous Serial Control register (read/write)
SSCR2 7 Bit Number 7 6 5 SSPE 6 Bit Mnemonic SSCR2 SSPE SSSTA SSSTA 5 SSST0 4 SSI 3 Description Synchronous Serial Control Rate bit 2 See Table 6.1. Synchronous Serial Peripheral Enable bit Set to enable the I2C interface. Synchronous Serial Start flag Clear not to send a START condition on the bus. Set to send a START condition on the bus. Synchronous Serial Stop flag Set to send a STOP condition on the bus. Synchronous Serial Interrupt flag Set by hardware when a serial interrupt is requested. Must be cleared by software to acknowledge interrupt. Synchronous Serial Assert Acknowledge flag Clear, in receiver mode, to force a not acknowledge (high level on SDA). Set, in receiver mode, to force an acknowledge (low level on SDA). This bit has no effect when in transmitter mode. Synchronous Serial Control Rate bit 1 See Table 6.1. Synchronous Serial Control Rate bit 0 See Table 6.1. SSAA 2 SSCR1 1 SSCR0 0
4 3
SSSTO SSI
2
SSAA
1 0
SSCR1 SSCR0
Reset value = 0000 0000b
Figure 6.6. SSCON register
II. 6.10
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
SSCS (S:94h) read Synchronous Serial Control and Status register
SSSC4 7 Bit Number 7 6 5 4 3 2 1 0 Reset value = F8h SSSC3 6 Bit Mnemonic SSSC4 SSSC3 SSSC2 SSSC1 SSSC0 0 0 0 SSSC2 5 SSSC1 4 SSSC0 3 Description Synchronous Serial Status Code bit 4 See Table 6.2. to Table 6.4. Synchronous Serial Status Code bit 3 See Table 6.2. to Table 6.4. Synchronous Serial Status Code bit 2 See Table 6.2. to Table 6.4. Synchronous Serial Status Code bit 1 See Table 6.2. to Table 6.4. Synchronous Serial Status Code bit 0 See Table 6.2. to Table 6.4. Always zero Always zero Always zero 0 2 0 1 0 0
2
Figure 6.7. SSCS register: read mode SSDAT (S:95h) Synchronous Serial Data register (read/write)
SD7 7 Bit Number 7 6 5 4 3 2 1 0 SD6 6 Bit Mnemonic SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Address bit 7 or Data bit 7. Address bit 6 or Data bit 6. Address bit 5 or Data bit 5. Address bit 4 or Data bit 4. Address bit 3 or Data bit 3. Address bit 2 or Data bit 2. Address bit 1 or Data bit 1. Address bit 0 (R/W) or Data bit 0. SD5 5 SD4 4 SD3 3 Description SD2 2 SD1 1 SD0 0
Reset value = 00h
Figure 6.8. SSDAT register
MATRA MHS Rev. A (18 Dec. 96)
II. 6.11
TSC 80251G1
SSCS (S:94h) write Synchronous Serial Control and Status register
SSBRS 7 Bit Number 7 - 6 Bit Mnemonic SSBRS - 5 - 4 - 3 Description Clock Source Selection bit (see Table 6.1. ) Clear to select bit rate controlled by SSCR0 to SSCR2. Set to select external bit rate generator. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Synchronous Serial Mode selection bit Clear to select I2C interface. - 2 - 1 SSM0D 0
6 5 4 3 2 1 0
- - - - - - SSMOD
Reset value = 0XXX XXX0b
Figure 6.9. SSCS register: write mode
II. 6.12
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
SSLC / Synchronous Peripheral Interface (mwire/SPI)
7.1. Introduction
The Synchronous Serial Link Controller (SSLC) provides the selection of one synchronous serial interface among the three most popular ones: D Inter-Integrated Circuit (I2C) interface. D mWire and Serial Peripheral Interface (SPI). When I2C is selected, I2C Interface is no longer available. This chapter describes the SPI. This synchronous interface allows several SPI microcontrollers or mWire and SPI-type peripherals to be interconnected on a bus. Figure 7.1. shows a typical SPI bus configuration using one TSC80251G1 master and many slaves. The bus is made of three wires connecting all the devices together: D Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a slave. It is driven by the master. D Master Input Slave Output (MISO): it is used to transfer data in series from a slave to the master. It is driven by the selected slave. D Serial Clock (SCK): it is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. Each slave is selected by one Slave Select pin (SS#). If there is only one slave, it may be continuously selected with SS# tied to a low level. Otherwise, the TSC80251G1 may select each device by software through port pins (Pn.x). Special care should be taken not to select two slaves at the same time to avoid bus conflicts.
Pn.z Pn.y Pn.x TSC80251G1 (Master) P1.5 P1.7 P1.6 MISO SCK MOSI SS#n SS#2 SS#1 SS Slave1 SS Slave2 SS SlaveN
2
MISO SCK MOSI
MISO SCK MOSI
MISO SCK MOSI
Figure 7.1. Typical SPI Bus Configuration using TSC80251G1
MATRA MHS Rev. A (18 Dec. 96)
II. 7.1
TSC 80251G1
7.2. Description
Figure 7.2. highlights the dedicated harware. MISO is connected to the input of an 8-bit shift register (Serial Synchronous Data, SSDAT) the output of which is connected to MOSI output. A bit rate generator provides the clock of the shift register and SCK accordingly, depending on the chosen transmission clock policy (See Interface Configuration below). Additional logic is also included to provide control and status information.
MOSI/P1.7 SSDAT MISO/P1.5 8-bit shift Register Control Logic SSBSY SSPE SSI SSCS.4 SSCON.6SSCON.3 4 1 0 00 01 10 11 FOSC/2 FOSC/3 FOSC /(24 (256 - TH1)) bit rate generator SSCPOL SSCPHA SSBRS SSCR1 SSCR0 SSCON.5 SSCON.4 SSCS.7 SSCS.1 SSCS.0 (SSBR+1) FOSC Serial Synchronous Interrupt request
SCK/P1.6
Figure 7.2. Wire and Serial Peripheral Interface The SPI configuration is made through three registers: D The Synchronous Serial Control register (SSCON) D The Synchronous Serial Control and Status register (SSCS) D The Synchronous Serial Bit Rate register (SSBR) Once the SPI is configured, the data exchange is made using: D SSDAT D SSCS D SSCON
II. 7.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
7.2.1. Interface Configuration
To avoid unexpected behavior, the Synchronous Serial Peripheral Enable bit (SSPE in SSCON register) must not been set when configuring the SPI. This bit may be cleared at any time and disable the SSLC whatever its configuration, then all the SPI outputs are disabled. Once the SPI has been configured (See below), SSPE may be set to enable the SPI operation, then its outputs are enabled and set according to the configuration. The Synchronous Serial Mode bit (SMOD in SSCS) must be set first to select the mwire/SPI mode. Then the rest of the configuration may be done. The Synchronous Serial Bit Rate Select bit (SSBRS in SSCS ) allows to choose between two bit rate generation modes, see Table 7.1. and Figure 7.2. . When SSBRS is set, the bit rate is programmed according to the Synchronous Serial Bit Rate register 8-bit value (SSBR). When SSBRS is cleared, the bit rate is selected according to the Synchronous Serial Control Rate bits (SSCR1 and SSCR0 in SSCON). Table 7.1. Serial Clock Rates
SSBRS 0 0 0 0 1 SSCR1 0 0 1 1 X SSCR0 0 1 0 1 X Bit frequency (kHz) FOSC = 12 MHz 3000 1500 1000 0.49 < . < 125 11.7 < . < 3000 FOSC = 16 MHz 4000 2000 1333.33 0.65 < . < 167 15.6 < . < 4000 FOSC divided by 4 8 12 96 . (256 - reload value Timer 1) (reload value range: 0-255 in mode 2) 4 . (SSBR value + 1)
2
The Synchronous Serial Polarity bit (SSPOL in SSCON) defines the default SCK line level in idle state (Note: when the peripheral is disabled, the default state is one). Then the Synchronous Serial Phase bit (SSPHA in SSCON) defines the edges on which the MISO input and the MOSI respectively output are sampled and shifted out respectively(See Figure 7.3. ).
MATRA MHS Rev. A (18 Dec. 96)
II. 7.3
TSC 80251G1
SCK cycle number (For reference) SSPE (Internal by soft) SCK (SSCPOL =0) 1 2 3 4 5 6 7 8
SCK (SSCPOL =1 )
MOSI (From Master) MISO (From Slave) SS (To Slave by soft) Capture
MSB
Bit6 Bit6
Bit5 Bit5
Bit4 Bit4
Bit3 Bit3
Bit2 Bit2
Bit1 Bit1
LSB LSB
MSB
a/ SSCPHA = 0 SCK cycle number (For reference) SSPE (Internal by soft) SCK (SSCPOL =0) 1 2 3 4 5 6 7 8
SCK (SSCPOL =1 )
MOSI (From Master) MISO (From Slave) SS (To Slave by soft) Capture
MSB
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
LSB
MSB
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
b/ SSCPHA = 1
Figure 7.3. Data Transmission (a/ SSCPHA = 0, b/ SSCPHA = 1) When the peripheral is in SPI mode, SSBR, SSCON, SSCS and SSDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken not to change the SSPHA and SSPOL bits once the SSPE bit has been set. Note: the Synchronous Serial Busy bit (SSBSY in SSCS) may be cleared to prevent any spurious data transmission when SSPE is set.
II. 7.4
MATRA MHS Rev. A (18 Dec. 96)
CCCC CCCC
LSB
CCC CCC
TSC 80251G1
7.2.2. Data Exchange
There are two possible policies to exchange data: D polling D interrupts To exchange data in polling mode: 1. 2. Loop: 3. 4. 5. 6. 7. 8. 9. 10. Ensure the SSLC interrupts are disabled (See IS section). Check SSBSY is not set in SSCS Assert SS# (as required) Clear the Synchronous Serial Interrupt bit (SSI) in SSCON Write the transmit data to SSDAT (or jump to next step if there is no data to transmit) Set SSBSY to start exchange Read SSBSY in SSCS until it has been cleared by hardware Read the received data in SSDAT (or jump to next step if there is no data to receive) Deassert SS# (as required) Jump to step 3 if there are more data to transmit or receive, otherwise exit
2
This policy provides the fastest effective transmission and is well adapted when communicating at high speed with other Microcontrollers. However, the procedure may then be interrupted at any time by higher priority tasks. To exchange data in interrupt mode: Main program: 1. Check SSBSY is not set in SSCS 2. Clear SSI 3. Ensure the SSLC interrupt service routine is well initialized and enable the SSLC interrupts (See IS section) 4. Assert SS# (as required) 5. Write the transmit data in SSDAT (or jump to next step if there is no data to transmit) 6. Set SSBSY to start exchange 7. Wait
MATRA MHS Rev. A (18 Dec. 96)
II. 7.5
TSC 80251G1
Interrupt service routine: 1. Deassert SS# (as required) 2. Read the received data in SSDAT (or jump to next step if there is no data to receive) 3. Write the transmit data to SSDAT (or jump to next step if there is no data to transmit) 4. Assert SS# (as required) 5. Clear SSI 6. Set SSBSY to continue (or jump to next step if exchange is completed) 7. Return from interrupt service routine This policy may be effective when communicating with slow devices. Then it may be executed at a high priority level preventing burst activity on the SPI bus. When the SPI is configured, SSBR, SSCON, SSCS and SSDAT may be read at any time while a transmission is on-going (i.e. SSBSY is set). Conversely, SSBR, SSCON and SSCS may be written at any time while a transmission is on-going. However, special care should be taken when writing to them: D Do not change SSBR if SSBRS is set D Do not change SSCR0 or SSCR1 if SSBRS is cleared D Do not change SSPHA or SSPOL D Clearing SSPE would immediately disable the peripheral D Do not change SSMOD or SSBRS D Clearing SSBSY would immediately complete the data shifting Furthermore, as there is no write protection of the shift register, SSDAT should not be written while a transmission is on-going.
II. 7.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
7.3. Registers
SSBR (S:92h) Synchronous Serial Bit Rate register (8-bit)
7 Bit Number 7-0 Reset Value = 00h
6 Bit Mnemonic
5
4
3 Description
2
1
0
Bit rate is given by the formula: Br = FOSC/(4.(SSBR value + 1))
Figure 7.4. SSBR Register SSCON (S:93h) Synchronous Serial Control register (read/write)
- 7 Bit Number 7 6 SSPE 6 SSCPOL 5 SSCPHA 4 SSI 3 - 2 SSCR1 1 SSCR0 0
2
5
4
3
2 1 0
Bit Description Mnemonic - Reserved The value read from this bit is indeterminate. Do not set this bit. SSPE Synchronous Serial Peripheral Enable bit Clear to disable the mWire/SPI interface. Set to enable the mWire/SPI interface. SSCPOL Synchronous Serial Clock Polarity bit Clear to have the clock output set to 0 in iddle state. Set to have the clock output set to 1 in iddle state. Note: when the peripheral is disabled, the clock output is pulled high not to conflict with other functions on the port. SSCPHA Synchronous Serial Clock Phase bit Clear to have the data sampled when the clock leave the iddle state (see SSCPOL) Set to have the data sampled when the clock return to the iddle state (see SSCPOL) SSI Synchronous Serial Interrupt flag Set by hardware when an 8-bit shift is completed. Must be cleared by software to acknowledge interrupt. - Reserved The value read from this bit is indeterminate. Do not set this bit. SSCR1 Synchronous Serial Control Rate bit 1 See Table 7.1. SSCR0 Synchronous Serial Control Rate bit 0 See Table 7.1.
Reset Value = X000 0000b
Figure 7.5. SSCON Register
MATRA MHS Rev. A (18 Dec. 96)
II. 7.7
TSC 80251G1
SSCS (S:94h) Synchronous Serial Control and Status register (read/write)
SSBRS 7 Bit Number 7 - 6 Bit Mnemonic SSBRS - 5 SSBSY 4 - 3 Description Synchronous Serial Bit Rate Selection bit Clear to select the bit rate controlled by SSCR1 and SSCR0 (See Table 7.1. ). Set to select the programmable bit rate generator (See Table 7.1. ). Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Synchronous Serial Busy bit Cleared by hardware when one byte shift is completed (then SSI is set) Clear to abort the transmission before it is completed (then SSI is not set). Set to start the transmission. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Synchronous Serial Mode selection bit Set to select the mwire/SPI mode. - 2 - 1 SSMOD 0
6 5 4
- - SSBSY
3 2 1 0
- - - SSMOD
Reset Value = 0XXX XXX0b
Figure 7.6. SSCS Register: write mode SSDAT (S:95h) Synchronous Serial Data register (8-bit read/write)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Figure 7.7. SSDAT Register
II. 7.8
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Hardware Watchdog Timer
8.1. Introduction
The TSC80251G1 derivatives contain a dedicated hardware Watchdog Timer (WDT) that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software malfunctions. The WDT described in this chapter is not associated with the PCA Watchdog Timer (See "Event and Waveform Controller" chapter), which may be disabled in software and is less reliable.
8.2. Description
The WDT is a 14-bit counter that counts peripheral cycles, i.e. the system clock divided by twelve (FOSC/12). The Hardware Watchdog Timer register (WDTRST, see Figure 8.1. ) provides control access to the WDT. Two operations control the WDT: D Chip reset clears and disables the WDT. D Writing a specific two-byte sequence to WDTRST register clears and enables the WDT. If it is not cleared, the WDT overflows on count 3FFFh +1 and forces a chip reset. With FOSC = 16 Mhz, a peripheral cycle is 750 ns and the WDT overflows in 750 16384 = 12.288 ms. The WDTRST is a write-only register. Attempts to read it return FFh. The WDT itself is not read or write accessible. The WDT does not drive the external RST pin.
2
8.3. Using the Hardware WDT
To recover from software malfunctions, the user should control the WDT as follows: D Following chip reset, write the two-byte sequence 1Eh-E1h to WDTRST register to enable the WDT. Then the WDT begins counting from 0. D Repeatedly for the duration of program execution, write the two-byte sequence 1Eh-E1h to WDTRST register to clear and enable the WDT before it overflows. The WDT starts over at 0. If the WDT overflows, it initiates a chip reset. Chip reset clears the WDT and disables it.
8.4. Hardware WDT during Idle and Power-Down Modes
Operation of the WDT during power reduction modes deserves special attention. The WDT continues to count while the TSC80251G1 is in Idle mode. This means that the user must dedicate some internal or external hardware to service the WDT during Idle mode. One approach is to use a peripheral Timer to generate an interrupt request when the Timer overflows. The interrupt service routine then clears the WDT, reloads the peripheral Timer for the next service period and puts the TSC80251G1 back into Idle mode.
MATRA MHS Rev. A (18 Dec. 96)
II. 8.1
TSC 80251G1
The Power-Down mode stops all phase clocks. This causes the WDT to stop counting and to hold its count. The WDT resumes counting from where it left off if the Power-Down mode is terminated by INT0# or INT1#. To ensure that the WDT does not overflow shortly after exiting the Power-Down mode, clear the WDT just before entering Power-down mode. The WDT is cleared and disabled if the Power-Down mode is terminated by a reset.
8.5. Register
WDTRST (S:A6h) Hardware Watchdog Timer Reset register (8-bit write-only)
7 6 Reset Value = 1111 1111b
5
4
3
2
1
0
Figure 8.1. WDTRST Register
II. 8.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Power Monitoring and Management
9.1. Introduction
The power monitoring and management can be used to supervise the Power Supply (VDD) and to start up properly when the TSC80251G1 is powered up. It consists of the features listed below and explained hereafter: D Power-On reset D Power-Fail reset D Power-Off flag D Clock prescaler D Idle mode D Power-Down mode All these features are controlled by four 8-bit registers, the Power Management register (POWM), the Power Filter register (PFILT), the Power Control register (PCON) and the Clock Reload register (CKRL) detailed at the end of this chapter.
2
9.2. Power-On Reset
When the power supply is under VRET, the digital parts of the circuit are not working properly. Then the I/O ports are controlled by the external Reset pin (RST). In order to keep them in a predictable state (See Table 9.1. ), RST pin must either be driven to a high level for the power rise duration or tied to VDD through an external capacitor. However, the internal oscillator is immediately enabled. When the power supply rises above VRET and as long as it stays below VRST+, the Power-On Flag (POF, see paragraph 9.4.) and the Reset Detection control bit (RSTD, see Figure 9.6. ) are set and the internal reset begins. When the power supply rises above VRST+, the internal reset completes after both RST pin has gone low and 64 clock periods on XTAL1 have occured. This ensures the external oscillator has stabilized. If an external capacitor is connected to RST, it is charged through an internal pull-down resistor RRST which determines the minimal reset period according to the capacitor value. Reducing VDD quickly to 0 V causes the RST pin voltage to momentarily fall below 0 V. This voltage is internally limited and does not harm the device. Table 9.1. Pin Conditions in Special Operating Modes
Mode Reset Idle Idle Program Memory Don't care Internal External ALE pin Weak High 1 1 0 0 PSEN# pin Weak High 1 1 0 0 Port 0 pin Floating Data Floating Data Floating Port 1 pins Weak High Data Data Data Data Port 2 pins Weak High Data Data Data Data Port 3 pins Weak High Data Data Data Data
Power-Down Internal Power-Down External
MATRA MHS Rev. A (18 Dec. 96)
II. 9.1
TSC 80251G1
9.3. Power-Fail Reset
The Power-Fail detector is enabled by RSTD bit in POWM register. Then the power supply is continuously monitored and an internal reset is generated if VDD goes below VRST- for at least 2xPFILTxTOSC (Note: this internal reset is not propagated outside). The Power Filter register (PFILT, see Figure 9.5. ) must be programmed by the user with an 8-bit value depending of the time constant he wants. If the power supply rises again over VRST+, the Power-On Flag (POF, see paragraph 9.4.) is set and the internal reset completes after 64 oscillator clock periods. If RSTD is cleared, the power supply monitoring is disabled. This is particularly usefull to save power in Power-Down mode. Then VDD may be reduced to VRET without generating a reset or losing data. In this case, the circuit behavior is unpredictable unless an external reset is applied when VDD goes below VRET.
9.4. Power-Off Flag
When the power is turned off or fails, the data retention is not guaranteed. A Power-Off Flag (POF, see Figure 9.4. ) allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail. This is a cold reset. A warm reset is an external or a watchdog reset without power failure, hence which preserves the internal memory content and POF. To use POF, test and clear this bit just after reset. Then it will be set only after a cold reset.
9.5. Clock Prescaler
In order to optimize the power consumption and the execution time needed for a specific task, an internal clock prescaler feature has been implemented to program the system clock frequency. It is possible to work at full speed for all tasks requiring quick response time at low frequency for background tasks which do not need CPU power but power consumption optimizing. Figure 9.1. shows the diagram of the on-chip oscillator where the clock programming block clearly appears. The CPU clock can be programmed via 8-bit CKRL register and by setting CKSRC bit in POWM register: F OSC + F XTAL 2(CKRL ) 1)
II. 9.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
XTAL1 8-bit Divider FXTAL CKSRC XTAL2 CKSRC CKRL Clock Prescaler OSC output (FOSC) CPU
PD PCON reg
IDL PCON reg
Figure 9.1. Block Diagram of the On-Chip Oscillator In all this document, the on-chip oscillator is used to be symbolized by Figure 8.7. Please notice that all the peripherals share the same clock. Special care should be taken when changing it to prevent any peripheral operating failure.
OSC OSC output
2
Figure 9.2. Symbolic of the On-Chip Oscillator
9.6. Idle Mode
Idle mode is a power reduction mode that reduces the power consumption to about 40% of the typical running power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked (See Figure 9.1. ). The CPU status before entering Idle mode is preserved, i.e., the program counter, program status word register, and register file retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins depends upon the location of the program memory: D Internal program memory: The ALE and PSEN# pins are pulled high the Ports 0, 1, 2 and 3 pins are reading data (See Table 9.1. ). D External program memory: The ALE and PSEN# pins are pulled high; the Port 0 pins are floating and the Ports 1, 2 and 3 pins are reading data (See Table 9.1. ).
9.6.1. Entering Idle Mode
To enter Idle mode, set IDL bit in PCON register. The TSC80251G1 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
MATRA MHS Rev. A (18 Dec. 96)
II. 9.3
TSC 80251G1
Caution: If IDL bit and PD bit are set simultaneously, the TSC80251G1 enters Power-Down mode. Then it does not go in Idle mode when exiting Power-Down mode.
9.6.2. Exiting Idle Mode
There are two ways to exit Idle mode: D Generate an enabled interrupt Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. D Reset the chip A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the TSC80251G1 and vectors the CPU to address FF:0000h.
Note:
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
9.6.3. Recovering from Idle Mode
To enable the recovering from Idle mode, set RPD bit in PCON register (beware that this bit sets also the recovering from Power-Down mode, see paragraph 9.7.3.). Then a disabled external interrupt clears IDL bit in PCON register which restores the clock to CPU. Execution continues with the instruction immediately following the instruction that activated Idle mode.
Notes:
D The external interrupt used to recover from Idle mode must be configured as level sensitive and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. D When RPD bit in PCON register is set, it is still possible to exit Idle mode using an enabled interrupt (See paragraph 9.6.2.).
9.7. Power-Down Mode
The Power-Down mode places the TSC80251G1 in a very low power state. Power-Down mode stops the oscillator and freezes all clock at known states (See Figure 9.1. ). The CPU status prior to entering Power-Down mode is preserved, i.e., the program counter, program status word register, and register file retain their data for the duration of Power-Down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins depends on the location of the program memory:
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MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
D Internal program memory: The ALE and PSEN# pins are pulled low, the Ports 0, 1, 2 and 3 pins are reading data (See Table 9.1. ). D External program memory: The ALE and PSEN# pins are pulled low; the Port 0 pins are floating and the Ports 1, 2 and 3 pins are reading data (See Table 9.1. ).
Note:
VDD may be reduced to as low as 2 V during Power-Down mode to further reduce power dissipation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.
9.7.1. Entering Power-Down Mode
To enter Power-Down mode, set PD bit in PCON register. The TSC80251G1 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.
9.7.2. Exiting Power-Down Mode
Caution: If VDD was reduced during the Power-Down mode, do not exit Power-Down mode until VDD is restored to the normal operating level.
2
There are two ways to exit the Power-Down mode: D Generate an enabled external interrupt. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-Down mode.
Note:
To enable an external interrupt, set EX0 and/or EX1 bit(s) in IE register. The external interrupt used to exit Power-Down mode must be configured as level sensitive and must be assigned the highest priority. In addition, the duration of the interrupt must be of sufficient length to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.
D Generate a reset. A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-Down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the TSC80251G1 and vectors the CPU to address FF:0000h.
Note:
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM.
MATRA MHS Rev. A (18 Dec. 96)
II. 9.5
TSC 80251G1
9.7.3. Recovering from Power-Down Mode
To enable the recovering from Power-Down mode, set RPD bit in PCON register (beware that this bit sets also the recovering from Idle mode, see paragraph 9.6.3.). Then a disabled external interrupt clears PD bit in PCON register which starts the oscillator and restores the clock to CPU and peripherals. Execution continues with the instruction immediately following the instruction that activated Power-Down mode.
Notes:
D The external interrupt used to recover from Power-Down mode must be configured as level sensitive and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. D When RPD bit in PCON register is set, it is still possible to exit Power-Down mode using an enabled external interrupt (See paragraph 9.7.2.).
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MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
9.8. Registers
CKRL (S:8Eh) Clock Reload register
7 6 Reset Value = 00h 5 4 3 2 1 0
Figure 9.3. CKRL Register PCON (S:87h) Power Configuration register
SMOD1 7 Bit Number 7 SMOD0 6 Bit Mnemonic SMOD1 RPD 5 POF 4 GF1 3 GF0 2 PD 1 IDL 0
Description Double Baud Rate bit Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register. SCON Select bit When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit. When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register. Recover from Idle/Power-Down bit Clear to disable the Recover from Idle and Power-Down modes feature. Set to enable the Recover from Idle and Power-Down modes feature. Power-Off flag Set by hardware when VDD rises above 3 V to indicate that the Power Supply has been off or VDD had fallen below 3 V and that on-chip volatile memory is indeterminated. Must be cleared by software. General Purpose flag 1 One use is to indicate wether an interrupt occured during normal operation or during Idle mode. General Purpose flag 0 One use is to indicate wether an interrupt occured during normal operation or during Idle mode. Power-Down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
2
6
SMOD0
5
RPD
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 0000 0000b
Figure 9.4. PCON Register
MATRA MHS Rev. A (18 Dec. 96)
II. 9.7
TSC 80251G1
PFILT (S:86h) Power Filter register
7 Reset Value = XXh 6 5 4 3 2 1 0
Figure 9.5. PFILT Register POWM (S:8Fh) Power Management register
CKSRC 7 Bit Number 7 - 6 Bit Mnemonic CKSRC - 5 - 4 RSTD 3 - 2 - 1 - 0
Description Clock Source bit Cleared by hardware after a Power-Up. In that case: FOSC = FXTAL. F XTAL F OSC + 2(CKRL ) 1) Set to enable the clock. In that case: The CPU frequency is FOSC/2. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Detector Disable bit Clear to enable the Reset detector. Set to disable the Reset detector. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit.
6 5 4 3
- - - RSTD
2 1 0
- - -
Reset Value = 0XXX 0XXX
Figure 9.6. POWM Register
II. 9.8
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Interrupt System
10.1. Introduction
The TSC80251G1, like other control-oriented computer architectures, employs a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal TSC80251G1 activity (e.g., Timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., Serial Port communication). In all cases, interrupt operation is programmed by the system designer, who determines priority of interrupt service relative to normal code execution and other interrupt service routines. Nine of the eleven interrupts are enabled or disabled by the system designer and may be manipulated dynamically. A typical interrupt event chain occurs as follows: D An internal or external device initiates an interrupt-request signal. D This signal, connected to an input pin and periodically sampled by the TSC80251G1, latches the event into a flag buffer. D The priority of the flag is compared to the priority of other interrupts by the interrupt handler. A high priority causes the handler to set an interrupt flag. D This signals the instruction execution unit to execute a context switch. This context switch breaks the current flow of instruction sequences. The execution unit completes the current instruction prior to a save of the program counter (PC) and reloads the PC with the start address of a software service routine. D The software service routine executes assigned tasks and as a final activity performs a RETI (return from interrupt) instruction. This instruction signals completion of the interrupt, resets the interrupt-in-progress priority and reloads the program counter. Program operation then continues from the original point of interruption. Table 10.1. Interrupt System Signals
Mnemonic INT0# Type I Description External Interrupt 0 This input sets IE0 bit in TCON register. If IT0 bit in TCON register is set, IE0 bit is controlled by a negative edge trigger on INT0#. If IT0 bit in TCON register is cleared, IE0 bit is controlled by a low level trigger on INT0#. External Interrupt 1 This input sets IE1 bit in TCON register. If IT1 bit in TCON register is set, IE1 bit is controlled by a negative edge trigger on INT1#. If IT1 bit in TCON register is cleared, IE1 bit is controlled by a low level trigger on INT1#. Non Maskable Input Multiplexed with P3.2
2
INT1#
I
P3.3
NMI
I
-
MATRA MHS Rev. A (18 Dec. 96)
II. 10.1
TSC 80251G1
Table 10.2. Interrupt System SFRs
Mnemonic IE0 Description Interrupt Enable register Used to enable and disable the nine lowest programmable interrupts. The reset value of this register is zero (interrupts disabled). Interrupt Enable register Used to enable and disable the nine highest programmable interrupts. The reset value of this register is zero (interrupts disabled). Interrupt Priority High register 0 Establishes relative four-level priority for the nine lowest programmable interrupts. Used in conjunction with IPL0. Interrupt Priority High register 1 Establishes relative four-level priority for the nine highest programmable interrupts. Used in conjunction with IPL1. Interrupt Priority Low register 0 Establishes relative four-level priority for the nine lowest programmable interrupts. Used in conjunction with IPH0. Interrupt Priority Low register 1 Establishes relative four-level priority for the nine lowest programmable interrupts. Used in conjunction with IPH1. Address S:A8h
IE1
S:B1h
IPH0
S:B7h
IPH1
S:B3h
IPL0
S:B8h
IPL1
S:B2h
The TSC80251G1 has one software interrupt: TRAP, NMI and nine peripheral interrupt sources: two external (INT0# and INT1#), one for Timer 0, one for Timer 1, one for Timer 2, one for Serial Port, one for Event and Waveform Controller, one for Synchronous Serial Link Controller, one for Keyboard.
Note: The Non Maskable Interrupt input is the second highest priority interrupt after the TRAP. It is always enabled and can not be disabled by software like others interrupts. NMI is active when a high level is applied on its input during a minimum of 24 oscillators clock periods.
Six interrupt registers are used to control the interrupt system. Two 8-bit registers are used to enable separately the interrupt sources: IE0 and IE1 (See Figure 10.3. and Figure 10.4. ). Four 8-bit registers are used to establish the priority level of the nine sources: IPL0, IPH0, IPL1 and IPH1 (See Figure 10.5. to Figure 10.8. ).
10.2. Interrupt System Priorities
Each of the nine interrupt sources on the TSC80251G1 may be individually programmed to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High registers (IPH0 or IPH1, see Figure 10.6. and Figure 10.8. ) and one in the Interrupt Priority Low registers (IPL0 or IPL1, see Figure 10.5. and Figure 10.7. ) This provides each interrupt source four possible priority levels select bits (See Table 10.3. ).
II. 10.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Table 10.3. Level of Priority
IPHxx 0 0 1 1 IPLxx 0 1 0 1 0 1 2 3 Highest Priority Level Lowest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal priority interrupts (i.e., sampled within the same four state interrupt cycle) is determined by a hardware priority-within-level resolver (See Table 10.4. ). Table 10.4. Interrupt Priority within Level
Interrupt Name TRAP Priority Number 1 Highest Priority Not interruptible 2 3 4 5 6 7 8 9 10 - - - - 15 16 Lowest Priority Interrupt Address Vectors FF:007Bh Interrupt request flag cleared by hardware (H) or by software (S) -
2
NMI INT0# Timer 0 INT1# Timer 1 Serial Port Timer 2 EWC Keyboard Reserved Reserved Reserved Reserved SSLC Reserved
FF:003Bh FF:0003h FF:000Bh FF:0013h FF:001Bh FF:0023h FF:002Bh FF:0033h FF:0043h FF:004Bh FF:0053h FF:005Bh FF:0063h FF:006Bh FF:0073h
- H if edge, S if level H H if edge, S if level H S S H S - - - S -
MATRA MHS Rev. A (18 Dec. 96)
II. 10.3
TSC 80251G1
10.3. External Interrupts
External interrupts INT0# and INT1# (INTn#, n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register. If ITn = 0, INTn# is triggered by a low level at the pin. If ITn = 1, INTn# is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IE0 register. Events on INTn# set the interrupt request flag IEn in TCON register. A request bit is cleared by hardware vectors to service routines only if the interrupt is edge triggered. If the interrupt is level-triggered, the interrupt service routine must clear the request bit. External hardware must deassert INTn# before the service routine completes, or an additional interrupt is requested. External interrupt pins must be deasserted for at least four state times prior to a request. External interrupt pins are sampled once every four state times (a frame length of 500 ns at 16 MHz). A level-triggered interrupt pin held low or high for five-state time period guarantees detection. Edge-triggered external interrupts must hold the request pin low for at least five state times. This ensures edge recognition and sets interrupt request bit EXn. The CPU clears EXn automatically during service routine fetch cycles for edge-triggered interrupts.
Edge-Triggered interrupt 5 states 5 states 4 states Level-Triggered Interrupt 5 states 4 states
4 states
Figure 10.1. Minimum Pulse Timings.
10.4. Keyboard Interface
Port 1 as some on-chip provisions to interface more easily a keyboard matrix. Each Port line may be connected to a Keyboard output and has the possibility to detect a programmable level. Port lines are sampled once every state, then a level must maintained during two states to be recognized (a frame length of 250 ns at 16 MHz). D The level to detect (high or low) on a Port line is selected by the corresponding Port 1 Level Selection bit in P1LS register (See Figure 10.11. ). D The detection of the programmed level sets the corresponding flag in P1F register (See Figure 10.9. ).
II. 10.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
D If the corresponding Port 1 Interrupt Enable bit in P1IE register (See Figure 10.10. ) is set, the flag setting generates the Keyboard interrupt request. But it must be enabled by the KBIE bit in IE1 register (See Figure 10.4. ). D The way to exit interrupt service routine is to wait for a level change on the corresponding Port line or to program an interrupt request on the complemented level. Then, the corresponding flag must be cleared by software.
Note: The keyboard interface is normally used for level detection, but it may be used in other ways since any pulse is stored in P1F. 0 detected P1.x 1 detected P1LS.x P1IE.x P1F.x Keyboard Interrupt Request
Figure 10.2. Keyboard Interface Interrupt Structure
2
10.5. Registers
IE0 (S:A8h) Interrupt Enable 0 register
EA 7 Bit Number 7 EC 6 Bit Mnemonic EA ET2 5 ES 4 ET1 3 EX1 2 Description Global Interrupt Enable bit Clear to disable all interrupts that are individually disabled by bits 6:0 in IE0 register and bits 5 and 0 in IE1 register, except the TRAP register which is always enabled. Set to enable all interrupts that are individually enabled by bits 6:0 in IE0 register and bits 5 and 0 in IE1 register. Enable Counter Interrupt bit Clear to disable EWC interrupt. Set to enable EWC interrupt. Enable Timer 2 Interrupt bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. Enable Serial Port Interrupt bit Clear to disable Serial Port interrupt. Set to enable Serial Port interrupt. ET0 1 EX0 0
6
EC
5
ET2
4
ES
MATRA MHS Rev. A (18 Dec. 96)
II. 10.5
TSC 80251G1
Bit Number 3 Bit Mnemonic ET1 Description Enable Timer 1 Interrupt bit Clear to disable Timer 1 overflow interrupt. Set to enable Timer 1 overflow interrupt. Enable External 1 Interrupt bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Enable Timer 0 Interrupt bit Clear to disable Timer 0 overflow interrupt. Set to enable Timer 0 overflow interrupt. Enable External 0 Interrupt bit Clear to disable External interrupt 0. Set to enable External interrupt 0.
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b
Figure 10.3. IE0 Register
II. 10.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
IE1 (S:B1h) Interrupt Enable 1 register
- 7 Bit Number 7 6 5 - 6 Bit Mnemonic - - SSIE SSIE 5 - 4 - 3 - 2 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SSLC Interrupt Enable bit Clear to disable the SSLC interrupt. Set to enable the SSLC interrupt. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Enable bit Clear to disable the Keyboard interrupt. Set to enable the Keyboard interrupt. - 1 KBIE 0
4 3 2 1 0
- - - - KBIE
2
Reset Value = XX0X XXX0b
Figure 10.4. IE1 Register
MATRA MHS Rev. A (18 Dec. 96)
II. 10.7
TSC 80251G1
IPH0 (S:B7h) Interrupt Priority High 0 register
- 7 Bit Number 7 6 IPHC 6 Bit Mnemonic - IPHC IPHT2 5 IPHS 4 IPHT1 3 IPHX1 2 IPHT0 1 IPHX0 0
Description Reserved The value read from this bit is indeterminate. Do not set this bit EWC Counter Interrupt Priority level most significant bit IPHC IPLC Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority Timer Interrupt Priority level most significant bit IPHT2 IPLT2 Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority Serial Port Interrupt Priority level most significant bit IPHS IPLS Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority Timer 1 Interrupt Priority level most significant bit IPHT1 IPLT1 Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority External Interrupt 1 Priority level most significant bit IPHX1 IPLX1 Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority Timer 0 Interrupt Priority level most significant bit IPHT0 IPLT0 Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority External Interrupt 0 Priority level most significant bit IPHX0 IPLX0 Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority
5
IPHT2
4
IPHS
3
IPHT1
2
IPHX1
1
IPHT0
0
IPHX0
Reset Value = X000 0000b
Figure 10.5. IPH0 Register
II. 10.8
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
IPH1 (S:B1h) Interrupt Priority High 1 register
- 7 Bit Number 7 6 5 - 6 Bit Mnemonic - - IPHSS IPHSS 5 - 4 - 3 - 2 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SSLC Interrupt Priority level most significant bit IPHSSLC IPLSSLC Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority level most significant bit IPHPKB IPLKB Priority level 0 0 0 Lowest priority 0 1 1 1 0 2 1 1 3 Highest priority - 1 IPHKB 0
4 3 2 1 0
- - - - IPHKB
2
Reset Value = XX0X XXX0b
Figure 10.6. IPH1 Register
MATRA MHS Rev. A (18 Dec. 96)
II. 10.9
TSC 80251G1
IPL0 (S:B8h) Interrupt Priority Low 0 register
- 7 Bit Number 7 6 5 4 3 2 1 0 IPLC 6 Bit Mnemonic - IPLC IPLT2 IPLS IPLT1 IPLX1 IPLT0 IPLX0 IPLT2 5 IPLS 4 IPLT1 3 IPLX1 2 Description Reserved The value read from this bit is indeterminate. Do not set this bit. EWC Counter Interrupt Priority level less significant bit Refer to IPHC for priority level. Timer 2 Interrupt Priority level less significant bit Refer to IPHADC for priority level. Serial Port Interrupt Priority level less significant bit Refer to IPHS for priority level. Timer 1 Interrupt Priority level less significant bit Refer to IPHT1 for priority level. External Interrupt 1 Priority level less significant bit Refer to IPHX1 for priority level. Timer 0 Interrupt Priority level less significant bit Refer to IPHT0 for priority level. External Interrupt 0 Priority level less significant bit Refer to IPHX0 for priority level. IPLT0 1 IPLX0 0
Reset Value = X000 0000b
Figure 10.7. IPL0 Register
II. 10.10
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
IPL1 (S:B2h) Interrupt Priority Low 1 register
- 7 Bit Number 7 6 5 4 3 2 1 0 - 6 Bit Mnemonic - - IPLSS - - - - IPLKB IPLSS 5 - 4 - 3 - 2 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SSLC Interrupt Priority level less significant bit Refer to IPHSSLC for priority level. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority level less significant bit. Refer to IPHPMU for priority level. - 1 IPLKB 0
2
Reset Value = XX0X XXX0b
Figure 10.8. IPL1 Register
MATRA MHS Rev. A (18 Dec. 96)
II. 10.11
TSC 80251G1
P1F (S:9Eh) Port 1 Flag register
P1F.7 7 Bit Number 7 P1F.6 6 Bit Mnemonic P1F.7 P1F.5 5 P1F.4 4 P1F.3 3 Description Port 1 line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.7 bit in P1IE register is set. Must be cleared by software. Port 1 line 6 flag Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.6 bit in P1IE register is set. Must be cleared by software. Port 1 line 5 flag Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.5 bit in P1IE register is set. Must be cleared by software. Port 1 line 4 flag Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.4 bit in P1IE register is set. Must be cleared by software. Port 1 line 3 flag Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.3 bit in P1IE register is set. Must be cleared by software. Port 1 line 2 flag Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.2 bit in P1IE register is set. Must be cleared by software. Port 1 line 1 flag Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.1 bit in P1IE register is set. Must be cleared by software. Port 1 line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the P1IE.0 bit in P1IE register is set. Must be cleared by software. P1F.2 2 P1F.1 1 P1F.0 0
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
6 P1F.6 5 P1F.5 4 P1F.4 3 P1F.3 2 P1F.2 1 P1F.1 0 P1F.0 Reset Value = 0000 0000b
Figure 10.9. P1F Register
II. 10.12
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
P1IE (S:9Dh) Port 1 Interrupt Enable register
P1IE.7 7 Bit Number 7 P1IE.6 6 Bit Mnemonic P1IE.7 P1IE.5 5 P1IE.4 4 P1IE.3 3 Description Port 1 line 7 Interrupt Enable bit Clear to disable P1F.7 bit in P1F register to generate an interrupt request. Set to enable P1F.7 bit in P1F register to generate an interrupt request. Port 1 line 6 Interrupt Enable bit Clear to disable P1F.6 bit in P1F register to generate an interrupt request. Set to enable P1F.6 bit in P1F register to generate an interrupt request. Port 1 line 5 Interrupt Enable bit Clear to disable P1F.5 bit in P1F register to generate an interrupt request. Set to enable P1F.5 bit in P1F register to generate an interrupt request. Port 1 line 4 Interrupt Enable bit Clear to disable P1F.4 bit in P1F register to generate an interrupt request. Set to enable P1F.4 bit in P1F register to generate an interrupt request. Port 1 line 3 Interrupt Enable bit Clear to disable P1F.3 bit in P1F register to generate an interrupt request. Set to enable P1F.3 bit in P1F register to generate an interrupt request. Port 1 line 2 Interrupt Enable bit Clear to disable P1F.2 bit in P1F register to generate an interrupt request. Set to enable P1F.2 bit in P1F register to generate an interrupt request. Port 1 line 1 Interrupt Enable bit Clear to disable P1F.1 bit in P1F register to generate an interrupt request. Set to enable P1F.1 bit in P1F register to generate an interrupt request. Port 1 line 0 Interrupt Enable bit Clear to disable P1F.0 bit in P1F register to generate an interrupt request. Set to enable P1F.0 bit in P1F register to generate an interrupt request. P1IE.2 2 P1IE.1 1 P1IE.0 0
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
6 P1IE.6 5 P1IE.5 4 P1IE.4 3 P1IE.3 2 P1IE.2 1 P1IE.1 0 P1IE.0 Reset Value = 0000 0000b
2
Figure 10.10. P1IE Register
MATRA MHS Rev. A (18 Dec. 96)
II. 10.13
TSC 80251G1
P1LS (S:C9h) Port 1 Level Selection register
7 Bit Number 7 6 Bit Mnemonic P1LS.7 5 4 3 Description Port 1 line 7 Level Selection bit Clear to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Port 1 line 6 Level Selection bit Clear to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. Port 1 line 5 Level Selection bit Clear to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. Port 1 line 4 Level Selection bit Clear to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. Port 1 line 3 Level Selection bit Clear to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. Port 1 line 2 Level Selection bit Clear to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. Port 1 line 1 Level Selection bit Clear to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Port 1 line 0 Level Selection bit Clear to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. 2 1 0
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA
6 P1LS.6 5 P1LS.5 4 P1LS.4 3 P1LS.3 2 P1LS.2 1 P1LS.1 0 P1LS.0 Reset Value = 0000 0000b
Figure 10.11. PILS Register
II. 10.14
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Section III
Electrical and Mechanical Information 3
TSC 80251G1
DC Characteristics
Table 1.1. Absolute Maximum Ratings
D Ambient Temperature Under Bias Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Storage Temperature . . . . . . . . . . . . . . . . . . . . . . D Voltage on EA#/VPP Pin to VSS . . . . . . . . . . . . D Voltage on any other Pin to VSS . . . . . . . . . . . . D IOL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . D Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C -40 to +85C 0 to +125C -65 to +150C 0 to +13.0 V -0.5 to +6.5 V 15 mA 1.5 W
Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 1.2. DC Characteristics Parameter values applied to all devices unless otherwise indicated.
Commercial TA = 0 to 70C VSS = 0 V VDD = 5 V 10 % Industrial TA = -40 to +85C VSS = 0 V VDD = 5 V 10 % Typical (4) Automotive TA = -40 to +125C VSS = 0 V VDD = 5 V 10 %
3
Symbol VIL VIL1 VIH VIH1 VOL
Parameter Input Low Voltage (except EA#) Input Low Voltage (EA#) Input high Voltage (except XTAL1, RST) Input high Voltage (XTAL1) Output Low Voltage (Ports 1, 2, 3)
Min -0.5 0 0.2VDD + 0.9 0.7 VDD
Max 0.2VDD - 0.1 0.2VDD - 0.3 VDD + 0.5 VDD + 0.5 0.3 0.45 1.0
Units V V V V V
Test Conditions
IOL = 100 A IOL = 1.6 mA IOL = 3.5 mA (1, 2)
VRST+ VRST-
Reset threshold on Reset threshold off
3.7 3.3
V V
MATRA MHS Rev. A (18 Dec. 96)
III. 1.1
TSC 80251G1
Symbol VRET VOL1 Parameter VDD data retention limit Output Low Voltage (Ports 0, ALE, PSEN#) Min Typical (4) 2 0.3 0.45 1.0 VDD -0.3 VDD -0.7 VDD -1.5 VDD -0.3 VDD -0.7 VDD -1.5 VDD -0.3 VDD -0.7 VDD -1.5 - 50 - 75 10 - 650 Max Units V V IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA (1, 2) IOH = -10 A IOH = -30 A IOH = -60 A (3) IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA VIN = 0.45 V Automotive range 0.45VOH
Output high Voltage (Ports 1, 2, 3, ALE, PSEN#)
V
VOH1
Output high Voltage (Port 0 in External Address) Output high Voltage (Port 2 in External Address during Page Mode) Logical 0 Input Current (Ports 1, 2, 3) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Ports 1, 2, 3) RST Pull-Down Resistor Pin Capacitance Powerdown Current Idle Mode C rrent Current
V
VOH2
V
IIL
A
ILI ITL
A A
RRST CIO IPD IDL
40 10 20 15 10
225
kW pF A mA mA FOSC = 16 MHz FOSC = 12 MHz FOSC = 16 MHz TA = 25C
III. 1.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Symbol Parameter Min Typical (4) 50 IDD Operating C rrent Current 40 Max Units mA mA Test Conditions FOSC = 16 MHz FOSC = 12 MHz
Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: . . . . . . . . . . . . . . . . . . 10 mA Port 0 . . . . . . . 26 mA Maximum IOL per 8-bit port: Ports 1-3 . . . . 15 mA Maximum Total IOL for all: Output Pins . . 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VDD = 5 V and TA = 25C with no guarantee. They are not tested and there is not guarantee on these values.
+5V IPD VDD P0 RST EA# VDD
3
TSC80251G1 (NC) Clock Signal XTAL2 XTAL1 VSS All other pins are unconnected
Figure 1.1. IPD Test Condition, Power-Down Mode
MATRA MHS Rev. A (18 Dec. 96)
III. 1.3
TSC 80251G1
+5V IDL VDD P0 RST EA# VDD
TSC80251G1 (NC) Clock Signal XTAL2 XTAL1 VSS All other pins are unconnected
Figure 1.2. IDL Test Condition, Idle Mode
+5V IDD VDD VDD RST P0 EA# VDD
TSC80251G1 (NC) Clock Signal XTAL2 XTAL1 VSS All other pins are unconnected
Figure 1.3. IDD Test Condition, Active Mode
PSEN#,RD#,WR#
RDY#
t set t hold
Figure 1.4. Wait Timings
III. 1.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Table 1.3. Electrical Parameters
Parameter tclcl tset thold Clock period Ready valid after strobe (RD#, WR# or PSEN#) low Ready hold after strobe low (2N+1).tclcl + 2 Definition
Min
Max
Units
62,50 (2N+1).tclcl - 15
ns
ns
ns
3
MATRA MHS Rev. A (18 Dec. 96)
III. 1.5
TSC 80251G1
AC Characteristics
Table 2.1. AC Characteristics (Capacitive Loading = 50 pF)
12 MHz Symbol TOSC TLHLL TAVLL TLLAX TRLRH (1) TWLWH TLLRL (1) TRHRL TLHAX TRLDV (1) TRHDX (1) TRLAZ (1) TRHDZ (1) 1/FOSC ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low RD# or PSEN# Pulse Width WR# Pulse Width ALE Low to RD# or PSEN# Low ALE High to RD# or PSEN# High ALE high to Address hold RD# or PSEN# Low to Valid Data/Instruction. Data/Instruct. hold After RD# or PSEN# high RD#/PSEN# Low to Address Float Data/Instruct. Float After RD# or PSEN# high 68 235 235 190 273 128 0 2 63 48 173 173 128 190 88 Parameter Min 83 73 63 63 65 65 73 73 147 33 0 2 43 TOSC - 15 3TOSC - 15 3TOSC - 15 3TOSC - 60 4TOSC - 60 2TOSC - 38 16 MHz Min FOSC Max Units ns TOSC -10 TOSC - 20 TOSC - 20 TOSC - 18 TOSC - 18 TOSC - 10 TOSC - 10 2TOSC - 20 13 TOSC - 50 0 2 TOSC - 20 ns (2) ns (2) ns ns (3) ns (3) ns ns ns (2) ns (3) ns ns ns ns (1) ns (1) ns ns (2, 3, 4) ns (2, 3, 4,) ns Max Min Max 63 53 43 43 45 45 53 53 105
3
TRHLH1 RD#/PSEN# high to ALE high (Instruction) (1) TRHLH2 RD#/PSEN# high to ALE high (Data) (1) TWHLH TAVDV1 TAVDV2 TAVDV3 WR# high to ALE high Address (P0) Valid to Valid Data/Instruction In Address (P2) Valid to Valid Data/Instruction In Address (P0) Valid to Valid Instruction In
MATRA MHS Rev. A (18 Dec. 96)
III. 2.1
TSC 80251G1
12 MHz Symbol TAVRL Parameter Address Valid to RD#/PSEN# Low Min 143 143 220 63 58 147 1000 870 720 0 700 Max 16 MHz Min Max 101 101 158 43 38 105 750 620 510 0 500 Min 2TOSC - 24 2TOSC - 24 3TOSC - 30 TOSC - 20 TOSC - 25 2TOSC - 20 12 TOSC 12 TOSC - 133 10 TOSC - 117 0 10 TOSC - 133 FOSC Max Units ns (2) ns (2) ns (2) ns ns (3) ns ns ns ns ns ns
TAVWL1 Address (P0) Valid to WR# Low TAVWL2 Address (P2) Valid to WR# Low TWHQX TQVWH TWHAX TXLXL TQVSH TXHQX TXHDX TXHDV Data hold after WR# high Data Valid to WR# high WR# high to Address hold Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid
Notes : 1. Specifications for PSEN# are identical to those for RD#. 2. If a wait state is added by extending ALE, add 2TOSC. 3. If a wait state is added by extending RD#/PSEN#/WR#, add 2TOSC. 4. If wait states are added as described in both Note 2 and Note 3, add a total of 4TOSC.
III. 2.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
ALE PSEN# TRLDVK TRLAZ TLHAXK TAVLLK TLLAX P0 A7:0 TAVRLK TAVDV1K TAVDV2K P2 A15:8 K The value of this parameter depends on wait states. See the table of AC characteristics. TRHDZ TRHDX D7:0 Instruction In TLHLLK TLLRLK TRLRHK TRHLH1
Figure 2.1. External Instruction Bus Cycle in Non-Page Mode
ALE PSEN#
TLHLLK TLLRLK TRLRHK TRHLH2
TRLDVK TRLAZ TRHDZ TRHDX D7:0 Data In
3
TLHAXK TAVLLK TLLAX P0 A7:0 TAVRLK TAVDV1K TAVDV2K P2 A15:8
K The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 2.2. External Data Read Cycle in Non-Page Mode
MATRA MHS Rev. A (18 Dec. 96)
III. 2.3
TSC 80251G1
ALE WR# TLHAXK TAVLLK P0 A7:0 TAVWL1 TAVWL2K P2
K
TLHLLK TWLWHK TWHLH
TQVWH TLLAX TWHQX D7:0 Data Out TWHAX A15:8
K The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 2.3. External Write Data Bus Cycle in Non-Page Mode
ALE
TLHLLK TLLRLK TRLRHK TRHRL TRHLH1
PSEN# TRLDVK TRLAZ TAVLLK P2 TLHAXK TLLAX
TRHDZ TRHDX D7:0 Instruction In D7:0 Instruction In
A15:8 TAVRLK TAVDV1K TAVDV2K
TAVDV3K A7:0 Page hit KK
P0
A7:0 Page Miss KK
K The value of this parameter depends on wait states. See the table of AC characteristics. KK A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2TOSC); a page miss requires two states (4TOSC).
Figure 2.4. External Instruction Bus Cycle in Page Mode
III. 2.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
ALE RD#PSEN# TRLDVK TRLAZ TLHAXK TAVLLK TLLAX P2 A15:8 TAVRLK TAVDV1K TAVDV2K P0 A7:0 K The value of this parameter depends on wait states. See the table of AC characteristics. TRHDZ TRHDX D7:0 Data In TLHLLK TLLRLK TRLRHK TRHLH2
Figure 2.5. External Read Data Bus Cycle in Page Mode
ALE
TLHLLK TWLWHK TWHLH
WR# TLHAXK TAVLLK P2 TQVWH TLLAX A15:8 TAVWL1 TAVWL2K P0
K
3
TWHQX D7:0 Data Out TWHAX A7:0
K The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 2.6. External Write Data Bus Cycle in Page Mode
MATRA MHS Rev. A (18 Dec. 96)
III. 2.5
TSC 80251G1
TXLXL TXD TXHQX TQVXH RXD (Out) RXD (In) 0 TXHDV Valid Valid 1 2 TXHDX Valid 3 TAV
K
Set TIK 4 5 6 7 Set RIK Valid Valid Valid Valid
Valid
K
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
Figure 2.7. Serial Port Waveform - Shift Register Mode
Notation for timing parameters name A = Address D = Data Q = Data out S = Supply (VPP )
E = Enable V = Valid
G = PROG# H = high X = No Longer Valid
L = Low Z = Floating
III. 2.6
MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A
3.1.1. SSLC (IC) Interface Timing
MATRA MHS Rev. A (18 Dec. 96)
3.1. AC Characteristics
IC Interface AC/DC Characteristics
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1s. 3. Spikes on the SDA and SCL lines with a duration of less than 3 TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400pF. 4. TCLCL = 1/fosc = one oscillator clock period at pin XTAL1. For 83ns < TCLCL < 285ns (12MHz > fosc > 3.5MHz) the SSLC interface meets the IC bus specification for bit-rate up to 100 kbit/s
TFD
TRD
TBUF
TSU; STO
TSU; STA
THD; DAT
TSU; DAT3
TSU; DAT2
TSU; DAT1
TFC
TRC
THIGH
TLOW
THD; STA
Symbol
SDA fall time
SDA rise time
Bus free time
STOP condition set-up time
Repeated START set-up time
Data hold time
SDA set-up time (before STOP condition)
SDA set-up time (before repeated START condition)
Data set-up time
SCL fall time
SCL rise time
SCL high time
SCL low time
Start condition hold time
Parameter
0.3s
1s
14 TCLCL
14 TCLCL
14 TCLCL
0ns
250ns
250ns
250ns
0.3s
1s
14 TCLCL
16 TCLCL
14 TCLCL
Input
TSC 80251G1
< 0.3s (3)
- (2)
> 4.7s (1)
> 4.0s (1)
> 4.7s (1)
> 8 TCLCL - TFC
> 8 TCLCL
> 1s (1)
> 20 TCLCL - TRD
< 0.3s (3)
- (2)
> 4.0s (1)
> 4.7s (1)
> 4.0s (1)
Output
III. 3.1
3
TSC 80251G1
3.2. DC Characteristics
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
Inputs VIL1 Input Low Voltage, SCL, SDA(5) -0.5 0.3 Vcc V V VIH2 Input High Voltage, SCL, SDA(5) 0.7 Vcc Vcc + 0.5 Outputs VOL Output Low Voltage, ports 1, 2, 3, SCL, SDA, PWM0-7 0.3 0.45 1.0 V V V IOL = 100A IOL = 1.6mA(4) IOL = 3.5mA Note: 5. The input threshold voltage of SCL and SDA (SIO1) meets the IC specification, so an input voltage below 0.3.VCC will be recognised as a logic 0 while an input voltage above 0.7.VCC will be recognised as a logic 1.
Symbol
Parameter
Min
Max
Unit
Test Conditions
3.2.1. SSLC (IC) Timing Waveforms
TXLXL TXD TXHQX TQVXH RXD (Out) RXD (In) 0 TXHDV Valid Valid 1 2 TXHDX Valid
Set TIK 3 TAVK Valid Valid Valid Valid 4 5 6 7 Set RIK Valid
K
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
Figure 3.1.
III. 3.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
EPROM Programming
4.1. Programming Modes
The TSC87251G1 derivatives in Window CQPJ are erasable by UV which set all the EPROM memory cells to one and allows a reprogrammation. The other TSC87251G1 derivatives are one time programmable as an EPROM cell cannot be reset once programmed to 0. Table 4.1. shows the hardware setup needed to program the TSC87251G1 EPROM areas: D The chip has to be maintained under reset and the PSEN# has to be to forced to 0 until the completion of the Programming sequence. D The Programming address are applied on Ports 1 and 3 which are respectively the upper and lower address lines. D The Programming data are applied on Port 2. D The EPROM Programming is done by applying VPP on the EA# pin and by generating 5 pulses on ALE/PROG# pin for the on-chip code memory and 25 for the Configuration bytes. Table 4.1. EPROM Programming Configuration
EPROM Mode On-chip code memory Configuration bytes RST 1 1 EA# VPP VPP PSEN# 0 0 ALE 5 Pulses 25 Pulses P0 68h 69h P2 Data Data P1(Upper)P3(Lower) Notes 0000h-5FFFh 0080h-0081h 1 1
Notes: 1. The ALE/PROG# pulse waveform is shown in Figure 4.2.
VDD VPP 5 x 100 s EA#/VPP ALE/PROG# RST PSEN# VDD +5V
3
Mode
P0
TSC87251G1
A7:0 A14:8 P3 XTAL1 P1 P2 VSS 4 to 6 MHz
PGM Data
Figure 4.1. Setup for EPROM Programming
MATRA MHS Rev. A (18 Dec. 96)
III. 4.1
TSC 80251G1
P1 = A14:8 P3 = A7:0 TAVGL P2 = D7:0 Data TDVGL VPP EA#/VPP VDD VSS TSHGL ALE/PROG# 1 TEHSH P0 2 3 4 5 TGLGH Mode = 68h or 69h TGHGL TGHSL TGHDX Address TGHAX
Note: The timing is the same for both Programming Modes excepted the number of Programming pulses. Only 5 Programming pulses are shown here.
Figure 4.2. Timings for EPROM Programming
III. 4.2
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
4.2. Verify Algorithm
Figure 4.3. show the setup needed to verify the TSC80251G1 EPROM areas. Table 4.2. shows the Configuration needed to verify the on-chip code memory and Configuration bytes. The 15 addresses must be connected to the Ports 3 and 1. ALE/PROG# and PSEN# are driven low while Port 0 receives the Configuration. Figure 4.4. shows the timings to apply in orded to execute the EPROM verify Mode. D Port 0 drives the verify Mode (28h for Programming Mode). D The address to access is driven on Port 1 and Port 3 while the PSEN# and ALE are driven low. The data is driven on Port 2, 48 clock periods after the address is stable. Table 4.2. EPROM Verifying Configuration
Verify EPROM On-chip code memory Configuration bytes RST 1 1 EA# 1 1 PSEN# 0 0 ALE 1 1 P0 28h 29h P2 Data Data P1(Upper) P3(Lower) 0000h-5FFFh 0080h-0083h
VDD EA#/VPP ALE/PROG# RST PSEN# VDD P2
+5V
PGM Data
3
Mode
P0
TSC87251G1
A7:0 A14:8 P3 XTAL1 P1 VSS 4 to 6 MHz
Figure 4.3. Setup for EPROM Verification
MATRA MHS Rev. A (18 Dec. 96)
III. 4.3
TSC 80251G1
P0 Mode = 28h or 29h TELQV P1 = A14:8 P3 = A7:0 Address TEHQZ
P2 = D7:0 TAVQV > = 48 x tclc
Data
Figure 4.4. Timings for EPROM Verification Table 4.3. EPROM Programming & Verification Characteristics ( TA = 21 to 27C ; VCC = 5V +/- 0.25V ; VSS= 0 )
Symbol VPP IPP TOSC TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG# low Address Hold after PROG# low Data Setup to PROG# low Data Hold after PROG# ENABLE High to VPP VPP Setup to PROG# low VPP Hold after PROG# PROG# Width Address to Data Valid ENABLE low to Data Valid Data Float after ENABLE PROG high to PROG# low 0 10 167 48TOSC 48TOSC 48TOSC 48TOSC 48TOSC 10 10 90 110 48TOSC 48TOSC 48TOSC ms ms ms ms Min 12,75 Max 13 75 250 Units V mA ns
III. 4.4
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Packages
5.1. List of Packages
All available packages are described in this chapter. D PDIL 40 D PLCC 44 D CQPJ 44 with Window D PQFP 44 D VQFP 44 (1010) D VQFP 44 (1414)
3
MATRA MHS Rev. A (18 Dec. 96)
III. 5.1
TSC 80251G1
5.2. PDIL 40
5.2.1. Mechanical Outline
Figure 5.1. Plastic Dual In Line Table 5.1. PDIL Package Size
MM Min A A1 A2 B B1 C D E E1 e eA eB L D1 - 2.93 0.13 - 0.38 3.18 0.36 0.76 0.20 50.29 15.24 12.32 2.54 B.S.C. 15.24 B.S.C. 17.78 3.81 - - .115 .005 Max 5.08 - 4.95 0.56 1.78 0.38 53.21 15.87 14.73 Min - .015 .125 .014 .030 .008 1.980 .600 .485 .100 B.S.C. .600 B.S.C. .700 .150 - INCH Max .200 - .195 .022 .070 .015 2.095 .625 .580
III. 5.2
MATRA MHS Rev. A (18 Dec. 96)
AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MATRA MHS Rev. A (18 Dec. 96)
5.2.2. Pin Assignment
Pin Number
VSS
XTAL1
XTAT2
P3.7/A16/RD#
P3.6/WR#
P3.5/T1
P3.4/T0
P3.3/INT13
P3.2/INT0#
P3.1/TXD
P3.0/RXD
RST
P1.7/A17/CEX4/SDA/MOSI
P1.6/CEX3/SCL/SCK
P1.5/CEX2/MISO
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T2EX
P1.0/T2
Pin Name
Table 5.2. PDIL Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Pin Number
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#VPP
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
TSC 80251G1
Pin Name
III. 5.3
3
TSC 80251G1
5.3. PLCC 44
5.3.1. Mechanical Outline
Figure 5.2. Plastic Lead Chip Carrier Table 5.3. PLCC Package Size
MM Min A A1 D D1 D2 E E1 E2 e G H J K Nd Ne 1.07 1.07 0.51 0.33 11 11 4.20 2.29 17.40 16.44 14.99 17.40 16.44 14.99 1.27 BSC 1.22 1.42 - 0.53 .042 .042 .020 .013 11 11 Max 4.57 3.04 17.65 16.66 16.00 17.65 16.66 16.00 Min .165 .090 .685 .647 .590 .685 .647 .590 .050 BSC .048 .056 - .021 INCH Max .180 .120 .695 .656 .630 .695 .656 .630
III. 5.4
MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A AAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MATRA MHS Rev. A (18 Dec. 96)
5.3.2. Pin Assignment
Pin Number
VSS
XTAL1
XTAL2
P3.7/A16/RD#
P3.6/WR#
P3.5/T1
P3.4/T0
P3.3/INT1#
P3.2/INT0#
P3.1/TXD
WAIT#
P3.0/RXD
RST
P1.7/A17/CEX4/SDA/MOSI
P1.6/CEX3/SCL/SCK
P1.5/CEX2/MISO
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T3EX
P1.0/T2
VSS1
Pin Name
Table 5.4. PLCC Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Number
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
VSS2
TSC 80251G1
Pin Name
III. 5.5
3
TSC 80251G1
5.4. CQPJ 44 with Window
5.4.1. Mechanical Outline
Figure 5.3. Ceramic Quad Pack J Table 5.5. CQPJ Package Size
MM Min A C D-E D1 - E1 e f J Q R N1 N2 0.43 0.86 15.49 0.86 TYP 11 11 - 0.15 17.40 16.36 1.27 TYP 0.53 1.12 16.00 .017 .034 .610 .034 TYP 11 11 Max 4.90 0.25 17.55 16.66 Min - .006 .685 .644 .050 TYP .021 .044 .630 INCH Max .193 .010 .691 .656
III. 5.6
MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A AAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MATRA MHS Rev. A (18 Dec. 96)
5.4.2. Pin Assignment
Pin Number
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
VSS2
VSS
XTAL1
XTAL2
P3.7/A16/RD#
P3.6/WR#
P3.5/T1
P3.4/T0
P3.3/INT1#
P3.2/INT0#
P3.1/TXD
WAIT#
P3.0/RXD
RST
P1.7/A17/CEX4/SDA/MOSI
P1.6/CEX3/SCL/SCK
P1.5/CEX2/MISO
Pin Name
Table 5.6. CQPJ Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Number
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T3EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
TSC 80251G1
Pin Name
III. 5.7
3
TSC 80251G1
5.5. PQFP 44
Figure 5.4. Plastic Quad Flat Pack Table 5.7. PQFP Package Size
MM Min A C D D1 E E1 e f J L N1 N2 0.20 0.00 0.65 11 11 2.00 0.10 13.65 9.90 13.65 9.90 0.80 B.S.C. 0.40 0.30 0.95 .008 .000 .025 11 11 Max 2.40 0.20 14.15 10.10 14.15 10.10 Min .079 .004 .537 .390 .537 .390 .0315 B.S.C. .016 .012 .037 INCH Max .094 .008 .557 .398 .557 .398
III. 5.8
MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A AAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MATRA MHS Rev. A (18 Dec. 96)
5.5.1. Pin Assignment
Pin Number
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
VSS2
VSS
XTAL1
XTAL2
P3.7/A16/RD#
P3.6/WR#
P3.5/T1
P3.4/T0
P3.3/INT1#
P3.2/INT0#
P3.1/TXD
WAIT#
P3.0/RXD
RST
P1.7/A17/CEX4/SDA/MOSI
P1.6/CEX3/SCL/SCK
P1.5/CEX2/MISO
Pin Name
Table 5.8. PQFP Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Number
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T3EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
TSC 80251G1
Pin Name
III. 5.9
3
TSC 80251G1
5.6. VQFP 44 (1010)
5.6.1. Mechanical Outline
Figure 5.5. Shrink Quad Flat Pack (Plastic) Table 5.9. VQFP Package Size
MM Min A A1 A2 A3 D D1 E E1 J L e f 1.35 11.90 9.90 11.90 9.90 0.05 0.45 0.80 BSC 0.35 BSC - 0.64 REF 0.64 REF 1.45 12.10 10.10 12.10 10.10 - 0.75 .053 .468 .390 .468 .390 .002 .018 .0315 BSC .014 BSC Max 1.60 Min - .025 REF .025REF .057 .476 .398 .476 .398 6 .030 INCH Max .063
III. 5.10
MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A AAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MATRA MHS Rev. A (18 Dec. 96)
5.6.2. Pin Assignment
Pin Number
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
VSS2
VSS
XTAL1
XTAL2
P3.7/A16/RD#
P3.6/WR#
P3.5/T1
P3.4/T0
P3.3/INT1#
P3.2/INT0#
P3.1/TXD
WAIT#
P3.0/RXD
RST
P1.7/A17/CEX4/SDA/MOSI
P1.6/CEX3/SCL/SCK
P1.5/CEX2/MISO
Pin Name
Table 5.10. VQFP Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Number
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T3EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
TSC 80251G1
Pin Name
III. 5.11
3
TSC 80251G1
5.7. VQFP 44 (1414)
5.7.1. Mechanical Outline
Figure 5.6. Shrink Quad Flat Pack Table 5.11. VQFP Package Size
MM Min A A1 A2 A3 D D1 E E1 J L e f 0.35 0.05 0.45 1.00 BSC 0.5 .0014 1.35 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.15 0.75 .002 .018 .0394 BSC .0197 - 0.64 REF 0.64 REF 1.45 Max 1.60 Min - .025 REF .025REF .053 BSC .63 BSC .55 BSC .63 BSC .55 BSC 6 .030 INCH Max .063
III. 5.12
MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A A AAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MATRA MHS Rev. A (18 Dec. 96)
5.7.2. Pin Assignment
Pin Number
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
VSS2
VSS
XTAL1
XTAL2
P3.7/A16/RD#
P3.6/WR#
P3.5/T1
P3.4/T0
P3.3/INT1#
P3.2/INT0#
P3.1/TXD
WAIT#
P3.0/RXD
RST
P1.7/A17/CEX4/SDA/MOSI
P1.6/CEX3/SCL/SCK
P1.5/CEX2/MISO
Pin Name
Table 5.12. VQFP Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Number
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
P1.1/T3EX
P1.0/T2
VSS1
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
TSC 80251G1
Pin Name
III. 5.13
3
TSC 80251G1
Section IV
Application Notes
4
TSC 80251G1
How to Plug a TSC80251G1 Step A in a C51 Board ?
1.1. Introduction
This application note assumes that the user is familiar with C51 microcontrollers. The purpose of this application note is to address the software and the hardware design considerations when migrating from C51 microcontrollers to the first general purpose TEMIC C251 microcontroller, the TSC80251G1 Step A. Without changing the code, the average performance will increase by a factor from 2 to 5 (See "Speed Increase" part). If the new instruction set is used, the performance may increase up to a factor of 15. To plug a TSC80251G1 into a C51 socket, the user has to consider three points: D the pin-to-pin replacement, D the programming of the two configuration bytes, D the speed increase. Caution: If the chip is a TSC80251G1-B (See Ordering Information in Product Design Guide), the microcontroller is already programmed to be C51 compatible and the user is not concerned with programming the configuration bytes.
1.2. Pin-to-Pin Replacement
The C51 microcontrollers have 4 NC (Not Connected) pins which are used on TSC80251G1 microcontrollers. In Step A, these pins must not be floating, so please connect VSS1, VSS2, NMI (respectively pins #1, #23 and #34 in PLCC44) to the Ground and WAIT# (pin #12 in PLCC44) to VCC. However, the TSC80251G1 Step C will provide a pin-to-pin replacement of C51 microcontrollers without these constraints.
4
1.3. Configuration Bytes
The TSC80251G1 Step A provides a variety of features and operating modes by programming two configuration bytes CONFIG0 and CONFIG1 (See Figure 1.1. and Figure 1.2. ). These bytes are read from specific registers (See Table 1.1. ) during the reset of the chip.
MATRA MHS Rev. A (18 Dec. 96)
II. 8.1
TSC 80251G1
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 1.1. Configuration Bytes Location
Location of registers (K) On-chip EPROM Microcontrollers Programming TSC87251G1 EPROM by user or ask factory by user or ask factory in factory in factory TSC87251G1 OTPROM On-chip OTPROM Metal Mask Metal Mask TSC83251G1 MaskROM TSC80251G1 ROMless (K) In Step C, user configuration bytes (UCONFIG0 and UCONFIG1) are used instead of CONFIG0 and CONFIG1. In all cases (EPROM, OTPROM, MaskROM, ROMless), the user is able to program these bytes. He must do it unless it has been ordered to factory (EPROM, OTPROM, MaskROM). II. 8.2 MATRA MHS Rev. A (18 Dec. 96)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
CONFIG0 (80h) Configuration byte 0
Note: The arrow () shows the recommended configuration for C51 compatibility. Bit Number 0 1 2 3 4 5 6 7 7 - Bit Mnemonic XALE PAGE WSA SRC RD0 RD1 - - 6 - 1 Source Mode/Binary Mode Select bit Clear for binary mode. Set for source mode. Page Mode Select bit Clear for page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0. Set for non-page mode with A15:8 on Port 2 and A7:0/D7:0 on Port 0. Memory Signal Selection bits Codes specify a 17-bit or 16-bit external address bus and address ranges for RD#, WR# and PSEN# signals. RD1 RD0 RD# P1.7 PSEN# Range Extend ALE bit Clear to extend the time of the ALE pules from TOSC to 3.TOSC. Set to keep the time of the ALE pulse to TOSC. Wait State A bit Clear to generate one wait state for memory regions 00:, FE: and FF:. Set for no wait states for regions 00:, FE: and FF:. Reserved Set this bit when writing to CONFIG0. Reserved Set this bit when writing to CONFIG0. 0 0 1 WSA 5
MATRA MHS Rev. A (18 Dec. 96)
Figure 1.1. Configuration Byte 0
1
1
0
0
XALE
4
RD#
A16
A16
I/O pin
RD1
I/O pin
I/O pin
A17
I/O pin
3
Description
PSEN# is the read signal for both external data and program address spaces (256 Kbytes). PSEN# is the read signal for both external data and program address spaces (128 Kbytes). PSEN# is the read signal for both external data and program address spaces (64 Kbytes). PSEN# is the read signal for the external program address spaces (64 Kbytes) and RD# is the read signal for the external data address space (64 Kbytes).
RD0
2
TSC 80251G1
PAGE
1
SRC
0
II. 8.3
4
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A
TSC 80251G1
CONFIG1 (81h) Configuration Byte 1
Note: The arrow () shows the recommended configuration for C51 compatibility. Bit Number 0 1 2 3 4 5 6 7 7 - Bit Mnemonic EMAP INTR WSB - - - - - 6 - EPROM Map bit Clear to map the upper 8 Kbytes of on-chip code memory (FF:2000h-FF:3FFFh) to 00:E000h-00:FFFFh. Set to not map the upper 8 Kbytes of on-chip code memory (FF:2000h-FF:3FFFh) Reserved Set this bit when writing to CONFIG1. Reserved Set this bit when writing to CONFIG1. Wait State B Clear to generate one wait state for memory region 01:. Set for no wait states for region 01:. Interrupt Mode bit Clear so that the interrupts push 2 bytes onto the stack (the 2 lower bytes of the PC register). Set so that the interrupts push 4 bytes onto the stack (the 3 bytes of the PC register and the PSW1 register). Reserved Set this bit when writing to CONFIG1. Reserved Set this bit when writing to CONFIG1. Reserved Set this bit when writing to CONFIG1. 5 -
II. 8.4
The default configuration for OTPROM/EPROM microcontrollers is CONFIG0 = 1111 1111b and CONFIG1 = 1111 1111b. The configuration recommended for C51 compatibility (hardware and software) is CONFIG0 = 1101 1110b and CONFIG1 = 1110 0111b. In details: D SRC = 0 for binary mode. D PAGE = 1 for non-page mode. D INTR = 0 to push 2 bytes onto the stack.
Figure 1.2. Configuration Byte 1
INTR
4
WSB
3
Description
2
-
1
-
MATRA MHS Rev. A (18 Dec. 96) EMAP 0
TSC 80251G1
D RD1 = 1 and RD0 = 1 for memory signals. D XALE = 0 to keep the ALE pulse width (0 wait state). D WSA = 0 and WSB = 0 to add 1 wait state for all external memory regions. D EMAP = 1. The first four points are mandatory to follow for C51 compatibility while the others are optional. In fact, the internal code memory of the TSC80251G1 is faster than most of the external memory and peripheral device available. When interfacing the TSC80251G1 with slower devices (used on C51 board), a wait state can be used to extend the external system bus cycle. The TSC80251G1 Step A can be configured to generate 0 or 1 wait state for ALE, PSEN#, RD# and WR# signals. With 0 wait state, the pulse of these signals is 1 oscillator period. With 1 wait state, the pulse widths are extended to 3 oscillator periods. The user may need to check the timing specifications for the TSC80251G1 and the external devices to ensure that the TSC80251G1 will be able to interface successfully with external devices.
1.4. Speed Increase
The TSC80251G1 uses the new C251 microcontroller's core that is different from the traditional C51's one. It is designed based on a pipelined architecture and a register-based machine. Therefore, the execution time decreases and the user must consider changing the the timing loops or sequences of C51 code running on TSC80251G1 when he relies on C51 execution time. For example, a delay time is used to provide a 13 s delay in a 12 MHz 80C51 application. The code and the taken time are shown on Listing 1.1.
; Internal or External Code Execution LOOP : MOV DJNZ R0,#06h R0,LOOP
Taken time in number of cycles ;1 ;2
; 1 cycle = 12 oscillator periods ; Total oscillator periods = [ 1 + ( 6 x 2 ) ] x 12 = 156 ; Total time taken in the timing loop = 156 x 83.33 ns = 13 s
4
Listing 1.1. Loop Executed at 12 MHz on 80C51
In the same application, the 80C51 microcontroller is replaced by a 12 MHz TSC80251G1 programmed using the recommended configuration for C51 compatibility in binary mode. No modification is made to the code shown on Listing 1.1. But to simplify timing loop calculation, the code is executed in internal memory. The code and the taken time is shown on Listing 1.2.
MATRA MHS Rev. A (18 Dec. 96)
II. 8.5
TSC 80251G1
; Internal Binary Code Execution LOOP: MOV DJNZ R0,#06h R0, LOOP Taken time in number of states ;1 ; 5 and 2 for exiting the loop
; 1 state = 2 oscillator periods ; Total oscillator clock periods = [ 1 + ( 5 x 5 + 2 ) ] x 2 = 56 ; Total time taken in the timing loop = 56 x 83.33 ns = 4.66 s
Listing 1.2. Loop Executed at 12 MHz on TSC80251G1 Without Code Modification
To maintain the same delay time, some changes in the assembly code are needed. The new code and the taken time are shown on Listing 1.3.
; Internal Binary Code Execution LOOP: MOV DJNZ R0,#0Fh R0, LOOP
Taken time in number of states ;1 ; 5 and 2 for exiting the loop
; 1 state = 2 oscillator periods ; Total oscillator clock periods = [ 1 + ( 15 x 5 + 2 ) ] x 2 = 156 ; Total time taken in the timing loop = 156 x 83.33 ns = 13 s
Listing 1.3. Loop executed at 12 MHz on TSC80251G1 With Code Modification
Calculating execution time for TSC80251G1 is not as easy as for 80C51. The execution time depends on whether the code is fetched: from internal or external memory. When bytes are fetched in external memory in non-page mode and with one wait state, each fetch takes 6 oscillator periods (3 states) and the corresponding speed increase factor is 2. When no wait states are added, this factor becomes 3. When bytes are fetched in external memory in page mode, each fetch requires only 2 oscillator periods (1 state) and this factor becomes 6. It is the same factor for internal code execution, which is the fastest case. But the average speed increase factor is 5 since all instructions do not take the same execution time. The user may note that, on Listing 2, the execution time is only divided by a factor of 2.7 because DJNZ is one of the slowest instruction. Caution: To execute code in page-mode, an address latch must be connected to Port 2 instead of Port 0 and the hardware of 80C51 applications must be changed. To use existing 80C51 applications without changing your hardware, please execute code in non-page mode.
II. 8.6
MATRA MHS Rev. A (18 Dec. 96)
TSC 80251G1
Section V
Ordering Information
5
TSC 80251G1
Ordering Information
TSC 80251G1 XXX - A 12 C B R
Customer ROM Code
12: 12 MHz version 16: 16 MHz version
Part Number 80251G1: External ROM 87251G1: 16 Kbytes OTP/EPROM 251G1: 16 Kbytes MaskROM A: C251 Default Mode B: C51 Binary Mode For other configurations, please contact your sales office
Packaging A: PDIL 40 B: PLCC 44 C: Window CQPJ 44 (EPROM version) D: PQFP 44 E: VQFP 44 (1010) F: VQFP 44 (1414)
Temperature Range C : Commercial 0 to 70C I : Industrial -40 to 85C A: Automotive -40 to 125C TEMIC Semiconductor Microcontroller Product Division
Conditioning R : Tape & Reel D : Dry Pack B : Tape & Reel Dry Pack
Examples
Part Number TSC80251G1-A16CBR TSC80251G1-B16CBR TSC87251G1-12CB TSC87251G1-12CC Description ROMless, C251 Default Mode, 16 MHz, PLCC 44, 0 to 70C, Tape and Reel ROMless, C51 Binary Mode, 16 MHz, PLCC 44, 0 to 70C, Tape and Reel OTP, 12 MHz, PLCC 44, 0 to 70C EPROM, 12 MHz, CQPJ 44, 0 to 70C
Development Tools
Part Number TSC80251G1-SKA TSC80251G1-SKB TSC80251G1-EKA TSC80251G1-EKB Software Starter Kit Keil Software Starter Kit Tasking Evaluation Kit Keil Evaluation Kit Tasking Description
Product Marking : TEMIC Customer P/N Temic P/N M (c) Intel'95 YYWW Lot Number
5
MATRA MHS Rev. A (18 Dec. 96)
V. 1.1

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