View TS68C000_1006170.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* * * * * * * * *
16-/32-bit Data and Address Register 16-Mbyte Direct Addressing Range 56 Powerful Instruction Types Operations on Five Main Data Types Memory Mapped Input/Output 14 Addressing Modes Three Available Versions: 8 MHz/10 MHz and 12.5 MHz Military Temperature Range: -55/+125C Power Supply: 5VDC 10%
Description
The TS68C000 reduced power consumption device dissipates an order of magnitude less power than the HMOS TS68000. The TS68C000 is an implementation of the TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data bus and 24-bit address bus while the full architecture provides for 32-bit address and databuses. It is completely code-compatible with the HMOS TS68000, TS68008 8-bit data bus implementation of the TS68000 and the TS68020 32-bit implementation of the architecture. Any user-mode programs written using the TS68C000 instruction set will run unchanged on the TS68000, TS68008 and TS68020. This is possible because the user programming model is identical for all processors and the instruction sets are proper sub-sets of the complete architecture.
Low Power HCMOS 16-/32-bit Hi-Rel Microprocessor TS68C000
Screening/Quality
This product is manufactured in full compliance with: * * * MIL-STD-883 class B DESC drawing 5962-89462 Atmel standards
C Suffix DIL 64 Ceramic Package
F Suffix CQFP 68 Ceramic Quad Flat Pack (on request)
E Suffix LCCC 68 Leadless Ceramic Chip Carrier
R Suffix PGA 68 Pin Grid Array
Rev. 2170A-HIREL-09/02
1
General Description
Introduction
This detail specification contains both a summary of the TS68C000 as well as detailed set of parametrics. The purpose is twofold to provide an instruction to the TS68C000 and support for the sophisticated user. For detail information on the TS68C000, refer to "68000 16-bit microprocessor user's manual". The functional block diagram is given in Figure 1 below.
Detailed Block Diagram
Figure 1. Block Diagram
Status and Control Clock Clock Gen. and Timing Control
Interrupt Control Instruction Decode Bus Control Logic
VCC VGND
Control Store M Store N Store Alu Function and Reg Selection
System Control Signals
Internal Control bus
Instruction Register
DATA BUS Data Bus Buffer 16-bit Data Bus
Address High Execution Unit and Registers 16-bit Alu
Address Low Execution Unit and Registers 16-bit Alu
Data Execution Unit and Registers 16-bit Alu
Addr. Bus Buffer
32-bit Address Bus
ADDRESS BUS
2
TS68C000
2170A-HIREL-09/02
TS68C000
Pin Assignments
Figure 2. 64-lead Dual-in-Line Package
Index
D4 D3 D2 D1 D0 AS UDS LDS R/W DTACK BG BGACK BR VCC CLK GND HALT RESET VMA E VPA BERR IPL2 IPL1 IPL0 FC2 FC1 FC0 A1 A2 A3 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND A23 A22 A21 VCC A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5
3
2170A-HIREL-09/02
Figure 3. 68-terminal Pin Grid Array
L J H
NC
FC2 FC0
A1
A3 A2
A4 A5
A6
A7
A9
NC
BERR IPL0 FC1 NC E IPL2 IPL1
A8 A10 A11 A14 A13 A12 A16 A15 A17
G VMA VPA F HALT RESET E D C BGACK BG B A R/W D3 D4 5 D6 D5 6 DTACK LDS UDS D0 NC 1 AS 2 D1 3 D2 4 CLK GND BR VCC BOTTOM VIEW
A18 A19 VCC A20 GND A21 D13 A23 A22
D9 D11 D14 D15 D7 7 D8 8 D10 D12 9 10
Index
Figure 4. 68-lead Quad Pack
Index
DTACK BG BGACK BR VCC CLK GND GND NC HALT RESET VMA E VPA BERR IPL2 IPL1
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
R/W LDS UDS AS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TOP VIEW
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
D13 D14 D15 GND GND A23 A22 A21 VCC A20 A19 A18 A17 A16 A15 A14 A13
4
TS68C000
2170A-HIREL-09/02
IPL0 FC2 FC1 FC0 NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
TS68C000
Figure 5. 68-ceramic Quad Flat Pack
Index 68 1
R/W LDS LDS AS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
52 51
DTACK BG BGACK BR VCC CLK GND GND NC HALT RESET VMA E VPA BERR IPL2 IPL1
TOP VIEW
17 18 34
D13 D14 D15 GND GND A23 A22 A21 VCC A20 A19 A18 A17 A16 A15 A14 A13
35
Terminal Designations
The function, category and relevant symbol of each terminal of the device are given in the following table: Table 1. Terminal Designations
Symbol VCC VSS
(1)
IPL0 FC2 FC1 FC0 NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Function Power Supply (2 terminals) Power Supply (2 terminals) Processor Status Interrupt Control Address Bus Asynchronous Bus Control
Category Supply Terminals Outputs Inputs Outputs Outputs
FC0 to FC2 IPL0 to IPL2 A1 to A23 AS R/W UDS LDS DTACK BR BGACK BG
Input Bus Arbitration Control Inputs
Output
5
2170A-HIREL-09/02
Table 1. Terminal Designations (Continued)
Symbol BERR RESET HALT VPA VMA E CLK D0 to D15 Note: Clock Data Bus 6800 Peripheral Control Input Output Output Input Input/Output Function System Control Category Input Input/Output
1. VSS is the reference terminal for the voltages
Signal Description
The input and output signals are illustrated functionally in Figure 6 and are described in the following paragraphs. Figure 6. Input and Output Signals
VCC GND CLK DATA BUS AS R/W UDS LDS DTACK BR BG BGACK IPL0 IPL1 IPL2 INTERRUPT CONTROL D0 - D15 ADDRESS BUS
A1 - A23
PROCESSOR STATUS
FC0 FC1 FC2 E VMA VPA BERR RESET HALT
MICROPROCESSOR
ASYNCHRONOUS BUS CONTROL
PERIPHERAL CONTROL
BUS ARBITRATION CONTROL
SYSTEM CONTROL
Table 2. Data Strobe Control of Data Bus
UDS High Low High Low Low High Low LDS High Low Low High Low Low High High High High Low Low High R/W D8-D15 No valid data Valid data bits 8-15 No valid data Valid data bits 8-15 Valid data bits 8-15 Valid data bits 0-7 Valid data bits 8-15 D0-D7 No valid data Valid data bits 0-7 Valid data bits 0-7 No valid data Valid data bits 0-7 Valid data bits 0-7 Valid data bits 8-15
6
TS68C000
2170A-HIREL-09/02
TS68C000
Address Bus (A1 through A23) This 24-bit, unidirectional, three-state bus is capable of addressing 16 megabytes of data. It provides the address for bus operation during all cycles except interrupt cycles. During interrupt cycles, address lines A1, A2 and A3 provide information about what level interrupt is being serviced while address lines A4 through A23 are set to a logic high. This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transfer and accept data in either word or byte length. During an interrupt acknowledge cycle, the external device supplies the vector number on data lines D0-07. Asynchronous data transfers are handled using the following control signals: address strobe, read/write, upper and lower data strobes, and data transfer acknowledge. These signals are explained in the following paragraphs. ADDRESS STROBE (AS) This signal indicates that there is a valid address on the address bus. READ/WRITE (R/W) This signal defines the data bus transfer as a read or write cycle. The R/W signal also works in conjunction with the data strobes as explained in the following paragraph. UPPER AND LOWER DATA STROBE (UDS, LDS) These signals control the flow of data on the data bus, as shown in Table 2. When the R/W line is high, the processor will read from the data bus as indicated. When the R/W line is low, the processor will write to the data bus as shown. DATA TRANSFER ACKNOWLEDGE (DTACK) This input indicates that the data transfer is completed. When the processor recognizes DTACK during a read cycle, data is latched and the bus cycle terminated. When DTACK is recognized during a write cycle, the bus cycle is terminated. Bus Arbitration Control The three signals, bus request, bus grant, and bus grant acknowledge, form a bus arbitration circuit to determine which device will be the bus master device. BUS REQUEST (BR) This input is wire ORed with all other devices that could be bus masters. This input indicates to the processor that some other device desires to become the bus master. BUS GRANT (BG) This output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle. BUS GRANT ACKNOWLEDGE (BGACK) This input indicates that some other device has become the bus master. This signal should not be asserted until the following four conditions are met: 1. a bus grant has been received, 2. address strobe is inactive which indicates that the microprocessor is not using the bus, 3. data transfer acknowledge is Inactive which indicates that neither memory nor peripherals are using the bus, and 4. bus grant acknowledge is inactive which indicates that no other device is still claiming bus mastership.
Data Bus (D0 Through D15)
Asynchronous Bus Control
7
2170A-HIREL-09/02
Interrupt Control (IPL0, IPL1, IPL2)
These Input pins indicate the encoded priority level of the device requesting an interrupt. Level seven is the highest priority white level zero indicates that no interrupts are requested. Level seven cannot be masked. The least significant bit is given in IPLO and the most significant bit is contained in IPL2. These lines must remain stable until the processor signals interrupt acknowledge (FC0-FC2 are all high) to insure that the interrupt is recognized. The system control inputs are used to either reset or halt the processor and to indicate to the processor that bus errors have occurred. The three system control inputs are explained in the following paragraphs. BUS ERROR (BERR) This input informs the processor that there is a problem with the cycle currently being executed. Problems may be a result of: 1. nonresponding devices, 2. interrupt vector number acquisition failure, 3. illegal access request as determined by a memory management unit, or 4. other application dependent errors. The bus error signal interacts with the halt signal to determine if the current bus cycle should be re-executed or if exception processing should be performed. RESET (RESET) This bidirectional signal line acts to reset (start a system initialization sequence) to processor in response to an external reset signal. An internally generated reset (result of a RESET instruction) causes all external devices to be reset and the internal of the processor is not affected. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied at the same time. HALT (HALT) When this bldirectional line is driven by an external device, it will cause the processor to stop at the completion of the current bus cycle. When the processor has been halted using this input, all controI signals are inactive and all three-state lines are put in their high-impedance state. When the processor has stopped executing Instructions, such as in a double bus fault condition, the HALT line is driven by the processor to indicate to external devices that the processor has stopped.
System Control
EF 6800 Peripheral Control
These control signals are used to allow the interfacing of synchronous EF 6800 peripheral devices with the asynchronous TS68C000. These signals are explained in the following paragraphs. ENABLE (E) This signal is the standard enable signal common to all EF 6800 type peripheral devices. The period for this output is ten TS68C000 clock periods (six clocks low, four clocks high). Enable is generated by an internal ring counter which may come up in any state (i.e., at power on, it Is impossible to guarantee phase relationship of E to CLK). E is a free-running crack and runs regardless of the state of the bus on the MPU.
8
TS68C000
2170A-HIREL-09/02
TS68C000
VALID PERIPHERAL ADDRESS (VPA) This input indicates that the device or region addressed is an TS68000 Family device and that data transfer should be synchronized with the enable (E) signal. This Input also indicates that the processor should use automatic vectoring for an interrupt during an IACK cycle. VALID MEMORY ADDRESS (VMA) This output is used to indicate to TS68000 peripheral devices that there is a valid address on the address bus and the processor is synchronized to enable. This signal only responds to a valid peripheral address (VPA) input which indicates that the peripheral is an TS68000 Family device. Processor Status (FC0, FC1, FC2) These function code outputs indicate the state (user or supervisor) and the cycle type currently being executed, as shown in Table 3. The information indicated by the function code outputs is valid whenever address strobe (AS) is active. Table 3. Processor Status Table
Function Code Output FC2 Low Low Low Low High High High High FC1 Low Low High High Low Low High High FC0 Low High Low High Low High Low High Cycle Time (Undefined, reserved) User data User program (Undefined, reserved) (Undefined, reserved) Supervisor data Supervisor program Interrupt Acknowledge
Clock (CLK)
The clock input is a TTL-compatible signal that is internally buffered for development of the internal clocks needed by the processor. The clock input should not be gated off at any time and the clock signal must conform to minimum and maximum pulse width times. The clock is a constant frequency square wave with no stretching or shaping techniques required.
Detailed Specifications
Scope Applicable Documents
MIL-STD-883 1. MIL-STD-883: Test Methods and Procedures For Electronics 2. MIL-PRF-38535 Appendix A: General Specifications for Microcircuits This drawing describes the specific requirements for the microprocessor TS68C000, 8 MHz, 10 MHz and 12.5 MHz, in compliance with MIL-STD-883 class B.
9
2170A-HIREL-09/02
Requirements
General The microcircuits are in accordance with the applicable document and as specified herein.
Design and Construction
Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2, Figure 3, Figure 4 and Figure 5. Lead material and finish shall be any option of MIL-PRF-38535 Appendix A-3-5-6 "Package Element Material and Finsh". The macrocircuits are packaged in hermetically sealed ceramic package which is conform to case outlines of MIL-PRF-38535 Appendix A-3-5-1. * * * * PGA68 64 DIL 68 LCCC 68 CQFP 64 LEAD DIP SQ. LCC 68 PINS 68 TERMINALS JCC
Lead Material and Finish
Package
The precise case outlines are described on figures and into MIL-M-38510. Electrical Characteristics Absolute Maximum Ratings Limiting conditions (ratings) defined below shall not be for inspection purposes. However some limiting conditions (ratings) may be taken in other parts of this specification as detail conditions for an applicable test. Unless otherwise stated, all voltages are referenced to the reference terminal as defined in Table 1, "Terminal Designations" on page 5 of this specification. Table 4. Absolute Maximum Ratings
Symbol VCC VI VO VOZ IO Ii PDMAX TSTG TJ TLEADS Parameter Supply Voltage Input Voltage Output Voltage Off State Voltage Output Currents Input Currents Max Power Dissipation Storage Temperature Junction Temperature Lead Temperature Max 5 sec. Soldering TCASE = -55C TCASE = +125C -55 Test Conditions Min -0.3 -0.3 NA -0.3 NA NA Max +6.5 +6.5 NA 11.0 NA NA 0.27 0.27 +150 +150 +270 Unit V V V V mA mA W W C C C
10
TS68C000
2170A-HIREL-09/02
TS68C000
Recommended Condition of Use and Guaranteed Characteristics 1. Guaranteed Characteristics (Table 8 and Table 11) The characteristics associated to a specified measurement in the detail specification shall only be for inspection purposes. Such characteristic defined in this specification is guaranteed only under the conditions and within the limits which are specified for the relevant measurement. Unless otherwise specified, this guarantee applies within all the recommended operating ranges specified below. 2. Recommended conditions of use (Table 5) To the correct operation of the device, the conditions of use shall be within the ranges specified below (see also above). These conditions shall not be for inspection purposes. Some recommended values may, however, be taken in other parts of this specification as detail conditions for an applicable test (Table 12). 3. Additional Electrical Characteristics (Table 12), see "Additional Electrical Characteristics" on page 31. Figure 7. Clock Input Timing Diagram
tcyc tCL 2.0V 0.8V tCr tCf tCH
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside, and pass through, the range such that the rise of fall will be linear between 0.8V and 2.0V.
Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1). Table 5. Recommended Condition of Use
Operating Range Symbol VCC VIL VIH TCASE RL CL tr(c) tf(c) Parameter Supply voltage Low level input voltage High level input voltage (see also "Package" on page 10) Operating temperature Value of output load resistance Output loading capacitance Clock rise time (see Figure 7) Clock fall time (see Figure 7) Model All All All All All All All All Min 4.5 0 2.0 -55
(1) (1)
Max 5.5 0.8 VCC +125
Unit V V V C pF ns ns
10 10
11
2170A-HIREL-09/02
Table 5. Recommended Condition of Use (Continued)
Operating Range Symbol Parameter Model TS68C000-8 fC Clock frequency (see Figure 7) TS68C000-10 TS68C000-12 TS68C000-8 tCYC Clock time (see Figure 7) TS68C000-10 TS68C000-12 TS68C000-8 tW(CL) Clock pulse width low (see Figure 7) TS68C000-10 TS68C000-12 TS68C000-8 tW(CH) Note: Cycle pulse width high (see Figure 7) TS68C000-10 TS68C000-12 Min 4.0 4.0 4.0 125 100 80 55 45 35 55 45 35 Max 8.0 10.0 12.5 250 250 250 125 125 125 125 125 125 Unit MHz MHz MHz ns ns ns ns ns ns ns ns ns
1. Load networks number 1 to 4 as specified in "Test Conditions Specific to the Device" on page 27 (Figure 8 and Figure 9) gives the maximum loading for the relevant output.
Special Recommended Conditions for CMOS Devices
1. CMOS Latch-up The CMOS cell is basically composed of two complementary transistors (a P-channel and an N-channel), and, in the steady state, only one transistor is turned-on. The active P-channel transistor sources current when the output is a logic high and presents a high impedance when the output is a logic low. Thus the overall result is extremely low power consumption because there is no power loss through the active P.channel transistor. Also since only once transistor is determined by leakage currents. Because the basic CMOS cell is composed of two complementary transistors, a virtual semiconductor controlled rectifier (SCR) may be formed when an input exceeds the supply voltage. The SCR that is formed by this high input causes the device to become "Iatched" in a mode that may result in excessive current drain and eventual destruction of the device. Although the device is Implemented with input protection diodes, care should be exercised to ensure that the maximum input voltages specification is not exceeded tram voltage transients; others may require no additional circuitry. 2. CMOS Applications * * The TS68C000 completely satisfies the input/output drive requirements of CMOS logic devices. The HCMOS TS68C000 provides an order of magnitude power dissipation reduction when compared to the HMOS TS68000. However, the TS68C000 does not offer a "power down" or "halt" mode. The minimum operating frequency of the TS68C000 is 4 MHz.
12
TS68C000
2170A-HIREL-09/02
TS68C000
Thermal Characteristics Table 6. Thermal Characteristics
Package DIL 64 Symbol JA JC JA JC JA JC JA JC Parameter Thermal resistance junction to ambient Thermal resistance junction to case Thermal resistance junction to ambient Thermal resistance junction to case Thermal resistance junction to ambient Thermal resistance junction to case Thermal resistance junction to ambient Thermal resistance junction to case Value 25 6 30 6 40 8 40 10 Unit
C/W C/W C/W C/W C/W C/W C/W C/W
PGA 68
LCCC 68
CQFP 68
Power Considerations
The average chip-junction temperature, TJ, in C can be obtained from: TJ = TA + (PD . JA) TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + PI/O PINT = ICC x VCC, Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output Pins - User Determined For most applications PI/O < PINT and can be neglected. An Approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K: (TJ + 273) Solving equations (1) and (2) for K gives: K = PD. (TA + 273) + JA * PD2 (3) (2) (1)
where K is constant pertaining to the particular part K can be determined from the equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case), surface (JC) and from the case to the outside ambient (CA). These terms are related by the equation: JA = JC + CA (4) JA is device related and cannot be influenced by the user. However, CA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce CA so that JA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature.
13
2170A-HIREL-09/02
Mechanical and Environmental Marking
The microcircuits shall meet all mechanical environmental requirements of MIL-STD883 for class B devices. The document where are defined the marking are identified in the related reference documents. Each microcircuit is legible and permanently marked with the following information as minimum: * * * * * * Atmel Logo Manufacturer's Part Number Class B Identification Date-code of inspection lot ESD Identifier if Available Country of Manufacturing
Quality Conformance Inspection
DESC/MIL-STD-883 Is in accordance with MIL-PRF-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot. Group C and D inspection are performed on a periodical basis.
Electrical Characteristics
General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurements conditions are given below: * * Table 7: Static Electrical Characteristics for all electrical variants. Table 8, Table 9, Table 10 and Table 11: Dynamic electrical characteristics for 8 MHz, 10 MHz and 12.5 MHz.
For static characteristics (Table 7), test methods refer to IEC 748-2 method number, where existing. For dynamic characteristics, test methods refer to clause "Test Conditions Specific to the Device" on page 27 of this specification (Table 8, Table 9, Table 10 and Table 11). Indication of "min" or "max" in the column "test temperature" means minimum or maximum operating temperatures as defined in sub-clause "Recommended Condition of Use and Guaranteed Characteristics" on page 11 here above.
14
TS68C000
2170A-HIREL-09/02
TS68C000
Table 7. Static Characteristics VCC = 5.0V VDC 10%; GND = 0 VDC; Tc = -55/+125C and -40C/+85C
Test Number 1 Ref Number (**) 41 Limits Test Conditions VCC = 5.5V FC = 8 MHz FC = 10 MHz FC = 12 MHz VCC = 4.5V Test Temperature Min (*) Max (*) 42 45 50 Unit
Symbol ICC
Parameter Supply current
All
mA
2
VOL(1)
Low level output voltage for: A1 to A23 FC0 to FC2; BG Low level output voltage for: HALT Low level output voltage for: AS; R/W: D0 to D15 UDS; LDS; VMA and E Low level output voltage for: RESET High level output voltage for all outputs
37
25C max 0.5 V
IOL = 3.2 mA 37 VCC = 4.5V
min 25C max 0.5 V
3
VOL(2)
IOL = 1.6 mA 37 VCC = 4.5V
min 25C max 0.5 V
4
VOL
(3)
IOL = 5.3 mA
min
5
VOL(4)
37
VCC = 4.5V
25C max 0.5 V
IOL = 5.0 mA 37 VCC = 4.5V
min 25C max 2.4 VCC - 0.75 V
6
VOH
IOH = -400 A 7 IIH
(1)
min 25C max 2.5 A
High level input current for all inputs excepted HALT and RESET Low level input current for all inputs excepted HALT and RESET High level input current for: HALT and RESET Low level input current for: HALT and RESET
38
VCC = 5.5V
VI = 5.5V 8 IIL(1) 38 VCC = 5.5V
min 25C max -2.5 A
VI = 0V 9 IIH(2) 38 VCC = 5.5V
min 25C max 20 A
VI = 5.5V 38 VCC = 5.5V
min 25C max -20 A
10
IIL
(2)
VI = 0V
min
15
2170A-HIREL-09/02
Table 7. Static Characteristics (Continued) VCC = 5.0V VDC 10%; GND = 0 VDC; Tc = -55/+125C and -40C/+85C
Test Number 11 Ref Number (**) Limits Test Conditions VCC = 5.5V Test Temperature 25C max VOH = 2.4V 12 IOLZ Low level output 3-state leakage current VCC = 5.5V min 25C max VOL = 0.4V 13 VIH High level input voltage for all inputs VCC = 4.5V min 25C max VCC = 5.5V 14 VIL Low level input voltage for all inputs VCC = 4.5V min 25C max VCC = 5.5V 14A CIN Input capacitance (all inputs) 11 Reverse voltage = 0V f = 1.0 MHz Reverse voltage = 0V f = 1.0 MHz See note 5 cycles
(9)
Symbol IOHZ
Parameter High level output 3-state leakage current
Min (*)
Max (*)
Unit
20
A
20
A
2.0
V
0.8 0.8 0.8 25 NA NA 20 NA NA -500 +500
V V V pF pF pF pF pF pF V
min 25C max min
14B
COUT
Output capacitance (all inputs)
11
25C max min
14C Note:
VTEST
Internal protection Transient energy rating
25C
* Algebraic values ** Measurement method: see "General Requirements" on page 14 and "Test Conditions Specific to the Device" on page 27.
Referred notes are given on page 25.
16
TS68C000
2170A-HIREL-09/02
TS68C000
Table 8. Dynamic Characteristics - TS68C000-8 VCC = 5.0 VDC 10%; GND = 0 VDC; Tc = -55/+125C and Tc = -40C/+85C
Test Number 27 Figure Number (**) 10 - 11 Limits Test Conditions See "Input and Output Signals for Dynamic Measurements" on page 31 (a) to (c) fC = 8 MHz Idem test 27 Test Temperature 25C max min 20(10) ns Min (*) Max (*) Unit
Symbol tSU (DICL)
Parameter Set-up time Data-in to clock low(1)
47
tSU (SDTCL)
Set-up time DTACK low to clock low(1) Set-up time BR low to clock low
(1)
10 - 11
25C max min 20(10) ns
47
tSU (SBRCL)
10 - 11
Idem test 27
25C max min 20(10) ns
47
tSU (SBGCL)
Set-up time BGACK low to clock low(1) Set-up time VPA low to clock low
(1)
10 - 11
Idem test 27
25C max min 20(10) ns
47
tSU (SVPACL)
10 - 11
Idem test 27
25C max min 20(10) ns
47
tSU (SBERCL)
Set-up time BERR low to clock low(1)
10 - 11
Idem test 27
25C max min 20(10) ns
2
tw (CL)
Clock width low
10 - 11
Idem test 27
25C max min 55(10) 125 ns
3
tw (CH)
Clock width high
10 - 11
Idem test 27
25C max min 55 125 ns
6A
tPLH tPHL (CHFCV) tPHL (CHSLX)
Propagation time clock high to FC valid
10 - 11
Idem test 27 Load: 3 Idem test 27 Load: 4
25C max min 70 ns
9
Propagation time clock high to AS low
10 - 11
25C max min 60(3)
17
2170A-HIREL-09/02
Table 8. Dynamic Characteristics - TS68C000-8 (Continued) VCC = 5.0 VDC 10%; GND = 0 VDC; Tc = -55/+125C and Tc = -40C/+85C
Test Number 9 Figure Number (**) 10 - 11 Limits Test Conditions Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Test Temperature 25C max min 12 tPLH (CLSH) Propagation time CLK low to AS high 10 - 11 25C max min 12 tPLH (CLSH) Propagation time CLK low to LDS, UDS high Propagation time CLK high to R/W high 10 - 11 25C max min 18 tPLH (CHRHX) 10 - 11 25C max min 20 tPHL (CHRL) Propagation time CLK high to R/W low 10 - 11 25C max min 23 tPZL tPZH (CLDO) tPZL tPZH (CLAV) tHRRF Propagation time CLK low to Data-out valid Propagation time CLK low to Address valid RESET/HALT input transition time 10 - 11 25C max min 6 10 - 11 25C max min 32 10 - 11 25C max min 33 tPHL (CHGL) Propagation time CLK high to BG low 12 Idem test 27 Load: 3 Idem test 27 Load: 3 Idem test 27 Load: 4 25C max min 34 tPLH (CHGH) Propagation time CLK high to BG high 12 25C max min 40 tPHL (CLVM) Propagation time CLK low to VMA low 13 25C max min 70 ns 70 ns 70 ns 200 ns 70 ns 70(3) ns 70(3) ns 70(3) ns 70(3) ns 70(3) ns 60(3) ns Min (*) Max (*) Unit
Symbol tPHL (CHSL)
Parameter Propagation time CLK high to LDS, UDS low
18
TS68C000
2170A-HIREL-09/02
TS68C000
Table 8. Dynamic Characteristics - TS68C000-8 (Continued) VCC = 5.0 VDC 10%; GND = 0 VDC; Tc = -55/+125C and Tc = -40C/+85C
Test Number 41 Figure Number (**) 13 Limits Test Conditions Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Load: 3 Idem test 27 Test Temperature 25C max min 8 th (SHAZ) Hold time CLK high to Address 10 - 11 25C max min 11 tSU (AVSL) Set-up time Address valid to AS, LDS, UDS low Propagation time BR low to BG low Propagation time BGACK low to BG high Set-up time BERR low to DTACK low Set-up time BERR low to DTACK low Hold time Data-out valid to LDS, UDS low 10 - 11 25C max min 35 tPHL (BRLGL) 12 25C max min 37 tPLH (GALEH) 12 25C max min 48 tSU (BELDAL) 11 25C max min 48 tSU (BELDAL) 10 - 11 Idem test 27 25C max min 26 th (DOSL) 11 Idem test 27 Load: 4 25C max min Note: * Algebraic values ** Measurement method: see "General Requirements" on page 14 and "Test Conditions Specific to the Device" on page 27 30(4) - ns 20(5) - ns 20(5) - ns 1.5 +90 1.5 +90 3.5 3.5 CLKS
(2)
Symbol tPHL (CLE)
Parameter Propagation time CLK low to E low
Min (*)
Max (*)
Unit
70
ns
0
ns
30(4)
ns
ns CLKS
(2)
ns
Referred notes are given on page 25.
19
2170A-HIREL-09/02
Table 9. Dynamic Characteristics - TS68C000-10
Figure Number (**) 10 - 11 Limits Test Conditions See "Input and Output Signals for Dynamic Measurements" on page 31 (a) to (c) fc = 10 MHz Idem test 27 Test Temperature 25C max min Min (*) 20
(10)
Test Number 27
Symbol tSU (DICL)
Parameter Set-up time Data-in to clock low(1)
Max (*)
Unit ns
47
tSU (SDTCL)
Set-up time DTACK low to clock low(1) Set-up time BR low to clock low
(1)
10 - 11
25C max min
20(10)
ns
47
tSU (SBRCL)
10 - 11
Idem test 27
25C max min
20(10)
ns
47
tSU (SBGCL)
Set-up time BGACK low to clock low(1) Set-up time VPA low to clock low
(1)
10 - 11
Idem test 27
25C max min
20(10)
ns
47
tSU (SVPACL)
10 - 11
Idem test 27
25C max min
20(10)
ns
47
tSU (SBERCL)
Set-up time BERR low to clock low(1)
10 - 11
Idem test 27
25C max min
20(10)
ns
2
tw (CL)
Clock width low
10 - 11
Idem test 27
25C max min
45
125
ns
3
tw (CH)
Clock width high
10 - 11
Idem test 27
25C max min
45
125
ns
6A
tPLH tPHL (CHFCV) tPHL (CHSLX)
Propagation time clock high to FC valid
10 - 11
Idem test 27 Load: 3 Idem test 27 Load: 4
25C max min
60
ns
9
Propagation time clock high to AS low
10 - 11
25C max min
55(3)
ns
20
TS68C000
2170A-HIREL-09/02
TS68C000
Table 9. Dynamic Characteristics - TS68C000-10 (Continued)
Figure Number (**) 10 - 11 Limits Test Conditions Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Test Temperature 25C max min 12 tPLH (CLSH) Propagation time CLK low to AS high 10 - 11 25C max min 12 tPLH (CLSH) Propagation time CLK low to LDS, UDS high Propagation time CLK high to R/W high 10 - 11 25C max min 18 tPLH (CHRHX) 10 - 11 25C max min 20 tPHL (CHRL) Propagation time CLK high to R/W low 10 - 11 25C max min 23 tPZL tPZH (CLDO) tPZL tPZH (CLAV) tHRRF (CHGL) Propagation time CLK low to Data-out valid Propagation time CLK low to Address valid RESET/HALT input transition time 10 - 11 25C max min 6 10 - 11 25C max min 32 10 - 11 25C max min 33 tPHL (CHGL) Propagation time CLK high to BG low 12 Idem test 27 Load: 3 Idem test 27 Load: 3 Idem test 27 Load: 4 25C max min 34 tPLH (CHGH) Propagation time CLK high to BG high 12 25C max min 40 tPHL (CLVM) Propagation time CLK low to VMA low 13 25C max min 70 ns 60 ns 60 ns 200 ns 60 ns 55(3) ns 60(3) ns 60(3) ns 55(3) ns 55(3) ns Min (*) Max (*) 55
(3)
Test Number 9
Symbol tPHL (CHSL)
Parameter Propagation time CLK high to LDS, UDS low
Unit ns
21
2170A-HIREL-09/02
Table 9. Dynamic Characteristics - TS68C000-10 (Continued)
Figure Number (**) 13 Limits Test Conditions Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Load: 3 Idem test 27 Test Temperature 25C max min 8 tH (SHAZ) Hold time CLK high to Address 10 - 11 25C max min 11 tSU (AVSL) Set-up time Address valid to AS, LDS, UDS low Propagation time BR low to BG low Propagation time BGACK low to BG high Set-up time BERR low to DTACK low Set-up time BERR low to DTACK low Hold time Data-out valid to LDS, UDS low 10 - 11 25C max min 35 tPHL (BRLGL) 12 25C max min 37 tPLH (GALGH) 12 25C max min 48 tSU (BELDAL) 11 25C max min 48 tSU (BELDAL) 10 - 11 Idem test 27 25C max min 26 tH (DOSL) 11 Idem test 27 Load: 4 25C max min Note: * Algebraic values ** Measurement method: see "General Requirements" on page 14 and "Test Conditions Specific to the Device" on page 27 20(4) ns 20(5) ns 20(5) +80 ns 1.5 +80 3.5 CLKS
(2)
Test Number 41
Symbol tPHL (CLE)
Parameter Propagation time CLK low to E low
Min (*)
Max (*) 55
Unit ns
0
ns
20(4)
ns
1.5
3.5
CLKS
(2)
ns
ns
Referred notes are given on page 25.
22
TS68C000
2170A-HIREL-09/02
TS68C000
Table 10. Dynamic Characteristics - TS68C000-12
Figure Number (**) 10 - 11 Limits Test Conditions See "Input and Output Signals for Dynamic Measurements" on page 31 (a) to (c) fC = 12 MHz Idem test 27 Test Temperature 25C max min 10(10) ns Min (*) Max (*) Unit
Test Number 27
Symbol tSU (DICL)
Parameter Set-up time Data-in to clock low(1)
47
tSU (SDTCL)
Set-up time DTACK low to clock low(1) Set-up time BR low to clock low(1) Set-up time BGACK low to clock low(1) Set-up time VPA low to clock low(1) Set-up time BERR low to clock low(1)
10 - 11
25C max min 20(10) ns
47
tSU (SBRCL)
10 - 11
Idem test 27
25C max min 20(10) ns
47
tSU (SBGCL)
10 - 11
Idem test 27
25C max min 20(10) ns
47
tSU (SVPACL)
10 - 11
Idem test 27
25C max min 20(10) ns
47
tSU (SBERCL)
10 - 11
Idem test 27
25C max min 20(10) ns
2
tw (CL)
Clock width low
10 - 11
Idem test 27
25C max min 35 125 ns
3
tw (CH)
Clock width high
10 - 11
Idem test 27
25C max min 35 125 ns
6A
tPLH tPHL (CHFCV) tPHL (CHSLX)
Propagation time clock high to FC valid Propagation time clock high to AS low
10 - 11
Idem test 27 Load: 3 Idem test 27 Load: 4
25C max min 55 ns
9
10 - 11
25C max min 55(3) ns
23
2170A-HIREL-09/02
Table 10. Dynamic Characteristics - TS68C000-12 (Continued)
Figure Number (**) 10 - 11 Limits Test Conditions Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Load: 4 Idem test 27 Test Temperature 25C max min 12 tPLH (CLSH) Propagation time CLK low to LDS, UDS high Propagation time CLK low to LDS, UDS high Propagation time CLK high to R/W high Propagation time CLK high to R/W low Propagation time CLK low to Dataout valid Propagation time CLK low to Address valid RESET/HALT transition time 10 - 11 25C max min 12 tPLH (CLSH) 10 - 11 25C max min 18 tPLH (CHRHX) 10 - 11 25C max min 20 tPHL (CHRL) 11 25C max min 23 tPZL tPZH (CLDO) tPZL tPZH (CLAV) tHRRF 11 25C max min 6 10 - 11 25C max min 32 10 - 11 25C max min 33 tPHL (CHGL) Propagation time CLK high to BG low Propagation time CLK high to BG high Propagation time CLK low to VMA low 8-9 Idem test 27 Load: 3 Idem test 27 Load: 3 Idem test 27 Load: 4 25C max min 34 tPLH (CHGH) 12 25C max min 40 tPHL (CLVM) 13 25C max min 70 ns 50 ns 50 ns 150 ns 55 ns 55(3) ns 60(3) ns 60(3) ns 50(3) ns 50(3) ns 55(3) ns Min (*) Max (*) Unit
Test Number 9
Symbol tPHL (CHSL)
Parameter Propagation time CLK high to LDS, UDS low
24
TS68C000
2170A-HIREL-09/02
TS68C000
Table 10. Dynamic Characteristics - TS68C000-12 (Continued)
Figure Number (**) 13 Limits Test Conditions Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Load: 4 Idem test 27 Load: 3 Idem test 27 Load: 3 Idem test 27 Test Temperature 25C max min 8 tH (SHAZ) Hold time CLK high to Address 10 - 11 25C max min 11 tSU (AVSL) Set-up time Address valid to AS, LDS, UDS low Propagation time BR low to BG low Propagation time BGACK low to BG high Set-up time BERR low to DTACK low Set-up time BERR low to DTACK low Hold time Data-out valid to LDS, UDS low 10 - 11 25C max min 35 tPHL (BRLGL) 12 25C max min 37 tPLH (GALGH) 12 25C max min 48 tSU (BELDAL) 11 25C max min 48 tSU (BELDAL) 10 - 11 Idem test 27 25C max min 26 tH (DOSL) 11 Idem test 27 Load: 4 25C max min Note: * Algebraic values ** Measurement method: see "General Requirements" on page 14 and "Test Conditions Specific to the Device" on page 27 15(4) ns 20(5) ns 20(5) ns 1.5 +70 1.5 +70 3.5 3.5 CLKS
(2)
Test Number 41
Symbol tPHL (CLE)
Parameter Propagation time CLK low to E low
Min (*)
Max (*)
Unit
45
ns
0
ns
15(4)
ns
ns CLKS
(2)
ns
Referred notes to Table 7, Table 8, Table 9, Table 10
Notes:
The following notes shall apply where referred into Table 7, Table 8, Table 9 and Table 10.
1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle. 2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of clock signal input multiply by the given number of CLKS limits. 3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maximum columns. 4. Actual value depends on period. 5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds. 6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK.
25
2170A-HIREL-09/02
7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock. 8. When AS and R/W are equally loaded (20%), substrate 10 nanoseconds from the values in these columns. 9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle consists of the application of the bath limits as given in Table 8, Table 9 and Table 10. 10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the maximum time.
Table 11. AC Electrical Specification - Clock Timing
8 MHz Symbol f tcyc tCL tCH tCr tCf Parameter Frequency of Operation Cycle Time Clock Pulse Width Rise and Fall Times Min 4.0 125 55 55 Max 8.0 250 125 125 10 10 10 MHz Min 4.0 100 45 45 Max 10.0 250 125 125 10 10 12.5 MHz Min 4.0 80 35 35 Max 12.5 250 125 125 10 10 Unit MHz ns ns ns
26
TS68C000
2170A-HIREL-09/02
TS68C000
Test Conditions Specific to the Device Loading Network The applicable loading network shall be as defined in column "Test Conditions" of Table 8, Table 9 and Table 10, referring to the loading network number as shown in Figure 8 and Figure 9 below. Figure 8. Passive Loads
+ VCC
Rn OUTPUT C1
Figure 9. Active Loads
+ VCC Rn OUTPUT 1N 914 C1 R1
Load NBR 1 2 3 4 Note:
Figure 5.1 5.1 5.2 5.2
R1 - - 6.0 k 6.0 k
Rn 910 2.9 k 1.22 k 740
C1(1) 130 pF 70 pF 130 pF 130 pF
Output Application RESET HALT A1 to A23, BG and FC0 to FC2 All other outputs
1. C1 includes all parasitic capacitances of test machines
Time Definitions
The times specified in Table 8, Table 9 and Table 10 as dynamic characteristics are defined in Figure 10 to Figure 13 below by a reference number given in the column "Method" of the tables together with the relevant figure number.
27
2170A-HIREL-09/02
Figure 10. Read Cycle Timing
1
S0
3 2
S1
S2
S3
S4
S5
S6
S7
CLK
5 4 7 6
A1-A23
8 10 14 15 9 12 13 15 19 18 17 11 12
AS
LDS/UDS
R/W
FC0-FC2
6A 11A 47
ASYNCHRONOUS INPUTS
HALT/RESET
32 56 47
32 30
BERR/BR
48 27 47 28
DTACK
31 29
DATA IN
28
TS68C000
2170A-HIREL-09/02
TS68C000
Figure 11. Write Cycle Timing
S0 S1 S2 S3 S4 S5 S6 S7 S0
CLK
7 6 10 8 9 14 10 15 9 14A
A1-A23
16
AS
13
LDS/UDS
21
20 22 23 53
R/W
7
21A 26 25
DATA OUT
6A 55
FC0-FC2 ASYNCHRONOUS INPUTS
47 32 32 56 47 30
HALT/RESET
BERR/BR
47 28
DTACK
48
29
2170A-HIREL-09/02
Figure 12. AC Electrical Waveforms - Bus Arbitration
STROBES AND R/W BR
37 46
16
36
BGACK
35 34 39
BG
33 38
CLK
Figure 13. Enable/Interface Timing
S0 S1 S2 S3 S4 w w w w w w w w w w w w w wwwwwww w w w w w w w w S5 S6 S7 S0 41
CLK A1-A23 AS
52 51 44 49 50 42 42 41 45 24 43 40
E
VPA VMA R/W (READ) DATA IN UDS/LDS READ R/W WRITE
23
27
54
DATA OUT UDS/LDS WRITE
30
TS68C000
2170A-HIREL-09/02
TS68C000
Input and Output Signals for Dynamic Measurements 1. Input pulse characteristics Where input pulse generator is loaded by only a 50 resistor, the input pulse characteristics shall be as shown in Figure 14. Figure 14. Input Pulse Characteristics
2.4V 2.0V 0.8V 0.45V tra = 0.5 ns
tra = 0.5 ns
2. Time measurement input voltage references Input voltages which are taken as reference for time measurement shall be: VIL = 0.8V VIH = 2.0V 3. Time measurement input voltage references Where output is (or becomes to) valid state, the output voltages which are taken as reference for time measurements, shall be as shown in Figure 15. Figure 15. Output Voltage References
Voltage Reference High Voltage Reference Low tPLH tPHL tPZH tPZL VOH = 2.4V
VOL = 0.5V
Additional Information Power Considerations Additional Electrical Characteristics
Additional information shall not be for any inspection purposes. See "Thermal Characteristics" on page 13. The following additional characteristics, which are obtained from circuit design, are given for Information only. Unless otherwise stated, for dynamic additional characteristics, the given reference numbers refer to Figure 7 to Figure 13 and loading number refer to Figure 8 and Figure 9 (see "Test Conditions Specific to the Device" on page 27 of this specification). The given limits should be valid for all operating temperature ranges as defined in "Recommended Condition of Use and Guaranteed Characteristics" on page 11 of this specification.
31
2170A-HIREL-09/02
Table 12. Additional Electrical Characteristics
TS68C000-8 Item NO. 6A Ref Number Load Number Limits Min Min Max VCC0.75 Min Min TS68C000-10 Limits Max VCC0.75 Min Min TS68C000-12 Limits Max VCC-0.75 Unit V
Symbol VOH
Parameter High level output voltage for E with pull up R = 1.1K to VCC Propagation time CLK low to Address 3-state Propagation time CLK high to AS, LDS, UDS 3-state Propagation time CLK high to R/W 3-state Propagation time CLK high to Data 3-state Hold time AS, LDS, UDS high to Address AS/DS width low AS, LDS, UDS width high Set-up time LDS, UDS high to R/W high Set-up time Address valid to R/W low Propagation time R/W low to lds, uds low Hold time LDS, UDS high to Data-out Hold time AS, LDS, UDS high to Data-in
37
tPLZ tPHZ (CLAZX) tPHZ (CHSZX)
Fig. 10 Ref. 7
3
80
70
60
ns
39
Fig. 11 Ref. 16
4
80
70
60
ns
40
tPLZ tPHZ (CHRZ) tPHZ tPLZ (CHAZX) tH (SHAZ) tw (SL) tw (SL) tSU (SHRH) tSU (AVRL) tPHL (RLSL) tH (SHDO) tH (SHDI)
Fig. 12 Ref. 16 Fig. 11 Ref. 7 Fig. 10 Ref. 13 Fig. 10 Ref. 14 Fig. 10 Ref. 15 Fig. 10 Ref. 17 Fig. 10 Ref. 21 Fig. 11 Ref. 22 Fig. 11 Ref. 25 Fig. 10 Ref. 29
4
80
70
60
ns
41
4
80
70
60
ns
43
3
30
20
10
ns
44 45 46
240
(4)
195
(4)
160
(4)
ns ns ns
150
(4)
105
(4)
65
(4)
4
40
(4)
20
(4)
10
(4)
47
4
20
(4)
0
(4)
0
(4)
ns
48
4
80
(4)
50
(4)
30
(4)
ns
49
4
30
(4)
20
(4)
15
(4)
ns
50
0
0
0
ns
32
TS68C000
2170A-HIREL-09/02
TS68C000
Table 12. Additional Electrical Characteristics (Continued)
TS68C000-8 Item NO. 52 Ref Number Fig. 12 Ref. 36 Fig. 12 Ref. 36 Load Number 3 Limits Min 1.5 Max 3.5 + 90 Min 1.5 TS68C000-10 Limits Max 3.5 + 80 Min 1.5 TS68C000-12 Limits Max 3.5 + 70 Unit CLKS
(2)
Symbol tH (BRHGH) tPHZ tPLZ (GLZ)
Parameter Propagation time BR high to BG high(6) Propagation time BG low to Data and Address 3-state BG width high Propagation time VMA low to E high Hold time AS, LDS, UDS high to VPA high
ns BG, address 3 Data 4 1.5 4 200 80 70 60 ns
54
55 56
tw (GH) tPLH (VMLEH) tH (SHVPH)
Fig. 12 Ref. 39 Fig. 13 Ref. 43 Fig. 20 Ref. 44 (see "Although UDS and LDS are asserted, no data is read from the bus during the autovector cycle. The vector number is generated internally)." on page 45) Fig. 13 Ref. 45 Fig. 12 Ref. 46 Fig. 13 Ref. 50 Fig. 13 Ref. 51 Fig. 10 Ref. 1A or 11A Fig. 10 Ref. 28 4
1.5 150
1.5 90
CLKS ns ns
57
4
0
120
0
90
0
70
ns
58 59 61 62 63
tH (ELAI) tw (BGL) tw (EH) tw (EL) tPHL (FCVSL)
Hold time E low to address BGACK width low E width high E width low Propagation time FC valid to AS, DS low Propagation time AS, DS high to DTACK high Propagation time AS, DS high to BERR high
3
30 1.5 450 700 60
(4)
10 1.5 350 550 50
(4)
10 1.5 280 440 40
(4)
ns CLKS
(2)
ns ns ns
64
tPHL (SHDAH)
4
0
245(4)
0
190(4)
0
150(4)
ns
65
tPLH (SHBEH)
Fig. 12 Ref. 30
4
0
0
0
ns
33
2170A-HIREL-09/02
Table 12. Additional Electrical Characteristics (Continued)
TS68C000-8 Item NO. 66 Ref Number Fig. 10 Ref. 31 Fig. 10 Ref. 32 Fig. 10 Ref. 56 10 Load Number Limits Min Max 90
(4)
TS68C000-10 Limits Min Max 65
(4)
TS68C000-12 Limits Min Max 50
(4)
Symbol tSU (DALDI) tTHL tTLH (RH) tw (HRPW)
Parameter Set-up time DTACK low to Data-in(1) Transition time HALT, RESET input HALT and RESET pulse width after power up Propagation time AS low to R/W valid Propagation time FC valid to R/W low Hold time CLK high to Data-out Propagation time R/W low to Data-bus impedance change Propagation time AS, DS low to E low Hold time E low to Data-out
Unit ns
67
200
200
200
ns
69
10
10
CLKS
(2)
70
tPHL (ASRV) tPHL (FCVRL) tH (CHDOI) tPLH tPHL (RLDBO)
Fig. 11 Ref. 20A Fig. 11 Ref. 21A Fig. 11 Ref. 53 Fig. 11 Ref. 55
4
20(8)
20(8)
20(8)
ns
71
4
60
(4)
50
(4)
30
(4)
ns
73
4
0
0
0
ns
74
4
30
20
10
ns
75
tPHL (SHEL) tH (ELDOI)
Fig. 13 Ref. 49 Fig. 13 Ref. 54
4(7)
-70
+70
-55
+55
-45
+45
ns
76
4
30
20
15
ns
Notes:
1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle. 2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of clock signal input multiply by the given number of CLKS limits. 3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maximum columns. 4. Actual value depends on period. 5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds. 6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK. 7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock. 8. When AS and R/W are equally loaded (20%), substrate 10 nanoseconds from the values in these columns. 9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle consists of the application of the bath limits as given in Table 8, Table 9 and Table 10.
34
TS68C000
2170A-HIREL-09/02
TS68C000
10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the maximum time.
Functional Description
Description of Registers Figure 16. User Programming Model
31 16 15 8 7 0 D0 D1 D2 D3 Eight Data Registers D4 D5 D6 D7
31
16
15
0 A0 A1 A2 A3 Seven Address Registers A4 A5 A6
31
16
15
0 A7 (USP) User Stack Pointer
31
0 PC 7 0 CCR Status Register Program Counter
As shown in the user programming model (Figure 16), the TS68C000 offers 16/32 bits registers and a 32 bits program counter. The first eight registers (D0 - D7) are used as data registers for byte (8-bit), and long word (32-bit) operations. The second set of seven registers (A0-A6) and the user stack pointer (USP) may be used as software stack pointers and base address registers. In addition, the registers may be used for word and long word operations. All of the 16 registers may be used as index registers. In supervisor mode, the upper byte of the status register and the supervisor stack pointer (SSP) are also available to the programmer. These registers are shown in Figure 17. 35
2170A-HIREL-09/02
Figure 17. Supervisor Programming Model Supplement
31 Supervisor Stack Pointer 15 Status Register 87 (CCR) 0 SR 16 15 0 A7 (SSP)
The status register (Figure 18) contains the interrupt mask (eight levels available) as well as the conditions codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional status bits indicate that the processor is in a trace (T) mode and in a supervisor (S) or user state. Figure 18. Status Register
System Byte User Byte (Condition Code Regiter)
15 T
13 S
10 8 I2 I 1 I0
4 X
0 NZVC
Trace Mode Supervisor State Interrupt Mask
Extend
Negative Zero Overflow Carry
Data Types and Addressing Modes
Five basic data types are supported. These data types are: * * * * * Bits BCD Digits (4 bits) Bytes (8 bits) Words (16 bits) Long Words (32 bits)
In addition, operations on other data types such as memory addresses, status ward data, etc. are provided in the instruction set. The 14 addressing modes, shown in Table 13, include six basic types: * * * * * * Register Direct Register Indirect Absolute program Counter Relative Immediate Implied
36
TS68C000
2170A-HIREL-09/02
TS68C000
Included in the register indirect addressing modes is the capability to do post incrementing, predecrementing, offsetting, and indexing. The program counter relative mode can also be modified via Indexing and offsetting. Data Transfer Operations Transfer of data between devices involves the following leads: 1. address bus A1 through A23, 2. data bus 00 through D15, and 3. control signals. The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at bath the stan and end of a cycle. In addition, the bus master Is responsible for deskewing the acknowledge and data signals tram the slave device. The following paragraphs explain the read, write, and read-modify.write cycles. The indivisible read-modify-write cycle is the method used by the TS68C000 for interlocked multiprocessor communications. Read Cycle During a read cycle, the processor receives data tram the memory of a peripheral devlce. The processor reads bytes of data in all cases. If the instruction specifies a ward (or double ward) operation, the processor reads both upper and lower bytes simultaneously. by asserting both upper and lower data strobes. When the instruction specifies byte operation, the processor uses an internal AO bit to determine which byte to read and then Issues the data strobe required for that byte. For byte operations, when the AO bit equals zero, the upper data strobes is issued. When the AO bit equals one, the lower data strobe is issued. When the data is received, the processor correctly positions is internally. During a write cycle, the processor sends data to either the memory of a peripheral device. The processor writes bytes of data in all cases. If the instruction specifies a ward operation, the processor writes bath bytes. When the instruction specifies a byte operation, the processor uses an internal AO bit to determine which byte to write and then issues the data strobe required for that byte. For byte operations, when the AO bit equals zero, the upper data strobe is issued. When the AO bit equals one, the lower data strobe is issued.
Write Cycle
Table 13. Addressing Modes
Addressing Modes Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with Offset Relative with Index Offset Syntax Dn An xxx.W xxx.L d16 (PC) d8 (PC, Xn)
37
2170A-HIREL-09/02
Table 13. Addressing Modes (Continued)
Addressing Modes Register Indirect Addressing Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Indexed Register Indirect with Offset Immediate Data Addressing Immediate Quick Immediate Implied Addressing Implied Register Notes: Syntax (An) (An) + - (An) d16 (An) d8 (An, Xn) = XXX = 1- = 8 SR/USP/SP/PC
Dn = Data Register An = Address Register Xn = Address of Data Register used as Index Register SR = Status Register PC = Program Counter SP = Stack Pointer USP = User Stack Pointer ( ) = Effective Address d8 = 8-bit Offset (Displacement) d16 = 16-bit Offset (Displacement) = xxx = Immediate Data Table 14. Instruction Set Summary
Mnemonic ABCD ADD AND ASL ASR Bcc BCHG BCLR BRA BSET BSR BTST CHK CLR CMP Description Add Decimal with Extend Add Logical AND Arithmetic Shift Left Arithmetic Shift Right Branch Conditionally Bit Test and Change Bit Test and Clear Branch Always Bit Test and Set Branch to Subroutine Bit Test Check Register Against Bounds Clear Operand Compare
38
TS68C000
2170A-HIREL-09/02
TS68C000
Table 14. Instruction Set Summary (Continued)
Mnemonic DBcc DIVS DIVU EOR EXG EXT JMP JSR LEA LINK LSL LSR MOVE MULS MULU NBCD NEG NOP NOT OR PEA RESET ROL ROR ROXL ROXR RTE RTR RTS SBCD Scc STOP SUB SWAP TAS TRAP TRAPV TST UNLK Description Test Condition, Decrement and Branch Signed Divide Unsigned Divide Exclusive OR Exchange Registers Sign Extend Jump Jump to Subroutine Lead Effective Address Link Stack Logical Shift Left Logical Shift Right Move Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate No Operation One's Complement Logical OR Push Effective Address Rest External Devices Rotate Left without Extend Rotate Right without Extend Rotate Left with Extend Rotate Right with Extend Return from Exception Return and Restore Return form Subroutine Subtract Decimal with Extend Set Conditional Stop Subtract Swap Data Register Halves Test and Set Operand Trap Trap on Overflow Test Unlink
39
2170A-HIREL-09/02
Read Modify Write Cycle
The read-modify-write cycle performs a read, modifies the data in the arithmetic-logic unit, and writes the data back to the same address. In the TS68C000, this cycle is indivisible in that the address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a multiple processor environment. This Instruction is the only instruction that uses the read-modify-write cycles and since the test and set instruction only operates on bytes, all read-modify-write are byte operations. The TS68C000 instruction set is shown in Table 14. Some additional instructions are variations, or sub-sets, of these and they appear in Table 15. Special emphasis has been given to the instruction set's support of structured high-level languages to facilitate ease of programming. Each instruction, with few exceptions, operates on bytes, words, and long words and most instructions can use any of the 14 addressing modes. Combining instruction types, data types, and addressing modes, over 1000 useful instructions are provided. These instructions include signed and unsigned, multiply and divide, "quick" arithmetic operations, BCD arithmetic, and expanded operations (through traps).
Instruction Set Overview
Table 15. Variations of Instruction Types
Instruction Type ADD Variation ADD ADDA ADDQ ADDI ADDX AND ANDI ANDI to CCR ANDI to SR CMP CMPA CMPM CMPI EOR EORI EORI to CCR EORI to SR MOVE MOVEA MOVEM MOVEP MOVEQ MOVE from SR MOVE to SR MOVE to CCR MOVE USP Description Add Add Address Add Quick Add Immediate Add with Extend Logical AND And Immediate And Immediate to Condition codes And Immediate to Status Register Compare Compare Address Compare Memory Compare Immediate Exclusive OR Exclusive OR Immediate Exclusive OR Immediate to condition Codes Exclusive OR Immediate to Status Register Move Move Address Move Multiple Registers Move Peripheral Data Move Quick Move from Status Register Move to Status Register Move to Condition Codes Move User Stack Pointer
AND
CMP
EOR
MOVE
40
TS68C000
2170A-HIREL-09/02
TS68C000
Table 15. Variations of Instruction Types (Continued)
Instruction Type NEG OR Variation NEG NEGX OR ORI ORI to CCR ORI to SR SUB SUBA SUBI SUBQ SUBX Description Negate Negate with Extend Logical OR OR Immediate OR Immediate to Condition Codes OR Immediate to Status Register Subtract Subtract Address Subtract Immediate Subtract Quick Subtract Extend
SUB
Processing States Normal Processing
The TS68C000 is always in one of three processing states: normal, exception, or halted. The normal processing state is that associated with instruction execution; the memory references are to fetch instructions and operands, and to store results. A special case of normal state is the stopped state which the processor enters when a stop instruction is executed. In this state, no further references are made. The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, by a bus error, or by a reset. Exception processing is designed to provide an efficient context switch so that the processor may handle unusual conditions. The halted processing state is an Indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus errors occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a processor in the stopped state is not in the halted state, nor vice versa. Asserting the reset and halt line for ten cycles will cause a processor reset, except when VCC is initially applied to the processor. In this case, an external reset must be applied for least 100 milliseconds.
Exception Processing
Halted Processing
Interface with EF 6800 Peripherals
Extensive line of EF6800 peripherals are directly compatible with the TS68C000.
Note: It is the own user's responsibility to verify the actual EF 6800 peripheral performances to be compatible to the actual used TS68C000 microprocessor performances. Soma of the EF 6800 peripheral that are particularly useful are: EF6821: Peripheral lnterface Adapter EF6840: Programmable Timer Module EF6850: Asynchronous Communications Interface Adapter EF6852: Synchronous Serial Data Adapter EF6854: Advanced Data Link Controller 41
2170A-HIREL-09/02
To interface the synchronous EF 6800 peripherals with the asynchronous TS68C000, the processor modifies its bus cycle to meet the EF 6800 cycle requirements whenever an EF 6800 device address is detected. This is possible since both processors use memory mapped 1/0. Figure 19 is a flowchart of the interface operation between the processor and EF 6800 devices. Figure 19. EF6800 Interfacing Flowchart
PROCESSOR Initiate the cycle 1) The Processor Starts a Normal Read or Write Cycle Define EF 6800 Cycle Synchronize with Enable 1) The Processor Monitors Enable (E) until it is low (Phase 1) 2) The Processor Asserts Valid Memory Address (VMA) Transfer the Data Terminate the Cycle 1) The Processor waits until E goes low (on a read cycle the data is latched as E goes low (internally) 2) The Processor negates VMA 3) The Processor negates AS, UDS and LDS 1) The Peripheral waits until E is active and then transfers the Data 1) External Hardware Asserts Valid Peripheral Address (VPA) SLAVE
Start Next Cycle
Data Transfer Operation
Three signals on processor provide the EF 6800 interface. They are: enable (E), valid memory address (VMA), and valid peripheral address (VPA). Enable corresponds to the E or phase 2 signal i n existing EF 6800 systems. The bus frequency is one tenth of the incoming TS68C000 clock frequency. The timing of E allows 1 MHz peripherals to be used 8 MHz TS68C000. Enable has a 60/40 duty cycle, that is, it is low for six input clocks and high for four input clocks. This duty cycle allows the processor to do successive VPA accesses on successive E pulses. EF6800 cycle timing is given in Figure 23 and Figure 24. At state zero (50) in the cycle, the address bus is in the high-impedance state. A function code is asserted on the function code output fines. One-half clock later, in state 1, the address bus is released from the high-impedance state. During state 2, the address strobe (AS) is asserted to indicate that there Is a valid address on the address bus. If the bus cycle is a read cycle, the upper and/or lower data strobes are also asserted in state 2. If the bus cycle is a write cycle, the read/write (R/W) signal is switched to low (write) during state 2. One-half clock later, in state 3, the write data Is placed on the data bus, and in state 4 the data strobes are issued to indicate valid data on the data bus. The processor now inserts wait states until it recognizes the assertion of VPA.
42
TS68C000
2170A-HIREL-09/02
TS68C000
The VPA input signals the processor that the address on the bus is the address of an EF 6800 device (or an area reserved for EF6800 devices) and that the bus should conform to the phase 2 transfer characteristics of the EF 6800 bus. Valid peripheral address is derived by decoding the address bus, conditioned by the address strobe. Chip select for the EF 6800 peripherals should be derived by decoding the address bus conditioned by VMA. After recognition of VPA, the processor assures that the enable (E) is low, by waiting if necessary, and subsequently asserts VMA. Valid memory address is then used as part of the chip select equation of the peripheral. This ensures that the EF6800 peripherals are selected and deselected at the correct time. The peripheral now runs its cycle during the high portion of the signal. Figure 23 and Figure 24 depict the best and worst case EF6800 cycle timing. This cycle length is dependent strictly upon when VPA Is asserted in relationship to the E clock. If it is assumed that external circuitry asserts VPA as soon as possible after the assertion of AS, then VPA will be recognized as being asserted on the falling edge of 54. In this case, no "extra" wait cycles will be inserted prior to the recognition of VPA asserted and only the wait cycles inserted to synchronize with the E clock will determine the total length of the cycle. In any case, the synchronization delay will be some integral number of clock cycles within the following two extremes: 1. Best Case - VPA is recognized as being asserted on the falling edge three crack cycles before E rizes (or three clock cycles after E falls). 2. Worst Case - VPA is recognized as being asserted on the falling edge two clock cycles before E rises (or four clock cycles after E falls). During a read cycle, the processor latches the peripheral data in state 6. For all cycles, the processor negates the address and data strobes one-half clack cycle rater in state 7 and the enable signal goes low at this time. Another half clock later, the address bus is put in the high-impedance state. During a write cycle the data bus is put in the highimpedance state and the read/write signal is switched high. The peripheral logic must remove VPA within one clock after the address strobe is negated. DTACK should not be asserted while VPA Is asserted. Notice that the TS68C000 VMA is active low, constrasted with the active high EF 6800 VMA. This allows the processor to put its buses in the high-impedance state on DMA requests without inadvertently selecting the peripherals.
43
2170A-HIREL-09/02
Figure 20. TS68C000 to EF6800 Peripheral Timing - Best Case
S0 CLK A1-A23 AS DTACK Data Out Data In FC0-FC2 E VPA VMA S2 S4 w w w w w S6 S0 S2
Figure 21. TS68C000 to EF6800 Peripheral Timing - Worst Case
S0 S2 S4 w w w w w w w w w w w w w w w S6 S0 CLK A1-A23 AS DTACK Data Out Data In FC0-FC2 E VPA VMA
Interrupt Interface Operation
During an interrupt acknowledge cycle while the processor is fetching the vector, the VPA is asserted, the TS68C000 will assert VMA and complete a normal EF 6800 read cycle as shown in Figure 22. The processor will then use an internally generated vector that is a function of the interrupt being serviced. This process is know as autovectorlng. The seven autovectors are vector number 25 through 31 (decimal). Autovectoring operates in the same fashion (but is not restricted to) the EF 6800 interrupt sequence. The basic difference is that there are six normal interrupt vectors and one NMI type vector. As with bath the EF 6800 and the TS68C(XX)'s normal vectored interrupt, the Interrupt service routine can be located any-where in the address space. This is due to the tact that while the vector numbers are fixed the contents of the vector table entries are assigned by the user.
44
TS68C000
2170A-HIREL-09/02
TS68C000
Since VMA is asserted during autovectoring. The EF 6800 peripheral address decoding should prevent unintended accesses. Figure 22. Autovector Operation Timing Diagram
S0 S2 S4 S6 S0 S2 S4 w CLK A1-A3 A4-A23 AS UDS* LDS R/W DTACK D8-D15 D0-D7 FC0-FC2 IPL0-IPL2 E VPA VMA Normal Cycle Autovector Operation w w w w ww w w w S6 S0 S2
Although UDS and LDS are asserted, no data is read from the bus during the autovector cycle. The vector number is generated internally). Table 16. Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral
8 MHz Limits Number 12 18 20 23 27 29 40 41 42 43 Symbol CLSH CHRH CHRL CLDO CLDO SHDII CLVML CLET Erf VMLEH Parameter Clock low to AS, DS high(1) Clock high to R/W high
(1) (1)
10 MHz Limits Min Max 55 0 60 60 55 10 0 70 70 25 70 55 25 150
12.5 MHz Limits Min Max 50 0 60 60 55 10 0 70 45 25 90 Unit ns ns ns ns ns ns ns ns ns ns
Min
Max 70
0
70 70 70
Clock high to R/W low (write)
Clock low to data out valid (write) Data in to clock low (set up time on read)(2) AS, DS high to Data in invalid (hold time on read) AS, DS high to VPA high Clock low to E transition E output rise and fall time VMA low to E high 200 15 0
45
2170A-HIREL-09/02
Table 16. Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral (Continued)
8 MHz Limits Number 44 45 47 49 50 51 54 Notes: Symbol SHVPH ELCAI ASI SHEL EH EL ELDOI Parameter AS, DS high to VPA high E low to control, address bus invalid (address hold time) Asynchronous input setup time(2) AS, DS high to E low(3) E width high E width low E low to data out invalid Min 0 30 20 -70 450 700 30 70 Max 120 10 MHz Limits Min 0 10 20 -55 350 550 20 55 Max 90 12.5 MHz Limits Min 0 10 20 -80 280 440 15 Max 70 Unit ns ns ns ns ns ns ns
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the maximum columns. 2. If the asynchronous setup time (47) requirements are satisfied, the DTACK low-to-data setup time (31) required can be ignored. The data must only satisfy the date in clock-low setup time (27) for the following cycle. 3. The falling edge of S6 triggers both the negation of the strobes (AS and X DS) and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal specification 49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock.
Figure 23. TS68C000 to EF6800 Peripheral Timing Diagram - Best Case
S0 CLK 45 A1-A23 41 AS 41 12 49 S1 S2 S3 S4
w
w
w
w
w
w
w
w
w
w
w
w S5
S6
S7 S0
R/W 18 E 42 VPA 40 43 VMA 54 DATA OUT 23 DATA IN 27 29 45 41 20 51 50 41 42 44 18
Note:
This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly attainable.
46
TS68C000
2170A-HIREL-09/02
TS68C000
Figure 24. TS68C000 to EF6800 Peripheral Timing Diagram - Worse Case
S0 S1 S2 S3 S4 w w w w w w w w w w w w w w w w w w w w w w w w w w w w S5 S6 S7S0 CLK 45 A1-A23 12 AS 18 R/W 41 E 47 VPA 40 VMA 23 DATA OUT 27 DATA IN 29 43 54 42 42 45 41 51 50 44 49 20 18
Note:
This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly attainable.
Preparation For Delivery
Packaging Certificate of Compliance Microcircuit are prepared for delivery in accordance with MIL-PRF-38535. Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance with MIL-STD-883 and guarantying the parameters not tested at extreme temperatures for the entire temperature range. MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Device should be handled on benches with conductive and grounded surface. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50%, if practical.
Handling
47
2170A-HIREL-09/02
Package Mechanical Data
Figure 25. 68-lead - Pin Grid Array
TOP VIEW .180 010 4.57 0.25 .050 010 1.27 0.254 .900 Typ 22.86 Typ
65 4
BOTTOM VIEW
Index corner
10
9
8
7
3
2
1
0.46 0.13
A B C D E F G H J K .065 005 1.65 0.13
.018 001
.100 Typ
26.92 0.25
1.060 010
.050 005
1.27 0.13
1.060 .010 26.92 0.25 .097 008 2.46 0.20
.080 008 2.03 0.20
Figure 26. 64-lead - Ceramic Side Brazed Package
.050 .010 1.27 0.25 .150 Min 3.81 Min .080 009 2.03 0.23
.010 002 0.25 0.05 .900 .010 22.86 0.25
2170A-HIREL-09/02
2.54 Typ 1.90 Max 4.83 Max
.100 .002 2.54 0.05
.018 002 0.46 0.05
64
33
22.73 0.25
.895 .010
1 Pin N 1 Index 3.200 030 81.28 0.76
32
48
TS68C000
TS68C000
Figure 27. 68-lead - Leadless Ceramic Chip Carrier
BOTTOM VIEW TOP VIEW
+.012 -.010
+0.30 -0.25
24.13
.950
1 2
.050 005 1.27 0.13 +.012 .950 -.010 24.13 +0.30 -0.25
.085 .009 2.16 0.23
.800 008 20.32 0.2
Figure 28. 68-lead - Ceramic Quad Flat Pack
1.133-1.147 28.78-29.13
68 1
52 51
.027-.037 0.69-0.94
Pin N 1 index
.940-.960 23.88-24.38
.005-.010 0.13-0.25
.050 BSC 1.27 BSC
1.133-1.147 28.78-29.13
.940-.960 23.88-24.38
.800 BSC 20.32 BSC
CQFP 68
0-8
17 18 .021-.025 0.53-0.64 .008 M 34
35
.018-.035 .046-0.88
ZXY
.135 3.43
.004
49
2170A-HIREL-09/02
Ordering Information
MIL-STD-883
TS68C000 M C1 B/C 8 A
Device Type M = -55/+125C
Revision level Operating frequency (MHz) MIL-STD-883 Class B Package: C: Ceramic DIL R: PGA E: LCCC C1: Ceramic DIL, tin dipped leads E1: LCCC, tin dipped leads F: CQFP
DESC
TS68C000DESC
02
T
A
A
Device Type Part number for DESC Drawing 82021 Device Type: 01: 8 MHz 02: 10 MHz 03: 12.5 MHz
Revision level Lead finish per MIL-M-38510 A = tin dipped C = gold plated
Note: Temperature range is -55C TC +125C for DESC product
Case outlines: U: PGA 68 Y: CDIL 64 X: LCCC 68 (on request) Z: CQFP 68 (on request)
50
TS68C000
2170A-HIREL-09/02
TS68C000
Standard Product
TS68C000 M C 8 A
Device Type M = -55C/+125C V = -40C/+85C
Revision level
Operating frequency (MHz) Package: C: Ceramic DIL R: PGA E: LCCC F: CQFP (on request)
Note:
1. For availability of the different versions, contact your Atmel sale office.
51
2170A-HIREL-09/02
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2170A-HIREL-09/02 0M

▲Up To Search▲

Price & Availability of TS68C000

	To Download TS68C000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .