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TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
D Single-Chip RF Transmitter for 433 MHz D D D D D D D D
ISM Band 420-MHz to 450-MHz Operation FM/FSK Operation for Transmit 24-Bit Direct Digital Synthesizer (DDS) With 11-Bit DAC On-Chip Voltage-Controlled Oscillator (VCO) and Phase-Locked Loop (PLL) On-Chip Reference Oscillator Minimal External Components Required Low Power Consumption Typical Output Power of 7 dBm
PW PACKAGE (TOP VIEW)
D Typical Output Frequency Resolution of
230 Hz
D Ultrafast Lock Times From DDS D D D D
Implementation Two Fully-Programmable Operational Modes 2.2-V to 3.6-V Operation Flexible Serial Interface to TI MSP430 Microcontroller 24-Pin Plastic Thin-Shrink Small-Outline Package (TSSOP)
PD_OUT1 PLL_VCC PD_SET VCO_TANK1 VCO_TANK2 PLL_GND DIG_GND CLOCK DATA STROBE MODE STDBY
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
PD_OUT2 LOCKDET PA_OUT PA_GND PA_VCC GND DIG_VCC XOSC2 XOSC1 DIG_GND TX_DATA NC
description
The TRF4400 single-chip solution is an integrated circuit intended for use as a low cost FSK transmitter to establish a frequency-agile RF link. The device is available in a 24-lead TSSOP package and is designed to provide a fully-functional multichannel transmitter. The chip is intended for linear (FM) or digital (FSK) modulated applications in the 433-MHz ISM band. The single-chip transmitter operates down to 2.2 V and is expressly designed for low power consumption. The synthesizer has a typical channel spacing of approximately 230 Hz to allow narrow-band as well as wide-band applications. Due to the narrow channel spacing of the direct digital synthesizer (DDS), the DDS can be used to adjust the TX frequency and allows the use of inexpensive reference crystals. Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings (e.g., TX_frequency_0/TX_frequency_1) without reprogramming the device. Each functional block of the transmitter can be specifically enabled or disabled via the serial interface.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
transmitter
The transmitter consists of an integrated VCO, a complete fully-programmable direct digital synthesizer, and a power amplifier. The internal VCO can be used with an external tank circuit or an external VCO. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete DDS with a typical frequency resolution of 230 Hz. The 8-bit FSK frequency deviation register determines the frequency deviation in FSK mode. The modulation itself is done in the direct digital synthesizer, hence no additional external components are necessary. Since the typical RF output power is approximately 7 dBm, no additional external RF power amplifier is necessary in most applications. The TRF4400 RF transmitter is suitable for use in applications that include the TRF6900 RF transceiver.
baseband interface
The TRF4400 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller (see Figure 1). The TRF4400 serial control registers are programmed by the MSP430, and the MSP430 performs baseband operations in software.
Antenna Microcontroller Section Transmit Data Lock Detect Mode Select Standby Serial Control Data Serial Control Clock Serial Control Strobe MSP430 Family C
RF Section TX_DATA LOCKDET RF Out PA_OUT TRF4400 TRANSMITTER + DISCRETES MODE STDBY DATA CLOCK STROBE
Programmable Digital I/O Pins
Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller
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functional block diagram
PD_OUT1 PLL_VCC PD_SET VCO_TANK1 VCO_TANK2 PLL_GND DIG_GND CLOCK DATA STROBE MODE STDBY 1 2 3 4 VCO 5 6 PLL Power Amplifier 22 21 20 PA_OUT PA_GND PA_VCC GND DIG_GND XOSC2 XOSC1 DIG_GND TX_DATA NC 24 23 PD_OUT2 LOCKDET
TRF4400
7 8 9 10 11 12 Serial Interface Direct Digital Synthesizer and Power-Down Logic
19 18 17 16 15 14 13
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TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
Terminal Functions
TERMINAL NAME CLOCK DATA DIG_GND DIG_VCC GND LOCKDET MODE NC PA_GND PA_OUT PA_VCC PD_OUT1 PD_OUT2 PD_SET PLL_GND PLL_VCC STDBY STROBE TX_DATA VCO_TANK1 VCO_TANK2 XOSC1 XOSC2 NO. 8 9 7, 15 18 19 23 11 13 21 22 20 1 24 3 6 2 12 10 14 4 5 16 17 I I I I I O I O O O O I I/O I I Serial interface clock signal Serial interface data signal Digital ground Digital supply voltage Ground PLL lock detect output, active high. PLL locked when LOCKDET = 1. Mode select input. The functionality of the device in Mode0 or Mode1 can be programmed via the A-, B-, C-, and D-words of the serial control interface. No connection Power amplifier ground Power amplifier output, open collector Power amplifier supply voltage Charge pump output - PLL in locked condition Charge pump output - PLL in unlocked condition Charge pump current setting terminal. An external resistor (RPD) is connected to this terminal to set the nominal charge pump current. PLL ground PLL supply voltage Standby control for the TRF4400, active low. While STDBY = 0, the contents of the control registers are still valid and can be programmed via the serial control interface. Serial interface strobe signal Digital modulation input for FSK/FM modulation of the carrier, active high VCO tank circuit connection. Should be left open if an external VCO is used. VCO tank circuit connection. May also be used to input an external VCO signal. Reference crystal oscillator connection Reference crystal oscillator connection. May be used as a single-ended clock input if an external crystal is not used. DESCRIPTION
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, PA_VCC, PLL_VCC, DIG_VCC, VCC (see Note 1) . . . . . . . . . . . . . . . . -0.6 to 4.5 Vdc Input voltage, VI (logic signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6 to 4.5 Vdc Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C ESD integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV HBM
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RF terminal 22, PA_OUT, is not protected against voltage stress higher than 800 V HBM. NOTE 1: All GND and VCC terminals must be connected to either ground or supply, respectively, even if the function block is not used.
recommended operating conditions
MIN Supply voltage, PA_VCC, PLL_VCC, DIG_VCC, DDS_VCC, VCC Operating temperature High-level input voltage, VIH (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY) Low-level input voltage, VIL (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY) High-level output voltage, VOH (LOCKDET); IOH = 0.5 mA Low-level output voltage, VOL (LOCKDET); IOL = 0.5 mA VCC-0.5 0.5 2.2 -20 VCC-0.5 0.5 TYP MAX 3.6 60 UNIT V C V V V V
electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DIG_VCC, VCC = 3 V, TA = 25C) (unless otherwise noted)
supply current consumption in each mode
MODE Power down (standby mode) PA STATE 0 dB attenuation TX 10 dB attenuation 20 dB attenuation PA disabled DDS, PLL, VCO, PA , , , 57 29 22 10 12.5 75 mA None ACTIVE STAGES MIN TYP 0.5 MAX UNIT A
VCO
PARAMETER Frequency range Phase noise Tuning voltage 50-kHz offset 0.5 TEST CONDITIONS MIN 420 TYP 433 -100 VCC - 0.4 MAX 450 UNIT MHz dBc/Hz V
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electrical characteristics over full range of operating conditions, (typical values are at PA_VCC, PLL_VCC, DIG_VCC, VCC = 3 V, TA = 25C) (unless otherwise noted) (continued)
direct digital synthesizer (DDS)
PARAMETER Reference oscillator input frequency ref frequency, Programmable DDS divider ratio DDS divider resolution, FSK - modulation register ratio FSK - modulation resolution 8 bits As oscillator As buffer 22 bits TEST CONDITIONS MIN 15 15 0 0 N x ref / 222 N x ref / 224 1020 TYP MAX 26 26 4194303 MHz UNIT
PLL
PARAMETER RF input frequency RF input power RF input divider ratio, N RF output frequency resolution Charge pump current Programmable with external resistor, 100-k nominal, APLL = 0 Internal VCO bypassed; external input applied to VCO_TANK2 256 N x ref / 224 70 A TEST CONDITIONS MIN 420 TYP 433 -10 512 MAX 450 UNIT MHz dBm
power amplifier
PARAMETER Frequency range 0-dB attenuation 10-dB attenuation Amplifier output power (see Note 2) 20-dB attenuation Amplifier off Optimal load impedance 2nd-order harmonic 3rd-order harmonic VCC = 3 V, 0-dB attenuation VCC = 3 V, 0-dB attenuation TEST CONDITIONS MIN 420 TYP 433 7 -3 -12 -70 See Figure 11 -10 -20 dBc dBc dBm MAX 450 UNIT MHz
NOTE 2: The device and output matching network (see Application Information section) is designed to provide the output power into a 50- load. The device stability was tested (no parasitic oscillations) with an output VSWR of 10:1 over all phase angles and is not tested in production.
typical mode switching and lock times
OPERATION Standby to transmit time TEST CONDITIONS From rising edge of STDBY to valid RF signal at PA_OUT, APLL = 111b (maximum) MIN TYP 500 MAX UNIT s
Highly dependent upon loop filter topology
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timing data for serial interface (see Figure 2)
PARAMETER f(CLOCK) tw(CLKHI) tw(CLKLO) tsu(DATA) th(DATA) tw(STROBEHI) CLOCK frequency CLOCK high-time pulse width, CLOCK high CLOCK low-time pulse width, CLOCK low Setup time, data valid before CLOCK high Hold time, data valid after CLOCK high Strobe high-time pulse width, STROBE high (see Note 3) 25 25 25 25 25 25 MIN MAX 20 UNIT MHz ns ns ns ns ns ns
tw(STROBELO) Strobe low-time pulse width, STROBE low NOTE 3: CLOCK and DATA must both be low when STROBE is asserted (STROBE = 1).
tw(CLKLO) tw(CLKHI) tw(STROBEHI) CLOCK tsu(DATA) DATA
th(DATA) STROBE
tw(STROBELO)
Figure 2. Serial Data Interface Timing
detailed description
reference oscillator The reference oscillator provides the DDS system clock. It allows operation, with a suitable external crystal, between 15 MHz and 26 MHz. An external oscillator can be used to supply clock frequencies between 15 MHz and 26 MHz. The external oscillator should be directly connected to XOSC2, terminal 17. The other oscillator terminal (XOSC1, terminal 16) should be left open or can be used as a buffered version of the signal applied at terminal 17 (see Figure 3). The same crystal or externally supplied oscillator signal is used to derive both the transmit and receive frequencies.
XOSC1 XOSC2
16 NC
17 External Signal, ref
Figure 3. Applying an External Oscillator Signal
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direct digital synthesizer
general principles of DDS operation In general, a direct digital synthesizer (DDS) is based on the principle of generating a sinewave signal in the digital domain. Benefits include high precision, wide frequency range, a high degree of software programmability, and extremely fast lock times. Figure 4 shows a block diagram of a typical DDS. It generally consists of an accumulator, sine lookup table, a digital-to-analog converter, and a low-pass filter. All digital blocks are clocked by the reference oscillator.
Synthesizer
+
Frequency Register
N-Bit Register
Sine Lookup Table
DAC
Low-Pass Filter
Analog Output Signal
Load With Frequency Word
Figure 4. Typical DDS Block Diagram The DDS constructs an analog sine waveform using an N-bit adder counting up from 0 to 2N in steps of the frequency register whereby generating a digital ramp waveform. Each number in the N-bit output register is used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog conversion, a low-pass filter is necessary to suppress unwanted spurious responses. The analog output signal can be used as a reference input signal for a phase-locked loop (PLL). The PLL circuit multiplies the reference frequency by a predefined factor. TRF4400 direct digital synthesizer implementation Figure 5 shows a block diagram of the DDS implemented in the TRF4400. It consists of a 24-bit accumulator clocked by the reference oscillator along with control logic settings.
24
Reference Frequency, ref
+
24-Bit Register
11
11-Bit DAC
Sine Shaper
Low-pass Filter
DDS
to PLL
DDS Frequency Register
MODE - (Terminal 11) A - Word B - Word
DDS Mode0 Frequency Setting DDS Mode1 Frequency Setting 22 22
Mode0/1 Select Logic
24
Modulation Control Logic
+
TX_DATA - (Terminal 14)
D - Word / DEV Bits (FSK Deviation)
FSK Frequency Deviation Register
8
C - Word / MM Bit (Modulation Mode Select)
Figure 5. DDS Block Diagram as Implemented in the TRF4400
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TRF4400 direct digital synthesizer implementation (continued) The frequency of the reference oscillator, ref, is the DDS sample frequency, which also determines the maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step size of the TRF4400 is calculated as follows: D + N ref 2 24
The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to 0. Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 6). This bit weight corresponds to a VCO output frequency of (ref/8) x N. Depending on the MODE terminal's (terminal 11) logic level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency (see Figure 5 and Figure 6).
22 DDS Frequency Setting For Mode0/1 From A-Word/B-Word
0 0 X X .... MSB
23 22 21 20 . . . Bit weight: 1/2 1/4 1/8 1/16 . . .
... X X X X X LSB
... 4 3 2 10 ... 1 2 24
DDS Frequency Register
8
FSK Frequency Deviation Register - DEV
0 0 .... MSB
23 22 . . . .
.... X X X X X X X X 0 0 ....9 8 7 6 5 4 3 2 1 0 LSB
DDS Frequency Register
Figure 6. Implementation of the DDS Frequency and FSK Frequency Deviation in the DDS Frequency Register The VCO output frequency, out, which is dependent on the DDS_x frequency settings (DDS_0 in the A-word or DDS_1 in the B-word), can be calculated as follows: out + DDS_x N ref 2 +N 24 ref DDS_x 2 24
If FSK modulation is selected (MM=0; C-Word, bit 16), then the 8-bit FSK deviation register can be used to program the frequency deviation of the 2-FSK modulation. Figure 6 illustrates where the 8 bits of the FSK deviation register map into the 24-bit DDS frequency register. Since the two LSBs are set to 0, the total FSK deviation can be determined as follows: D 2-FSK + N DEV 2 22 ref ref (DDS_x ) 4 2 24 DEV) ref
Hence, the 2-FSK frequency, set by the level on the TX_DATA is calculated as follows: out1:TX_DATA+Low + N DDS_x 2 24 out2:TX_DATA+High + N
This frequency modulated output signal is used as a reference input signal for the PLL circuit. Channel width (frequency deviation) for 2-FSK modulation and channel spacing are software programmable. The minimum channel width and minimum channel spacing depend on the RF system frequency plan.
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TRF4400 direct digital synthesizer implementation (continued) Note that the frequencies out1 and out2 are centered about the frequency center = (out1 + out2)/2. When transmitting FSK, center is considered to be the effective carrier frequency and any receiver local oscillator (LO) should be set to the same center frequency the receiver's IF frequency (IF) for proper reception and demodulation. For the case of low-side injection, the receiver LO would be set to LO = center - IF. Conversely, for high-side injection, the receiver LO would be set to LO = center + IF. Since the DDS registers are static, preprogrammed values are retained during standby mode. This feature greatly reduces turnon time, reduces current consumption when coming out of standby mode, and enables very fast lock-times. The PLL lock-times ultimately determine when data can be transmitted or received.
phase-locked loop
The phase-locked loop (PLL) of the TRF4400 consists of a phase detector (PD) and a frequency acquisiton aid (FD) (including two charge pumps), an external loop filter, voltage-controlled oscillator (VCO), and a programmable fixed prescaler (N-divider) in the feedback loop (see Figure 7). The PLL as implemented in the TRF4400 multiplies the DDS output frequency and further suppresses the unwanted spurious signals produced by the direct digital synthesizer.
DDS
DDS
PD
1 IPD_1 IPD_2 External Loop Filter 4, 5 VCO
out
ref
FD
24 N-Divider 256 / 512
Figure 7. Basic PLL Structure
VCO
A modified Colpitts oscillator architecture with an external resonant circuit is used for the TRF4400. The internal bias current network adjusts the signal amplitude of the VCO. This allows a wide range of Q-factors (30...60) for the external tank circuit. The VCO can be bypassed by applying an external RF signal at VCO_TANK2, terminal 5. To drive the internal PLL and power amplifier, a typical level of -10 dBm should be applied. When an external VCO is used, the x_VCO bit should be set to 0.
phase detector and charge pumps
The TRF4400 contains two charge pumps for locking to the desired frequency: one for coarse tuning of the frequency differences (called the frequency acquisition aid), and one for fine tuning of the phase differences (used in conjunction with the phase detector). The XOR phase detector and charge pumps produce a mean output current that is proportional to the phase difference between the reference frequency and the VCO frequency divided by N; N = 256 or 512. The TRF4400 generates the current pulses IPD_1 during normal operation (PLL locked). An additional slip detector and acquisition aid charge pump generates current pulses at terminal PD_OUT2 during the lock-in of the PLL. This charge pump is turned off when the PLL locks in order to reduce current consumption. The multiplication factor of the acquisition aid current IPD_2 can be programmed by three bits (APLL) in the C-word.
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phase detector and charge pumps (continued)
The slip detector output, PD_OUT2, at terminal 24 should be connected directly to the loop-filter capacitor C1, as shown in Figure 10. The nominal charge pump current I0 is determined by the external resistor RPD, connected to terminal 3, and can be calculated as follows: I0 + 7 V R PD During normal operation (PLL locked), the acquisition aid charge pump is disabled and the maximum charge pump current IPD_1 is determined by the nominal value I0 (see Figure 8).
I0 1 IPD_1
Figure 8. Normal Operation Charge Pump Current, IPD_1 Each time the PLL is in an unlocked condition, the acquisition aid charge pump generates current pulses IPD_2. The IPD_2 current pulses are APLL times larger than I0 (see Figure 9).
I0 1 IPD_1
APLL
IPD_2
Figure 9. Acquisition Aid, IPD_2, and Normal Operation, IPD_1, Charge Pump Currents
programmable divider
The internal divider ratio, N, can be set to 256 or 512 via the C-word. Since a higher divider ratio adds additional noise within the multiplication loop, the lowest divider ratio possible for the target application should be used.
loop filter
Loop filter designs are a balance between lock-time, noise, and spurious suppression. For the TRF4400, common loop filter design rules can be used to determine an appropriate low-pass filter. Standard formulas can be used as a first approach to calculate a basic loop filter. Figure 10 illustrates a basic 3rd-order loop filter.
VCO_TANK1 C3 1 PD_OUT1 C3c R1 PD_OUT2 24 C1 C2 C3d R2 L1 4 VCO_TANK2 5
VCO
C4
2nd-Order Loop Filter 3rd-Order Loop Filter
Figure 10. Basic 3rd-Order Loop Filter Structure
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loop filter (continued)
For maximum suppression of the unwanted frequency components, the loop filter bandwidth should generally be made as narrow as possible. At the same time, the filter bandwidth has to be wide enough to allow for the 2-FSK modulation and appropriate lock-time. A detailed simulation of the phase-locked loop should be performed and later verified on PCB implementations.
power amplifier
The power amplifier (PA) can be programmed via two bits (P0 and P1 in the D-word) to provide varying output power levels. Several control loops are implemented internally to set the output power and to minimize the sensitivity of the power amplifier to temperature, load impedance, and power supply variations. The output stage of the PA usually operates in Class-C and enables easy impedance matching. PA_OUT, terminal 22, is an open collector output terminal.
CH1 S22 1 U 1 2
0.5
5
CAL OFS
0
0.2
0.5
1
2
10
CPL 1-5
FIL 1k -0.5 -1 START 420 MHz STOP 450 MHz -2
Figure 11. Power Amplifier Output Impedance (S22) at Device Terminal 22
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PRINCIPLES OF OPERATION serial control interface
A 3-wire unidirectional serial bus (CLOCK, DATA, STROBE) is used to program the TRF4400 (see Figure 12). The internal registers contain all user programmable variables including the DDS frequency setting registers, as well as all control registers. At each rising edge of the CLOCK signal, the logic value on the DATA terminal is written into a 24-bit shift register. Setting the STROBE terminal high loads the programmed information into the selected latch. While the STROBE signal is high, the DATA and CLOCK lines must be low (see Figure 2). Since the CLOCK and STROBE signals are asynchronous, care should be taken to ensure the signals remain free of glitches and noise. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. Due to the static CMOS design, the serial interface consumes virtually no current and it can be programmed in active as well as in standby mode.
CLOCK STROBE Serial Interface Logic Shift Register 22 22 ADDR 3 ADDR Decoder 21 21 21 B - Latch A - Latch
DATA
C - Latch D - Latch E - Latch
Figure 12. Serial Interface Block Diagram The control words are 24 bits in length. The first incoming bit functions as the most significant bit (MSB). To fully program the TRF4400, four 24-bit words must be sent: the A-, B-, C-, and D-words. If individual bits within a word are to be changed, then it is sufficient to program only the appropriate 24-bit word. Figure 13 shows the definition of the control words. Tables 1, 2, and 3 describe the function of each parameter. The E-Latch, addressed by an ADDR equal to 111, is reserved for test purposes and should not be used. Inadvertently addressing the E-Latch activates the test modes of the TRF4400. If the test mode has been inadvertently activated, it can only be exited by switching VCC on and off or by clearing the E-Latch. The E-Latch can be cleared by addressing it and resetting its entire contents by programming 1110 0000 0000 0000 0000 0000. As part of a proper power-up sequence, it is recommended to clear the E-Latch each time VCC is applied before starting further operations with the TRF4400.
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PRINCIPLES OF OPERATION
A-Word (Programming of DDS_0) MSB 23 0 22 21 0 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LSB 0
DDS Frequency Setting for Mode0 (DDS_0 [21-0])
ADDR B-Word (Programming of DDS_1) MSB 23 0 22 21 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LSB 0
DDS Frequency Setting for Mode1 (DDS_1 [21-0])
ADDR C-Word (Control Register for PLL, Data Slicer, and Mode1 Settings) MSB 23 1 22 21 0 1 20 19 18 17 PLL
APLL NPLL MM A0
LSB 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X
16 15 X
14 13 X X
12 11
10
9
Mode1 Control Register [12-9] PA P1 P0
PLL VCO
ADDR
A2
A1
D-Word (Control Register for Modulation and Mode0 Settings) MSB 23 1 22 21 1 0 20 19 18 17 16 15 14 13 12 11 10 9 8 X
PLL VCO P1 PA P0
LSB 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X
Mode0 Control Register [12-9]
Modulation Register [20-13]
DEV
ADDR
DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
NOTE: Start programming with MSB and ensure that the CLOCK and DATA lines are low during the rising edge of the strobe signal.
Figure 13. Serial Control Word Format
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PRINCIPLES OF OPERATION
Table 1. Mode0 Control Register Description (D-Word)
INITIAL SETTINGS AFTER POWER UP DESCRIPTION DEFAULT STATE Disabled DEFAULT VALUE 00b
SYMBOL
BIT LOCATION [10-9]
NUMBER OF BITS Power amplifier mode 2 P1 0 0 1 1
0_PA
P0 0 = disabled 1 = 10 dB attenuation, enable modulation via TX_DATA 0 = 20 dB attenuation, enable modulation via TX_DATA 1 = 0 dB attenuation, enable modulation via TX_DATA Disabled Disabled 0b 0b
0_VCO 0_PLL
[11] [12]
1
During operation, this bit should always be enabled (1 = enabled), unless an external VCO is used. Enable PLL (DDS system, VCO, RF divider, phase comparator and charge pump) 1 = enabled 0 = disabled
1
Table 2. Mode1 Control Register Description (C-Word)
INITIAL SETTINGS AFTER POWER UP DESCRIPTION DEFAULT STATE Disabled DEFAULT VALUE 00b
SYMBOL
BIT LOCATION [10-9]
NUMBER OF BITS Power amplifier mode 2 P1 0 0 1 1
1_PA
P0 0 = disabled 1 = 10 dB attenuation, enable modulation via TX_DATA 0 = 20 dB attenuation, enable modulation via TX_DATA 1 = 0 dB attenuation, enable modulation via TX_DATA Disabled Disabled 0b 0b
1_VCO 1_PLL
[11] [12]
1
During operation, this bit should always be enabled (1 = enabled), unless an external VCO is used. Enable PLL (DDS system, VCO, RF divider, phase comparator and charge pump) 1 = enabled 0 = disabled
1
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PRINCIPLES OF OPERATION
Table 3. Miscellaneous Control Register Description
BIT LOCATION [21-0] [21-0] [20-13] [20-18] NUMBER OF BITS 22 22 8 3 INITIAL SETTINGS AFTER POWER UP DESCRIPTION DEFAULT STATE 0 0 0 0 DEFAULT VALUE All 0s All 0s All 0s 000b
SYMBOL
WORD
DDS_0 DDS_1 DEV APLL
A-word B-word D-word C-word
DDS frequency setting in Mode0 DDS frequency setting in Mode1 FSK frequency deviation register Acceleration factor for the frequency acquisition aid charge pump A2 A1 A0 0 0 0 =1 0 0 1 = 20 0 1 0 = 40 0 1 1 = 60 L 1 1 1 = 140 PLL divider ratio 0 = divide by 256 1 = divide by 512 Modulation mode select. Sets the behavior of pin TX_DATA to FSK data input. 0 = FSK/FM 1 = do not use
NPLL
C-word
[17]
1
256
0b
MM
C-word
[16]
1
FSK mode
0b
operating modes
Tables 4 and 5 illustrate operating modes and transmit frequencies as set by the STDBY, MODE, and TX_DATA terminals used in conjunction with the DDS frequency settings. Table 4. Transmitting Data in FSK Mode (MM bit set to 0)
TERMINAL STDBY 1 1 1 1 MODE 0 0 1 1 TX_DATA 0 1 0 1 TRANSMIT FREQUENCY out = ref x N x (DDS_0)/224 out = ref x N x (DDS_0 + 4 x DEV)/224 out = ref x N x (DDS_1)/224 out = ref x N x (DDS_1 + 4 x dev)/224
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TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
PRINCIPLES OF OPERATION operating modes (continued)
Table 5. Operating Mode Per STDBY Terminal
STDBY 0 1 OPERATING MODE Standby/programming mode - Power down of all blocks Operating mode and programming mode
Two independent operating modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings by toggling the MODE terminal. Each mode can be viewed as a bank of configuration registers which store the frequency settings and the enable/disable settings for each functional block of the TRF4400. The MODE terminal is then used to asynchronously switch between Mode0 and Mode1 as shown in Figure 14. Table 6 shows several examples of operating sequences.
MODE Terminal (Terminal 11) = 1
Mode0 Register Settings (D-Word) Power Amplifier Mode VCO Enable PLL Enable Synthesizer: DDS Frequency
Mode1 Register Settings (C-Word) Power Amplifier Mode VCO Enable PLL Enable Synthesizer: DDS Frequency
MODE Terminal (Terminal 11) = 0
Figure 14. Interaction Between MODE Terminal and Preprogrammed Mode0 and Mode1 Control Registers Table 6. Operating Mode Examples
FUNCTION/DESCRIPTION Transmit on two different frequencies Emulate FSK transmit operation using the MODE terminal for wideband FSK MODE0 Transmit on frequency 0 Transmit on frequency 0 MODE1 Transmit on frequency 1 Transmit on frequency 0 + deviation
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17
TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
APPLICATION INFORMATION
A typical application schematic for an FSK system operating in the 433-MHz ISM band as shown in Figure 15.
R4 6.2 k C1 4.7 nF C32 470 pF 1 2 C6 0.1 F R1 10 k C2 R3 100 k 27 nH L8 3 4 VCO 5 6 TRF4400 5.2 pF R8 100 k 7 PLL Power Amplifier 22 21 20 19 18 8 9 10 11 12 Serial Interface Direct Digital Synthesizer and Power-Down Logic 17 16 15 14 13 NC TX_DATA C34 0.1 F R9 15 C5 0.1 F J1 RF_OUT SMA/B/L R2 51 L1 47 nH C14 3.9 pF 24 23 LOCKDET
8.2 pF V1 SMV1247-079 C4
CLOCK DATA STROBE MODE STDBY
R5 100
CQ1
25.6 MHz or 26 MHz 1M R6 C24 10 pF
C25 10 pF
C26 SAT DNP
Figure 15. Typical Application Schematic for 433-MHz ISM Band
18
POST OFFICE BOX 655303
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TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
APPLICATION INFORMATION external component list for Figure 15 (5% tolerance unless otherwise noted)
DESIGNATOR C1 C2 C4 C5 C6 C14 C24 C25 C26 C32 C34 L1 L8 R1 R2 R3 R4 R5 R6 R8 R9 V1 CQ1 DESCRIPTION (SIZE) Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Coil Coil Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Varactor diode Crystal 470 pF 0.1 F 47 nH 27 nH 10 k 51 100 k 6.2 k 100 1 M 100 k 15 SMV1247-079 25.6 MHz or 26 MHz Alpha Industries ICM (International Crystal Manufacturing, Incorporated) 865842: 25.6 MHz 865850: 26 MHz Murata Murata LQN21A6N8D04 LQW1608 VALUE 4.7 nF 8.2 pF 5.2 pF 0.1 F 0.1 F 3.9 pF 10 pF 10 pF Select at test (SAT), Do not place (DNP) MANUFACTURER PART NUMBER/COMMENTS
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19
TRF4400 SINGLE-CHIP 433-MHz RF TRANSMITTER
SLWS113C -NOVEMBER 2000 - REVISED SEPTEMBER 2001
MECHANICAL DATA
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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