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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
D D D D D D D D D D D D D D D
Eight 8-Bit Voltage Output DACs 3-V Single Supply Operation Serial Interface High-Impedance Reference Inputs Programmable for 1 or 2 Times Output Range Simultaneous Update Facility Internal Power-On Reset Low Power Consumption Half-Buffered Output
DW OR N PACKAGE (TOP VIEW)
DACB DACA GND DATA CLK VDD DACE DACF
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
DACC DACD REF1 LDAC LOAD REF2 DACH DACG
applications
Programmable Voltage Sources Digitally Controlled Amplifiers/Attenuators Mobile Communications Automatic Test Equipment Process Monitoring and Control Signal Synthesis
description
The TLV5628C and TLV5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLV5628C and TLV5628I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs are updated simultaneously through control of the LDAC terminal. The digital inputs feature Schmitt triggers for high noise immunity. The 16-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLV5628C is characterized for operation from 0C to 70C. The TLV5628I is characterized for operation from - 40C to 85C. The TLV5628C and TLV5628I do not require external trimming.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SMALL OUTLINE (DW) TLV5628CDW TLV5628IDW PLASTIC DIP (N) TLV5628CN TLV5628IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
functional block diagram
REF1 + - 9 Latch Latch 8
DAC
x2
+ -
DACA
DAC Latch REF2 + - Latch Latch 8 Latch 8
x2
+ -
DACD
DAC
x2
+ -
DACE
DAC Latch Latch 8
x2
+ -
DACH
CLK DATA LOAD
Serial Interface
LDAC
Power-On Reset
Terminal Functions
TERMINAL NAME CLK DACA DACB DACC DACD DACE DACF DACG DACH DATA GND LDAC LOAD REF1 REF2 VDD NO. 5 2 1 16 15 7 8 9 10 4 3 13 12 14 11 6 I/O I O O O O O O O O I I I I I I I DESCRIPTION Serial-interface clock, data enters on the negative edge DACA analog output DACB analog output DACC analog output DACD analog output DACE analog output DACF analog output DACG analog output DACH analog output Serial-interface digital data input Ground return and reference terminal DAC-update latch control Serial-interface load control Reference voltage input to DACA Reference voltage input to DACB Positive supply voltage
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
detailed description
The TLV5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance of the output buffer. Because the inputs are buffered, the DACs always present a high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2 is used by DACE through DACH. Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or times 2 gain. On power-up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D|E|F|G|H) O
+ REF
CODE 256
(1
) RNG bit value)
where CODE is in the range of 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated and LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data transfers using two 8 clock cycle periods are shown in Figures 3 and 4.
CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A2 A1 A0 RNG D7 D6 D5 D4 tsu(LOAD-CLK) D2 D1 D0 tw(LOAD)
tsu(CLK-LOAD) LOAD
DAC Update
Figure 1. LOAD-Controlled Update (LDAC = Low)
CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0
tsu(LOAD - LDAC) LOAD tw(LDAC) LDAC DAC Update
Figure 2. LDAC-Controlled Update
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
CLK Low CLK
DATA
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
LOAD LDAC
Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)
CLK Low CLK
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DATA
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
LOAD LDAC
Figure 4. LDAC Controlled Update Using 8-Bit Serial Word
IIIII IIIII
IIII IIII
IIII IIII III III
IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII
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Template Release Date: 7-11-94
TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
data interface (continued)
Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND. Table 1. Ideal Output Transfer
D7 0 0 * * 0 1 * * 1 D6 0 0 * * 1 0 * * 1 D5 0 0 * * 1 0 * * 1 D4 0 0 * * 1 0 * * 1 D3 0 0 * * 1 0 * * 1 D2 0 0 * * 1 0 * * 1 D1 0 0 * * 1 0 * * 1 D0 0 1 * * 1 0 * * 1 OUTPUT VOLTAGE GND (1/256) x REF (1+RNG) * * (127/256) x REF (1+RNG) (128/256) x REF (1+RNG) * * (255/256) x REF (1+RNG)
Table 2. Serial Input Decode
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 DAC UPDATED DACA DACB DACC DACD DACE DACF DACG DACH
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
linearity, offset, and gain error When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, since the most negative supply rail is ground, the output cannot drive to a negative voltage. So when the output offset voltage is negative, the output voltage remains at 0 volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage resulting in the transfer function shown in Figure 5.
Output Voltage
0V Negative Offset DAC Code
Figure 5. Effect of Negative Offset (Single Supply) The negative offset error produces a breakpoint, not a linearity error. The transfer function would follow the dotted line if the output buffer could drive to a negative voltage. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale is adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. The linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. The code is calculated from the maximum specification for the negative offset.
equivalent inputs and outputs
INPUT CIRCUIT VDD Input from Decoded DAC Register String _ + x1 84 k ISINK 60 A Typical GND DAC Voltage Output OUTPUT CIRCUIT VDD
Vref Input To DAC Resistor String GND
Output Range x 2 Select
84 k
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD - GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 V to VDD + 0.3 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5628I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage, VDD High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref [A|B|C|D|E|F|G|H], X1 gain Load resistance, RL Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) Valid time, data input valid after CLK, tv(DATA-CLK) (see Figures 1 and 2) Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) Setup time, LOAD to CLK, tsu(LOAD-CLK) (see Figure 1) Pulse duration, LOAD, tw(LOAD) (see Figure 1) Pulse duration, LDAC, tw(LDAC) (see Figure 2) Setup time, LOAD to LDAC, tsu(LOAD-LDAC) (see Figure 2) CLK frequency Operating free-air temperature, TA free air temperature TLV5628C TLV5628I 0 - 40 10 50 50 50 50 250 250 0 1 70 85 2.7 0.8 VDD 0.8 VDD- 1.5 NOM 3.3 MAX 5.25 UNIT V V V V k ns ns ns ns ns ns ns MHz C C
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted)
PARAMETER IIH IIL IO(sink) IO(source) Ci IDD Iref EL ED EZS EFS PSRR High-level digital input current Low-level digital input current Output sink current Output source current Input capacitance Reference input capacitance Supply current Reference input current Linearity error (end point corrected) Differential linearity error Zero-scale error Zero-scale error temperature coefficient Full-scale error Full-scale error temperature coefficient Power supply sensitivity VDD = 3.3 V VDD = 3.3 V, Vref = 1.5 V Vref = 1.25 V, x 2 gain (see Note 1) Vref = 1.25 V, x 2 gain (see Note 2) Vref = 1.25 V, x 2 gain (see Note 3) Vref = 1.25 V, x 2 gain (see Note 4) Vref = 1.25 V, x 2 gain (see Note 5) Vref = 1.25 V, x 2 gain (see Note 6) See Notes 7 and 8 0 10 60 25 0.5 TEST CONDITIONS VI = VDD VI = 0 V Each DAC output 20 1 15 15 4 10 1 0.9 30 MIN TYP MAX 10 10 UNIT A A A mA pF mA A LSB LSB mV V/C mV V/C mV/V
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero-scale and full scale (excluding the effects of zero code and full-scale errors). 2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) - ZSE(Tmin)]/Vref x 106/(Tmax - Tmin). 5. Full-scale error is the deviation from the ideal full-scale output (Vref - 1 LSB) with an output load of 10 k . 6. Full-scale temperature coefficient is given by: FSETC = [FSE(Tmax) - FSE (Tmin)]/Vref x 106/(Tmax - Tmin). 7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect of this signal on the zero-code output voltage. 8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of this signal on the full-scale output voltage.
operating characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, x 1 gain output range (unless otherwise noted)
TEST CONDITIONS Output slew rate Output settling time Large-signal bandwidth Digital crosstalk Reference feedthrough Channel-to-channel isolation Reference input bandwidth CL = 100 pF, To 0.5 LSB, RL = 10 k CL = 100 pF, RL = 10 k, See Note 9 MIN TYP 1 10 100 - 50 - 60 - 60 100 MAX UNIT V/s s kHz dB dB dB kHz
Measured at - 3 dB point CLK = 1-MHz square wave measured at DACA-DACH See Note 10 See Note 11 See Note 12
NOTES: 9. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 00 hex to FF hex or FF hex to 00 hex. For TLC5628C VDD = 5 V, Vref = 2 V and range = x 2. For TLC5628I VDD = 3 V, Vref = 1.25 V and range x 2. 10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz. 11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1 V dc + 1 VPP at 10 kHz. 12. Reference bandwidth is a -3 dB bandwidth with an input at Vref = 1.25 V dc + 2 VPP and with a full-scale digital input code.
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
TLV5628 DACA DACB * * * DACH
10 k
CL = 100 pF
Figure 6. Slewing Settling Time and Linearity Measurements
TYPICAL CHARACTERISTICS
POSITIVE RISE TIME AND SETTLING TIME
3 2.5 2 1.5 1 0.5 0 - 0.5 -1 0 2 4 6 8 10 12 Time - s 14 16 18 20 3 2.5 2 1.5 1 0.5 0 - 0.5 -1 0 2 4 6 8 10 12 14 16 18 20 Time - s NOTE B: Fall time = 4.25 s, negative slew rate = 0.46 V/s, settling time = 8.5 s. VDD = 3 V TA = 25C Code FF to 00 Hex Range = x2 Vref = 1.25 V (see Note B)
NEGATIVE FALL TIME AND SETTLING TIME
VO - Output Voltage - V
VDD = 3 V TA = 25C Code 00 to FF Hex Range = x2 Vref = 1.25 V (see Note A)
NOTE A: Rise time = 2.05 s, positive slew rate = 0.96 V/s, settling time = 4.5 s.
VO - Output Voltage - V
Figure 7
Figure 8
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE vs LOAD
3 2.8 VO - DAC Output Voltage - V 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0 10 20 30 40 50 60 Load - k 70 80 90 100 VDD = 3 V, Vref = 1.5 V, Range = 2x VO - DAC Output Voltage - V 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 Load - k VDD = 3 V, Vref = 1.5 V, Range = 1x
DAC OUTPUT VOLTAGE vs LOAD
Figure 9
SUPPLY CURRENT vs TEMPERATURE
1.2 1.15 I DD - Supply Current - mA 1.1 1.05 1 0.95 0.9 0.85 0.8 - 50 Range = x 2 Input Code = 255 VDD = 3 V Vref 1.25 V
Figure 10
0
50
100
t - Temperature - C
Figure 11
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
APPLICATION INFORMATION
TLV5628 DACA DACB * * * DACH _ + R VO
NOTE A: Resistor R
w 10 k
Figure 12. Output Buffering Scheme
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
MECHANICAL DATA
DW (R-PDSO-G**)
16 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) DIM 0.020 (0,51) 0.014 (0,35) 16 9 0.010 (0,25) M
PINS **
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78)
A MAX
A MIN
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 10/94 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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TLV5628C, TLV5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A - JANUARY 1995 - REVISED NOVEMBER 1995
MECHANICAL DATA
N (R-PDIP-T**)
16 PIN SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
A 16 9 PINS ** DIM A MAX 0.260 (6,60) 0.240 (6,10) 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23.37) 0.850 (21.59) 20 0.975 (24,77) 0.940 (23,88)
A MIN
1
8 0.070 (1,78) MAX
0.035 (0,89) MAX
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
14 Pin Only 4040049 / C 7/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
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