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TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
10-BIT DIGITAL-TO-ANALOG CONVERTERS
FEATURES
* * * * * * * * 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package 5-V Single Supply Operation 3-Wire Serial Interface High-Impedance Reference Inputs Voltage Output Range . . . 2 Times the Reference Input Voltage Internal Power-On Reset Low Power Consumption . . . 1.75 mW Max Update Rate of 1.21 MHz * * * Settling Time to 0.5 LSB . . . 12.5 s Typ Monotonic Over Temperature Pin Compatible With the Maxim MAX515
APPLICATIONS
* * * * * Battery-Powered Test Instruments Digital Offset and Gain Adjustment Battery Operated/Remote Industrial Controls Machine and Motion Control Devices Cellular Telephones
D, P, OR DGK PACKAGE (TOP VIEW)
DIN SCLK CS DOUT
1 2 3 4
8 7 6 5
VDD OUT REFIN AGND
DESCRIPTION
The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPITM, QSPITM, and MicrowireTM standards. The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5615C is characterized for operation from 0C to 70C. The TLC5615I is characterized for operation from -40C to 85C.
AVAILABLE OPTIONS
PACKAGE TA 0C to 70C 40C to 85C (1) SMALL OUTLINE (1) (D) TLC5615CD TLC5615ID PLASTIC SMALL OUTLINE (DGK) TLC5615CDGK TLC5615IDGK PLASTIC DIP (P) TLC5615CP TLC5615IP
Available in tape and reel as the TLC5615CDR and the TLC5615IDR
SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996 - 2003, Texas Instruments Incorporated
TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
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FUNCTIONAL BLOCK DIAGRAM
_ REFIN + DAC + _2 OUT (Voltage Output) R
AGND Power-ON Reset R
10-Bit DAC Register Control Logic 2 0s (LSB) (MSB) 4 Dummy Bits DOUT
CS SCLK DIN
10 Data Bits
16-Bit Shift Register
Terminal Functions
TERMINAL NAME DIN SCLK CS DOUT AGND REFIN OUT VDD NO. 1 2 3 4 5 6 7 8 I O I/O I I I O Serial data input Serial clock input Chip select, active low Serial data output for daisy chaining Analog ground Reference input DAC analog voltage output Positive power supply DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT Supply voltage (VDD to AGND) Digital input voltage range to AGND Reference input voltage range to AGND Output voltage at OUT from external source Continuous current at any terminal Operating free-air temperature range, TA Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) TLC5615C TLC5615I 7V - 0.3 V to VDD + 0.3 V - 0.3 V to VDD + 0.3 V VDD + 0.3 V 20 mA 0C to 70C -40C to 85C -65C to 150C 260C
Stresses beyond those listed under,, absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VDD High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REFIN terminal Load resistance, RL Operating free-air temperature, TA TLC5615C TLC5615I 2 2 0 40 70 85 2.048 4.5 2.4 0.8 VDD-2 NOM 5 MAX 5.5 UNIT V V V V k C C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VDD = 5 V 5%, Vref = 2.048 V (unless otherwise noted)
STATIC DAC SPECIFICATIONS PARAMETER Resolution Integral nonlinearity, end point adjusted (INL) Differential nonlinearity (DNL) EZS EG Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient Gain error Gain-error temperature coefficient PSRR Power-supply rejection ratio Analog full scale output (1) Zero scale Gain Vref = 2.048 V, Vref = 2.048 V, Vref = 2.048 V, Vref = 2.048 V, Vref = 2.048 V, Vref = 2.048 V, See (7) (8) RL = 100 k See (1) See (2) See (3) See (4) See (5) See (6) 80 80 2Vref(1023/1024) TEST CONDITIONS MIN 10 1 0.1 3 3 1 0.5 3 TYP MAX UNIT bits LSB LSB LSB ppm/C LSB ppm/C dB V
(2)
(3) (4) (5) (6) (7) (8)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code 1024. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 3 to code 1024. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text). Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vrefx 106/(Tmax - Tmin). Gain error is the deviation from the ideal output (Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-scale error. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vrefx 106/(Tmax - Tmin). Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero-scale change.
VOLTAGE OUTPUT(OUT)
PARAMETER VO IOSC VOL(low) VOH(high) VI ri Voltage output range Output load regulation accuracy Output short circuit current Output voltage, low-level Output voltage, high-level Input voltage Input resistance RL= 10 k VO(OUT) = 2 V, OUT to VDD or AGND IO(OUT) 5 mA IO(OUT) -5 mA 4.75 0 10 VDD-2 RL = 2 k 20 0.25 TEST CONDITIONS MIN 0 TYP MAX VDD-0.4 0.5 UNIT V LSB mA V V V M
REFERENCE INPUT (REFIN)
3
TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
www.ti.com
VOLTAGE OUTPUT(OUT) (continued)
PARAMETER Ci VIH VIL IIH IIL Ci VOH VOL VDD IDD Input capacitance High-level digital input voltage Low-level digital input voltage High-level digital input current Low-level digital input current Input capacitance Output voltage, high-level Output voltage, low-level Supply voltage VDD = 5.5 V, No load, All inputs = 0 V or VDD VDD= 5.5 V, No load, All inputs = 0 V or VDD Vref = 0 Vref = 2.048 V IO= -2 mA IO= 2 mA 4.5 5 150 230 VDD-1 0.4 5.5 250 350 VI = VDD VI = 0 8 2.4 0.8 1 1 DIGITAL INPUTS (DIN, SCLK, CS) V V A A pF V V V A A TEST CONDITIONS MIN TYP 5 MAX UNIT pF
DIGITAL OUTPUT (DOUT)
POWER SUPPLY
Power supply current
ANALOG OUTPUT DYNAMIC PERFORMANCE Signal-to-noise + distortion, S/(N+D) (1) Vref = 1 Vpp at 1 kHz + 2.048 Vdc, code = 11 1111 1111, See (1) 60 dB
The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.
DIGITAL INPUT TIMING REQUIRMENTS (SEE FIGURE 1)
PARAMETER tsu(DS) th(DH) tsu(CSS) tsu(CS1) th(CSH0) th(CSH1) tw(CS) tw(CL) tw(CH) Setup time, DIN before SCLK high Hold time, DIN valid after SCLK high Setup time, CS low to SCLK high Setup time, CS high to SCLK high Hold time, SCLK low to CS low Hold time, SCLK low to CS high Pulse duration, minimum chip select pulse width high Pulse duration, SCLK low Pulse duration, SCLK high MIN 45 0 1 50 1 0 20 25 25 NOM MAX UNIT ns ns ns ns ns ns ns ns ns
OUTPUT SWITCHING CHARACTERISTICS
PARAMETER tpd(DOUT) Propagation delay time, DOUT CL = 50 pF TEST CONDITIONS MIN NOM MAX 50 UNIT ns
OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, VDD = 5 V 5%, Vref = 2.048 V (unless otherwise noted)
PARAMETER ANALOG OUTPUT DYNAMIC PERFORMANCE SR Output slew rate CL = 100 pF, TA= 25C RL = 10 k, 0.3 0.5 V/s TEST CONDITIONS MIN TYP MAX UNIT
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TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
OPERATING CHARACTERISTICS (continued)
over recommended operating free-air temperature range, VDD = 5 V 5%, Vref = 2.048 V (unless otherwise noted)
PARAMETER ANALOG OUTPUT DYNAMIC PERFORMANCE ts Output settling time Glitch energy REFERENCE INPUT (REFIN) Reference feedthrough Reference input bandwidth (f-3dB) (1) (2) REFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see (2) REFIN = 0.2 Vpp + 2.048 Vdc -80 30 dB kHz To 0.5 LSB, RL = 10 k, DIN = All 0s to all 1s CL = 100 pF, See (1) 12.5 5 s nV*s TEST CONDITIONS MIN TYP MAX UNIT
Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048 Vdc + 1 Vpp at 1 kHz.
PARAMETER MEASURMENT INFORMATION
CS th(CSH0)

tsu(CSS) tw(CH)
tw(CS) tw(CL) th(CSH1)

tsu(CS1)

See Note A tsu(DS) DIN

tpd(DOUT) DOUT Previous LSB See Note B NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge MSB LSB
Figure 1. Timing Diagram

SCLK
See Note C th(DH)
See Note A
5
TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
www.ti.com
TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE
20 18 16 IO - Output Sink Current - mA 14 12 10 8 6 4 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 1.1 1.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 VO - Output Pullup Voltage - V 3.2 3 VDD = 5 V VREFIN = 2.048 V TA = 25C 30 VDD = 5 V VREFIN = 2.048 V TA = 25C
OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE
IO - Output Source Current - mA
25
20
15
10
5
VO - Output Pulldown Voltage - V Figure 2.
Figure 3. VREFIN TO V(OUT) RELATIVE GAIN vs INPUT FREQUENCY
4 2 0 G - Relative Gain - dB VDD = 5 V VREFIN = 0.2 VPP + 2.048 V dc TA = 25 C
SUPPLY CURRENT vs TEMPERATURE
280 240 I DD - Supply Current - A 200 160 120 80 VDD = 5 V VREFIN = 2.048 V TA = 25C 0 20 40 60 80 t - Temperature - C 100 120 140
-2 -4 -6 -8 - 10
40
- 12 - 14 1 100 1k 10 k 100 k fI - Input Frequency - Hz
0 - 60 - 40 - 20
Figure 4.
Figure 5.
6
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TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY AT REFIN
70 60 Signal-To-Noise + Distortion - dB VDD = 5 V TA = 25 C VREFIN = 4 VPP
50 40 30
20 10 0 1k
10 k
100 k
300 k
Frequency - Hz
Figure 6.
0.2 Differential Nonlinearity - LSB 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 255 511 Input Code 767 1023
Figure 7 Differential Nonlinearity With Input Code
1 Integral Nonlinearity - LSB 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 255 511 Input Code 767 1023
Figure 8 Integral Nonlinearity With Input Code
7
TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
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APPLICATION INFORMATION GENERAL FUNCTION
The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1). An internal circuit resets the DAC register to all zeros on power up.
DIN SCLK CS DOUT
REFIN
+ _
Resistor String DAC
+ _ R
OUT
R
AGND
VDD 5V
0.1 F
Figure 9. TLC5615 Typical Operating Circuit Table 1. Binary Code Table (0 V to 2 VREFINOutput),Gain = 2
INPUT (1) 1111 1111 : 1000 0000 01(00) 11(00) OUTPUT
1023 2 VREFIN 1024
:
513 2 VREFIN 1024 512 2 VREFIN + V REFIN 1024
1000
0000
00(00)
0111
1111 :
11(00)
2 VREFIN 1024
511
: 01(00) 00(00)
1 2 VREFIN 1024
0000 0000 (1)
0000 0000
0V
A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide.
BUFFER AMPLIFIER
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-k load with a 100-pF load capacitance. Settling time is 12.5 s typical to within 0.5 LSB of final value.
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TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
EXTERNAL REFERENCE
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10 M and the REFIN input capacitance is typically 5 pF independent of input code. The reference voltage determines the DAC full-scale output.
LOGIC INTERFACE
The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:
f(SCLK)max + t w CH 1 )t w CL
or approximately 14 MHz. The digital update rate is limited by the chip-select period, which is:
tp(CS) + 16 t )t )t
w CH
w CL
w CS
and is equal to 820 ns which is a 1.21 MHz update rate. However, the DAC settling time to 10 bits of 12.5 s limits the update rate to 80 kHz for full-scale input step transitions.
SERIAL INTERFACE
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The rising edge of the SLCK input shifts the data into the input register. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked into the input register. All CS transitions should occur when the SCLK input is low. If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data sequence with the MSB first can be used as shown in Figure 10:
12 Bits 10 Data Bits MSB x = don't care LSB x x
2 Extra (Sub-LSB) Bits
Figure 10. 12-Bit Input Data Sequence or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.
16 Bits 4 Upper Dummy Bits MSB x = don't care 10 Data Bits LSB x x
2 Extra (Sub-LSB) Bits
Figure 11. 16-Bit Input Data Sequence
9
TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
www.ti.com
The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal (see Figure 1). The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data converter transfers. The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The hardware connections are shown in Figure 12 and Figure 13. The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC input register in one write cycle.
SCLK DIN TLC5615 CS DOUT SK SO Microwire Port I/O SI
NOTE A: The DOUT-SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired.
Figure 12. Microwire Connection
SCLK DIN TLC5615 CS DOUT
SCK MOSI I/O SPI/QSPI Port
MISO CPOL = 0, CPHA = 0
NOTE A: The DOUT-MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer.
Figure 13. SPI/QSPI Connection
DAISY-CHAINING DEVICES
DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain, providing that the setup time, tsu(CSS), (CS low to SCLK high) is greater than the sum of the setup time, tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements section). The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT remains at the value of the last data bit and does not go into a high-impedance state.
10
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TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
LINEARITY, OFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
Output Voltage
0V Negative Offset DAC Code
Figure 14. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. For the TLC5615, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the maximum specification for the negative offset.
POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-F ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 15 shows the ground plane layout and bypassing technique.
11
TLC5615C, TLC5615I
SLAS142D - OCTOBER 1996 - REVISED AUGUST 2003
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Analog Ground Plane
1 2 3 4
8 7 6 5 0.1 F
Figure 15. Power-Supply Bypassing
SAVING POWER
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output load when the system is not using the DAC.
AC CONSIDERATIONS
Digital Feedthrough Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT. Analog Feedthrough Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to REFIN, and monitoring the DAC output.
12
MECHANICAL DATA
MPDI001A - JANUARY 1995 - REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
MECHANICAL DATA
MPDS028B - JUNE 1997 - REVISED SEPTEMBER 2001
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,08 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/C 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
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1
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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