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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
WIDEBAND, LOW DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS
FEATURES D D D D D D D
Fully Differential Architecture Bandwidth: 260 MHz Slew Rate: 1800 V/s IMD3: -73 dBc at 30 MHz OIP3: 29 dBm at 30 MHz Output Common-Mode Control Wide Power Supply Voltage Range: 5 V, 5 V, 12 V, 15 V Include the Negative Power Supply Rail
APPLICATIONS D High Linearity Analog-to-Digital Converter D D D Differential Line Driver D Active Filtering of Differential Signals
VIN- VOCM VS+ VOUT+
1 2 3 4 8 7 6 5
Preamplifier Wireless Communication Receiver Chains Single-Ended to Differential Conversion
VIN+ PD VS- VOUT-
D Input Common-Mode Range Shifted to D Power-Down Capability (THS4504) D Evaluation Module Available DESCRIPTION
The THS4504 and THS4505 are high-performance fully differential amplifiers from Texas Instruments. The THS4504, featuring power-down capability, and the THS4505, without power-down capability, set new performance standards for fully differential amplifiers with unsurpassed linearity, supporting 12-bit operation through 40 MHz. Package options include the 8-pin SOIC and the 8-pin MSOP with PowerPAD for a smaller footprint, enhanced ac performance, and improved thermal dissipation capability.
RELATED DEVICES
DEVICE(1) THS4504/5 THS4500/1 THS4502/3 THS4120/1 THS4130/1 THS4140/1 THS4150/1 DESCRIPTION 260 MHz, 1800 V/s, VICR Includes VS- 370 MHz, 2800 V/s, VICR Includes VS- 370 MHz, 2800 V/s, Centered VICR 3.3 V, 100 MHz, 43 V/s, 3.7 nVHz 15 V, 150 MHz, 51 V/s, 1.3 nVHz 15 V, 160 MHz, 450 V/s, 6.5 nVHz 15 V, 150 MHz, 650 V/s, 7.6 nVHz
(1) Even numbered devices feature power-down capability
APPLICATION CIRCUIT DIAGRAM
5V 0.1 F 487 53.6 1 F + - +
8.2 pF
499
50 VS
10 F 24.9 IN IN 24.9
5V
VOCM -
ADC 12 Bit/80 MSps Vref
523 499
8.2 pF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.
Copyright 2002, Texas Instruments Incorporated
THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) UNIT
Supply voltage, VS Input voltage, VI Output current, IO (2) Differential input voltage, VID Continuous power dissipation Maximum junction temperature, TJ Operating free-air temperature range, TA Storage temperature range, Tstg
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
16.5 V VS 150 mA 4V
See Dissipation Rating Table
PACKAGE DISSIPATION RATINGS
PACKAGE D (8 pin) DGN (8 pin) JC (C/W) 38.3 4.7 JA(1) (C/W) 167 58.4 POWER RATING TA 25C 740 mW 2.14 W TA = 85C 390 mW 1.11 W
150C -40C to 85C -65C to 150C 300C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
RECOMMENDED OPERATING CONDITIONS
MIN Dual supply Supply voltage Single supply 4.5 -40 Operating free-air temperature, TA NOM 5 5 MAX 7.5 15 85 UNIT V C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The THS450x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER PLASTIC SMALL OUTLINE(1) (D) THS4504D THS4505D PLASTIC MSOP (DGN) THS4504DGN THS4505DGN PACKAGE MARKING BDB BDC
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS4504DR).
PIN ASSIGNMENTS
THS4504 (TOP VIEW)
V IN- V OCM V S+ V OUT+
1 8
D AND DGN
THS4505 (TOP VIEW)
V IN- V OCM V S+ V OUT+
1 8
D AND DGN
V IN+ PD V S- V OUT-
V IN+ NC V S- V OUT-
2
7
2
7
3
6
3
6
4
5
4
5
2
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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4504 AND THS4505 PARAMETER TEST CONDITIONS TYP 25C AC PERFORMANCE G = 1, PIN= -20 dBm, Rf = 499 Small-signal bandwidth G = 2, PIN= -20 dBm, Rf = 499 G = 5, PIN= -20 dBm, Rf = 499 G = 10, PIN = -20 dBm, Rf = 499 Gain-bandwidth product Bandwidth for 0.1dB flatness Large-signal bandwidth Slew rate Rise time Fall time Settling time to 0.01% 0.1% Harmonic distortion 2nd harmonic 3rd harmonic Third-order intermodulation distortion Third-order output intercept point Input voltage noise Input current noise Overdrive recovery time G > +10 PIN = -20 dBm G = 1, VP = 2 V 4 VPP Step 2 VPP Step 2 VPP Step VO = 4 VPP VO = 4 VPP G = 1, VO = 2 VPP f = 8 MHz f = 30 MHz f = 8 MHz f = 30 MHz VO = 2 VPP, fc = 30 MHz, Rf = 499 , 200 kHz tone spacing fc = 30 MHz, Rf = 499 , Referenced to 50 f > 1 MHz f > 100 kHz Overdrive = 5.5 V -79 -66 -93 -65 -73 29 8 2 60 dBc dBc dBc dBc dBc dBm nV/Hz pA/Hz ns 260 110 40 20 210 65 250 1800 0.8 1 100 20 MHz MHz MHz MHz MHz MHz MHz V/s ns ns ns ns Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX
DC PERFORMANCE Open-loop voltage gain Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift 0.5 1 4 4.6 55 -4 52 -7 / -1 50 -8 / 0 10 5 10 2 40 50 -9 / +1 10 5.2 10 2 40 dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ
INPUT Common-mode input range Common-mode rejection ratio Input impedance OUTPUT Differential output voltage swing Differential output current drive Output balance error Closed-loop output impedance (single-ended) RL = 1 k RL = 20 PIN = -20 dBm, f = 100 kHz f = 1 MHz 8 130 -65 0.1 7.6 110 7.4 100 7.4 100 V mA dB Min Min Typ Typ 3 -5.7 / 2.6 80 107 || 1 -5.4 / 2.3 74 -5.1 / 2 70 -5.1 / 2 70 V dB || pF Min Min Typ
THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
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ELECTRICAL CHARACTERISTICS VS = 5 V (continued)
Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4504 AND THS4505 PARAMETER TEST CONDITIONS TYP 25C OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth Slew rate Minimum gain Maximum gain Common-mode offset voltage Input bias current Input voltage range Input impedance Maximum default voltage Minimum default voltage POWER SUPPLY Specified operating voltage Maximum quiescent current Minimum quiescent current Power supply rejection (PSRR) POWER DOWN (THS4505 ONLY) Enable voltage threshold Disable voltage threshold Power-down quiescent current Input bias current Input impedance Turnon time delay Turnoff time delay Device enabled ON above -2.9 V Device disabled OFF below -4.3 V 800 200 50 || 1 1000 800 -2.9 -4.3 1000 240 1200 260 1200 260 V V A A k || pF ns ns Min Max Max Max Typ Typ Typ 5 16 16 80 7.5 20 13 76 7.5 23 11 73 7.5 25 9 70 V mA mA dB Max Max Min Min VOCM left floating VOCM left floating VOCM = 2.5 V RL = 400 2 VPP step 200 92 1 1 -0.4 100 4 25 || 1 0 0 0.05 -0.05 0.10 -0.10 0.10 -0.10 0.98 1.02 -4.6/+3.8 150 3.7 0.98 1.02 -6.6/+5.8 170 3.4 0.98 1.02 -7.6/+6.8 170 3.4 MHz V/s V/V V/V mV A V k || pF V V Typ Typ Min Max Max Max Min Typ Max Min 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX
4
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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4504 AND THS4505 PARAMETER TEST CONDITIONS TYP 25C AC PERFORMANCE G = 1, PIN = -20 dBm, Rf = 499 Small-signal bandwidth G = 2, PIN = -20 dBm, Rf = 499 G = 5, PIN = -20 dBm, Rf = 499 G = 10, PIN = -20 dBm, Rf = 499 Gain-bandwidth product Bandwidth for 0.1 dB flatness Large-signal bandwidth Slew rate Rise time Fall time Settling time to 0.01% 0.1% Harmonic distortion 2nd harmonic 3rd harmonic Third-order intermodulation distortion Third-order output intercept point Input voltage noise Input current noise Overdrive recovery time DC PERFORMANCE Open-loop voltage gain Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift INPUT Common-mode input range Common-mode rejection ratio Input impedance OUTPUT Differential output voltage swing Output current drive Output balance error Closed-loop output impedance (single-ended) RL = 1 k, Referenced to 2.5 V RL = 20 PIN = -20 dBm, f = 100 kHz f = 1 MHz 3.3 110 -38 0.1 3 90 2.8 80 2.8 80 V mA dB Min Min Typ Typ -0.7/2.6 80 107 || 1 -0.4 / 2.3 74 -0.1 / 2 70 -0.1 / 2 70 V dB || pF Min Min Typ 0.5 0.7 4 4.6 54 -4 51 -7 / -1 49 -8 / 0 10 5 10 1.2 20 49 -9 / +1 10 5.2 10 1.2 20 dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ G > +10 PIN = -20 dBm G = 1, VP = 1 V 2 VPP Step 2 VPP Step 2 VPP Step VO = 2 V Step VO = 2 V Step G = 1, VO = 2 VPP f = 8 MHz, f = 30 MHz f = 8 MHz f = 30 MHz VO = 2 VPP, fc = 30 MHz, Rf = 499 , 200 kHz tone spacing fc = 30 MHz, Rf = 499 , Referenced to 50 f > 1 MHz f > 100 kHz Overdrive = 5.5 V -77 -56 -74 -57 -72 28 8 2 60 dBc dBc dBc dBc dBc dBm nV/Hz pA/Hz ns 210 120 40 20 200 100 200 900 1.1 1 100 20 MHz MHz MHz MHz MHz MHz MHz V/s ns ns ns ns Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX
5
THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
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ELECTRICAL CHARACTERISTICS VS = 5 V (continued)
Rf = Rg = 499 , RL = 800 , G = +1, Single-ended input unless otherwise noted. THS4504 AND THS4505 PARAMETER TEST CONDITIONS TYP 25C OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth Slew rate Minimum gain Maximum gain Common-mode offset voltage Input bias current Input voltage range Input impedance Maximum default voltage Minimum default voltage POWER SUPPLY Specified operating voltage Maximum quiescent current Minimum quiescent current Power supply rejection (+PSRR) POWER DOWN (THS4505 ONLY) Enable voltage threshold Disable voltage threshold Power-down quiescent current Input bias current Input impedance Turnon time delay Turnoff time delay Device enabled ON above 2.1 V Device disabled OFF below 0.7 V 600 100 50 || 1 1000 800 2.1 0.7 800 125 1200 140 1200 140 V V A A k || pF ns ns Min Max Max Max Typ Typ Typ 5 14 14 75 15 17 11 72 15 19 10 69 15 21 8 66 V mA mA dB Max Max Min Min VOCM left floating VOCM left floating VOCM = 2.5 V RL = 400 2 VPP Step 160 80 1 1 0.4 1 1/4 25 || 1 2.5 2.5 2.55 2.45 2.6 2.4 2.6 2.4 0.98 1.02 -2.6/3.4 2 1.2 / 3.8 0.98 1.02 -4.2/5.4 3 1.3 / 3.7 0.98 1.02 -5.6/6.4 3 1.3 / 3.7 MHz V/s V/V V/V mV A V k || pF V V Typ Typ Min Max Max Max Min Typ Max Min 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ MAX
6
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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
TYPICAL CHARACTERISTICS Table of Graphs (5 V)
FIGURE Small signal unity gain frequency response Small signal frequency response 0.1 dB gain flatness frequency response Large signal frequency response Harmonic distortion (single-ended input to differential output) vs Frequency Harmonic distortion (single-ended input to differential output) vs Output voltage swing Harmonic distortion (single-ended input to differential output) vs Load resistance Third order intermodulation distortion (single-ended input to differential output) vs Frequency Third order output intercept point vs Frequency Slew rate vs Differential output voltage step Settling time Large signal transient response Small signal transient response Overdrive recovery Voltage and current noise vs Frequency Rejection ratios vs Frequency Rejection ratios vs Case temperature Output balance error vs Frequency Open-loop gain and phase vs Frequency Open-loop gain vs Case temperature Input bias offset current vs Case temperature Quiescent current vs Supply voltage Input offset voltage vs Case temperature Common-mode rejection ratio vs Input common-mode range Output voltage vs Load resistance Closed-loop output impedance vs Frequency Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage Small signal frequency response at VOCM Output offset voltage at VOCM vs Output common-mode voltage Quiescent current vs Power-down voltage Turnon and turnoff delay times Single-ended output impedance in power down vs Frequency Power-down quiescent current vs Case temperature Power-down quiescent current vs Supply voltage 1 2 3 4 5 6, 7 8 9 10 11 12, 13 14 15 16, 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
7
THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
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TYPICAL CHARACTERISTICS Table of Graphs (5 V)
FIGURE Small signal unity gain frequency response Small signal frequency response 0.1 dB gain flatness frequency response Large signal frequency response Harmonic distortion (single-ended input to differential output) vs Frequency Harmonic distortion (single-ended input to differential output) vs Output voltage swing Harmonic distortion (single-ended input to differential output) vs Load resistance Third-order intermodulation distortion vs Frequency Third-order intercept point vs Frequency Slew rate vs Differential output voltage step Settling time Overdrive recovery Large-signal transient response Small-signal transient response Voltage and current noise vs Frequency Rejection ratios vs Frequency Rejection ratios vs Case temperature Output balance error vs Frequency Open-loop gain and phase vs Frequency Open-loop gain vs Case temperature Input bias offset current vs Case temperature Quiescent current vs Supply voltage Input offset voltage vs Case temperature Common-mode rejection ratio vs Input common-mode range Output voltage vs Load resistance Closed-loop output impedance vs Frequency Harmonic distortion (single-ended and differential input) vs Output common-mode voltage Small signal frequency response at VOCM Output offset voltage vs Output common-mode voltage Quiescent current vs Power-down voltage Turnon and turnoff delay times Single-ended output impedance in power down vs Frequency Power-down quiescent current vs Case temperature Power-down quiescent current vs Supply voltage 38 39 40 41 42 43, 44 45 46 47 48 49, 50 51, 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
8
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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
TYPICAL CHARACTERISTICS (5 V Graphs)
SMALL SIGNAL UNITY GAIN FREQUENCY SMALL SIGNAL FREQUENCY RESPONSE RESPONSE
1 0.5 Small Signal Unity Gain - dB 0 Small Signal Gain - dB -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 0.1 1 10 100 1000 f - Frequency - MHz Gain = 1 RL = 800 Rf = 499 PIN = -20 dBm VS = 5 V 22 20 18 16 14 12 10 8 6 4 2 0 -2 0.1 RL = 800 Rf =499 PIN = -20 dBm VS = 5 V 1 10 100 1000 Gain = 2 Gain = 5 0.1 dB Gain Flatness - dB Gain = 10 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 1 10 100 1000 f - Frequency - MHz f - Frequency - MHz Gain = 1 RL = 800 PIN = -20 dBm VS = 5 V Rf = 499
0.1 dB GAIN FLATNESS FREQUENCY RESPONSE
Figure 1
Figure 2 HARMONIC DISTORTION vs FREQUENCY
0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 HD3 1 10 100 HD2 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V 0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.5 1
Figure 3 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V
LARGE SIGNAL FREQUENCY RESPONSE
25 20 Large Signal Gain - dB Gain = 10, Rf = 1.8 k RL = 800 VO = 2 VPP VS = 5 V
15 10
Gain = 5, Rf = 1.8 k
Gain = 2, Rf = 1.8 k 5 Gain = 1, Rf = 499 0 -5 0.1 1 10 100 1000 f - Frequency - MHz
HD2
HD3 1.5 2 2.5 3 3.5 4 4.5 5
-100 0.1
f - Frequency - MHz
VO - Output Voltage Swing - V
Figure 4 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - Output Voltage Swing - V HD3 HD2 Single Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 30 MHz VS = 5 V 0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 0 HD3, 8 MHz 400
Figure 5
Figure 6 THIRD-ORDER INTERMODULATION DISTORTION vs FREQUENCY
Third-Order Intermodulation Distortion - dBc -30 -40 -50 -60 -70 -80 -90 200 kHz Tone Spacing -100 10 f - Frequency - MHz 100 VO = 1 VPP Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VS = 5 V VO = 2 VPP
HARMONIC DISTORTION vs LOAD RESISTANCE
Single-Ended Input to Differential Output Gain = 1 VO = 2 VPP Rf = 499 VS = 5 V HD3, 30 MHz HD2, 30 MHz
HD2, 8 MHz
800
1200
1600
RL - Load Resistance -
Figure 7
Figure 8
Figure 9
9
THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
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TYPICAL CHARACTERISTICS (5 V Graphs)
THIRD-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
60 50 Gain = 1 Rf = 499 VO = 2 VPP VS = 5 V 200 kHz Tone Spacing Normalized to 50
OIP - Third-Order Output Intersept Point - dBm 3
SLEW RATE vs DIFFERENTIAL OUTPUT VOLTAGE STEP
2000 1800 SR - Slew Rate - V/ s 1600 1400 1200 1000 800 600 400 200 0 -1.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - Differential Output Voltage Step - V Gain = 1 RL = 800 Rf = 499 VS = 5 V Fall 1.5
SETTLING TIME
Rising Edge 1
Rise
VO - Output Voltage - V
40
0.5
30
0
Gain = 1 RL = 800 Rf = 499 f= 1 MHz VS = 5 V Falling Edge
20 10 0 0
Normalized to 200 RL = 800 200 kHz Tone Spacing 20 40 60 80 100
-0.5 -1
0
50
100
150
200
250
300
f - Frequency - MHz
t - Time - ns
Figure 10
Figure 11
Figure 12
SETTLING TIME
3 Rising Edge 2
LARGE-SIGNAL TRANSIENT RESPONSE
2 1.5 VO - Output Voltage - V
SMALL-SIGNAL TRANSIENT RESPONSE
0.4 0.3 VO - Output Voltage - V 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -100 Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V
VO - Output Voltage - V
1 0.5 0 -0.5 -1 -1.5 -2 -100 0 100 200 300 400 500 Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V
1
0 -1
Gain = 1 RL = 800 Rf = 499 f= 1 MHz VS = 5 V
Falling Edge -2
-3
0
5
10
15
20
25
30
35
40
0
100
200
300
400
500
t - Time - ns
t - Time - ns
t - Time - ns
Figure 13
Figure 14
Figure 15
OVERDRIVE RECOVERY
5 Single-Ended Output Voltage - V 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t - Time - s Gain = 4 RL = 800 Rf = 499 Overdrive = 4.5 V VS = 5 V 2.5 2 Single-Ended Output Voltage - V 1.5 VI - Input Voltage - V 1 0.5 0 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0
OVERDRIVE RECOVERY
3 Gain = 4 RL = 800 Rf = 499 Overdrive = 5.5 V VS = 5 V 2 1 VI - Input Voltage - V Hz
VOLTAGE AND CURRENT NOISE vs FREQUENCY
100 Hz 10 Vn In 1 0.01 0.1 1 10 100 1000 10 k f - Frequency - kHz
0 -1 -2 -3 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t - Time - s
-0.5 -1
-1.5 -2 -2.5
Figure 16 10
Figure 17
Vn - Voltage Noise - nV/
Figure 18
I n - Current Noise - pA/
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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
TYPICAL CHARACTERISTICS (5 V Graphs)
REJECTION RATIOS vs FREQUENCY
90 80 70 Rejection Ratios - dB 60 50 40 30 20 10 0 -10 0.1 1 10 f - Frequency - MHz 100 RL = 800 VS = 5 V PSRR- CMMR Rejection Ratios - dB PSRR+ 100 PSRR+ 80 60 40 120 CMMR Output Balance Error - dB
REJECTION RATIOS vs CASE TEMPERATURE
10 0 -10 -20 -30 -40 -50 -60 -70 -80 0.1
OUTPUT BALANCE ERROR vs FREQUENCY
PIN = 16 dBm RL = 800 Rf = 499 VS = 5 V
20
RL = 800 VS = 5 V
0 -40 -30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
1
10
100
f - Frequency - MHz
Figure 19 OPEN-LOOP GAIN AND PHASE vs FREQUENCY
60 Gain 50 Open-Loop Gain - dB PIN = -30 dBm RL = 800 VS = 5 V 30 58 57 0 56 Open-Loop Gain - dB -30 Phase - -60 Phase 20 10 0 0.01 -90 -120 50 0.1 1 10 100 -150 1000 55 54 53 52 51
Figure 20 OPEN-LOOP GAIN vs CASE TEMPERATURE
RL = 800 VS = 5 V
Figure 21 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE
3.4 3.3 I IB - Input Bias Current - A 3.2 3.1 3 2.9 2.8 2.7 2.6 IOS IIB+ VS = 5 V 0 I OS - Input Offset Current - A IIB- -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08
40 30
49 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
f - Frequency - MHz
-0.09 2.5 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
Figure 22
Figure 23
Figure 24
QUIESCENT CURRENT vs SUPPLY VOLTAGE
25 TA = 85C VOS - Input Offset Voltage - mV 20 Quiescent Current - mA TA = 25C 15 TA = -40C 10 4 5
INPUT OFFSET VOLTAGE vs CASE TEMPERATURE
CMRR - Common-Mode Rejection Ratio - dB VS = 5 V
COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE
110 100 90 80 70 60 50 40 30 20 10 0 -10 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 Input Common-Mode Voltage Range - V VS = 5 V
3
2
5
1
0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V
0 -40 -30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
Figure 25
Figure 26
Figure 27 11
THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
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TYPICAL CHARACTERISTICS (5 V Graphs)
OUTPUT VOLTAGE vs LOAD RESISTANCE
5 4 VO - Output Voltage - V 3 2 1 0 -1 -2 -3 -4 -5 10 100 1000 10000 VS = 5 V TA = -40 to 85C
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100 ZO - Closed Loop Output Impedance - Gain = 1 RL = 400 Rf = 499 VI = -4 dBm VS = 5 V
HARMONIC DISTORTION vs OUTPUT COMMON-MODE VOLTAGE
0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 HD2, 3 MHz HD2, 8 MHz Single-Ended to Differential Output Gain = 1 VO = 2 VPP Rf = 499 VS = 5 V HD3, 30 MHz HD2, 30 MHz
10
1
0.1 0.1
RL - Load Resistance -
1 10 f - Frequency - MHz
100
-100 -3.5 -2.5 -1.5 -0.5
0.5
1.5
2.5
3.5
VOCM - Output Common-Mode Voltage - V
Figure 28
Figure 29 OUTPUT OFFSET VOLTAGE at VOCM vs OUTPUT COMMON-MODE VOLTAGE
600 VOS - Output Offset Voltage - mV 30 25 Quiescent Current - mA 20 15 10 5 0 -5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Figure 30 QUIESCENT CURRENT vs POWER-DOWN VOLTAGE
Small Signal Frequency Response at VOCM - dB
SMALL SIGNAL FREQUENCY RESPONSE at VOCM
3 2 Gain = 1 RL = 400 Rf = 499 PIN= -20 dBm VS = 5 V
400 200
1
0 -1 -2
0
-200
-400 -600
-3 1 10 100 1000 f - Frequency - MHz
-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 Power-Down Voltage - V
VOC - Output Common-Mode Voltage - V
Figure 31
Figure 32
Figure 33
TURNON AND TURNOFF DELAY TIME
0.03 Powerdown Voltage Signal - V 0.02 0.01 Current 0 -1 -2 -3 -4 -5 -6 0 0.5 1 1.5 2 2.5 3 100.5 101 t - Time - ms 102 103 0 Quiescent Current - mA
SINGLE-ENDED OUTPUT IMPEDANCE IN POWER DOWN vs FREQUENCY
1500 ZO- Single-Ended Output Impedance in Powerdown -
1200
900
600 Gain = 1 RL = 800 Rf = 499 VI = -1 dBm VS = 5 V 1 10 100 1000
300
0 0.1
f - Frequency - MHz
Figure 34 12
Figure 35
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THS4504 THS4505
SLOS363A - AUGUST 2002 - REVISED AUGUST 2003
TYPICAL CHARACTERISTICS (5 V Graphs)
POWER-DOWN QUIESCENT CURRENT vs CASE TEMPERATURE
1000 Power-Down Quiescent Current - A 900 800 700 600 500 400 300 200 100 0 -40 -30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C Power-Down Quiescent Current - A RL = 800 VS = 5 V
POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE
1000 900 800 700 600 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V RL = 800
Figure 36
Figure 37
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TYPICAL CHARACTERISTICS (5 V Graphs)
SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE
1
SMALL SIGNAL FREQUENCY RESPONSE
22 20 Gain = 10 0.05 0 0.1 dB Gain Flatness - dB Gain = 5 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 10 100 1000 1
0.1 dB GAIN FLATNESS FREQUENCY RESPONSE
Small Signal Unity Gain - dB
0 Small Signal Gain - dB
18 16 14 12 10 8 6 4 2 0 -2 0.1 RL = 800 Rf = 499 PIN = -20 dBm VS = 5 V 1 Gain = 2
Rf = 499
-1
-2 Gain = 1 RL = 800 Rf = 499 PIN = -20 dBm VS = 5 V 0.1 1 10 100 1000
-3
-4 f - Frequency - MHz
Gain = 1 RL = 800 PIN = -20 dBm VS = 5 V 10 100 1000
f - Frequency - MHz
f - Frequency - MHz
Figure 38
Figure 39
Figure 40
LARGE SIGNAL FREQUENCY RESPONSE
25 Gain = 10, Rf = 1.8 k 20 Large Signal Gain - dB Gain = 5, Rf = 1.8 k RL = 800 VO = 2 VPP VS = 5 V 0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60
HARMONIC DISTORTION vs FREQUENCY
0 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VO = 2 VPP VS = 5 V -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 0
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 8 MHz VS = 5 V
15 10
Gain = 2, Rf = 1.8 k 5 Gain = 1, Rf = 1.8 k
HD3 -70 -80 -90 HD2
HD3 HD2
0 -5 0.1
1
10
100
1000
-100 0.1
0.5
1
1.5
2
2.5
3
3.5
4
f - Frequency - MHz
f - Frequency - MHz
VO - Output Voltage Swing - V
Figure 41
Figure 42
Figure 43 THIRD-ORDER INTERMODULATION DISTORTION vs FREQUENCY
Third-Order Intermodulation Distortion - dBc -30 -40 -50 -60 -70 -80 -90 200 kHz Tone Spacing -100 10 f - Frequency - MHz 100 VO = 1 VPP Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 VS = 5 V VO = 2 VPP
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 HD3 Single-Ended Input to Differential Output Gain = 1 RL = 800 Rf = 499 f= 30 MHz VS = 5 V HD2 0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 0
HARMONIC DISTORTION vs LOAD RESISTANCE
Single-Ended Input to Differential Output Gain = 1 VO = 2 VPP Rf = 499 VS = 5 V HD3, 30 MHz HD2, 30 MHz
HD3, 8 MHz 400
HD2, 8 MHz 800 1200 1600
VO - Output Voltage Swing - V
RL - Load Resistance -
Figure 44 14
Figure 45
Figure 46
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TYPICAL CHARACTERISTICS (5 V Graphs)
THIRD-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
60 50 Gain = 1 Rf = 499 VO = 2 VPP VS = 5 V 200 kHz Tone Spacing Normalized to 50
OIP - Third-Order Output Intersept Point - dBm 3
SLEW RATE vs DIFFERENTIAL OUTPUT VOLTAGE STEP
1200 1000 SR - Slew Rate - V/ s 800 Gain = 1 RL = 800 Rf = 499 VS = 5 V 1.5 Fall 1 VO - Output Voltage - V Rise 0.5
SETTLING TIME
Rising Edge
40
30
600 400 200
0 -0.5
Gain = 1 RL = 800 Rf = 499 f= 1 MHz VS = 5 V
20 10 0 0
Normalized to 200 RL = 800
Falling Edge -1
0 20 40 60 80 100 f - Frequency - MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
-1.5
0
50
100
150
200
250
300
VO - Differential Output Voltage Step - V
t - Time - ns
Figure 47
Figure 48
Figure 49
SETTLING TIME
3 Rising Edge Single-Ended Output Voltage - V 2 VO - Output Voltage - V 1 Gain = 1 RL = 800 Rf = 499 f= 1 MHz VS = 5 V 5 4 3 2 1 0 -1 -2 -3 -4 -3 0 5 10 15 20 25 30 35 40 -5 0
OVERDRIVE RECOVERY
2.5 Single-Ended Output Voltage - V Gain = 4 RL = 800 Rf = 499 Overdrive = 4.5 V VS = 5 V 2 1.5 VI - Input Voltage - V 1 0.5 0 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0
OVERDRIVE RECOVERY
3 Gain = 4 RL = 800 Rf = 499 Overdrive = 5.5 V VS = 5 V 2 1 VI - Input Voltage - V I n - Current Noise - pA/ 10 k Hz 10 Vn In 1 0.01 0.1 1 10 100 1000 f - Frequency - kHz
0 -1
0 -1 -2 -3 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t - Time - s
-0.5 -1
Falling Edge -2
-1.5 -2 -2.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t - Time - s
t - Time - ns
Figure 50
Figure 51
Figure 52 VOLTAGE AND CURRENT NOISE vs FREQUENCY
100 Hz
LARGE-SIGNAL TRANSIENT RESPONSE
2 1.5 VO - Output Voltage - V
SMALL-SIGNAL TRANSIENT RESPONSE
0.4 0.3 VO - Output Voltage - V 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -100 Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V
0.5 0 -0.5 -1 -1.5 -2 -100 0
Gain = 1 RL = 800 Rf = 499 tr/tf = 300 ps VS = 5 V
100
200
300
400
500
0
100
200
300
400
500
t - Time - ns
t - Time - ns
Figure 53
Figure 54
Vn - Voltage Noise - nV/
1
Figure 55 15
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TYPICAL CHARACTERISTICS (5 V Graphs)
REJECTION RATIOS vs FREQUENCY
90 80 70 Rejection Ratios - dB 60 50 40 30 20 10 0 -10 0.1 1 10 f - Frequency - MHz 100 RL = 800 VS = 5 V PSRR- CMMR Rejection Ratios - dB PSRR+ 100 120
REJECTION RATIOS vs CASE TEMPERATURE
0 CMMR Output Balance Error - dB PSRR- 80 PSRR+ 60 40 -10 -20 -30 -40 -50 -60 -70 -80 0.1
OUTPUT BALANCE ERROR vs FREQUENCY
PIN = 16 dBm RL = 800 Rf = 499 VS = 5 V
20
RL = 800 VS = 5 V
0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
1
10
100
f - Frequency - MHz
Figure 56
Figure 57
Figure 58 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE
3.75 I IB - Input Bias Current - A RL = 800 VS = 5 V 3.5 VS = 5 V IIB+ IIB- 0 -0.01 -0.02 -0.03 -0.04 -0.05 IOS -0.06 -0.07 -0.08 -0.09 I OS - Input Offset Current - A
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
60 Gain 50 Open-Loop Gain - dB PIN = -30 dBm RL = 800 VS = 5 V 30 57 56 0 Open-Loop Gain - dB -30 -60 Phase 20 10 0 0.01 -90 -120 -150 1000 55 54 53 52 51 50 49 48 47 46 0.1 1 10 100 Phase -
OPEN-LOOP GAIN vs CASE TEMPERATURE
3.25 3
40 30
2.75 2.5
2.25 2
1.75 1.5
-40-30-20-100 10 20 30 40 50 60 70 80 90 Case Temperature - C
-0.1 1.25 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
f - Frequency - MHz
Figure 59 QUIESCENT CURRENT vs SUPPLY VOLTAGE
25 TA = 85C 20 Quiescent Current - mA TA = 25C 15 TA = -40C 10 VOS - Input Offset Voltage - mV 4 5 VS = 5 V
Figure 60 INPUT OFFSET VOLTAGE vs CASE TEMPERATURE
CMRR - Common-Mode Rejection Ratio - dB
Figure 61 COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE
110 100 90 80 70 60 50 40 30 20 10 0 -10 -1 0 1 2 3 4 5 Input Common-Mode Range - V VS = 5 V
3
2
5
1
0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V
0 -40 -30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
Figure 62 16
Figure 63
Figure 64
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TYPICAL CHARACTERISTICS (5 V Graphs)
OUTPUT VOLTAGE vs LOAD RESISTANCE
ZO - Closed Loop Output Impedance - 5 4 VO - Output Voltage - V 3 2 1 0 -1 -2 -3 -4 -5 10 100 1000 10000 VS = 5 V TA = -40 to 85C
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100 Gain = 1 RL = 400 Rf = 499 VIN = -4 dBm VS = 5 V
HARMONIC DISTORTION vs OUTPUT COMMON-MODE VOLTAGE
0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 HD2, 8 MHz 1 1.5 HD3, 8 MHz Single-Ended to Differential Output Gain = 1, VO = 2 VPP Rf = 499 , VS = 5 V HD2, 30 MHz HD3, 30 MHz
10
1
0.1 0.1
-80 1 10 f - Frequency - MHz 100
2
2.5
3
3.5
4
RL - Load Resistance -
VOC - Output Common-Mode Voltage - V
Figure 65
Figure 66
Figure 67 QUIESCENT CURRENT vs POWER-DOWN VOLTAGE
25 VS = 5 V Quiescent Current - mA 20
Small Signal Frequency Response at VOCM - dB
SMALL SIGNAL FREQUENCY RESPONSE at VOCM
3 2 VOS - Output Offset Voltage - mV Gain = 1 RL = 400 Rf = 499 PIN= -20 dBm VS = 5 V
OUTPUT OFFSET VOLTAGE vs OUTPUT COMMON-MODE VOLTAGE
800 600 400 200 0
1
15
0 -1 -2
-200 -400 -600 -800
10
5
-3 1 10 100 1000 f - Frequency - MHz
0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Power-down Voltage - V VOC - Output Common-Mode Voltage - V
Figure 68
Figure 69
Figure 70
TURNON AND TURNOFF DELAY TIME
0.03 Power-Down Voltage Signal - V 0.02 0.01 Current 0 -1 -2 -3 -4 -5 -6 0 0.5 1 1.5 2 2.5 3 100.5 101 t - Time - ms 102 103 0 Quiescent Current - mA
Figure 71
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TYPICAL CHARACTERISTICS (5 V Graphs)
SINGLE-ENDED OUTPUT IMPEDANCE IN POWER DOWN vs FREQUENCY
Power-Down Quiescent Current - A 1500 ZO- Single-Ended Output Impedance in Power Down -
POWER-DOWN QUIESCENT CURRENT vs CASE TEMPERATURE
800 700 600 500 400 300 200 100 0 -40 -30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C RL = 800 VS = 5 V
POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE
1000 Power-Down Quiescent Current - A 900 800 700 600 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V
1200
900
600
300
Gain = 1 RL = 800 Rf = 499 PIN = -1 dBm VS = 5 V 1 10 100 1000
0 0.1
f - Frequency - MHz
Figure 72
Figure 73
Figure 74
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APPLICATION INFORMATION FULLY DIFFERENTIAL AMPLIFIERS
Differential signaling offers a number of performance advantages in high-speed analog signal processing systems, including immunity to external common-mode noise, suppression of even-order nonlinearities, and increased dynamic range. Fully differential amplifiers not only serve as the primary means of providing gain to a differential signal chain, but also provide a monolithic solution for converting single-ended signals into differential signals for easier, higher performance processing. The THS4500 family of amplifiers contains the flagship products in Texas Instruments' expanding line of high-performance fully differential amplifiers. Information on fully differential amplifier fundamentals, as well as implementation specific information, is presented in the applications section of this data sheet to provide a better understanding of the operation of the THS4500 family of devices, and to simplify the design process for designs using these amplifiers. The THS4504 and THS4505 are intended to be low-cost alternatives to the THS4500/1/2/3 devices. From a topology standpoint, the THS4504/5 have the same architecture as the THS4500/1. Specifically, the input common-mode range is designed to include the negative power supply rail.
D D
Evaluation Fixtures, Spice Models, and Applications Support Additional Reference Material
FULLY DIFFERENTIAL AMPLIFIER TERMINAL FUNCTIONS
Fully differential amplifiers are typically packaged in eight-pin packages as shown in the diagram. The device pins include two inputs (VIN+, VIN-), two outputs (VOUT-, VOUT+), two power supplies (VS+, VS-), an output common-mode control pin (VOCM), and an optional power-down pin (PD).
VIN- 1 VOCM 2 VS+ 3 VOUT+ 4
8 VIN+ 7 PD 6 VS- 5 VOUT-
Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in the figure. The functionality of a fully differential amplifier can be imagined as two inverting amplifiers that share a common noninverting terminal (though the voltage is not necessarily fixed). For more information on the basic theory of operation for fully differential amplifiers, refer to the Texas Instruments application note titled Fully Differential Amplifiers, literature number SLOA054.
Applications Section
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Fully Differential Amplifier Terminal Functions Input Common-Mode Voltage Range and the THS4500 Family Choosing the Proper Value for the Feedback and Gain Resistors Application Circuits Using Fully Differential Amplifiers Key Design Considerations for Interfacing to an Analog-to-Digital Converter Setting the Output Common-Mode Voltage With the VOCM Input Saving Power with Power-Down Functionality Linearity: Definitions, Terminology, Circuit Techniques, and Design Tradeoffs An Abbreviated Analysis of Noise in Fully Differential Amplifiers Printed-Circuit Board Layout Techniques for Optimal Performance Power Dissipation and Thermal Considerations Power Supply Decoupling Techniques and Recommendations
INPUT COMMON-MODE VOLTAGE RANGE AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the THS4502/3 is the input common-mode range for the two devices. The input common-mode range of the THS4504/5 is the same as the THS4500/1. The THS4502 and THS4503 have an input common-mode range that is centered around midrail, and the THS4500 and THS4501 have an input common-mode range that is shifted to include the negative power supply rail. Selection of one or the other is determined by the nature of the application. Specifically, the THS4500 and THS4501 are designed for use in single-supply applications where the input signal is ground-referenced, as depicted in Figure 75. The THS4502 and THS4503 are designed for use in single-supply or split-supply applications where the input signal is centered between the power supply voltages, as depicted in Figure 76.
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RS VS
Rg1 RT VOCM
Rf1 VIN+ +VS +- -+
Rg
Rf
Vp VOCM Vn
+- -+
VOUT- VOUT+
Rg2
VIN- Rf2
Rg
Rf
Application Circuit for the THS4500 and THS4501, Featuring Single-Supply Operation With a Ground-Referenced Input Signal
Diagram For Input Common-Mode Range Equations
Figure 77
The two tables below depict the input common-mode range requirements for two different input scenarios, an input referenced around the negative rail and an input referenced around midrail. The tables highlight the differing requirements on input common-mode range, and illustrate reasoning for choosing either the THS4500/1 or the THS4502/3. For signals referenced around the negative power supply, the THS4500/1 should be chosen since its input common-mode range includes the negative supply rail. For all other situations, the THS4502/3 offers slightly improved distortion and noise performance for applications with input signals centered between the power supply rails.
Figure 75
RS VS Rg1 RT VOCM Rf1 +VS +- -+ -VS Rg2 Rf2
Application Circuit for the THS4500 and THS4501, Featuring Split-Supply Operation With an Input Signal Referenced at the Midrail
Figure 76
Equations 1-5 allow for calculation of the required input common-mode range for a given set of input conditions. The equations allow calculation of the input commonmode range requirements given information about the input signal, the output voltage swing, the gain, and the output common-mode voltage. Calculating the maximum and minimum voltage required for VN and VP (the amplifier's input nodes) determines whether or not the input common-mode range is violated or not. Four equations are required. Two calculate the output voltages and two calculate the node voltages at VN and VP (note that only one of these needs calculation, as the amplifier forces a virtual short between the two nodes). V (1-)-V IN-(1-) ) 2V OCM (1) V OUT) + IN) 2 -V IN)(1-) ) V IN-(1-) ) 2V OCM V OUT- + 2 V N + V IN-(1-) ) V OUT) Where: RG + RF ) RG (2) (3) (4) (5)
Gain (V/V) 1 2 4 8
Table 1. Negative-Rail Referenced
VIN+ (V) -2.0 to 2.0 -1.0 to 1.0 -0.5 to 0.5 -0.25 to 0.25 VIN- (V) 0 0 0 0 VIN (VPP) 4 2 1 0.5 VOCM (V) 2.5 2.5 2.5 2.5 VOD (VPP) 4 4 4 4 VNMIN (V) 0.75 0.5 0.3 0.167 VNMAX (V) 1.75 1.167 0.7 0.389
NOTE: This table assumes a negative-rail referenced, single-ended input signal on a single 5-V supply as shown in Figure 75. VNMIN = VPMIN and VNMAX = VPMAX.
Table 2. Midrail Referenced
Gain (V/V) 1 2 4 8 VIN+ (V) 0.5 to 4.5 1.5 to 3.5 2.0 to 3.0 2.25 to 2.75 VIN- (V) 2.5 2.5 2.5 2.5 VIN (VPP) 4 2 1 0.5 VOCM (V) 2.5 2.5 2.5 2.5 VOD (VPP) 4 4 4 4 VNMIN (V) 2 2.16 2.3 2.389 VNMAX (V) 3 2.83 2.7 2.61
V P + V IN)(1-) ) V OUT-
NOTE:
The equations denote the device inputs as VN and VP, and the circuit inputs as VIN+ and VIN-.
20
NOTE: This table assumes a midrail referenced, single-ended input signal on a single 5-V supply. VNMIN = VPMIN and VNMAX = VPMAX.
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CHOOSING THE PROPER VALUE FOR THE FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts circuit performance in a number of ways. The values in this section provide the optimum high frequency performance (lowest distortion, flat frequency response). Since the THS4500 family of amplifiers is developed with a voltage feedback architecture, the choice of resistor values does not have a dominant effect on bandwidth, unlike a current feedback amplifier. However, resistor choices do have second-order effects. For optimal performance, the following feedback resistor values are recommended. In higher gain configurations (gain greater than two), the feedback resistor values have much less effect on the high frequency performance. Example feedback and gain resistor values are given in the section on basic design considerations (Table 3). Amplifier loading, noise, and the flatness of the frequency response are three design parameters that should be considered when selecting feedback resistors. Larger resistor values contribute more noise and can induce peaking in the ac response in low gain configurations, and smaller resistor values can load the amplifier more heavily, resulting in a reduction in distortion performance. In addition, feedback resistor values, coupled with gain requirements, determine the value of the gain resistors, directly impacting the input impedance of the entire circuit. While there are no strict rules about resistor selection, these trends can provide qualitative design guidance.
Table 3. Resistor Values for Balanced Operation in Various Gain Configurations
Gain VOD VIN 1 1 2 2 5 5 10 10 R2 & R4 () 392 499 392 1.3k 1.3k 3.32k 1.3k 6.81k R1 () 412 523 215 665 274 681 147 698 R3 () 383 487 187 634 249 649 118 681 RT () 54.9 53.6 60.4 52.3 56.2 52.3 64.9 52.3
NOTE: Values in the table above assume a 50 source impedance. R1 R2
Vn RS VS R3 VP RT
-
+ +-
Vout+ Vout- VOCM
R4
Figure 78
Equations for calculating fully differential amplifier resistor values in order to obtain balanced operation in the presence of a 50- source impedance are given in equations 6 through 9. RT + 1 1- K 1 - 2(1)K) RS R3 K + R2 R1 R2 + R4 (6)
APPLICATION CIRCUITS USING FULLY DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a great deal of flexibility in a wide variety of applications. This section provides an overview of some common circuit configurations and gives some design guidelines. Designing the interface to an ADC, driving lines differentially, and filtering with fully differential amplifiers are a few of the circuits that are covered.
R3 + R1 * Rs || R T (7)
1 +
R3 ) RT || R S R1 2 + R1 ) R2 R3 ) RT || R S ) R4 RT RT ) RS
V OD 1- 2 +2 1 ) 2 VS V OD 1- 2 +2 1 ) 2 V IN
(8) (9)
BASIC DESIGN CONSIDERATIONS
The circuits in Figures 75 through 78 are used to highlight basic design considerations for fully differential amplifier circuit designs.
For more detailed information about balance in fully differential amplifiers, see Fully Differential Amplifiers, referenced at the end of this data sheet.
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INTERFACING TO AN ANALOG-TO-DIGITAL CONVERTER
The THS4500 family of amplifiers are designed specifically to interface to today's highest-performance analog-to-digital converters. This section highlights the key concerns when interfacing to an ADC and provides example ADC/fully differential amplifier interface circuits. Key design concerns when analog-to-digital converter: interfacing to an
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Terminate the input source properly. In high-frequency receiver chains, the source feeding the fully differential amplifier requires a specific load impedance (e.g., 50 ). Design a symmetric printed-circuit board layout. Even-order distortion products are heavily influenced by layout, and careful attention to a symmetric layout will minimize these distortion products. Minimize inductance in power supply decoupling traces and components. Poor power supply decoupling can have a dramatic effect on circuit performance. Since the outputs are differential, differential currents exist in the power supply pins. Thus, decoupling capacitors should be placed in a manner that minimizes the impedance of the current loop. Use separate analog and digital power supplies and grounds. Noise (bounce) in the power supplies (created by digital switching currents) can couple directly into the signal path, and power supply noise can create higher distortion products as well. Use care when filtering. While an RC low-pass filter may be desirable on the output of the amplifier to filter broadband noise, the excess loading can negatively impact the amplifier linearity. Filtering in the feedback path does not have this effect. AC-coupling allows easier circuit design. If dc-coupling is required, be aware of the excess power dissipation that can occur due to level-shifting the output through the output common-mode voltage control. Do not terminate the output unless required. Many open-loop, class-A amplifiers require 50- termination for proper operation, but closed-loop fully differential amplifiers drive a specific output voltage regardless of the load impedance present. Terminating the output of a fully differential amplifier with a heavy load adversely effects the amplifier's linearity. Comprehend the VOCM input drive requirements. Determine if the ADC's voltage reference can provide
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the required amount of current to move VOCM to the desired value. A buffer may be needed. Decouple the VOCM pin to eliminate the antenna effect. VOCM is a high-impedance node that can act as an antenna. A large decoupling capacitor on this node eliminates this problem. Be cognizant of the input common-mode range. If the input signal is referenced around the negative power supply rail (e.g., around ground on a single 5 V supply), then the THS4500/1 accommodates the input signal. If the input signal is referenced around midrail, choose the THS4502/3 for the best operation. Packaging makes a difference at higher frequencies. If possible, choose the smaller, thermally enhanced MSOP package for the best performance. As a rule, lower junction temperatures provide better performance. If possible, use a thermally enhanced package, even if the power dissipation is relatively small compared to the maximum power dissipation rating to achieve the best results. Comprehend the effect of the load impedance seen by the fully differential amplifier when performing system-level intercept point calculations. Lighter loads (such as those presented by an ADC) allow smaller intercept points to support the same level of intermodulation distortion performance.
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EXAMPLE ANALOG-TO-DIGITAL CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive high-performance ADCs with extremely high linearity, allowing for the maximum effective number of bits at the output of the data converter. Two representative circuits shown below highlight single-supply operation and split supply operation. Specific feedback resistor, gain resistor, and feedback capacitor values are not specified, as their values depend on the frequency of interest. Information on calculating these values can be found in the applications material above.
CF RS VS Rg RT 5V 10 F +- VOCM + - THS4503 -5 V 10 F 0.1 F 0.1 F Rf CF 0.1 F 5V Riso IN ADS5410 12 Bit/80 MSps IN CM Rf
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1 F Rg
Riso
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22
Using the THS4503 With the ADS5410
Figure 79
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CF
RS VS
Rg RT 5V
Rf
10 F +- VOCM + -
0.1 F
5V Riso IN ADS5421 14 Bit/40 MSps IN CM Riso
applicable to many different types of systems. The first pole is set by the resistors and capacitors in the feedback paths, and the second pole is set by the isolation resistors and the capacitor across the outputs of the isolation resistors.
CF1
1 F Rg
THS4501
RS Rf CF 0.1 F VS RT
Rg1
Rf1 Riso + - - + Riso Rf2 C VO
Rg2
Using the THS4501 With the ADS5421
Figure 80
CF2
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as high-frequency, high-swing differential line drivers. Their high power supply voltage rating (16.5 V absolute maximum) allows operation on a single 12-V or a single 15-V supply. The high supply voltage, coupled with the ability to provide differential outputs enables the ability to drive 26 VPP into reasonably heavy loads (250 or greater). The circuit in Figure 81 illustrates the THS4500 family of devices used as high speed line drivers. For line driver applications, close attention must be paid to thermal design constraints due to the typically high level of power dissipation.
RS CG Rg Rf 15 V Riso VOCM 0.1 F + -
THS4504
A Two-Pole, Low-Pass Filter Design Using a Fully Differential Amplifier With Poles Located at: P1 = (2RfCF)-1 in Hz and P2 = (4RisoC)-1 in Hz
Figure 82
Often times, filters like these are used to eliminate broadband noise and out-of-band distortion products in signal acquisition systems. It should be noted that the increased load placed on the output of the amplifier by the second low-pass filter has a detrimental effect on the distortion performance. The preferred method of filtering is using the feedback network, as the typically smaller capacitances required at these points in the circuit do not load the amplifier nearly as heavily in the pass-band.
VS
RT
CS RL
SETTING THE OUTPUT COMMON-MODE VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a critical function to the fully differential amplifier; it accepts an input voltage and reproduces that input voltage as the output common-mode voltage. In other words, the VOCM input provides the ability to level-shift the outputs to any voltage inside the output voltage swing of the amplifier. A description of the input circuitry of the VOCM pin is shown below to facilitate an easier understanding of the VOCM interface requirements. The VOCM pin has two 50-k resistors between the power supply rails to set the default output common-mode voltage to midrail. A voltage applied to the VOCM pin alters the output common-mode voltage as long as the source has the ability to provide enough current to overdrive the two 50-k resistors. This phenomenon is depicted in the VOCM equivalent circuit diagram. The table contains some representative examples to aid in determining the current drive requirement for the VOCM voltage source. This parameter is especially important when using the reference voltage
23
-+
VDD Riso CS
Rg CG
Rf
VOD = 26 VPP
Fully Differential Line Driver With High Output Swing
Figure 81
FILTERING WITH FULLY DIFFERENTIAL AMPLIFIERS
Similar to their single-ended counterparts, fully differential amplifiers have the ability to couple filtering functionality with voltage gain. Numerous filter topologies can be based on fully differential amplifiers. Several of these are outlined in A Differential Circuit Collection, (literature number SLOA064) referenced at the end of this data sheet. The circuit below depicts a simple two-pole low-pass filter
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of an analog-to-digital converter to drive VOCM. Output current drive capabilities differ from part to part, so a voltage buffer may be necessary in some applications.
RS
I1 =
VOCM Rf1+ Rg1 + RS || RT DC Current Path to Ground
Rg1 RT VOCM = 2.5 V
Rf1 5V +- -+ 2.5-V DC
VS+ R = 50 k VOCM IIN R = 50 k IIN = 2 VOCM - VS+ - VS- R
VS
RL
Rg2
Rf2
2.5-V DC
DC Current Path to Ground
VS- Equivalent Input Circuit for VOCM
VOCM I2 = Rf2 + Rg2
Figure 83
Depiction of DC Power Dissipation Caused By Output Level-Shifting in a DC-Coupled Circuit
Figure 84
By design, the input signal applied to the VOCM pin propagates to the outputs as a common-mode signal. As shown in the equivalent circuit diagram, the VOCM input has a high impedance associated with it, dictated by the two 50-k resistors. While the high impedance allows for relaxed drive requirements, it also allows the pin and any associated printed-circuit board traces to act as an antenna. For this reason, a decoupling capacitor is recommended on this node for the sole purpose of filtering any high frequency noise that could couple into the signal path through the VOCM circuitry. A 0.1-F or 1-F capacitance is a reasonable value for eliminating a great deal of broadband interference, but additional, tuned decoupling capacitors should be considered if a specific source of electromagnetic or radio frequency interference is present elsewhere in the system. Information on the ac performance (bandwidth, slew rate) of the VOCM circuitry is included in the specification table and graph section. Since the VOCM pin provides the ability to set an output common-mode voltage, the ability for increased power dissipation exists. While this does not pose a performance problem for the amplifier, it can cause additional power dissipation of which the system designer should be aware. The circuit shown in Figure 84 demonstrates an example of this phenomenon. For a device operating on a single 5-V supply with an input signal referenced around ground and an output common-mode voltage of 2.5 V, a dc potential exists between the outputs and the inputs of the device. The amplifier sources current into the feedback network in order to provide the circuit with the proper operating point. While there are no serious effects on the circuit performance, the extra power dissipation may need to be included in the system's power budget.
SAVING POWER WITH POWER-DOWN FUNCTIONALITY
The THS4500 family of fully differential amplifiers contains devices that come with and without the power-down option. Even-numbered devices have power-down capability, which is described in detail here. The power-down pin of the amplifiers defaults to the positive supply voltage in the absence of an applied voltage (i.e. an internal pullup resistor is present), putting the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the negative rail. The threshold voltages for power-on and power-down are relative to the supply rails and given in the specification tables. Above the enable threshold voltage, the device is on. Below the disable threshold voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 50% of the nominal quiescent current. The time delays are on the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions.
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LINEARITY: DEFINITIONS, TERMINOLOGY, CIRCUIT TECHNIQUES, AND DESIGN TRADEOFFS
POUT (dBm) OIP3
1X
The THS4500 family of devices features unprecedented distortion performance for monolithic fully differential amplifiers. This section focuses on the fundamentals of distortion, circuit techniques for reducing nonlinearity, and methods for equating distortion of fully differential amplifiers to desired linearity specifications in RF receiver chains. Amplifiers are generally thought of as linear devices. In other words, the output of an amplifier is a linearly scaled version of the input signal applied to it. In reality, however, amplifier transfer functions are nonlinear. Minimizing amplifier nonlinearity is a primary design goal in many applications. Intercept points are specifications that have long been used as key design criteria in the RF communications world as a metric for the intermodulation distortion performance of a device in the signal chain (e.g., amplifiers, mixers, etc.). Use of the intercept point, rather than strictly the intermodulation distortion, allows for simpler system-level calculations. Intercept points, like noise figures, can be easily cascaded back and forth through a signal chain to determine the overall receiver chain's intermodulation distortion performance. The relationship between intermodulation distortion and intercept point is depicted in Figure 85 and Figure 86.
PO
IMD3 3X
IIP3
PIN (dBm)
PS
Figure 86
Due to the intercept point's ease of use in system level calculations for receiver chains, it has become the specification of choice for guiding distortion-related design decisions. Traditionally, these systems use primarily class-A, single-ended RF amplifiers as gain blocks. These RF amplifiers are typically designed to operate in a 50- environment, just like the rest of the receiver chain. Since intercept points are given in dBm, this implies an associated impedance (50 ). However, with a fully differential amplifier, the output does not require termination as an RF amplifier would. Because closed-loop amplifiers deliver signals to their outputs regardless of the impedance present, it is important to comprehend this when evaluating the intercept point of a fully differential amplifier. The THS4500 series of devices yields optimum distortion performance when loaded with 200 to 1 k, very similar to the input impedance of an analog-to-digital converter over its input frequency band. As a result, terminating the input of the ADC to 50 can actually be detrimental to system performance. This discontinuity between open-loop, class-A amplifiers and closed-loop, class-AB amplifiers becomes apparent when comparing the intercept points of the two types of devices. Equation 10 gives the definition of an intercept point, relative to the intermodulation distortion. OIP 3 + P O ) IMD 3 2 where (10)
PO fc = fc - f1 fc = f2 - fc
PO
Power
IMD3 = PS - PO
PS
PS
fc - 3f
f1 fc
f2
fc + 3f
f - Frequency - MHz
P O + 10 log
V2 Pdiff 2RL 0.001
(11)
Figure 85
NOTE: Po is the output power of a single tone, RL is the differential load resistance, and VP(diff) is the differential peak voltage for a single tone. 25
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As can be seen in the equation, when a higher impedance is used, the same level of intermodulation distortion performance results in a lower intercept point. Therefore, it is important to comprehend the impedance seen by the output of the fully differential amplifier when selecting a minimum intercept point. The graphic below shows the relationship between the strict definition of an intercept point with a normalized, or equivalent, intercept point for the THS4502.
THIRD-ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
OIP - Third-Order Output Intersept Point - dBm 3 60 50 Gain = 1 Rf = 499 VO = 2 VPP VS = 5 V 200 kHz Tone Spacing Normalized to 50
delivered to the amplifier by the source (NI) and input noise power are used to calculate the noise factor and noise figure as shown in equations 23 through 27.
Ni NA eg Rg Rf ef
Si Ni Rs Rt es et iii eg Rg ini
en No
+ fully-diff amp -
So No
40
Rf
ef
30
20 10 0 0
Normalized to 200 RL = 800
Figure 88. Noise Sources in a Fully Differential Amplifier Circuit
80 100
20
40
60
f - Frequency - MHz
NA: Fully Differential Amplifier Noise Source Scale Factor
2
Figure 87
Comparing specifications between different device types becomes easier when a common impedance level is assumed. For this reason, the intercept points on the THS4500 family of devices are reported normalized to a 50- load impedance.
(eni)2 Rg Rg ) R sR t Rf Rg ) 2 Rs)R t
(12)
(ini)2 (iii)2
Rg2 Rg2 2RsR G Rs)2R g Rt ) 2RsRg Rs)2R g
2 2
(13) (14)
AN ANALYSIS OF NOISE IN FULLY DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is analogous to noise analysis in single-ended amplifiers. The same concepts apply. Below, a generic circuit diagram consisting of a voltage source, a termination resistor, two gain setting resistors, two feedback resistors, and a fully differential amplifier is shown, including all the relevant noise sources. From this circuit, the noise factor (F) and noise figure (NF) are calculated. The figures indicate the appropriate scaling factor for each of the noise sources in two different cases. The first case includes the termination resistor, and the second, simplified case assumes that the voltage source is properly terminated by the gain-setting resistors. With these scaling factors, the amplifier's input noise power (NA) can be calculated by summing each individual noise source with its scaling factor. The noise
4kTRt
(15)
4kTRf
2
Rg Rf
(16)
2
4kTRg
2
Rg R sR t Rg ) 2 R s)Rt
(17)
Figure 89. Scaling Factors for Individual Noise Sources Assuming a Finite Value Termination Resistor
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NA: Fully Differential Amplifier; termination = 2Rg Noise Source Scale Factor
2
D
(eni)2
Rg ) Rf
Rg Rg )
Rs
2
(18)
(ini)2 (iii)2 4kTRf
Rg2 Rg2 2 Rg Rf
2
Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1-F decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 F or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return paths. Careful selection and placement of external components preserve the high frequency performance of the THS4500 family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 k, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with
27
(19) (20) (21)
2
D
Rg
4kTRg 2
R Rg ) 2s
(22)
Figure 90. Scaling Factors for Individual Noise Sources Assuming No Termination Resistance is Used (e.g., RT is open).
2
2RtRg Ni + 4kTR s R t)2Rg 2R tRg R s) Rt)2R g
D
(23)
Figure 91. Input Noise With a Termination Resistor
Ni + 4kTR s 2R g Rs ) 2Rg
2
(24)
Figure 92. Input Noise Assuming No Termination Resistor Noise Factor and Noise Figure Calculations
N A + S Noise Source N F+1) A NI NF + 10 log (F) Scale Factor (25) (26) (27)
PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE
Achieving optimum performance with a high frequency amplifier-like devices in the THS4500 family requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include:
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ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an RS since the THS4500 family is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- environment is normally not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS4500 family is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 93(a) and Figure 93(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 93(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
DIE
Thermal Pad
End View (b)
Bottom View (c)
Figure 93. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach.
0.205 0.060 0.017 Pin 1 0.013
D
Socketing a high speed part like the THS4500 family is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4500 family parts directly onto the board.
0.030 0.075 0.025 0.094
0.010 vias
0.035
0.040
Top View
Figure 94. Views of Thermally Enhanced Package
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PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown in Figure 94. There should be etch for the leads as well as etch for the thermal pad. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS4500 family IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. Connect all holes to the internal ground plane. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS4500 family PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. Apply solder paste to the exposed thermal pad area and all of the IC terminals. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed.
temperature of 150C is exceeded. For best performance, design for a maximum junction temperature of 125C. Between 125C and 150C, damage does not occur, but the performance of the amplifier begins to degrade. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. P Dmax + Tmax-T A q JA (28)
2.
3.
4. 5.
Where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (C). TA is the ambient temperature (C). JA = JC + CA JC is the thermal coefficient from the silicon junctions to the case (C/W). CA is the thermal coefficient from the case to ambient air (C/W).
For systems where heat dissipation is more critical, the THS4500 family of devices is offered in an 8-pin MSOP with PowerPAD. The thermal coefficient for the MSOP PowerPAD package is substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the two packages. The data for the DGN package assumes a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application notes in the Additional Reference Material section at the end of the data sheet.
3.5 PD - Maximum Power Dissipation - W 8-Pin DGN Package 3 2.5 2 8-Pin D Package 1.5 1 0.5 0 -40
6.
7. 8.
-20 0 20 40 60 TA - Ambient Temperature - C
80
JA = 170C/W for 8-Pin SOIC (D) JA = 58.4C/W for 8-Pin MSOP (DGN) J = 150C, No Airflow
Figure 95. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem.
29
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The THS4500 family of devices does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction
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DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for driving large capacitive loads. If necessary, however, the load capacitance should be isolated by two isolation resistors in series with the output. The requisite isolation resistor size depends on the value of the capacitance, but 10 to 25 is a good place to begin the optimization process. Larger isolation resistors decrease the amount of peaking in the frequency response induced by the capacitive load, but this comes at the expense of larger voltage drop across the resistors, increasing the output swing requirements of the system.
Rf VS +- RT - + Riso Riso = 10 - 25 Rf Rg
EVALUATION FIXTURES, SPICE MODELS, AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has been developed for the THS4500 family of fully differential amplifiers. The evaluation board can be obtained by ordering through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. Schematic for the evaluation board is shown below with their default component values. Unpopulated footprints are shown to provide insight into design flexibility.
C4 R4 C0805
RS VS
Rg
Riso CL
J1 C1 R1 C0805 C2 R1206 C0805 R2 R0805 R0805 R3
R0805 VS 1 8 3 _
PD U1 THS450X R6 4 7 R0805 5
C5 C0805
J2
J2
-VS
+ 2 6 -VS
C7 C0805 R0805 R7 C6 C0805
J3
J3
PwrPad R5 R0805
VOCM
C3 C0805
Use of Isolation Resistors With a Capacitive Load.
J2 R0805 J3
Figure 96
R8 R9 R0805 R0805 R9
4 5 6 T1
3 R11 R1206 1
J4
POWER SUPPLY DECOUPLING TECHNIQUES AND RECOMMENDATIONS
Power supply decoupling is a critical aspect of any high-performance amplifier design process. Careful decoupling provides higher quality ac performance (most notably improved distortion performance). The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power supply inputs as possible, with the goal of minimizing the inductance of the path from ground to the power supply. Placement priority should be as follows: smaller capacitors should be closer to the device. Use of solid power and ground planes is recommended to reduce the inductance along power supply return current paths. Recommended values for power supply decoupling include 10-F and 0.1-F capacitors for each supply. A 1000-pF capacitor can be used across the supplies as well for extremely high frequency return currents, but often is not required.
Simplified Schematic of the Evaluation Board. Power Supply Decoupling, VOCM, and Power Down Circuitry Not Shown
Figure 97
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4500 family of devices is available through either the Texas Instruments web site (www.ti.com) or as one model on a disk from the Texas Instruments Product Information Center (1-800-548-6132). The PIC is also available for design assistance and detailed product information at this number. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself.
2. 3.
4.
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ADDITIONAL REFERENCE MATERIAL
D D D D D D D
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004. PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002. Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number SLOA054D. Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001. Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature Number SLOA064. Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments Literature Number SLOA072. Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications Journal, July 2001.
31
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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