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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER
FEATURES D Unity Gain Stability D Wide Bandwidth: 1 GHz D High Slew Rate: 970 V/s D Low Distortion
- -90 dBc THD at 30 MHz
D High Output Drive, IO = 200 mA D Excellent Video Performance
- 130 MHz Bandwidth (0.1 dB, G = 2) - 0.007% Differential Gain - 0.003 Differential Phase Supply Voltages - +5 V, 5 V, +12 V, +15 V Power Down Functionality (THS4215)
APPLICATIONS D High Linearity ADC Preamplifier D Differential to Single-Ended Conversion D DAC Output Buffer D Active Filtering D Video Applications
THS4211
D
NC IN- IN+ VS-
1 2 3 4
8 7 6 5
NC VS+ VOUT NC
D D Evaluation Module Available DESCRIPTION
The THS4211 and THS4215 are high slew rate, unity gain stable voltage feedback amplifiers designed to run from supply voltages as low as 5 V and as high as 15 V. The THS4215 offers the same performance as the THS4211 with the addition of power-down capability. The combination of high slew rate, wide bandwidth, low distortion, and unity gain stability make the THS4211 and THS4215 high performance devices across multiple ac specifications.
Designers using the THS4211 are rewarded with higher dynamic range over a wider frequency band without the stability concerns of decompensated amplifiers. The devices are available in SOIC, MSOP with PowerPAD, and leadless MSOP with PowerPAD packages.
RELATED DEVICES
DEVICE THS4271 THS4503 THS3202 DESCRIPTION 1.4 GHz voltage feedback amplifier Wideband fully differential amplifier Dual, wideband current feedback amplifier
Low-Distortion, Wideband Application Circuit
50 Source 50 VI 49.9 THS4211 _ VO
Harmonic Distortion - dBc
+5 V
-50 -55
HARMONIC DISTORTION vs FREQUENCY
Gain = 2 Rf = 392 RL = 150 VO = 2 VPP VS = 5 V
+
-60 -65 -70 -75 -80 -85 -90 -95 -100 1
-5 V 392 392
HD2 HD3
NOTE: Power supply decoupling capacitors not shown
10 f - Frequency - MHz
100
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.
Copyright 2002, Texas Instruments Incorporated
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted UNIT
Supply voltage, VS Input voltage, VI Output current, IO (1) Continuous power dissipation Maximum junction temperature, TJ Operating free-air temperature range, TA Storage temperature range, Tstg
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
16.5 V VS 100 mA
See Dissipation Rating Table
150C -40C to 85C -65C to 150C 300C
PACKAGE DISSIPATION RATINGS
PACKAGE D (8 pin)(1) DGN (8 pin)(2) JC (C/W) 38.3 4.7 JA (C/W) 176 58.4 POWER RATING TA 25C 710 mW 2.14 W TA = 85C 370 mW 1.11 W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
The THS4211/5 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package.
DRB (8 pin)(2) 5 45.8 2.73 W 1.42 W (1) This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K test PCB, JA is 95_C/W with power rating at TA = 25_C of 1.32 W. (2) This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. x 3 in. PCB. For further information, refer to Application Information section of this data sheet.
RECOMMENDED OPERATING CONDITIONS
MIN Dual supply Supply voltage (VS+ and VS-) voltage, Input common-mode voltage range Single supply 2.5 5 VS- +1.2 MAX 7.5 15 VS+ -1.2 UNIT V V
PACKAGING/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER PLASTIC SMALL OUTLINE(1) (D) THS4211D LEADLESS MSOP 8(1) (DRB) THS4211DRB PACKAGE MARKING BET PLASTIC MSOP(1) (DGN) THS4211DGN PACKAGE MARKING BFN
TEMPERATURE
THS4215D THS4215DRB BEU THS4215DGN BFQ (1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS4211DGNR)
PIN ASSIGNMENTS
(TOP VIEW)
THS4211
D, DRB, AND DGN
(TOP VIEW)
THS4215
D, DRB, AND DGN
NC IN- IN+ VS-
1 2 3 4
8 7 6 5
NC VS+ VOUT NC
REF IN- IN+ VS-
1 2 3 4
8 7 6 5
PD VS+ VOUT NC
2
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
ELECTRICAL CHARACTERISTICS VS = 5 V
RF = 392 , RL = 499 , G = +1, unless otherwise noted. PARAMETER AC PERFORMANCE G = 1, Small signal bandwidth POUT = -7 dBm G = -1, POUT = -16 dBm G = 2, POUT = -16 dBm POUT = -16 dBm G = 10, POUT = -16 dBm 0.1 dB flat bandwidth Gain bandwidth product Full-power bandwidth Slew rate Settling time to 0.1% Settling time to 0.01% Harmonic distortion Second harmonic distortion Third harmonic distortion Harmonic distortion Second harmonic distortion Third harmonic distortion Third order intermodulation (IMD3) Third order output intercept (OIP3) Differential gain (NTSC, PAL) Differential phase (NTSC, PAL) Input voltage noise Input current noise DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift VO = 0.3 V, VCM = 0 V VCM = 0 V VCM = 0 V VCM = 0 V VCM = 0 V VCM = 0 V RL = 499 70 3 7 0.3 65 12 15 6 62 14 40 18 10 7 10 60 14 40 20 10 8 10 dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ POUT = -7 dBm G > 10 , f = 1 MHz G = -1, VO = 2 Vp G = 1, VO = 2 V Step G = -1, VO = 2 V Step G = -1, VO = 4 V Step G = -1, VO = 4 V Step G = 1, VO = 1 VPP, f = 30 MHz -78 -90 -100 -100 -68 -70 -80 -82 -53 32 0.007 0.003 7 4 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm % _ nV/Hz pAHz Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ RL = 150 RL = 499 RL = 150 RL = 499 G = 2, VO = 2 VPP, f = 30 MHz RL = 150 RL = 499 RL = 150 RL = 499 G = 2, VO = 2 VPP, RL = 150 , f = 70 MHz G = 2, VO = 2 VPP, RL = 150 , f = 70 MHz G = 2, G = 2, RL = 150 RL = 150 G = 1, G = 5, 1 325 325 70 35 70 350 77 970 850 22 55 GHz MHz MHz MHz MHz MHz MHz MHz V/s V/s ns ns Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ TYP TEST CONDITIONS 25C 25C OVER TEMPERATURE 0C TO 70C -40C TO 85C UNITS MIN/ TYP/ MAX
f = 1 MHz f = 1 MHz
3
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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ELECTRICAL CHARACTERISTICS VS = 5 V (continued)
RF = 392 , RL = 499 , G = +1, unless otherwise noted. PARAMETER INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio Input resistance Input capacitance OUTPUT CHARACTERISTICS Output voltage swing Output current (sourcing) Output current (sinking) Output impedance POWER SUPPLY Specified operating voltage Maximum quiescent current Minimum quiescent current Power supply rejection (+PSRR) Power supply rejection (-PSRR) VS+ = 5.5 V to 4.5 V, VS- = 5 V VS+ = 5 V, VS- = -5.5 V to -4.5 V 5 19 19 64 65 7.5 22 16 58 60 7.5 23 15 54 56 7.5 24 14 54 56 V mA mA dB dB Max Max Min Min Min RL = 10 RL = 10 f = 1 MHz 4.0 220 170 0.3 3.8 200 140 3.7 190 130 3.6 180 120 V mA mA Min Min Min Typ VCM = 1 V Common-mode Common-mode / differential 4 56 4 0.3 / 0.2 3.8 52 3.7 50 3.6 48 V dB M pF Min Min Typ Typ TYP TEST CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX
POWER-DOWN CHARACTERISTICS (THS4215 ONLY) REF = 0 V, or VS- REF = VS+ or Floating Power-down quiescent current P d i t t Turnon time delay(t(ON)) Turnoff time delay (t(Off)) Input impedance Output impedance f = 1 MHz Enable Power-down Enable Power-down 650 450 4 3 4 250 REF+1.8 REF+1 REF-1 REF-1.5 850 650 900 800 1000 900 V V V V A A s s G k Min Max Min Max Max Max Typ Typ Typ Typ
Power-down voltage l P d lt level l
PD = Ref +1.0 V, Ref = 0 V PD = Ref -1.5 V, Ref = 5 V 50% of final supply current value 50% of final supply current value
4
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
ELECTRICAL CHARACTERISTICS VS = 5 V
RF = 392 , RL = 499 , G = +1, unless otherwise noted PARAMETER AC PERFORMANCE POUT = -7 dBm G = -1, POUT = -16 dBm G = 2, POUT = -16 dBm G = 5, 0.1 dB flat bandwidth Gain bandwidth product Full-power bandwidth Slew rate Settling time to 0.1% Settling time to 0.01% Harmonic distortion Second harmonic distortion Third harmonic distortion Thirdorder intermodulation (IMD3) Third order output intercept (OIP3) Input-voltage noise Input-current noise DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift Input bias current Average bias current drift Input offset current Average offset current drift INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio Input resistance Input capacitance OUTPUT CHARACTERISTICS Output voltage swing Output current (sourcing) Output current (sinking) Output impedance RL = 10 RL = 10 f = 1 MHz 1/4 230 150 0.3 1.2 / 3.8 210 120 1.3 / 3.7 190 100 1.4 / 3.6 180 90 V mA mA Min Min Min Typ VCM = 0.5 V, VO = 2.5 V Common-mode Common-mode / differential 1/4 54 4 0.3 / 0.2 1.2 / 3.8 50 1.3 / 3.7 48 1.4 / 3.6 45 V dB M pF Min Min Typ Typ VO = 0.3 V, VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 RL = 499 68 3 7 0.3 63 12 15 6 60 14 40 17 10 7 10 60 14 40 18 10 8 10 dB mV V/C A nA/C A nA/C Min Max Typ Max Typ Max Typ POUT = -16 dBm G = 10, POUT = -16 dBm G = 1, POUT = -7 dBm G > 10, f = 1 MHz G = -1, VO = 2 Vp G = 1, VO = 2 V Step G = -1, VO = 2 V Step G = -1, VO = 2 V Step G = -1, VO = 2 V Step G = 1, VO = 1 VPP, f = 30 MHz RL = 150 RL = 499 RL = 150 RL = 499 G = 1, VO = 1 VPP , RL = 150 , f = 70 MHz G = 1, VO = 1 VPP, RL = 150 , f = 70 MHz f = 1 MHz f = 10 MHz G = 1, Small signal bandwidth 980 300 300 65 30 90 300 64 800 750 22 84 -60 -60 -68 -68 -70 34 7 4 MHz MHz MHz MHz MHz MHz MHz MHz V/s V/s ns ns dBc dBc dBc dBc dBc dBm nV/Hz pA/Hz Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ TYP TEST CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX
5
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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ELECTRICAL CHARACTERISTICS VS = 5 V (continued)
RF = 392 , RL = 499 , G = +1, unless otherwise noted PARAMETER POWER SUPPLY Specified operating voltage Maximum quiescent current Minimum quiescent current Power supply rejection (+PSRR) Power supply rejection (-PSRR) VS+ = 5.5 V to 4.5 V, VS- = 0 V VS+ = 5 V, VS- = -0.5 V to 0.5 V 5 19 19 63 65 15 22 16 58 60 15 23 15 54 56 15 24 14 54 56 V mA mA dB dB Max Max Min Min Min TYP TEST CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ TYP/ MAX
POWER-DOWN CHARACTERISTICS (THS4215 ONLY) Enable REF = 0 V or VS V, S- Power-down Power down voltage level REF = VS or floating S+ Power-down quiescent current Power-down quiescent current Turnon-time delay(t(ON)) Turnoff-time delay (t(Off)) Input impedance Output impedance f = 1 MHz PD = Ref +1.0 V, PD = Ref -1.5 V, 50% of final value 50% of final value Power down Enable Power down 450 400 4 3 6 75 Ref = 0 V Ref = 5 V REF+1.8 REF+1 REF-1 REF-1.5 650 650 750 750 850 850 V V V V A A s ns G k Min Max Min Max Max Max Typ Typ Typ Typ
6
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS Table of Graphs (5 V)
FIGURE Small-signal unity gain frequency response Small-signal frequency response 0.1 dB gain flatness frequency response Large-signal frequency response Slew rate vs Output voltage Harmonic distortion vs Frequency Harmonic distortion vs Output voltage swing Third order intermodulation distortion vs Frequency Third order output intercept point vs Frequency Voltage and current noise vs Frequency Differential gain vs Number of loads Differential phase vs Number of loads Settling time Quiescent current vs supply voltage Output voltage vs Load resistance Frequency response vs Capacitive load Open-loop gain and phase vs Frequency Open-loop gain vs Case temperature Rejection ratios vs Frequency Rejection ratios vs Case temperature Common-mode rejection ratio vs Input common-mode range Input offset voltage vs Case temperature Input bias and offset current vs Case temperature Small signal transient response Large signal transient response Overdrive recovery Closed-loop output impedance vs Frequency Power-down quiescent current vs Supply voltage Power-down output impedance vs Frequency Turnon and turnoff delay times 1 2 3 4 5 6, 7, 8, 9 10, 11, 12, 13 14, 16 15, 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
7
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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TYPICAL CHARACTERISTICS Table of Graphs (5 V)
FIGURE Small-signal unity gain frequency response Small-signal frequency response 0.1 dB gain flatness frequency response Large signal frequency response Slew rate vs Output voltage Harmonic distortion vs Frequency Harmonic distortion vs Output voltage swing Third order intermodulation distortion vs Frequency Third order intercept point vs Frequency Voltage and current noise vs Frequency Settling time Quiescent current vs Supply voltage Output voltage vs Load resistance Frequency response vs Capacitive load Open-loop gain and phase vs Frequency Open-loop gain vs Case temperature Rejection ratios vs Frequency Rejection ratios vs Case temperature Common-mode rejection ratio vs Input common-mode range Input offset voltage vs Case temperature Input bias and offset current vs Case temperature Small signal transient response Large signal transient response Overdrive recovery Closed-loop output impedance vs Frequency Power-down quiescent current vs Supply voltage Power-down output impedance vs Frequency Turnon and turnoff delay times 39 40 41 42 43 44, 45, 46, 47 48, 49, 50, 51 52, 54 53, 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
8
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS (5 V GRAPHS)
SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE
5 4 Small Signal Gain - dB 3 2 1 0 -1 -2 -3 -4 100 k 1M 10 M 100 M 1G 10 G Gain = 1 RL = 499 VO = 250 mV VS = 5 V
SMALL SIGNAL FREQUENCY RESPONSE
22 20 18 Small Signal Gain - dB 16 14 12 10 8 6 4 2 0 Gain = -1 -2 -4 100 k 1M Gain = 10 Gain = 5 RL = 499 Rf = 392 VO = 250 mV VS = 5 V Gain = 2 Small Signal Gain - dB 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 10 M 100 M f - Frequency - Hz 1G -1 1M
0.1 dB GAIN FLATNESS FREQUENCY RESPONSE
Gain = 1 RL = 499 VO = 250 mV VS = 5 V 10 M 100 M f - Frequency - Hz 1G
f - Frequency - Hz
Figure 1
Figure 2 SLEW RATE vs OUTPUT VOLTAGE
1400 Rise, Gain = 1 1200 SR - Slew Rate - V/ s Harmonic Distortion - dBc -60 -65 -70 -75 -80 -85 -90 -95 5 -100 1
Figure 3 HARMONIC DISTORTION vs FREQUENCY
Gain = 1 VO = 1 VPP VS = 5 V
LARGE SIGNAL FREQUENCY RESPONSE
1
Large Signal Gain - dB
0
Fall, Gain = 1
1000 800 600 400 200 0 RL = 499 Rf = 392 VS = 5 V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Fall, Gain =- 1 Rise, Gain = -1
HD3, RL = 150 and RL = 499
-1
HD2, RL = 150 HD2, RL = 499
-2 Gain = 1 RL = 499 VO = 2 VPP VS = 5 V
-3
-4 100 k
1M
10 M
100 M
1G
10 f - Frequency - MHz
100
f - Frequency - Hz
VO - Output Voltage - V
Figure 4 HARMONIC DISTORTION vs FREQUENCY
-50 -55 Harmonic Distortion - dBc -60 -65 -70 -75 -80 -85 -90 -95 -100 1 10 f - Frequency - MHz 100 HD2, RL = 499 HD2, RL = 150 -55 Gain = 1 VO = 2 VPP VS = 5 V HD3, RL = 150 and RL = 499 Harmonic Distortion - dBc -60 -65 -70 -75 -80 -85 -90 -95 -100 1
Figure 5 HARMONIC DISTORTION vs FREQUENCY
-50 Gain = 2 Rf = 392 VO = 1 VPP VS = 5 V HD3, RL = 150, and RL = 499 HD2, RL = 499 HD2, RL = 150 -55 Harmonic Distortion - dBc -60 -65 -70
Figure 6
HARMONIC DISTORTION vs FREQUENCY
Gain = 2 Rf = 392 VO = 2 VPP VS = 5 V
HD2, RL = 499 -75 -80 -85 -90 -95 HD2, RL = 150 HD3, RL = 150, and RL = 499
10 f - Frequency - MHz
100
-100
1
10 f - Frequency - MHz
100
Figure 7
Figure 8
Figure 9
9
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
-70 Gain = 1 f= 8 MHz VS = 5 V HD2, RL = 150 -50 HD3, RL = 150 Harmonic Distortion - dBc -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -100 0
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
Gain = 1 f= 32 MHz VS = 5 V -65 HD3, RL = 150 Harmonic Distortion - dBc -70 -75 -80 -85
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
Gain = 2 Rf = 249 f = 8 MHz VS = 5 V
-75 Harmonic Distortion - dBc -80
HD3, RL = 499
HD2, RL = 499
HD2, RL = 499 HD2, RL = 150
HD3, RL = 150
-85 -90 HD2, RL = 499 -95
HD3, RL = 499 -90 -95 HD2, RL = 150
HD3, RL = 499 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - Output Voltage Swing - V
VO - Output Voltage Swing - V
VO - Output Voltage Swing - V
Figure 10
Figure 11
Figure 12
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
Third-Order Intermodulation Distortion - dBc -40 -45 -50 Harmonic Distortion - dBc -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - Output Voltage Swing - V HD2, RL = 150 HD2, RL = 499 Gain = 2 Rf = 249 f = 32 MHz VS = 5 V HD3, RL = 150 HD3, RL = 499
-45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100
THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY
Gain = 1 RL = 150 VS = 5 V 200 kHz Tone Spacing Third-Order Output Intersept Point - dBm
THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
60 Gain = 1 RL = 150 VS = 5 V 200 kHz Tone Spacing
55 50
VO = 2 VPP
45 VO = 1 VPP 40 VO = 2 VPP 35 30 0 20 40 60 80 100 f - Frequency - MHz
VO = 1 VPP 10 f - Frequency - MHz 100
Figure 13 THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY
Third-Order Intermodulation Distortion - dBc -40 Third-Order Output Intersept Point - dBm -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 10 f - Frequency - MHz 100 VO = 1 VPP VO = 2 VPP Gain = 2 RL = 150 VS = 5 V 200 kHz Tone Spacing
Figure 14 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
60 Hz 55 50 45 40 35 VO = 2 VPP 30 25 20 0 20 40 60 80 100 f - Frequency - MHz 1 1k 10 k VO = 1 VPP Gain = 2 RL = 150 VS = 5 V 200 kHz Tone Spacing
Figure 15
VOLTAGE AND CURRENT NOISE vs FREQUENCY
100 100 Hz Vn 10 10 In 100 k 1M 10 M 1 100 M f - Frequency - Hz
Figure 16
Figure 17
Vn - Voltage Noise - nV/
Figure 18
10
I n - Current Noise - pA/
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
DIFFERENTIAL GAIN vs NUMBER OF LOADS
0.030 0.025 Differential Gain - % Gain = 2 Rf = 392 VS = 5 V 40 IRE - NTSC and Pal Worst Case 100 IRE Ramp PAL NTSC 0.010 0.005 0 0 1 2 3 4 5 6 7 8 Number of Loads - 150 0.20 0.18
DIFFERENTIAL PHASE vs NUMBER OF LOADS
3 Gain = 2 Rf = 392 VS = 5 V 40 IRE - NTSC and Pal Worst Case 100 IRE Ramp 2 VO - Output Voltage - V
SETTLING TIME
Differential Phase -
0.020 0.015
0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0
Rising Edge 1 0 -1 Gain = -1 RL = 499 Rf = 392 f= 1 MHz VS = 5 V Falling Edge
PAL NTSC
-2 -3
1
2
3
4
5
6
7
8
0
5
10
15
20
25
Number of Loads - 150
t - Time - ns
Figure 19 QUIESCENT CURRENT vs SUPPLY VOLTAGE
22 TA = 85C VO - Output Voltage - V TA = 25C 5 4 3 2 1 0 -1 -2 -3 -4 10 2.5 3 3.5 4 4.5 5 VS - Supply Voltage - V -5 10
Figure 20 OUTPUT VOLTAGE vs LOAD RESISTANCE
1 0.5 Normalized Gain - dB 0 -0.5 -1 -1.5 -2 -2.5 -3 100 k
Figure 21 FREQUENCY RESPONSE vs CAPACITIVE LOAD
R(ISO) = 10 CL = 100 pF VS =5 V
20 Quiescent Current - mA 18
16 14
TA = -40C
TA = -40 to 85C
R(ISO) = 15 CL = 50 pF R(ISO) = 25 CL = 10 pF
12
100 RL - Load Resistance -
1000
1M
10 M
100 M
1G
Capacitive Load - Hz
Figure 22 OPEN-LOOP GAIN AND PHASE vs FREQUENCY
80 70 60 Open-Loop Gain - dB 50 40 30 20 10 0 -10 10 k 100 k 1M 10 M 100 M VS = 5 V 180 160 140 Open-Loop Gain - dB 120 100 80 60 40 20 0 1G 60 2.5 3 Phase - 85 80 90
Figure 23 OPEN-LOOP GAIN vs CASE TEMPERATURE
70 TA = 25C TA = 85C Rejection Ratios - dB 50 40 30 20 10 0 100 k 60
Figure 24 REJECTION RATIOS vs FREQUENCY
VS = 5 V PSRR-
CMRR
75 TA = -40C 70
PSRR+
65
3.5
4
4.5
5
1M
10 M
100 M
1G
f - Frequency - Hz
Case Temperature - C
f - Frequency - Hz
Figure 25
Figure 26
Figure 27
11
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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REJECTION RATIOS vs CASE TEMPERATURE
80 VS = 5 V 70 Rejection Ratios - dB 60 50 40 30 20 10 0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C PSRR+ CMMR PSRR- CMRR - Common-Mode Rejection Ratio - dB
COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE
60 55 VOS - Input Offset Voltage - mV 50 45 40 35 30 25 20 15 10 5 0 -4.5 -3 VS = 5 V TA = 25C -1.5 0 1.5 3 4.5 9 8 7 6 5 4 3 2 1
INPUT OFFSET VOLTAGE vs CASE TEMPERATURE
VS = 5 V
VS = 5 V
0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - C
Input Common-Mode Range - V
Figure 28 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE
6.6 I IB - Input Bias Current - A 6.5 6.4 6.3 6.2 6.1 6 5.9 5.8 5.7 5.6 IIB+ IOS IIB- VS = 5 V 0.7 I OS - Input Offset Current - A 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - C
Figure 29
Figure 30
SMALL SIGNAL TRANSIENT RESPONSE
0.12 0.1 0.08 VO - Output Voltage - V 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.12 -1 0 1 Gain = -1 RL = 499 Rf =392 tr/tf = 300 ps VS = 5 V 2 3456 t - Time - ns 7 8 9 10
LARGE SIGNAL TRANSIENT RESPONSE
1.5 1 VO - Output Voltage - V 0.5 0 Gain = -1 RL = 499 Rf = 392 tr/tf = 300 ps VS = 5 V 2 4 6 8 10 12 14 16 18 20
-0.5 -1 -1.5 -2 0
t - Time - ns
Figure 31
Figure 32 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
3 100 k Closed-Loop Output Impedance - 10 k 1k 100 10 1 0.1 0.01 100 k 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 VI - Input Voltage - V Power-Down Quiescent Current - A RL = 499 , RF = 392 , PIN = -4 dBm VS = 5 V
Figure 33 POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE
800 700 600 500 400 TA = -40C 300 200 100 0 2.5 3 3.5 4 4.5 VS - Supply Voltage - V 5 TA = 25C TA = 85C
OVERDRIVE RECOVERY
6 5 Single-Ended Output Voltage - V 4 3 2 1 0 -1 -2 -3 -4 -5 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t - Time - s 1 VS = 5 V
1M 10 M 100 M f - Frequency - Hz
1G
Figure 34
Figure 35
Figure 36
12
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
POWER-DOWN OUTPUT IMPEDANCE vs FREQUENCY
Power-Down Output Impedance - Gain = 1 RL = 499 PIN = -1 dBm VS = 5 V
TURNON AND TURNOFF TIMES DELAY TIME
0.035 0.03 VO - Output Voltage Level - V 0.025 0.02 0.015 0.01 0.005 0 Gain = -1 RL = 499 VS = 5 V 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -7.5 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 t - Time - ns V I - Input Voltage Level - V 0.04 6
1000
10
0.1
0.001 100 k
1M
10 M
100 M
1G
10 G
-0.005 -0.01
f - Frequency - Hz
Figure 37
Figure 38
13
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
www.ti.com
TYPICAL CHARACTERISTICS (5 V GRAPHS)
SMALL SIGNAL UNITY GAIN FREQUENCY RESPONSE
4 3 Small Signal Gain - dB 2 1 0 -1 -2 -3 -4 100 k Gain = 1 RL = 499 VO = 250 mV VS = 5 V
SMALL SIGNAL FREQUENCY RESPONSE
22 20 18 Small Signal Gain - dB 16 14 12 10 8 6 4 2 0 Gain = -1 -2 -4 100 k 1M Gain = 10 Gain = 5 RL = 499 Rf = 392 VO = 250 mV VS = 5 V Gain = 2 Small Signal Gain - dB 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 10 M 100 M f - Frequency - Hz 1G -1 1M
0.1 dB GAIN FLATNESS FREQUENCY RESPONSE
Gain = 1 RL = 499 VO = 250 mV VS = 5 V 10 M 100 M f - Frequency - Hz 1G
1M
10 M
100 M
1G
10 G
f - Frequency - Hz
Figure 39
Figure 40 SLEW RATE vs OUTPUT VOLTAGE
1000 900 Fall, G = 1 -55 Harmonic Distortion - dBc Rise, G = 1 -60 -65 -70 -50
Figure 41 HARMONIC DISTORTION vs FREQUENCY
Gain = 1 VO = 1 VPP RL = 150 , and 499 VS = 5 V
LARGE SIGNAL FREQUENCY RESPONSE
1
0 Large Signal Gain - dB SR - Slew Rate - V/ s
800 700 600 500 400 300 200 100 0
-1
Rise, G = -1 Fall, G = -1
HD2 -75 -80 -85 -90 -95 -100 HD3
-2 Gain = 1 RL = 499 VO = 2 VPP VS = 5 V 1M 10 M 100 M 1G
-3
-4 100 K
RL = 499 Rf = 392 VS = 5 V 0.4 0.6 0.8 1 1.2 1.4 1.6 VO - Output Voltage -V 1.8 2
1
f - Frequency - Hz
10 f - Frequency - MHz
100
Figure 42 HARMONIC DISTORTION vs FREQUENCY
-40 -45 Harmonic Distortion - dBc -50 -55 -60 -65 -70 -75 -80 -85 -90 1 10 f - Frequency - MHz 100 -100 1 HD2 Gain = 1 VO = 2 VPP RL = 150 , and 499 VS = 5 V HD3 -40 -50 Harmonic Distortion - dBc
Figure 43 HARMONIC DISTORTION vs FREQUENCY
-30
Figure 44 HARMONIC DISTORTION vs FREQUENCY
-40 Harmonic Distortion - dBc -50 -60
-60 -70 -80
HD2
HD2 HD3
HD3
-90
Gain = 2 VO = 1 VPP Rf = 392 RL = 150 and 499 VS = 5 V 10 f - Frequency - MHz 100
-70 -80 -90 1
Gain = 2 VO = 2 VPP Rf = 392 RL = 150 and 499 VS = 5 V 10 f - Frequency - MHz 100
Figure 45
Figure 46
Figure 47
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
-60 -65 Harmonic Distortion - dBc Harmonic Distortion - dBc HD2 -70 -75 HD3 -80 -85 -90 -95 -100 0 Gain = 1 RL = 150 , and 499 , f = 8 MHz VS = 5 V 0.5 1 1.5 2 VO - Output Voltage Swing - V 2.5 -45 -50
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
-50 -55 HD2 Harmonic Distortion - dBc -60 -65 -70 -75 -80 -85 -90 -95 -100 0 0.5 1 1.5 2 VO - Output Voltage Swing - V 2.5 0
HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
HD2
-55 -60 -65 -70 -75 -80 -85 -90
HD3
HD3
Gain = 1 RL = 150 , and 499 , f = 32 MHz VS = 5 V
Gain = 2 Rf = 392 RL = 150 and 499 f = 8 MHz VS = 5 V 0.5 1 1.5 2 2.5
VO - Output Voltage Swing - V
Figure 48 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING
Third-Order Intermodulation Distortion - dBc -40 -45 Harmonic Distortion - dBc -50 -55 HD3 -60 -65 -70 -75 -80 0 0.5 1 1.5 2 2.5 VO - Output Voltage Swing - V Gain = 2 Rf = 392 RL = 150 and 499 f = 32 MHz VS = 5 V HD2
Figure 49 THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 10 f - Frequency - MHz 100 VO = 1VPP VO = 2VPP Gain = 1 RL = 150 VS = 5 V 200 kHz Tone Spacing Third-Order Output Intersept Point - dBm
Figure 50 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
50 Gain = 1 RL = 150 VS = 5 V 200 kHz Tone Spacing VO = 1VPP 40
45
35
VO = 2VPP
30 0 10 20 30 40 50 60 70 80 f - Frequency - MHz
Figure 51 THIRD ORDER INTERMODULATION DISTORTION vs FREQUENCY
Third-Order Intermodulation Distortion - dBc -30 Third-Order Output Intersept Point - dBm -40 -50 -60 -70 -80 -90 -100 10 f - Frequency - MHz VO = 2 VPP Gain = 1 RL = 150 VS = 5 V 200 kHz Tone Spacing
Figure 52 THIRD ORDER OUTPUT INTERCEPT POINT vs FREQUENCY
50 Hz 45 40 35 30 25 20 15 10 0 20 40 60 80 100 f - Frequency - MHz 1 1k 10 k VO = 2 VPP Gain = 2 RL = 150 VS = 5 V 200 kHz Tone Spacing VO = 1 VPP
Figure 53
VOLTAGE AND CURRENT NOISE vs FREQUENCY
100 100 Hz Vn 10 10 In 100 k 1M 10 M 1 100 M f - Frequency - Hz
VO = 1 VPP
100
Figure 54
Figure 55
Vn - Voltage Noise - nV/
Figure 56
15
I n - Current Noise - pA/
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
www.ti.com
SETTLING TIME
1.5 Rising Edge 1 VO - Output Voltage - V Quiescent Current - mA 0.5 20 Gain = -1 RL = 499 Rf = 392 f= 1 MHz VS = 5 V 18 22
QUIESCENT CURRENT vs SUPPLY VOLTAGE
2 TA = 85C VO - Output Voltage - V TA = 25C TA = -40C 1.5 1 0.5
OUTPUT VOLTAGE vs LOAD RESISTANCE
0 -0.5 -1 -1.5 0 5
16 14
TA = -40 to 85C 0 -0.5 -1 -1.5
Falling Edge
12 10 -2 2.5 3 3.5 4 4.5 5 10 VS - Supply Voltage - V 100 RL - Load Resistance - 1000
10 15 t - Time - ns
20
25
Figure 57 FREQUENCY RESPONSE vs CAPACITIVE LOAD
1 0.5 Normalized Gain - dB 0 -0.5 -1 -1.5 -2 -2.5 -3 100 k VS = 5 V 1M 10 M 100 M 1G R(ISO) = 15 CL = 50 pF R(ISO) = 10 CL = 100 pF R(ISO) = 25 , CL = 10 pF Open-Loop Gain - dB 80 70 60 50 40 30 20 10 0 -10 10 k 100 k
Figure 58 OPEN-LOOP GAIN AND PHASE vs FREQUENCY
180 VS = 5 V 160 140 Open-Loop Gain - dB 120 100 80 60 40 20 1M 10 M 100 M 0 1G 60 2.5 3 Phase - 85 80 90
Figure 59 OPEN-LOOP GAIN vs CASE TEMPERATURE
TA = 25C TA = 85C
75 TA = -40C 70
65
3.5
4
4.5
5
Capacitive Load - Hz
f - Frequency - Hz
Case Temperature - C
Figure 60 REJECTION RATIOS vs FREQUENCY
70 VS = 5 V 60 Rejection Ratios - dB 50 40 30 20 10 0 100 k PSRR+ PSRR- Rejection Ratios - dB 80 VS = 5 V 70 60 50 40 30 20 10
Figure 61 REJECTION RATIOS vs CASE TEMPERATURE
CMRR - Common-Mode Rejection Ratio - dB PSRR-
Figure 62 COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE
60 55 50 45 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 Input Common-Mode Voltage Range - V VS = 5 V
CMRR
PSRR+
CMMR
1M
10 M
100 M
1G
0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C
f - Frequency - Hz
Figure 63
Figure 64
Figure 65
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
INPUT OFFSET VOLTAGE vs CASE TEMPERATURE
9 8 VOS - Input Offset Voltage - mV I IB - Input Bias Current - A 7 6 5 4 3 2 1 0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - C VS = 5 V VS = 5 V
INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE
6.6 6.5 6.4 6.3 6.2 6.1 6 5.9 5.8 5.7 IOS IIB+ IIB- VS = 5 V 0.7 I OS - Input Offset Current - A 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25
SMALL SIGNAL TRANSIENT RESPONSE
0.12 0.1 0.08 VO - Output Voltage - V 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.12 -1 0 1 Gain = -1 RL = 499 Rf =392 tr/tf = 300 ps VS = 5 V 2 3456 t - Time - ns 7 8 9 10
0.2 5.6 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - C
Figure 66
Figure 67
Figure 68 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
1.5 100 k Closed-Loop Output Impedance - 10 k 1k 100 10 1 0.1 0.01 100 k RL = 499 , RF = 392 , PIN = -4 dBm VS = 5 V
LARGE SIGNAL TRANSIENT RESPONSE
1.5 Single-Ended Output Voltage - V 1 VO - Output Voltage - V 0.5 0 Gain = -1 RL = 499 Rf = 392 tr/tf = 300 ps VS = 5 V 2 4 6 8 10 12 14 16 18 20 3
OVERDRIVE RECOVERY
VS = 5 V 2 1 0.5 VI - Input Voltage - V
1 0
0 -0.5 -1
-0.5 -1 -1.5 -2 0
-1
-2 -3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t - Time - s 1
-1.5
t - Time - ns
1M 10 M 100 M f - Frequency - Hz
1G
Figure 69 POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE
800 Power-Down Quiescent Current - A 700 600 500 400 TA = -40C 300 200 100 0 2.5 3 3.5 4 4.5 VS - Supply Voltage - V 5 TA = 25C TA = 85C Power-Down Output Impedance -
Figure 70
Figure 71
POWER-DOWN OUTPUT IMPEDANCE vs FREQUENCY TURNON AND TURNOFF TIMES DELAY TIME
Gain = 1 RL = 499 PIN = -1 dBm VS = 5 V 10 0.03 0.025 VO - Output Voltage Level - V 0.02 0.015 0.01 0.005 0 Gain = -1 RL = 499 VS = 5 V 3 1.5 0 -1.5 -3 -4.5 -6 V I - Input Voltage Level - V 1000 0.035 4.5
0.1
0.001 100 k
1M
10 M 100 M f - Frequency - Hz
1G
10 G
-0.005 -0.01 0
-7.5 0.01 0.02 0.03 0.04 0.05 0.06 0.07 t - Time - ns
Figure 72
Figure 73
Figure 74
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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APPLICATION INFORMATION HIGH-SPEED OPERATIONAL AMPLIFIERS
The THS4211 and the THS4215 operational amplifiers set new performance levels, combining low distortion, high slew rates, low noise, and a unity-gain bandwidth in excess of 1 GHz. To achieve the full performance of the amplifier, careful attention must be paid to printed-circuit board layout and component selection. The THS4215 provides a power-down mode, providing the ability to save power when the amplifier is inactive. A reference pin is provided to allow the user the flexibility to control the threshold levels of the power-down control pin. 50- source impedance, and with measurement equipment presenting a 50- load impedance. In Figure 75, the 49.9- shunt resistor at the VIN terminal matches the source impedance of the test generator. The total 499- load at the output, combined with the 784- total feedback network load, presents the THS4211 and THS4215 with an effective output load of 305 for the circuit of Figure 75. Voltage feedback amplifiers, unlike current feedback designs, can use a wide range of resistors values to set their gain with minimal impact on their stability and frequency response. Larger-valued resistors decrease the loading effect of the feedback network on the output of the amplifier, but this enhancement comes at the expense of additional noise and potentially lower bandwidth. Feedback resistor values between 392 and 1 k are recommended for most situations.
5 V +V S + 50 Source VI 49.9
Applications Section Contents
D D D D D D D D D D D D D D D D D D
Wideband, Noninverting Operation Wideband, Inverting Gain Operation Single Supply Operation Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin Power Supply Decoupling Techniques and Recommendations Using the THS4211 as a DAC Output Buffer Driving an ADC With the THS4211 Active Filtering With the THS4211 Building a Low-Noise Receiver With the THS4211 Linearity: Definitions, Terminology, Circuit Techniques and Design Tradeoffs An Abbreviated Analysis of Noise in Amplifiers Driving Capacitive Loads Printed-Circuit Board Layout Techniques for Optimal Performance Power Dissipation and Thermal Considerations Performance vs Package Options Evaluation Fixtures, Spice Models, and Applications Support Additional Reference Material Mechanical Package Drawings
100 pF + _
THS4211
0.1 F 6.8 F
VO 499
Rf 392 Rg 392
0.1 F 6.8 F 100 pF
-VS +
-5 V
Figure 75. Wideband, Noninverting Gain Configuration
WIDEBAND, INVERTING GAIN OPERATION
Since the THS4211 and THS4215 are general-purpose, wideband voltage-feedback amplifiers, several familiar operational amplifier applications circuits are available to the designer. Figure 76 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 75 are retained in an inverting circuit configuration. Inverting operation is one of the more common requirements and offers several performance benefits. The inverting configuration shows improved slew rates and distortion due to the pseudo-static voltage maintained on the inverting input.
WIDEBAND, NONINVERTING OPERATION
The THS4211 and the THS4215 are unity gain stable 1-GHz voltage feedback operational amplifiers, with and without power-down capability, designed to operate from a single 5-V to 15-V power supply. Figure 75 is the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves. Most of the curves were characterized using signal sources with
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002 5 V +V S + 100 pF 0.1 F 6.8 F
+
CT 0.1 F 50 Source Rg VI 392 RM 57.6 Rf 392 0.1 F 100 pF -VS 6.8 F + RT 200
THS4211
_
VO 499
The last major consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input. If the resistance is set equal to the total dc resistance looking out of the inverting terminal, the output dc error, due to the input bias currents, is reduced to (input offset current) multiplied by Rf in Figure 76, the dc source impedance looking out of the inverting terminal is 392 || (392 + 26.8 ) = 200 . To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, and power-supply feedback, RT is bypassed with a capacitor to ground.
SINGLE SUPPLY OPERATION
The THS4211 is designed to operate from a single 5-V to 15-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure 77 demonstrate methods to configure an amplifier in a manner conducive for single supply operation.
+VS 50 Source
-5 V
Figure 76. Wideband, Inverting Gain Configuration
In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (Rg) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other transmission line conductors), Rg may be set equal to the required termination value and Rf adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting Rg to 49.9 for input matching eliminates the need for RM but requires a 100- feedback resistor. This has an advantage of the noise gain becoming equal to 2 for a 50- source impedance--the same as the noninverting circuit in Figure 75. However, the amplifier output now sees the 100- feedback resistor in parallel with the external load. To eliminate this excessive loading, it is preferable to increase both Rg and Rf, values, as shown in Figure 76, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of Rg and RM. The next major consideration is that the signal source impedance becomes part of the noise gain equation and hence influences the bandwidth. For example, the RM value combines in parallel with the external 50- source impedance (at high frequencies), yielding an effective source impedance of 50 || 57.6 = 26.8 . This impedance is then added in series with Rg for calculating the noise gain. The result is 1.9 for Figure 76, as opposed to the 1.8 if RM is eliminated. The bandwidth is lower for the gain of -2 circuit, Figure 76, (NG=+1.9) than for the gain of +2 circuit in Figure 75.
+
VI RT +VS 2 Rg 392 +VS 2 49.9
_
THS4211
VO 499
Rf 392
Rf 392 VS
50 Source Rg VI 57.6 +VS 2 392 RT +VS 2
_
THS4211
+
VO 499
Figure 77. DC-Coupled Single Supply Operation Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin
The THS4215 features a power-down pin (PD) which lowers the quiescent current from 19-mA down to 650-A, ideal for reducing system power. The power-down pin of the amplifiers defaults to the positive supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the
19
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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negative rail. The threshold voltages for power-on and power-down are relative to the supply rails and given in the specification tables. Above the Enable Threshold Voltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a highimpedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach 50% of the nominal quiescent current. The time delays are on the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions.
Power Supply Decoupling Techniques and Recommendations
Power supply decoupling is a critical aspect of any high-performance amplifier design process. Careful decoupling provides higher quality ac performance (most notably improved distortion performance). The following guidelines ensure the highest level of performance.
1.
Place decoupling capacitors as close to the power supply inputs as possible, with the goal of minimizing the inductance of the path from ground to the power supply. Placement priority should put the smallest valued capacitors closest to the device. Use of solid power and ground planes is recommended to reduce the inductance along power supply return current paths, with the exception of the areas underneath the input and output pins. Recommended values for power supply decoupling include a bulk decoupling capacitor (6.8 to 22 F), a mid-range decoupling capacitor (0.1 F) and a high frequency decoupling capacitor (1000 pF) for each supply. A 100 pF capacitor can be used across the supplies as well for extremely high frequency return currents, but often is not required.
2. 3.
4.
Power-Down Reference Pin Operation
In addition to the power-down pin, the THS4215 also features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. Operation of the reference pin as it relates to the power-down pin is described below. In most split-supply applications, the reference pin will be connected to ground. In some cases, the user may want to connect it to the negative or positive supply rail. In either case, the user needs to be aware of the voltage level thresholds that apply to the power-down pin. The table below illustrates the relationship between the reference voltage and the power-down thresholds.
POWER-DOWN PIN VOLTAGE REFERENCE VOLTAGE VS- to 0.5(VS- + VS+) 0.5(VS- + VS+) to VS+ DEVICE DISABLED Ref + 1.0 V Ref - 1.5 V DEVICE ENABLED Ref + 1.8 V Ref - 1 V
APPLICATION CIRCUITS
Driving an Analog-to-Digital Converter With the THS4211
The THS4211 can be used to drive high-performance analog-to-digital converters. Two example circuits are presented below. The first circuit uses a wideband transformer to convert a single-ended input signal into a differential signal. The differential signal is then amplified and filtered by two THS4211 amplifiers. This circuit provides low intermodulation distortion, suppressed even-order distortion, 14 dB of voltage gain, a 50- input impedance, and a single-pole filter at 100 MHz. For applications without signal content at dc, this method of driving ADCs can be very useful. Where dc information content is required, the THS4500 family of fully differential amplifiers may be applicable.
The recommended mode of operation is to tie the reference pin to mid-rail, thus setting the threshold levels to mid-rail +1.0 V and midrail +1.8 V.
NO. OF CHANNELS Single (8-pin) PACKAGES THS4215D, THS4215DGN, and THS4215DRB
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002 5V 3.3 V 3.3 V 100 100 392 196 392 -5 V 392 LO 392 +5 V
VCM
+
THS4211
_
50 (1:4 ) Source 1:2 196
-5 V 392
DAC5675
24.9 14-Bit, 400 MSps
_
THS4211
49.9
RF
+
15 pF 15 pF 196 392 24.9
ADS5422
14-Bit, 62 Msps
_
THS4211
Figure 80. Differential to Single-Ended Conversion of a High-Speed DAC Output
For cases where a differential signaling path is desirable, a pair of THS4211 amplifiers can be used as output buffers. The circuit depicts differential drive into a mixer's IF inputs, coupled with additional signal gain and filtering.
THS4211
3.3 V 3.3 V 100 100 1 nF
VCM
+
Figure 78. A Linear, Low Noise, High Gain ADC Preamplifier
The second circuit depicts single-ended ADC drive. While not recommended for optimum performance using converters with differential inputs, satisfactory performance can sometimes be achieved with single-ended input drive. An example circuit is shown here for reference.
50 Source VI 49.9 RT +5 V
+ _
CF 1 nF IF+ 392 392 49.9 49.9 1 nF RF(out) IF- 1 nF
+
THS4211
RISO 16.5
0.1 F 68 pf
IN
DAC5675 ADS807
12-Bit,
CM 53 Msps IN
_
14-Bit, 400 MSps
392 100 392
-5 V
Rf 392
1.82 k
0.1 F
_ +
CF
Rg
392
THS4211 NOTE: For best performance, high-speed ADCs should be driven differentially. See the THS4500 family of devices for more information.
Figure 81. Differential Mixer Drive Circuit Using the DAC5675 and the THS4211 Active Filtering With the THS4211
High-frequency active filtering with the THS4211 is achievable due to the amplifier's high slew-rate, wide bandwidth, and voltage feedback architecture. Several options are available for high-pass, low-pass, bandpass, and bandstop filters of varying orders. A simple two-pole low pass filter is presented here as an example, with two poles at 100 MHz.
Figure 79. Driving an ADC With a Single-Ended Input Using the THS4211 as a DAC Output Buffer
Two example circuits are presented here showing the THS4211 buffering the output of a digital-to-analog converter. The first circuit performs a differential to single-ended conversion with the THS4211 configured as a difference amplifier. The difference amplifier can double as the termination mechanism for the DAC outputs as well.
21
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002 3.9 pF 50 Source 392 VI 392 57.6 5V VI- 100
www.ti.com
+
THS4211
Rg2
Rf2
_
Rf1 Rg1 VO 33 pF
_
THS4211
49.9
+
-5 V
_
100
Rf1 Rg2
_
THS4211
49.9
VO
THS4211
+
Rf2
Figure 82. A Two-Pole Active Filter With Two Poles Between 90 MHz and 100 MHz
+
49.9
VI+
Figure 84. A High-Speed Instrumentation Amplifier A Low-Noise Receiver With the THS4211
A combination of two THS4211 amplifiers can create a high-speed, low-distortion, low-noise differential receiver circuit as depicted in Figure 83. With both amplifiers operating in the noninverting mode of operation, the circuit presents a high load impedance to the source. The designer has the option of controlling the impedance through termination resistors if a matched termination impedance is desired.
2R f1 VO + 1 1 ) 2 Rg1
V i)-V i-
R f2 Rg2
(1)
THEORY AND GUIDELINES
Distortion Performance
The THS4211 provides excellent distortion performance into a 150- load. Relative to alternative solutions, it provides exceptional performance into lighter loads, as well as exceptional performance on a single 5-V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the total harmonic distortion with a negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. The total load includes the feedback network; in the noninverting configuration (Figure 75) this is the sum of Rf and Rg, while in the inverting configuration (Figure 76), only Rf needs to be included in parallel with the actual load.
100 VI+
+ _
49.9 VO+
392 787 392
100
_
VI- 100
49.9 VO-
LINEARITY: DEFINITIONS, TERMINOLOGY, CIRCUIT TECHNIQUES, AND DESIGN TRADEOFFS
The THS4211 features execllent distortion performance for monolithic operational amplifiers. This section focuses on the fundamentals of distortion, circuit techniques for reducing nonlinearity, and methods for equating distortion of operational amplifiers to desired linearity specifications in RF receiver chains. Amplifiers are generally thought of as linear devices. The output of an amplifier is a linearly scaled version of the input signal applied to it. However, amplifier transfer functions are nonlinear. Minimizing amplifier nonlinearity is a primary design goal in many applications.
+
Figure 83. A High Input Impedance, Low Noise, Differential Receiver
A modification on this circuit to include a difference amplifier turns this circuit into a high-speed instrumentation amplifier, as shown in Figure 84.
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
Intercept points are specifications long used as key design criteria in the RF communications world as a metric for the intermodulation distortion performance of a device in the signal chain (e.g., amplifiers, mixers, etc.). Use of the intercept point, rather than strictly the intermodulation distortion, allows simpler system-level calculations. Intercept points, like noise figures, can be easily cascaded back and forth through a signal chain to determine the overall receiver chain's intermodulation distortion performance. The relationship between intermodulation distortion and intercept point is depicted in Figure 85 and Figure 86.
Due to the intercept point's ease of use in system level calculations for receiver chains, it has become the specification of choice for guiding distortion-related design decisions. Traditionally, these systems use primarily class-A, single-ended RF amplifiers as gain blocks. These RF amplifiers are typically designed to operate in a 50- environment. Giving intercept points in dBm implies an associated impedance (50 ). However, with an operational amplifier, the output does not require termination as an RF amplifier would. Because closed-loop amplifiers deliver signals to their outputs regardless of the impedance present, it is important to comprehend this when evaluating the intercept point of an operational amplifier. The THS4211 yields optimum distortion performance when loaded with 150 to 1 k, very similar to the input impedance of an analog-to-digital converter over its input frequency band. As a result, terminating the input of the ADC to 50 can actually be detrimental to systems performance. The discontinuity between open-loop, class-A amplifiers and closed-loop, class-AB amplifiers becomes apparent when comparing the intercept points of the two types of devices. Equations 1 and 2 gives the definition of an intercept point, relative to the intermodulation distortion.
PO fc = fc - f1 fc = f2 - fc
PO
Power
IMD3 = PS - PO
PS
PS
fc - 3f
f1 fc
f2
fc + 3f
f - Frequency - MHz
OIP 3 + P O )
IMD 3 2
(2)
where
(3)
Figure 85
POUT (dBm) OIP3
P O + 10 log
1X
V2 P 2RL 0.001
NOTE: PO is the output power of a single tone, RL is the load resistance, and VP is the peak voltage for a single tone.
NOISE ANALYSIS
PO
IMD3 3X
IIP3
PIN (dBm)
PS
Figure 86
High slew rate, unity gain stable, voltage-feedback operational amplifiers usually achieve their slew rate at the expense of a higher input noise voltage. The 7 nV/Hz input voltage noise for the THS4211 and THS4215 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms (4 pA/Hz), combine to give low output noise under a wide variety of operating conditions. Figure 87 shows the amplifier noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/Hz or pA/Hz.
23
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002 ENI
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THS4211/THS4215 +
RS ERS
IBN
_
Rf Rg ERF
EO
4kTRS 4kT Rg
of the THS4211. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the THS4211 output pin (see Board Layout Guidelines). The criterion for setting this R(ISO) resistor is a maximum bandwidth, flat frequency response at the load. For a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load, requiring relatively high values of R(ISO) to flatten the response at the load. Increasing the noise gain also reduces the peaking.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1 0.5 Normalized Gain - dB R(ISO) = 10 CL = 100 pF VS =5 V
IBI
4kTRf
4kT = 1.6E-20J at 290K
Figure 87. Noise Analysis Model
The total output shot noise voltage can be computed as the square of all square output noise voltage contributors. Equation 3 shows the general form for the output noise voltage using the terms shown in Figure 87:
EO + ENI 2 ) IBNRS
2
) 4kTR S NG 2 ) IBIRf
2
) 4kTRfNG
(4)
0 -0.5 -1 -1.5 -2 -2.5 -3 100 k R(ISO) = 25 CL = 10 pF R(ISO) = 15 CL = 50 pF
Dividing this expression by the noise gain (NG=(1+ Rf/Rg)) gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 4:
EO +
E NI ) I BNRS
2
2
IR ) 4kTR S ) BI f NG
2
4kTR f ) NG
(5)
1M
10 M
100 M
1G
Capacitive Load - Hz
Driving Capacitive Loads
One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance, which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the THS4211 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier's open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. When the primary considerations are frequency response flatness, pulse response fidelity, or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended isolation resistor vs capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance
24
Figure 88. Isolation Resistor Diagram
BOARD LAYOUT
Achieving optimum performance with a high frequency amplifier like the THS4211 requires careful attention to board layout parasitics and external component types.
Recommendations that optimize performance include the following:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1-F de-coupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
2.
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decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2-F to 6.8-F) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. 3. Careful selection and placement of external components preserves the high frequency performance of the THS4211. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input-termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 k, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. A good starting point for design is to set the Rf to 249 for low-gain, noninverting applications. This setting automatically keeps the resistor noise terms low and minimizes the effect of their parasitic capacitance. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic capacitive loads (<4 pF) may not need an R(ISO), since the THS4211 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R(ISO) are allowed as the signal gain increases (increasing the unloaded phase margin). If
a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined on the basis of board material and trace dimensions, a matching series resistor into the trace from the output of the THS4211 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of R(ISO) vs capacitive load. This setting does not preserve signal integrity or a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. 5. Socketing a high speed part like the THS4211 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4211 onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS4211 and THS4215 are available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 89(a) and Figure 89(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 89(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package.
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the heretofore awkward mechanical methods of heatsinking.
DIE
heat transfer during soldering operations. This resistance makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS4211 and THS4215 PowerPAD package should make their connection to the internal ground plane, with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. Apply solder paste to the exposed thermal pad area and all of the IC terminals. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed.
Side View (a)
DIE
Thermal Pad
End View (b)
Bottom View (c)
Figure 89. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach.
Single or Dual
7. 8.
Figure 90. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown in Figure 90. There should be etching for the leads as well as etch for the thermal pad. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. They help dissipate the heat generated by the THS4211 and THS4215 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered, so wicking is not a problem. Connect all holes to the internal ground plane. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the
2.
3.
4. 5.
26
OOO O OO OOO O OOOOOOO OOOOOOO OOO OOO O OOO OOOOOOO O OOO
68 Mils x 70 Mils (Via Diameter = 13 Mils)
For a given JA , the maximum power dissipation is shown in Figure 91 and is calculated by the equation 5:
PD +
Tmax * T A q JA
(6)
where PD = Maximum power dissipation of THS4211 (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient temperature (C) JA = JC + CA JC = Thermal coefficient from junction to the case CA = Thermal coefficient from the case to ambient air (C/W).
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class AB), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, JA decreases and the heat dissipation capability increases. For a single package, the sum of the RMS output currents and voltages should be used to choose the proper package.
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THERMAL ANALYSIS
The THS4211 device does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of 150_ C is exceeded.
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often maximum power dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem.
The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula: Tmax-T A P Dmax + q JA
where PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (C). TA is the ambient temperature (C). JA = JC + CA JC is the thermal coefficient from the silicon junctions to the case (C/W). CA is the thermal coefficient from the case to ambient air (C/W).
DESIGN TOOLS
Performance vs Package Options
The THS4211 and THS4215 are offered in a different package options. However, performance may be limited due to package parasitics and lead inductance in some packages. In order to achieve maximum performance of the THS4211 and THS4215, Texas Instruments recommends using the leadless MSOP (DRB) or MSOP (DGN) packages, in additions to proper high-speed PCB layout. Figure 92 shows the unity gain frequency response of the THS4211 using the leadless MSOP, MSOP, and SOIC package for comparison. Using the THS4211 and THS4215 in a unity gain with the SOIC package may result in the device becoming unstable. In higher gain configurations, this effect is mitigated by the reduced bandwidth. As such, the SOIC is suitable for application with gains equal to or higher than +2 V/V or (-1 V/V).
12 _ 10 Normalized Gain - dB 8 6 4 2 0 -2 PIN = -7 dB VS =5 V -4 10 M Leadless MSOP, & MSOP Rf = 0 100 M f - Frequency - Hz 1G SOIC, Rf = 100 Rf SOIC, Rf = 0
For systems where heat dissipation is more critical, the THS4211 is offered in an 8-pin MSOP with PowerPAD. The thermal coefficient for the MSOP PowerPAD package is substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the two packages. The data for the DGN package assumes a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application notes in the Additional Reference Material section at the end of the data sheet.
3.5 PD - Maximum Power Dissipation - W 8-Pin DGN Package 3 2.5 2 8-Pin D Package 1.5 1 0.5 0 -40
+ 499 49.9
Figure 92. Effects of Unity Gain Frequency Response for Differential Packages
-20 0 20 40 60 TA - Ambient Temperature - C
80
JA = 170C/W for 8-Pin SOIC (D) JA = 58.4C/W for 8-Pin MSOP (DGN) TJ= 150C, No Airflow
Figure 91. Maximum Power Dissipation vs Ambient Temperature
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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Evaluation Fixtures, Spice Models, and Applications Support
Small Signal Gain - dB
5 4 3 2 1 0 -1 -2 -3 PIN = -7 dBm VS = 5 V 1M 10 M 100 M f - Frequency - Hz 1G 10 G _ 499 49.9 +
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, evaluation boards have been developed for the THS4211 operational amplifier. Three evaluation boards are available: one THS4211 and one THS4215, both configurable for different gains, and a third for a gain of +1 (THS4211 only). These boards are easy to use, allowing for straightforward evaluation of the device. These evaluation boards can be ordered through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. Schematics for the evaluation boards are shown below. The THS4211/THS4215 EVM board shown in Figure 96 through Figure 99 accommodates different gain configurations. Its default component values are set to give a gain of 2. The EVM can be configured in a gain of +1; however, it is strongly not recommended. Evaluating the THS4211/THS4215 in a gain of +1 using this EVM may cause the part to become unstable. The stability of the device can be controlled by adding a large resistor in the feedback path, but the performance is sacrificed. Figure 93 shows the small signal frequency response of the THS4211 with different feedback resistors in the feedback path. Figure 94 is the small frequency response of the THS4211 using the gain of +1 EVM.
17 15 13 Small Signal Gain - dB 11 9 7 5 3 1 -1 PIN = -7 dBm VS = 5 V -5 10 M 100 M -3 Rf = 100 Rf = 200 _ + Rf Rf = 0
-4 100 k
Figure 94. Frequency Response Using the EDGE # 6443547 G = +1 EVM
The peaking in the frequency response is due to the lead inductance in the feedback path. Each pad and trace on a PCB has an inductance associated with it, which in conjunction with the inductance associated with the package may cause peaking in the frequency response, causing the device to become unstable. In order to achieve the maximum performance of the device, PCB layout is very critical. Texas Instruments has developed an EVM for the evaluation of the THS4211 in a gain of 1. The EVM is shown in Figure 101 through Figure 104. This EVM is designed to minimize peaking in the unity gain configuration. Minimizing the inductance in the feedback path is critical for reducing the peaking of the frequency response in unity gain. The recommended maximum inductance allowed in the feedback path is 4 nH. This inductance can be calculated by using equation 7:
499 49.9
Rf = 50
L(nH) + K ln
2 ) 0.223 W ) T ) 0.5 W)T
(7)
1G
10 G
f - Frequency - Hz
Figure 93. Frequency Response vs Feedback Resistor Using the EDGE #6439527 EVM
where W = Width of trace in inches. = Length of the trace in inches. T = Thickness of the trace in inches. K = 5.08 for dimensions in inches, and K = 2 for dimensions in cm.
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002 J9 Power Down Vs+ R8
C8 R5 Vs+ J1 Vin - R3 78 2_ 3+ R2 41 Vs - R7 J8 Power Down Ref U1 6 R6 Vs -
R9
J4 Vout
J2 Vin+ R4
R1
C7
J7 VS-
J6 GND
TP1
J5 VS+
FB1 VS- VS+ C1 C2
FB2
Figure 96. THS4211/THS4215 EVM Board Layout (Top Layer)
+
C3 C4
C5
C6
+
Figure 95. THS4211/THS4215 EVM Circuit Configuration
Figure 97. THS4211/THS4215 EVM Board Layout (Second Layer, Ground)
29
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002 Vs+ 78 2_ 3+ 41 J2 Vin+ R4 Vs - U1 6 R6
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R7
J4 Vout
J7 VS-
J6 GND
TP1
J5 VS+
FB1 VS- VS+ C1 C2
FB2
+
C3 C4
C5
C6
+
Figure 98. THS4211/THS4215 EVM Board Layout (Third Layer, Power)
Figure 100. THS4211 Unity Gain EVM Circuit Configuration
Figure 99. THS4211/THS4215 EVM Board Layout (Bottom Layer)
Figure 101. THS4211 Unity Gain EVM Board Layout (Top Layer)
30
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
Figure 102. THS4211 Unity Gain EVM Board Layout (Second Layer, Ground)
Figure 104. THS4211 Unity Gain EVM Board Layout (Bottom Layer)
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits, where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4211 is available through either the Texas Instruments web site (www.ti.com) or as one model on a disk from the Texas Instruments Product Information Center (1-800-548-6132). The PIC is also available for design assistance and detailed product information at this number. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself.
ADDITIONAL REFERENCE MATERIAL
Figure 103. THS4211 Unity Gain EVM Board Layout (Third Layer, Power)
D D
PowerPAD Made Easy, application brief (SLMA004) PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
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THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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MECHANICAL DATA
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES:A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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THS4211 THS4215
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MECHANICAL DATA
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,65 8 5
0,38 0,25
0,08 M
Thermal Pad (See Note D)
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073271/B 08/01 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heat sink to the thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments. 33
THS4211 THS4215
SLOS400A - SEPTEMBER 2002 - REVISED OCTOBER 2002
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MECHANICAL DATA
DRB (S-PDSO-N8) PLASTIC SMALL OUTLINE
3,25 2,75
3,25 2,75
Pin 1 Index Area Top and Bottom
1,00 0,80 0,20 REF. Seating Plane 0,08 0,05 0,00
1,85 MAX 8X 0,65 0,45 0,65 1 4
1,59 MAX
Exposed Metalized Feature (4x)
1,95
8
5
Exposed Thermal Die Pad (See Nore D)
8X 0,37 0,25 0,10
4203482/B 03/02 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Small Outline No-lead (SON) package configuration. The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
34
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Copyright 2002, Texas Instruments Incorporated

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