 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TSC80251G1D Extended 8-bit Microcontroller with Serial Communication Interfaces 1. Description The TSC80251G1D products are derivatives of the TEMIC Microcontroller family based on the extended 8-bit C251 Architecture. This family of products is tailored to 8-bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines. The TSC80251G1D derivatives are pin-out and software compatible with standard 80C51/Fx/Rx with extended on-chip data memory (1 Kbyte RAM) and up to 256 Kbytes of external code and data. Additionally, the TSC83251G1D provides on-chip code memory (16 Kbytes ROM). They provide transparent enhancements to Intel's 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I2C, Wire and SPI protocols), a Keyboard interrupt interface and Power Monitoring and Management features. TSC80251G1D Mask ROM and ROMless derivatives are optimized both for speed and for low power consumption on a wide voltage range. Notes: This Datasheet provides the technical description of the TSC80251G1D derivatives. For further information on the device usage, please request the TSC80251 Programmers' Guide and the TSC80251G1D Design Guide. For information on the EPROM/OTP devices, please refer to the TSC87251G1A Datasheet. 2. Typical Applications D ISDN terminals D High-Speed modems D PABX (SOHO) D Networking D Line cards D Computer peripherals D Printers D Plotters D Scanners D Banking machines D Barcode readers D Smart cards readers D High-end digital monitors D High-end joysticks Purchase of TEMIC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Rev. C - October 14, 1998 1 TSC80251G1D 3. Features D Pin-Out and software compatibility with standard 80C51 products and 80C51FA/FB/RA/RB D Plug-in replacement of Intel's 80C251Sx D C251 core: Intel's MCSR251 step D compliance G G G G G 83 ns Instruction cycle time @ 24 MHz 40-byte Register File Registers Accessible as Bytes, Words or Dwords Six-stage Instruction Pipeline 16-bit Internal Code Fetch D Secure 14-bit Hardware Watchdog Timer D Power Monitoring and Management G Power-Fail reset G Power-On reset (integrated on the chip) G Power-Off flag (cold and warm resets) G Software programmable system clock G Idle and Power-Down modes D Keyboard interrupt interface on Port 1 D Non Maskable Interrupt input (NMI) D Real-time Wait states inputs (WAIT#/AWAIT#) D On-chip Code Verify with Encryption for Mask ROM versions D ONCE mode and full speed Real-Time In-Circuit Emulation support (Third Party Vendors) D High speed versions: G 16 MHz and 24 MHz G 5 V 10 % G Typical operating current: 34 mA @ 24 MHz 23 mA @ 16 MHz G Power-Down mode typical current 2 A D Low voltage version: G 2.7 V to 5.5 V G 12 MHz operation G Typical operating current: 8 mA @ 3 V G Power-Down mode typical current 1 A D Temperature ranges: G Commercial (0C to +70C) G Industrial (-40C to +85C) G Option: extended range (-55C to +125C) D Packages: G PDIL 40, PLCC 44 and VQFP 44 G Options: known good dice and ceramic packages D Enriched C51 Instruction Set G 16-bit and 32-bit ALU G Compare and Conditional Jump Instructions G Expanded Set of Move Instructions D Linear Addressing D 1 Kbyte of on-chip RAM D External memory space (Code/Data) programmable from 64 Kbytes to 256 Kbytes D TSC83251G1D: 16 Kbytes of on-chip masked ROM (Engineering and fast production with TSC87251G1A OTP/EPROM version) D TSC80251G1D: ROMless version D Four 8-bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the standard 80C51) D Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator D SSLC: Synchronous Serial Link Controller G multi-master and slave protocols G Wire and SPI master and slave protocols I 2C D Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the standard 80C51) D EWC: Event and Waveform Controller G Compatible with Intel's Programmable Counter Array (PCA) G Common 16-bit Timer/Counter reference with four possible clock sources (Fosc/4, Fosc/12, Timer 1 and external input) G Five modules with four programmable modes: - 16-bit software Timer/Counter - 16-bit Timer/Counter Capture Input and software pulse measurement - High-speed output and 16-bit software Pulse Width Modulation (PWM) - 8-bit hardware PWM without overhead G 16-bit Watchdog Timer/Counter capability 2 Rev. C - October 14, 1998 TSC80251G1D 4. Block Diagram P3(A16) P2(A15-8) P1(A17) P0(AD7-0) PSEN# PORTS 0-3 ALE UART 16-bit Memory Code 16-bit Memory Address EA# Event and Waveform Controller ROM 16 Kbytes RAM 1 Kbyte Timers 0, 1 and 2 AWAIT# Bus Interface Unit Peripheral Interface Unit I2C/SPI/mWire Controller Watchdog Timer 24-bit Prog. Counter Bus 24-bit Data Address Bus 16-bit Inst. Bus RST 8-bit Internal Bus Power Monitoring XTAL2 Clock Unit Clock System Prescaler XTAL1 8-bit Data Bus Keyboard Interface CPU Interrupt Handler Unit NMI VDD VSS VSS1 VSS2 Figure 1. TSC80251G1D Block Diagram Rev. C - October 14, 1998 3 TSC80251G1D 5. Pin Description 5.1. Pinout P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS# P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA# ALE PSEN# P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 TSC80251G1D Figure 2. TSC80251G1D 40-pin DIP package P1.4/CEX1/SS# P1.3/CEX0 P1.2/ECI P1.1/T2EX P1.0/T2 VSS1 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 TSC80251G1D P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA# NMI ALE PSEN# P2.7/A15 P2.6/A14 P2.5/A13 Figure 3. TSC80251G1D 44-pin PLCC Package 4 Rev. C P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS VSS2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 18 19 20 21 22 23 24 25 26 27 28 - October 14, 1998 TSC80251G1D P1.4/CEX1/SS# P1.3/CEX0 P1.2/ECI P1.1/T2EX P1.0/T2 VSS1 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 TSC80251G1D 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA# NMI ALE PSEN# P2.7/A15 P2.6/A14 P2.5/A13 Figure 4. TSC80251G1D 44-pin VQFP Package Table 1. TSC80251G1D Pin Assignment DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLCC VQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS1 P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS# Name P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS VSS2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 12 13 14 15 16 17 18 19 20 21 22 DIP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PLCC VQFP 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VSS2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN# ALE NMI EA# P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD Name P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS Rev. C - October 14, 1998 5 TSC80251G1D 5.2. Signals Table 2. TSC80251G1D Signal Descriptions Signal Name A17 Type O 18th Address Bit Description Alternate Function P1.7 Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see NO TAG). A16 O 17th Address Bit Output to memory as 17th external address bit (A16) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see NO TAG). A15:8(1) AD7:0(1) ALE O I/O O Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information are available onlines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address from address/databus. AWAIT# I Real-time Asynchronous Wait States Input When this pin is active (low level), the memory cycle is stretched until it becomes high. When using the TSC80251G1D as a pin-for-pin replacement for a 8xC51 product, AWAIT# can be unconnected without loss of compatibility or power consumption increase (on-chip pull-up). Not available on DIP package. CEX4:0 O PCA Input/Output pins CEXx are input signals for the PCA capture mode and output signals for the PCA compare and PWM modes. EA# I External Access Enable EA# directs program memory accesses to on-chip or off-chip code memory. For EA#= 0, all program memory accesses are off-chip. For EA#= 1, an access is on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without ROM on-chip, EA# must be strapped to ground. ECI MISO O I/O PCA External Clock input ECI is the external clock input to the 16-bit PCA timer. SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. MOSI I/O SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. INT1:0# I External Interrupts 0 and 1. INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0# NMI I Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. When using the TSC80251G1D as a pin-for-pin replacement for a 8xC51 product, NMI can be unconnected without loss of compatibility or power consumption increase (on-chip pull- down). Not available on DIP package. P0.0:7 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. AD7:0 P3.3:2 P1.7 P1.5 P1.2 P1.7:3 P0.7:0 P2.7:0 P3.7 6 Rev. C - October 14, 1998 TSC80251G1D Signal Name P1.0:7 Type I/O Port 1 Description Alternate Function P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability for a keyboard interface. P2.0:7 P3.0:7 PSEN# I/O I/O O Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. Program Store Enable/Read signal output PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCONFIG0 byte (see NO TAG). RD# O Read or 17th Address Bit (A16) Read signal output to external data memory depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see NO TAG). RST I Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. RXD SCL I/O I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial modes I/O 1, 2 and 3. I2C Serial Clock When I2C controller is in master mode, SCL outputs the serial clock to slave peripherals. When I2C controller is in slave mode, SCL receives clock from the master controller. SCK I/O SPI Serial Clock When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in slave mode, SCK receives clock from the master controller. SDA SS# T1:0 T2 I/O I I/O I/O I2C Serial Data SDA is the bidirectional I2C data line. SPI Slave Select Input When in Slave mode, SS# enables the slave mode. Timer 1:0 External Clock Inputs When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode, T2 is the clock output. T2EX I Timer 2 External Input In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter mode, this signal determines the count direction: 1= up, 0= down. TXD VDD VSS I/O PWR GND Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Digital Supply Voltage Connect this pin to +5V or +3V supply voltage. Circuit Ground Connect this pin to ground. P3.1 P1.1 P1.0 P1.4 P1.7 P1.6 P1.6 P3.0 P3.7 A15:8 Rev. C - October 14, 1998 7 TSC80251G1D Signal Name VSS1 Type GND Secondary Ground 1 Description Alternate Function This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G1D as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of compatibility. Not available on DIP package. VSS2 GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G1D as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. WAIT# I Real-time Synchronous Wait States Input The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the WAIT# input signal. WCLK O Wait Clock Output The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When enabled, the WCLK output produces a square wave signal with a period of one half the oscillator frequency. WR# XTAL1 O I Write Write signal output to external memory. Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. XTAL2 O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Note: 1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the non-page mode chip configuration. If the chip is configured in page mode operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0). P3.6 P1.7 P1.6 8 Rev. C - October 14, 1998 TSC80251G1D 6. Address Spaces The TSC80251G1D implements four different address spaces: D On-chip ROM program/code memory (not present in ROMless devices) D On-chip RAM data memory D Special Function Registers (SFRs) D Configuration array 6.1. Program/Code Memory The TSC83251G1D implements 16 Kbytes of on-chip program/code memory. Figure 5 shows the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 16-Kbyte on-chip program memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The rest of the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. For the masked ROM products, the internal program/code is provided in a masked ROM. For the ROMless products, there is no possible internal program/code and EA# must be tied to a low level. Program/code External Memory Space 48 Kbytes 16 Kbytes FF:4000h FF:3FFFh EA#= 0 FF:0000h FE:FFFFh FE:0000h FD:FFFFh Reserved 02:0000h 01:FFFFh EA#= 1 16 Kbytes Program/code Segments FF:FFFFh On-chip Memory ROM Code 64 Kbytes 128 Kbytes Figure 5. Program/Code Memory Mapping Notes: Special care should be taken when the Program Counter (PC) increments: - If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight bytes of the on-chip ROM (FF:3FF8h-FF:3FFFFh). Because of its pipeline capability, the TSC80251G1D may attempt to prefetch code from external memory (at an address above FF:3FFFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does not affect Ports 0 and 2. - When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC increments beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area). Rev. C - October 14, 1998 EEEE EEEE EEEE 01:0000h 00:FFFFh 00:0000h 9 TSC80251G1D 6.2. Data Memory The TSC80251G1D implements 1 Kbyte of on-chip data RAM. Figure 6 shows the split of the internal and external data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers area (see TSC80251 Programmers' Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit addressable. This on-chip RAM is not accessible through the program/code memory space. For faster computation with the on-chip ROM code of the TSC83251G1D, its upper 8 Kbytes are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit is cleared (EMAP# bit in UCONFIG1 byte, see Figure 8). However, if EA# is tied to a low level, the TSC80251G1D derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory (i.e. the upper 8 Kbytes of the lower 16 Kbytes of the segment FF:). If EMAP# bit is set, the on-chip ROM is not accessible through the region 00:. All the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external memory. Data External Memory Space 48 Kbytes 16 Kbytes EA#= 0 FF:4000h FF:3FFFh FF:0000h FE:FFFFh FE:0000h EA#= 1 8 Kbytes On-chip Memory ROM Code Data Segments FF:FFFFh 64 Kbytes 64 Kbytes 8 Kbytes 56 Kbytes EMAP#= 1 Figure 6. Data Memory Mapping 6.3. Special Function Registers The Special Function Registers (SFRs) of the TSC80251G1D derivatives fall into the categories detailed in Table 3 to Table 11. SFRs are placed in a reserved on-chip memory region S: which is not represented in the data memory mapping (Figure 6). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12. They are upward compatible with the SFRs of the standard 80C51 and the Intel's 80C251Sx family. In this table, the C251 core registers are in italics and are described in the TSC80251 Programmer's Guide. The other SFRs are described in the TSC80251G1D Design Guide. All the SFRs are bit-addressable using the C251 instruction set. 10 Rev. C EEEEE EEEEE EEEEE EEEEE FD:FFFFh Reserved 02:0000h 01:FFFFh 01:0000h 00:FFFFh 00:E000h 00:DFFFh 00:0420h 8 Kbytes EMAP#= 0 RAM Data 1 Kbyte 32 bytes reg. - October 14, 1998 TSC80251G1D Table 3. C251 Core SFRs Mnemonic ACC(1) B(1) PSW PSW1 SP(1) Name Accumulator B Register Program Status Word Program Status Word 1 Stack Pointer - LSB of SPX Mnemonic SPH(1) DPL(1) DPH(1) DPXL(1) Name Stack Pointer High - MSB of SPX Data Pointer Low byte - LSB of DPTR Data Pointer High byte - MSB of DPTR Data Pointer Extended Low byte of DPX - Region number Note: 1. These SFRs can also be accessed by their corresponding registers in the register file. Table 4. I/O Port SFRs Mnemonic P0 P1 Name Port 0 Port 1 Mnemonic P2 P3 Name Port 2 Port 3 Table 5. Timers SFRs Mnemonic TL0 TH0 TL1 TH1 TL2 TH2 TCON Name Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte Timer/Counter 1 High Byte Timer/Counter 2 Low Byte Timer/Counter 2 High Byte Timer/Counter 0 and 1 Control Mnemonic TMOD T2CON T2MOD RCAP2L RCAP2H WDTRST Name Timer/Counter 0 and 1 Modes Timer/Counter 2 Control Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture Low Byte Timer/Counter 2 Reload/Capture High Byte WatchDog Timer Reset Table 6. Serial I/O Port SFRs Mnemonic SCON SBUF SADEN Name Serial Control Serial Data Buffer Slave Address Mask Mnemonic SADDR BRL BDRCON Name Slave Address Baud Rate Reload Baud Rate Control Table 7. SSLC SFRs Mnemonic SSCON SSDAT SSCS Name Synchronous Serial control Synchronous Serial Data Synchronous Serial Control and Status Mnemonic SSADR SSBR Name Synchronous Serial Address Synchronous Serial Bit Rate Rev. C - October 14, 1998 11 TSC80251G1D Table 8. Event Waveform Control SFRs Mnemonic CCON CMOD CL CH CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCAP0L Name EWC-PCA Timer/Counter Control EWC-PCA Timer/Counter Mode EWC-PCA Timer/Counter Low Register EWC-PCA Timer/Counter High Register EWC-PCA Timer/Counter Mode 0 EWC-PCA Timer/Counter Mode 1 EWC-PCA Timer/Counter Mode 2 EWC-PCA Timer/Counter Mode 3 EWC-PCA Timer/Counter Mode 4 EWC-PCA Compare Capture Module 0 Low Register Mnemonic CCAP1L CCAP2L CCAP3L CCAP4L CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H Name EWC-PCA Compare Capture Module 1 Low Register EWC-PCA Compare Capture Module 2 Low Register EWC-PCA Compare Capture Module 3 Low Register EWC-PCA Compare Capture Module 4 Low Register EWC-PCA Compare Capture Module 0 High Register EWC-PCA Compare Capture Module 1 High Register EWC-PCA Compare Capture Module 2 High Register EWC-PCA Compare Capture Module 3 High Register EWC-PCA Compare Capture Module 4 High Register Table 9. System Management SFRs Mnemonic PCON POWM PFILT Name Power Control Power Management Power Filter Mnemonic CKRL WCON Name Clock Reload Synchronous Real-Time Wait State Control Table 10. Interrupt SFRs Mnemonic IE0 IE1 IPH0 Name Interrupt Enable Control 0 Interrupt Priority Control 1 Interrupt Priority Control High 0 Mnemonic IPL0 IPH1 IPL1 Name Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 Table 11. Keyboard Interface SFRs Mnemonic P1IE P1F Name Port 1 Input Interrupt Enable Port 1 Flag Mnemonic P1LS Name Port 1 Level Selection 12 Rev. C - October 14, 1998 TSC80251G1D Table 12. SFR Addresses and Reset Values 0/8 F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h IPL0 X000 0000 P3 1111 1111 IE0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 SBUF XXXX XXXX 1/9 CH 0000 0000 2/A CCAP0H 0000 0000 3/B CCAP1H 0000 0000 4/C CCAP2H 0000 0000 5/D CCAP3H 0000 0000 6/E CCAP4H 0000 0000 7/F FFh F7h B(1) 0000 0000 CL 0000 0000 ACC(1) 0000 0000 CCON 00X0 0000 PSW(1) 0000 0000 T2CON 0000 0000 CMOD 00XX X000 PSW1(1) 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 CCAP0L 0000 0000 CCAP1L 0000 0000 CCAP2L 0000 0000 CCAP3L 0000 0000 CCAP4L 0000 0000 EFh E7h DFh D7h CFh C7h SADEN 0000 0000 IE1 XX0X XXX0 SADDR 0000 0000 IPL1 XX0X XXX0 IPH1 XX0X XXX0 SPH(1) 0000 0000 IPH0 X000 0000 BFh B7h AFh WDTRST 1111 1111 BRL 0000 0000 SSBR 0000 0000 TL0 0000 0000 DPL(1) 0000 0000 2/A BDRCON XXX0 0000 SSCON (2) WCON XXXX XX00 A7h 9Fh 97h P1LS 0000 0000 SSCS (3) P1IE 0000 0000 SSDAT 0000 0000 TH1 0000 0000 P1F 0000 0000 SSADR 0000 0000 CKRL 0000 1000 PFILT XXXX XXXX TL1 0000 0000 DPH(1) 0000 0000 3/B TH0 0000 0000 DPXL(1) 0000 0001 4/C POWM 0XXX 0XXX PCON 0000 0000 7/F 8Fh 87h 5/D 6/E reserved Notes: 1. These registers are described in the TSC80251 Programmer's Guide (C251 core registers). 2. In I 2C and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in I 2C mode and 0000 0100 in SPI mode. 3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode. Rev. C - October 14, 1998 13 TSC80251G1D 6.4. Configuration Bytes The TSC80251G1D derivatives provide user design flexibility by configuring certain operating features at device reset. These features fall into the following categories: D external memory interface (page mode, address bits, programmed wait states and the address range for RD#, WR#, and PSEN#) D source mode/binary mode opcodes D selection of bytes stored on the stack by an interrupt D mapping of the upper portion of on-chip code memory to region 00: Two user configuration bytes UCONFIG0 (see Figure 7) and UCONFIG1 (see Figure 8) provide the information. When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G1D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h. For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory. UCONFIG0 Configuration Byte 0 7 - Bit Number 7 6 WSA1# Bit Mnemonic - 5 WSA0# 4 XALE# 3 RD1 2 RD0 1 PAGE# 0 SRC Description Reserved Set this bit when writing to UCONFIG0. Wait State A bits Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses (all regions except 01:). WSA1# 0 0 1 1 WSA0# 0 1 0 1 Number of wait states 3 2 1 0 6 WSA1# 5 WSA0# 4 3 2 1 XALE# RD1 RD0 PAGE# Extend ALE bit Clear to extend the duration of the ALE pulse from TOSC to 3xTOSC. Set to minimize the duration of the ALE pulse to 1xTOSC. Memory Signal Select bits Specify a 18 bit 17 bit or 16 bit external address bus and the usage of RD# WR# and PSEN# signals 18-bit, 17-bit 16-bit RD#, (see Table 13). Page Mode Select bit(1) Clear to select the faster page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0. Set to select the non-page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port 0. Source Mode/Binary Mode Select bit Clear to select the binary mode. Set to select the source mode. 0 SRC Notes: 1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page modes. If P2.1 is cleared during the first data phase, a page mode configuration is used, otherwise the subsequent fetches are performed in Non-Page mode. 2. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0. Figure 7. Configuration Byte 0 14 Rev. C - October 14, 1998 TSC80251G1D UCONFIG1 Configuration Byte 1 7 - Bit Number 7 6 5 6 - Bit Mnemonic - - - 5 - 4 INTR 3 WSB 2 WSB1# 1 WSB0# 0 EMAP# Description Reserved Set this bit when writing to UCONFIG1. Reserved Set this bit when writing to UCONFIG1. Reserved Set this bit when writing to UCONFIG1. Interrupt Mode bit(1) Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register). Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the PSW1 register). Wait State B bit(2) Clear to generate one wait state for memory region 01:. Set for no wait states for memory region 01:. Wait State B bits Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses (only region 01:). WSB1# 0 0 1 1 WSB0# 0 1 0 1 Number of wait states 3 2 1 0 4 INTR 3 WSB 2 WSB1# 1 WSB0# 0 EMAP# On-Chip Code Memory Map bit Clear to map the upper 8 Kbytes of on-chip code memory (at FF:2000h-FF:3FFFh) to the data space (at 00:E000h-00:FFFFh). Set not to map the upper 8 Kbytes of on-chip code memory (at FF:2000h-FF:3FFFh) to the data space. Notes: 1. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used with code executing outside region FF:. 2. Use only for Step A compatibility; set this bit when WSB1:0# are used. Figure 8. Configuration Byte 1 Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals RD1 0 0 1 1 RD0 0 1 0 1 P1.7 A17 I/O pin I/O pin I/O pin P3.7/RD# A16 A16 I/O pin Read signal for regions 00: and 01: PSEN# Read signal for all external memory locations Read signal for all external memory locations Read signal for all external memory locations Read signal for regions FE: and FF: WR# Write signal for all external memory locations Write signal for all external memory locations Write signal for all external memory locations Write signal for all external memory locations External Memory 256 Kbytes 128 Kbytes 64 Kbytes 2 x 64 Kbytes(1) Note: 1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code. Rev. C - October 14, 1998 15 TSC80251G1D 7. Instruction Set Summary This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are two concurrent processes limiting the effective instruction throughput: D Instruction Fetch D Instruction Execution Table 20 to Table 34 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and this is never limiting the execution speed. If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). The maximum average instruction throughput is provided by Table 14 depending on the external memory configuration (from Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values. Table 14. Minimum Number of States per Instruction for given Average Sizes Average size of Instructions (bytes) 1 2 3 4 5 Page Mode (states) 1 2 3 4 5 Non-Page Mode (states) 0 Wait State 2 4 6 8 10 1 Wait State 3 6 9 12 15 2 Wait States 4 8 12 16 20 3 Wait States 5 10 15 20 25 4 Wait States 6 12 18 24 30 If the average execution time of the considered instructions is larger than the number of states given by Table 14, this larger value will prevail as the limiting factor. Otherwise, the value from Table 14 must be taken. This is providing a fair estimation of the execution speed but only the actual code execution can provide the final value. 7.1. Notation for Instruction Operands Table 15 to Table 19 provide Notation for Instruction Operands. Table 15. Notation for Direct Addressing Direct Address dir8 dir16 Description A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80h-FFh). It is a byte (default), word or double word depending on the other operand. A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing. C251 n n C51 n Table 16. Notation for Immediate Addressing Immediate Address #data #data16 #0data16 #1data16 #short Description An 8-bit constant that is immediately addressed in an instruction A 16-bit constant that is immediately addressed in an instruction A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with zeros (#0data16) or ones (#1data16). A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. C251 n n n n C51 n 16 Rev. C - October 14, 1998 TSC80251G1D Table 17. Notation for Bit Addressing Direct Address bit51 Description A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits in the 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR. C251 C51 n bit n Table 18. Notation for Destination in Control Instructions Direct Address rel addr11 addr16 addr24 Description A signed (two's complement) 8-bit relative address. The destination is -128 to +127 bytes relative to the next instruction's first byte. An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next instruction's first byte. A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as the next instruction's first byte. A 24-bit target address. The target can be anywhere within the 16-Mbyte address space. C251 n C51 n n n n Table 19. Notation for Register Operands Register @Ri Rn n Rm Rmd Rms m, md, ms WRj WRjd WRjs @WRj @WRj +dis16 j, jd, js DRk DRkd DRks @DRk @DRk +dis16 k, kd, ks Description A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1 Byte register R0-R7 of the currently selected register bank Byte register index: n= 0-7 Byte register R0-R15 of the currently selected register file Destination register Source register Byte register index: m, md, ms= 0-15 Word register WR0, WR2, ..., WR30 of the currently selected register file Destination register Source register A memory location (00:0000h-00:FFFFh) addressed indirectly through word register WR0-WR30, is the target address for jump instructions. A memory location (00:0000h-00:FFFFh) addressed indirectly through word register (WR0-WR30) + 16-bit signed (two's complement) displacement value Word register index: j, jd, js= 0-30 Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file Destination register Source register A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register DR0-DR28, DR56 and DR60, is the target address for jump instruction A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register (DR0-DR28, DR56, DR60) + 16-bit (two's complement) signed displacement value Dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60 C251 C51 n n n n n Rev. C - October 14, 1998 17 TSC80251G1D 7.2. Size and Execution Time for Instruction Families Table 20. Summary of Add and Subtract Instructions Add Subtract Add with Carry Subtract with Borrow ADD Mnemonic A, Rn A, dir8 Register to ACC Binary Mode Comments Bytes 1 2 1 2 3 3 3 4 5 5 4 4 5 5 4 4 1 2 1 2 Source Mode Bytes 2 2 2 2 2 2 2 3 4 4 3 3 4 4 3 3 2 2 2 2 States 1 1(2) 2 1 2 3 5 3 4 6 3(2) 4 3(3) 4(4) 3(3) 4(3) 1 1(2) 2 1 States 2 1(2) 3 1 1 2 4 2 3 5 2(2) 3 2(3) 3(4) 2(3) 3(3) 2 1(2) 3 1 Direct address to ACC Indirect address to ACC Immediate data to ACC Byte register to/from byte register Word register to/from word register Dword register to/from dword register Immediate 8-bit data to/from byte register Immediate 16-bit data to/from word register 16-bit unsigned immediate data to/from dword register Direct address (on-chip RAM or SFR) to/from byte register Direct address (on-chip RAM or SFR) to/from word register Direct address (64K) to/from byte register Direct address (64K) to/from word register Indirect address (64K) to/from byte register Indirect address (16M) to/from byte register Register to/from ACC with carry Direct address (on-chip RAM or SFR) to/from ACC with carry Indirect address to/from ACC with carry Immediate data to/from ACC with carry ADD A, @Ri A, #data Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 ADD / SUB Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk A, Rn A, dir8 ADDC / SUBB A, @Ri A, #data Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). 18 Rev. C - October 14, 1998 TSC80251G1D Table 21. Summary of Increment and Decrement Instructions Increment Increment Decrement Decrement INC Mnemonic A ACC by 1 Register by 1 Binary Mode Comments Bytes 1 1 2 1 3 3 3 3 1 Source Mode Bytes 1 2 2 2 2 2 2 2 1 States 1 1 2(2) 3 2 2 4 5 1 States 1 2 2(2) 4 1 1 3 4 1 INC DEC Rn dir8 @Ri Direct address (on-chip RAM or SFR) by 1 Indirect address by 1 Byte register by 1, 2, or 4 Word register by 1, 2, or 4 Double word register by 1, 2, or 4 Double word register by 1, 2, or 4 Data pointer by 1 INC DEC INC DEC INC Rm, #short WRj, #short DRk, #short DRk, #short DPTR Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. Table 22. Summary of Compare Instructions Compare CMP Mnemonic Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 Register with register Binary Mode Comments Bytes 3 3 3 4 5 5 5 4 4 5 5 4 4 Source Mode Bytes 2 2 2 3 4 4 4 3 3 4 4 3 3 States 2 3 5 3 4 6 6 3(1) 4 3(2) 4(3) 3(2) 4(2) States 1 2 4 2 3 5 5 2(1) 3 2(2) 3(3) 2(2) 3(2) Word register with word register Dword register with dword register Register with immediate data Word register with immediate 16-bit data Dword register with zero-extended 16-bit immediate data Dword register with one-extended 16-bit immediate data Direct address (on-chip RAM or SFR) with byte register Direct address (on-chip RAM or SFR) with word register Direct address (64K) with byte register Direct address (64K) with word register Indirect address (64K) with byte register Indirect address (16M) with byte register CMP DRk, #1data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk Notes: 1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). Rev. C - October 14, 1998 19 TSC80251G1D Table 23. Summary of Logical Instructions (1/2) Logical AND(1) Logical OR(1) Logical Exclusive OR(1) Clear(1) Complement(1) Rotate Left Rotate Left Carry ANL Rotate Right Rotate Right Carry RR A RRC A Mnemonic A, Rn A, dir8 A, @Ri A, #data dir8, A dir8, #data Rmd, Rms register to ACC Binary Mode Comments Bytes 1 2 1 2 2 3 3 3 4 5 4 4 5 5 4 4 1 1 1 1 1 1 Source Mode Bytes 2 2 2 2 2 3 2 2 3 4 3 3 4 4 3 3 1 1 1 1 1 1 States 1 1(3) 2 1 2(4) 3(4) 2 3 3 4 3(3) 4 3(5) 4(6) 3(5) 4(5) 1 1 1 1 1 1 States 2 1(3) 3 1 2(4) 3(4) 1 2 2 3 2(3) 3 2(5) 3(6) 2(5) 3(5) 1 1 1 1 1 1 Direct address (on-chip RAM or SFR) to ACC Indirect address to ACC Immediate data to ACC ACC to direct address Immediate 8-bit data to direct address Byte register to byte register Word register to word register Immediate 8-bit data to byte register Immediate 16-bit data to word register Direct address to byte register Direct address to word register Direct address (64K) to byte register Direct address (64K) to word register Indirect address (64K) to byte register Indirect address (16M) to byte register Clear ACC Complement ACC Rotate ACC left Rotate ACC left through CY Rotate ACC right Rotate ACC right through CY ANL ORL XRL WRjd, WRjs Rm, #data WRj, #data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk CLR CPL RL RLC RR RRC A A A A A A Notes: 1. Logical instructions that affect a bit are in Table 29. 2. A shaded cell denotes an instruction in the C51 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. 5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). 20 Rev. C - October 14, 1998 TSC80251G1D Table 24. Summary of Logical Instructions (2/2) Shift Left Logical SLL Shift Right Arithmetic SRA Shift Right Logical SRL Swap SWAP A Mnemonic Rm Binary Mode Comments Bytes Shift byte register left through the MSB Shift word register left through the MSB Shift byte register right Shift word register right Shift byte register left Shift word register left Swap nibbles within ACC 3 3 3 3 3 3 1 Source Mode Bytes 2 2 2 2 2 2 1 States 2 2 2 2 2 2 2 States 1 1 1 1 1 1 2 SLL WRj Rm SRA WRj Rm SRL WRj SWAP A Note: 1. A shaded cell denotes an instruction in the C51 Architecture. Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions Multiply Divide Divide Decimal-adjust ACC for Addition (BCD) MUL AB MUL Mnemonic AB Multiply A and B Binary Mode Comments Bytes 1 3 3 1 3 3 1 Source Mode Bytes 1 2 2 1 2 2 1 States 5 6 12 10 11 21 1 States 5 5 11 10 10 20 1 MUL Rmd, Rms WRjd, WRjs AB Multiply byte register and byte register Multiply word register and word register Divide A and B Divide byte register and byte register Divide word register and word register Decimal adjust ACC DIV Rmd, Rms WRjd, WRjs DA A Note: 1. A shaded cell denotes an instruction in the C51 Architecture. Rev. C - October 14, 1998 21 TSC80251G1D Table 26. Summary of Move Instructions (1/3) Move to High word Move with Sign extension Move with Zero extension Move Code Move eXtended MOVH Mnemonic MOVH MOVS MOVZ MOVC DRk, #data16 WRj, Rm WRj, Rm A, @A +DPTR A, @A +PC A, @Ri A, @DPTR Binary Mode Comments Bytes 16-bit immediate data into upper word of dword register Byte register to word register with sign extension Byte register to word register with zeros extension Code byte relative to DPTR to ACC Code byte relative to PC to ACC Extended memory (8-bit address) to ACC(2) Extended memory (16-bit address) to ACC(2) ACC to extended memory (8-bit address)(2) ACC to extended memory (16-bit address)(2) 5 3 3 1 1 1 1 1 1 Source Mode Bytes 4 2 2 1 1 1 1 1 1 States 3 2 2 6(3) 6(3) 4 3(4) 4 4(3) States 2 1 1 6(3) 6(3) 5 3(4) 4 4(3) MOVX @Ri, A @DPTR, A Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. Extended memory addressed is in the region specified by DPXL (reset value= 01h). 3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states). 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). Table 27. Summary of Move Instructions (2/3) Move(1) MOV Mnemonic A, Rn A, dir8 A, @Ri A, #data Rn, A Rn, dir8 Register to ACC Binary Mode Comments Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 Direct address (on-chip RAM or SFR) to ACC Indirect address to ACC Immediate data to ACC ACC to register Direct address (on-chip RAM or SFR) to register Immediate data to register ACC to direct address Register to direct address Direct address to direct address Indirect address to direct address Immediate data to direct address ACC to indirect address Direct address to indirect address Immediate data to indirect address Load Data Pointer with a 16-bit constant Source Mode Bytes 2 2 2 2 2 3 3 2 3 3 3 3 2 3 3 3 States 1 1(3) 2 1 1 1(3) 1 2(3) 2(3) 3(4) 3(3) 3(3) 3 3(3) 3 2 States 2 1(3) 3 1 2 2(3) 2 2(3) 3(3) 3(4) 4(3) 3(3) 4 4(3) 4 2 MOV Rn, #data dir8, A dir8, Rn dir8, dir8 dir8, @Ri dir8, #data @Ri, A @Ri, dir8 @Ri, #data DPTR, #data16 Notes: 1. Instructions that move bits are in Table 29. 2. Move instructions from the C51 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. Apply note 3 for each dir8 operand. 22 Rev. C - October 14, 1998 TSC80251G1D Table 28. Summary of Move Instructions (3/3) Move(1) MOV Mnemonic Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 DRk, #1data16 Rm, dir8 WRj, dir8 DRk, dir8 Rm, dir16 WRj, dir16 DRk, dir16 Rm, @WRj Rm, @DRk WRjd, @WRjs WRj, @DRk dir8, Rm Binary Mode Comments Bytes Byte register to byte register Word register to word register Dword register to dword register Immediate 8-bit data to byte register Immediate 16-bit data to word register zero-ext 16bit immediate data to dword register one-ext 16bit immediate data to dword register Direct address to byte register Direct address to word register Direct address to dword register Direct address (64K) to byte register Direct address (64K) to word register Direct address (64K) to dword register Indirect address (64K) to byte register Indirect address (16M) to byte register Indirect address (64K) to word register Indirect address (16M) to word register Byte register to direct address Word register to direct address Dword register to direct address Byte register to direct address (64K) Word register to direct address (64K) Dword register to direct address (64K) Byte register to indirect address (64K) Byte register to indirect address (16M) Word register to indirect address (64K) Word register to indirect address (16M) Indirect with 16-bit dis (64K) to byte register Indirect with 16-bit dis (64K) to word register Indirect with 16-bit dis (16M) to byte register Indirect with 16-bit dis (16M) to word register Byte register to indirect with 16-bit dis (64K) Word register to indirect with 16-bit dis (64K) Byte register to indirect with 16-bit dis (16M) Word register to indirect with 16-bit dis (16M) 3 3 3 4 5 5 5 4 4 4 5 5 5 4 4 4 4 4 4 4 5 5 5 4 4 4 4 5 5 5 5 5 5 5 5 Source Mode Bytes 2 2 2 3 4 4 4 3 3 3 4 4 4 3 3 3 3 3 3 3 4 4 4 3 3 3 3 4 4 4 4 4 4 4 4 States 2 2 3 3 3 5 5 3(3) 4 6 3(4) 4(5) 6(6) 3(4) 4(4) 4(5) 5(5) 4(3) 5 7 4(4) 5(5) 7(6) 4(4) 5(4) 5(5) 6(5) 6(4) 7(5) 7(4) 8(5) 6(4) 7(5) 7(4) 8(5) States 1 1 2 2 2 4 4 2(3) 3 5 2(4) 3(5) 5(6) 2(4) 3(4) 3(5) 4(5) 3(3) 4 6 3(4) 4(5) 6(6) 3(4) 4(4) 4(5) 5(5) 5(4) 6(5) 6(4) 7(5) 5(4) 6(5) 6(4) 7(5) MOV dir8, WRj dir8, DRk dir16, Rm dir16, WRj dir16, DRk @WRj, Rm @DRk, Rm @WRjd, WRjs @DRk, WRj Rm, @WRj +dis16 WRj, @WRj +dis16 Rm, @DRk +dis24 WRj, @WRj +dis24 @WRj +dis16, Rm @WRj +dis16, WRj @DRk +dis24, Rm @DRk +dis24, WRj Notes: 1. Instructions that move bits are in Table 29. 2. Move instructions unique to the C251 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states). Rev. C - October 14, 1998 23 TSC80251G1D Table 29. Summary of Bit Instructions Clear Bit Set Bit Complement Bit AND Carry with Bit AND Carry with Complement of Bit OR Carry with Bit OR Carry with Complement of Bit Move Bit to Carry Move Bit from Carry CLR Mnemonic CY Clear carry Clear direct bit Clear direct bit Set carry Set direct bit Set direct bit Complement carry Binary Mode Comments Bytes 1 2 4 1 2 4 1 2 4 2 4 2 4 2 4 2 4 2 4 2 4 Source Mode Bytes 1 2 3 1 2 3 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 States 1 2(3) 4(3) 1 2(3) 4(3) 1 2(3) 4(3) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 2(3) 4(3) States 1 2(3) 3(3) 1 2(3) 3(3) 1 2(3) 3(3) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 2(3) 3(3) CLR bit51 bit CY SETB bit51 bit CY CPL bit51 bit CY, bit51 CY, bit Complement direct bit Complement direct bit And direct bit to carry And direct bit to carry And complemented direct bit to carry And complemented direct bit to carry Or direct bit to carry Or direct bit to carry Or complemented direct bit to carry Or complemented direct bit to carry Move direct bit to carry Move direct bit to carry Move carry to direct bit Move carry to direct bit ANL CY, /bit51 CY, /bit CY, bit51 CY, bit ORL CY, /bit51 CY, /bit CY, bit51 CY, bit MOV bit51, CY bit, CY Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. 24 Rev. C - October 14, 1998 TSC80251G1D Table 30. Summary of Exchange, Push and Pop Instructions Exchange bytes Exchange Digit Push Pop XCH A, Mnemonic A, Rn ACC and register Binary Mode Comments Bytes 1 2 1 1 2 4 5 3 3 3 2 3 3 3 Source Mode Bytes 2 2 2 2 2 3 4 2 2 2 2 2 2 2 States 3 3(3) 4 4 2(2) 4 5 4 5 9 3(2) 3 5 9 States 4 3(3) 5 5 2(2) 3 5 3 4 8 3(2) 2 4 8 XCH A, dir8 A, @Ri ACC and direct address (on-chip RAM or SFR) ACC and indirect address ACC low nibble and indirect address (256 bytes) Push direct address onto stack Push immediate data onto stack Push 16-bit immediate data onto stack Push byte register onto stack Push word register onto stack Push double word register onto stack Pop direct address (on-chip RAM or SFR) from stack Pop byte register from stack Pop word register from stack Pop double word register from stack XCHD A, @Ri dir8 #data #data16 PUSH Rm WRj DRk dir8 Rm POP WRj DRk Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. Table 31. Summary of Conditional Jump Instructions (1/2) Jump conditional on status Jcc rel (PC) (PC) + size (instr); IF [cc] THEN (PC) (PC) + rel Mnemonic JC JNC JE JNE JG JLE JSL JSLE JSG JSGE rel rel rel rel rel rel rel rel rel rel Jump if carry Jump if not carry Jump if equal Jump if not equal Jump if greater than Binary Mode(2) Comments Bytes 2 2 3 3 3 3 3 3 3 3 Source Mode(2) Bytes 2 2 2 2 2 2 2 2 2 2 States 1/4(3) 1/4(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) States 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) Jump if less than, or equal Jump if less than (signed) Jump if less than, or equal (signed) Jump if greater than (signed) Jump if greater than or equal (signed) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. States are given as jump not-taken/taken. 3. In internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd. Rev. C - October 14, 1998 25 TSC80251G1D Table 32. Summary of Conditional Jump Instructions (2/2) Jump if bit Jump if not bit Jump if bit and clear JB Jump if accumulator is zero Jump if accumulator is not zero Compare and jump if not equal JZ rel JNZ rel CJNE Decrement and jump if not zero DJNZ Mnemonic bit51, rel Binary Mode(2) Comments Bytes Jump if direct bit is set Jump if direct bit of 8-bit address location is set Jump if direct bit is not set Jump if direct bit of 8-bit address location is not set Jump if direct bit is set & clear bit Jump if direct bit of 8-bit address location is set and clear Jump if ACC is zero Jump if ACC is not zero Compare direct address to ACC and jump if not equal Compare immediate to ACC and jump if not equal Compare immediate to register and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct address and jump if not zero 3 5 3 5 3 5 2 2 3 3 3 3 2 3 Source Mode(2) Bytes 3 4 3 4 3 4 2 2 3 3 4 4 3 3 States 2/5(3)(6) 4/7(3)(6) 2/5(3)(6) 4/7(3)(6) 4/7(5)(6) 7/10(5)(6) 2/5(6) 2/5(6) 2/5(3)(6) 2/5(6) 2/5(6) 3/6(6) 2/5(6) 3/6(4)(6) States 2/5(3)(6) 3/6(3)(6) 2/5(3)(6) 3/6(3) 4/7(5)(6) 6/9(5)(6) 2/5(6) 2/5(6) 2/5(3)(6) 2/5(6) 3/6(6) 4/7(6) 3/6(6) 3/6(4)(6) JB JNB JBC JZ JNZ bit, rel bit51, rel bit, rel bit51, rel bit, rel rel rel A, dir8, rel A, #data, rel CJNE Rn, #data, rel @Ri, #data, rel Rn, rel DJNZ dir8, rel Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. States are given as jump not-taken/taken. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. 5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR. 6. In internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd. 26 Rev. C - October 14, 1998 TSC80251G1D Table 33. Summary of unconditional Jump Instructions Absolute jump Extended jump Long jump Short jump Jump indirect No operation AJMP Mnemonic AJMP EJMP LJMP SJMP JMP NOP addr11 addr24 @DRk @WRj addr16 rel @A +DPTR Absolute jump Extended jump Binary Mode Comments Bytes 2 5 3 3 3 2 1 1 Source Mode Bytes 2 4 2 2 3 2 1 1 States 3(2)(3) 6(2)(4) 7(2)(4) 6(2)(4) 5(2)(4) 4(2)(4) 5(2)(4) 1 States 3(2)(3) 5(2)(4) 6(2)(4) 5(2)(4) 5(2)(4) 4(2)(4) 5(2)(4) 1 Extended jump (indirect) Long jump (indirect) Long jump (direct address) Short jump (relative address) Jump indirect relative to the DPTR No operation (Jump never) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. In internal execution only, add 1 to the number of states if the destination address is internal and odd. 3. Add 2 to the number of states if the destination address is external. 4. Add 3 to the number of states if the destination address is external. Table 34. Summary of Call and Return Instructions Absolute call Extended call Long call Return from subroutine Extended return from subroutine Return from interrupt Trap interrupt ACALL Mnemonic ACALL ECALL LCALL RET ERET RETI TRAP addr11 @DRk addr24 @WRj addr16 Binary Mode Comments Bytes Absolute subroutine call Extended subroutine call (indirect) Extended subroutine call Long subroutine call (indirect) Long subroutine call Return from subroutine Extended subroutine return Return from interrupt Jump to the trap interrupt vector 2 3 5 3 3 1 3 1 2 Source Mode Bytes 2 2 4 2 3 1 2 1 1 States 9(2)(3) 14(2)(3) 14(2)(3) 10(2)(3) 9(2)(3) 7(2) 9(2) 7(2)(4) 12(4) States 9(2)(3) 13(2)(3) 13(2)(3) 9(2)(3) 9(2)(3) 7(2) 8(2) 7(2)(4) 11(4) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd. 3. Add 2 to the number of states if the destination address is external. 4. Add 5 to the number of states if INTR= 1. Rev. C - October 14, 1998 27 TSC80251G1D 8. ROM Verifying 8.1. Internal ROM Features Mask ROM Devices The internal ROM of the TSC83251G1D contains four different areas: Code Memory, Configuration Bytes, Encryption Array and Signature Bytes. All the Internal ROM of TSC83251G1D products is made of Mask ROM cells. They can be verified using the same algorithm as the EPROM/OTP devices. ROMless Devices The TSC80251G1D products include only Signature Bytes made of Mask ROM cells. They can be verified using the same algorithm as the EPROM/OTP devices. These products do not include on-chip Configuration Bytes, Code Memory and Encryption Array. 8.2. Encryption Features In some microcontrollers applications, it is desirable that the user program code be secured from unauthorized access. The TSC83251G1D products include a 128-byte Encryption Array located in non volatile memory outside the memory address space. During verification of the on-chip code memory, the seven low-order address bits also address the Encryption Array. As the byte of the code memory is read, it is exclusive-NOR'ed (XNOR) with the key byte from the Encryption Array. If the Encryption Array is not programmed (still all 1s), the user program code is placed on the data bus in its original, unencrypted form. If the Encryption Array is programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the key byte sequence. Note: When a MOVC instruction is executed the content of the ROM is not encrypted. In order to fully protect the user program code, MOVC to the on-chip Code Memory can only be executed from the on-chip Code Memory when the encryption is used for mask ROM devices. Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array is programmed. Caution: If the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with "random" byte values other than FFh to prevent the encryption key sequence from being revealed. To preserve the secrecy of the encryption key byte sequence, the Encryption Array cannot be verified. 8.3. Signature Bytes The TSC80251G1D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the procedure described in paragraph "Verify Algorithm". The values of the Signature Bytes are listed in Table 35. Table 35. Signature Bytes (Electronic ID) Signature Address Vendor Architecture Memory Revision TEMIC C251 16K MaskROM or ROMless None (TSC80251G1 derivative) ( ) First (TSC80251G1D derivative) 30h 31h 60h 61h Signature Data 58h 40h 7Bh FFh FEh Note: The way Configuration Bytes are used is changing from TSC80251G1 derivatives to TSC80251G1D derivatives. The verify algorithm should check the product revision to select the right model. 28 Rev. C - October 14, 1998 TSC80251G1D 8.4. Verify Algorithm Figure 9 shows the hardware setup needed to verify the internal ROM areas of the TSC80251G1D derivatives: D D D D D D D D The chip has to be put under reset and maintained in this state until the completion of the verify sequence. The voltage on the EA# pin has to be set to VDD. PSEN# and the other control signals (ALE and Port 0) have to be set to a logic high level. Then PSEN# has to be to forced to a logic low level after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence. The Verify Mode is selected according to the code applied on Port 0 (see Table 36). It has to be applied until the completion of this verification. The verification address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address. Then device is driving the data on Port 2. PSEN# and the other control signals have to be released to complete a sequence of verify operations. Table 36. Verifying Modes Verify ROM On-chip code memory Configuration Bytes Signature Bytes RST 1 1 1 EA# 1 1 1 PSEN# 0 0 0 ALE 1 1 1 P0 28h 29h 29h P2 Data Data Data P1(MSB) P3(LSB) 16-bit Address: 0000h-3FFFh (16K) UCONFIG0: FFF8h UCONFIG1: FFF9h 30h, 31h, 60h, 61h VDD EA# ALE RST PSEN# VDD VDD Mode P0[7:0] P2[7:0] Data TSC80251G1D A[15:8] P1[7:0] XTAL1 A[7:0] P3[7:0] VSS VSS1 VSS2 4 to 12 MHz Figure 9. Setup for ROM Verifying Rev. C - October 14, 1998 29 TSC80251G1D 9. Absolute Maximum Rating and Operating Conditions 9.1. Absolute Maximum Rating Table 37. Absolute Maximum Ratings D Storage Temperature . . . . . . . . . . . . . . . . . . . . D Voltage on any other Pin to VSS . . . . . . . . . . . D IOL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . D Power Dissipation . . . . . . . . . . . . . . . . . . . . . . -65 to +150C -0.5 to +6.5 V 15 mA 1.5 W 9.2. Operating Conditions Table 38. Operating Conditions D Ambient Temperature Under Bias Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D VDD High Speed versions . . . . . . . . . . . . . . . . . . . . . Low Voltage versions . . . . . . . . . . . . . . . . . . . . 0 to +70C -40 to +85C 4.5 to 5.5 V 2.7 to 5.5 V Note: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 30 Rev. C - October 14, 1998 TSC80251G1D 10. DC Characteristics - Commercial & Industrial 10.1. DC Characteristics: High Speed versions - Commercial & Industrial Table 39. DC Characteristics; VDD= 4.5 to 5.5 V, TA= -40 to +85C Symbol VIL VIL1(5) VIL2 VIH VIH1(5) VOL Parameter Input Low Voltage (except EA#, SCL, SDA) Input Low Voltage (SCL, SDA) Input Low Voltage (EA#) Input high Voltage (except XTAL1, RST, SCL, SDA) Input high Voltage (XTAL1, RST, SCL, SDA) Output Low Voltage (Ports 1, 2, 3) Output Low Voltage (Ports 0, ALE, PSEN#,Port 2 in Page Mode during External Address) Output high Voltage (Ports 1, 2, 3, ALE, PSEN#) Output high Voltage (Port 0, Port 2 in Page Mode during External Address) Reset threshold on Reset threshold off VDD data retention limit Logical 0 Input Current (Ports 1, 2, 3) Logical 1 Input Current (NMI) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Ports 1, 2, 3 - AWAIT#) RST Pull-Down Resistor Pin Capacitance Min -0.5 -0.5 0 0.2VDD + 0.9 0.7VDD Typical(4) Max 0.2VDD - 0.1 0.3VDD 0.2VDD - 0.3 VDD + 0.5 VDD + 0.5 0.3 0.45 1.0 0.3 0.45 1.0 Units V V V V V V Test Conditions IOL= 100 A(1)(2) IOL= 1.6 mA(1)(2) IOL= 3.5 mA(1)(2) IOL= 200 A(1)(2) IOL= 3.2 mA(1)(2) IOL= 7.0 mA(1)(2) IOH= -10 A(3) IOH= -30 A(3) IOH= -60 A(3) IOH= -200 A IOH= -3.2 mA IOH= -7.0 mA VOL1 V VOH VDD -0.3 VDD -0.7 VDD -1.5 VDD -0.3 VDD -0.7 VDD -1.5 3.9 3.4 4.1 3.6 4.3 3.8 1.8 - 50 + 50 10 - 650 40 170 10 18 25 30 40 6 8 12 20 23 34 5 6.5 9.5 2 225 V VOH1 V VRST+ VRST- VRET IIL0 IIL1 ILI ITL RRST CIO IDD V V V A A A A kW pF mA mA mA mA mA mA A TA= 25C FOSC= 12 MHz FOSC= 16 MHz FOSC= 24 MHz FOSC= 12 MHz FOSC= 16 MHz FOSC= 24 MHz VRET < VDD < 5.5 V VIN= 0.45 V VIN= VDD 0.45 V < VIN < VDD VIN= 2.0 V Operating Current p g IDL IPD Idle Mode Current Power-Down Current Rev. C - October 14, 1998 31 TSC80251G1D Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum IOL per 8-bit port: Port 0 . . . . . . . 26 mA Ports 1-3 . . . . . 15 mA Maximum Total IOL for all: Output Pins . . . 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VDD = 5 V and TA = 25C with no guarantee. They are not tested and there is not guarantee on these values. 5. The input threshold voltage of SCL and SDA meets the I 2C specification, so an input voltage below 0.3.VDD will be recognized as a logic 0 while an input voltage above 0.7.VDD will be recognized as a logic 1. 40 30 IDD/IDL (mA) 20 10 0 2 4 6 8 10 12 14 16 18 20 22 24 max Active mode (mA) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA) Note: 1. The clock prescaler is not used: FOSC = FXTAL . Frequency at XTAL(1) (MHz) Figure 10. IDD/IDL versus Frequency; VDD= 4.5 to 5.5 V 32 Rev. C - October 14, 1998 TSC80251G1D 10.2. DC Characteristics: Low Voltage versions - Commercial & Industrial Table 40. DC Characteristics from 2.7 to 5.5 V, TA= -40 to +85C Symbol VIL VIL1(5) VIL2 VIH VIH1(5) VOL VOL1 Parameter Input Low Voltage (except EA#, SCL, SDA) Input Low Voltage (SCL, SDA) Input Low Voltage (EA#) Input high Voltage (except XTAL1, RST, SCL, SDA) Input high Voltage (XTAL1, RST, SCL, SDA) Output Low Voltage (Ports 1, 2, 3) Output Low Voltage (Ports 0, ALE, PSEN#,Port 2 in Page Mode during External Address) Output high Voltage (Ports 1, 2, 3, ALE, PSEN#) Output high Voltage (Port 0, Port 2 in Page Mode during External Address) Reset threshold on Reset threshold off VDD data retention limit Logical 0 Input Current (Ports 1, 2, 3 - AWAIT#) Logical 1 Input Current (NMI) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Ports 1, 2, 3) RST Pull-Down Resistor Pin Capacitance Min -0.5 -0.5 0 0.2VDD + 0.9 0.7VDD Typical(4) Max 0.2VDD - 0.1 0.3VDD 0.2VDD - 0.3 VDD + 0.5 VDD + 0.5 0.45 0.45 Units V V V V V V V Test Conditions IOL= 0.8 mA(1)(2) IOL= 1.6 mA(1)(2) VOH VOH1 0.9VDD 0.9VDD V V IOH= -10 A(3) IOH= -40 A VRST+ VRST- VRET IIL0 IIL1 ILI ITL RRST CIO 2.1 1.8 2.3 2.0 2.4 2.1 1.8 - 50 + 50 10 - 650 V V V A A A A kW pF TA= 25C 5 MHz, VDD < 3.6 V 10 MHz, VDD < 3.6V 12 MHz, VDD < 3.6 V 5 MHz, VDD < 3.6 V 10 MHz, VDD < 3.6 V 12 MHz, VDD < 3.6 V VRET < VDD < 3.6 V VIN= 0.45 V VIN= VDD 0.45 V < VIN < VDD VIN= 2.0 V 40 170 10 3.5 225 8 11 13 1 4 5 10 mA mA mA mA mA mA A IDD Operating Current 7 8 0.5 IDL Idle Mode Current 1.5 2 IPD Power-Down Current 2 Rev. C - October 14, 1998 33 TSC80251G1D Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum IOL per 8-bit port: Port 0 . . . . . . . 26 mA Ports 1-3 . . . . . 15 mA Maximum Total IOL for all: Output Pins . . . 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VDD = 3 V and TA = 25C with no guarantee. They are not tested and there is not guarantee on these values. 5.The input threshold voltage of SCL and SDA meets the I 2C specification, so an input voltage below 0.3.VDD will be recognized as a logic 0 while an input voltage above 0.7.VDD will be recognized as a logic 1. 15 IDD/IDL (mA) 10 5 0 1 2 3 4 5 6 7 8 9 10 11 12 max Active mode (mA) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA) Note: 1. The clock prescaler is not used: FOSC = FXTAL . Frequency at XTAL(1) (MHz) Figure 11. IDD/IDL versus XTAL Frequency; VDD= 2.7 to 5.5 V 34 Rev. C - October 14, 1998 TSC80251G1D 10.3. DC Characteristics: IDD, IDL and IPD Test Conditions VDD IDD VDD VDD P0 RST TSC80251G1D (NC) Clock Signal EA# VDD XTAL2 XTAL1 VSS All other pins are unconnected Figure 12. IDD Test Condition, Active Mode VDD IDL VDD P0 RST TSC80251G1D (NC) Clock Signal EA# VDD XTAL2 XTAL1 VSS All other pins are unconnected Figure 13. IDL Test Condition, Idle Mode VDD IPD VDD P0 RST TSC80251G1D (NC) EA# VDD XTAL2 XTAL1 VSS All other pins are unconnected Figure 14. IPD Test Condition, Power-Down Mode Rev. C - October 14, 1998 35 TSC80251G1D 11. AC Characteristics - Commercial & Industrial 11.1. AC Characteristics - External Bus Cycles Definition of symbols Table 41. External Bus Cycles Timing Symbol Definitions Signals A D L Q R W Address Data In ALE Data Out RD#/PSEN# WR# H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Test conditions: capacitive load on all pins= 50 pF. Table 42 and Table 43 list AC timing parameters for the TSC80251G1D with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states. Figure 15 to Figure 20 show the bus cycles with the timing parameters. 36 Rev. C - October 14, 1998 TSC80251G1D Table 42. Bus Cycles AC Timings; VDD= 4.5 to 5.5 V, TA= -40 to 85C 12 MHz Symbol TOSC TLHLL TAVLL TLLAX TRLRH(1) TWLWH TLLRL(1) TLHAX TRLDV(1) TRHDX(1) TRHAX(1) TRLAZ(1) TRHDZ1 TRHDZ2 TRHLH1 TRHLH2 TWHLH TAVDV1 TAVDV2 TAVDV3 TAXDX TAVRL(1) TAVWL1 TAVWL2 TWHQX TQVWH TWHAX 1/FOSC ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low RD#/PSEN# Pulse Width WR# Pulse Width ALE Low to RD#/PSEN# Low ALE High to Address Hold RD#/PSEN# Low to Valid Data Data Hold After RD#/PSEN# High Address Hold After RD#/PSEN# High RD#/PSEN# Low to Address Float Instruction Float After RD#/PSEN# High Data Float After RD#/PSEN# High RD#/PSEN# high to ALE High (Instruction) RD#/PSEN# high to ALE High (Data) WR# High to ALE High Address (P0) Valid to Valid Data In Address (P2) Valid to Valid Data In Address (P0) Valid to Valid Instruction In Data Hold after Address Hold Address Valid to RD# Low Address (P0) Valid to WR# Low Address (P2) Valid to WR# Low Data Hold after WR# High Data Valid to WR# High WR# High to Address Hold 0 125 124 162 81 135 168 24 189 192 262 300 146 0 91 90 119 60 104 126 0 0 2 23 188 24 148 150 187 217 104 0 57 53 75 37 74 84 16 MHz Min 62 61 59 19 118 120 27 81 24 MHz Unit Min 41 40 38 2.5 76 78 14 43 Parameter Min 83 82 80 27 158 160 41 116 144 0 0 2 23 146 24 104 103 110 137 62 Max Max Max ns ns(2) ns(2) ns ns(3) ns(3) ns ns(2) 59 ns(3) ns ns 2 23 104 ns ns ns ns ns ns ns(2)(3) ns(2)(3) ns ns ns (2) ns (2) ns (2) ns ns(3) ns 102 0 0 Notes: 1. Specification for PSEN# are identical to those for RD#. 2. If a wait state is added by extending ALE, add 2xTOSC. 3. If wait states are added by extending RD#/PSEN#/WR#, add 2NxTOSC (N= 1..3). Rev. C - October 14, 1998 37 TSC80251G1D Table 43. Bus Cycles AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85C 12 MHz Symbol TOSC TLHLL TAVLL TLLAX TRLRH(1) TWLWH TLLRL(1) TLHAX TRLDV(1) TRHDX(1) TRHAX(1) TRLAZ(1) TRHDZ1 TRHDZ2 TRHLH1 TRHLH2 TWHLH TAVDV1 TAVDV2 TAVDV3 TAXDX TAVRL(1) TAVWL1 TAVWL2 TWHQX TQVWH TWHAX 1/FOSC ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low RD#/PSEN# Pulse Width WR# Pulse Width ALE Low to RD#/PSEN# Low ALE High to Address Hold RD#/PSEN# Low to Valid Data Data Hold After RD#/PSEN# High Address Hold After RD#/PSEN# High RD#/PSEN# Low to Address Float Instruction Float After RD#/PSEN# High Data Float After RD#/PSEN# High RD#/PSEN# high to ALE High (Instruction) RD#/PSEN# high to ALE High (Data) WR# High to ALE High Address (P0) Valid to Valid Data In Address (P2) Valid to Valid Data In Address (P0) Valid to Valid Instruction In Data Hold after Address Hold Address Valid to RD# Low Address (P0) Valid to WR# Low Address (P2) Valid to WR# Low Data Hold after WR# High Data Valid to WR# High WR# High to Address Hold 0 114 112 161 87 135 164 24 189 192 214 271 131 0 0 2(4) 35 199 Parameter Min 83 81 66 5 152 155 34 93 115 Unit Max ns ns(2) ns(2) ns ns (3) ns (3) ns ns(2) ns(3) ns ns ns ns ns ns ns ns ns(2)(3) ns(2)(3) ns ns ns (2) ns (2) ns(2) ns n (3) ns Notes: 1. Specification for PSEN# are identical to those for RD#. 2. If a wait state is added by extending ALE, add 2xTOSC. 3. If wait states are added by extending RD#/PSEN#/WR#, add 2NxTOSC (N= 1..3). 4. TRLAZ max is 0 ns if VDD < 3.6V. 38 Rev. C - October 14, 1998 TSC80251G1D Waveforms in Non-Page Mode ALE TLHLL(1) TLLRL(1) RD#/PSEN# TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) TLLAX P0 A7:0 TAVRL(1) TAVDV1(1) TAVDV2(1) P2/A16/A17 A15:8/A16/A17 TRHDZ1 TRHDX D7:0 Instruction In TRHAX TRLRH(1) TRHLH1 Note: 1. The value of this parameter depends on wait states. See Table 42 and Table 43. Figure 15. External Bus Cycle: Code Fetch (Non-Page Mode) ALE TLHLL(1) TLLRL(1) TRLRH(1) TRHLH2 RD#/PSEN# TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) TLLAX P0 A7:0 TAVRL(1) TAVDV1(1) TAVDV2(1) P2/A16/A17 A15:8/A16/A17 TRHDZ2 TRHDX D7:0 Data In TRHAX Note: 1. The value of this parameter depends on wait states. See Table 42 and Table 43. Figure 16. External Bus Cycle: Data Read (Non-Page Mode) Rev. C - October 14, 1998 39 TSC80251G1D ALE TLHLL(1) TWLWH(1) WR# TLHAX(1) TAVLL(1) P0 TLLAX TQVWH TWHQX D7:0 Data Out TWHAX A15:8/A16/A17 TWHLH A7:0 TAVWL1(1) TAVWL2(1) P2/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 42 and Table 43. Figure 17. External Bus Cycle: DataWrite (Non-Page Mode) Waveforms in Page Mode ALE TLHLL(1) TLLRL(1) RD#/PSEN#(3) TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) TLLAX P2 A15:8 TAVRL(1) TAVDV1(1) TAVDV2(1) P0/A16/A17 A7:0/A16/A17 Page Miss(2) D7:0 Instruction In TAXDX TAVDV3(1) A7:0/A16/A17 Page hit(2) TRHDZ1 TRHDX D7:0 Instruction In TRHAX Notes: 1. The value of this parameter depends on wait states. See Table 42 and Table 43. 2. A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2xTOSC );a page miss requires two states (4xTOSC ). 3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. Figure 18. External Bus Cycle: Code Fetch (Page Mode) 40 Rev. C - October 14, 1998 TSC80251G1D ALE TLHLL(1) TLLRL(1) RD#/PSEN# TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) TLLAX P2 A7:0 TAVRL(1) TAVDV1(1) TAVDV2(1) P0/A16/A17 A15:8/A16/A17 TRHDZ2 TRHDX D7:0 Data In TRHAX TRLRH(1) TRHLH2 Note: 1. The value of this parameter depends on wait states. See Table 42 and Table 43. Figure 19. External Bus Cycle: Data Read (Page Mode) ALE TLHLL(1) TWLWH(1) TWHLH WR# TLHAX(1) TAVLL(1) P2 TLLAX TQVWH TWHQX D7:0 Data Out TWHAX A15:8/A16/A17 A7:0 TAVWL1(1) TAVWL2 (1) P0/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 42 and Table 43. Figure 20. External Bus Cycle: DataWrite (Page Mode) Rev. C - October 14, 1998 41 TSC80251G1D 11.2. AC Characteristics - Real-Time Synchronous Wait State Definition of symbols Table 44. Real-Time Synchronous Wait Timing Symbol Definitions Signals C R W Y WCLK RD#/PSEN# WR# WAIT# L V X Conditions Low Valid No Longer Valid Timings Table 45. Real-Time Synchronous Wait AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol TCLYV TCLYX TRLYV TRLYX TWLYV TWLYX Parameter Wait Clock Low to Wait Set-up Wait Hold after Wait Clock Low PSEN#/RD# Low to Wait Set-up Wait Hold after PSEN#/RD# Low WR# Low to Wait Set-up Wait Hold after WR# Low Min 0 2WxTOSC + 5 0 2WxTOSC + 5 0 2WxTOSC + 5 Max TOSC - 20 (1+2W)xTOSC - 20 TOSC - 20 (1+2W)xTOSC - 20 TOSC - 20 (1+2W)xTOSC - 20 Unit ns ns ns ns ns ns Waveforms State 1 WCLK TCLYXmin State 2 State 3 State 1 (next cycle) ALE TCLYV TCLYXmax RD#/PSEN# TRLYXmax TRLYXmin TRLYV RD#/PSEN# stretched WAIT# P0 P2 A7:0 A15:8 D7:0 stretched stretched A7:0 A15:8 Figure 21. Real-time Synchronous Wait State: Code Fetch/Data Read 42 Rev. C - October 14, 1998 TSC80251G1D State 1 WCLK TCLYXmin State 2 State 3 State 4 ALE TCLYV TCLYXmax WR# TWLYXmax TWLYXmin TWLYV WR# stretched WAIT# P0 P2 A7:0 A15:8 D7:0 stretched stretched Figure 22. Real-time Synchronous Wait State: Data Write 11.3. AC Characteristics - Real-Time Asynchronous Wait State Definition of symbols Table 46. Real-Time Asynchronous Wait Timing Symbol Definitions Signals S Y PSEN#/RD#/WR# AWAIT# L V X Conditions Low Valid No Longer Valid Timings Table 47. Real-Time Asynchronous Wait AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol TSLYV TSLYX Parameter PSEN#/RD#/WR# Low to Wait Set-up Wait Hold after PSEN#/RD#/WR# Low Min Max TOSC - 10 Unit ns ns(1) (2N-1)xTOSC + 10 Note: 1. N is the number of wait states added (N 1). Waveforms RD#/PSEN#/WR# TSLYX TSLYV AWAIT# Figure 23. Real-time Asynchronous Wait State Timings Rev. C - October 14, 1998 43 TSC80251G1D 11.4. AC Characteristics - Serial Port in Shift Register Mode Definition of symbols Table 48. Serial Port Timing Symbol Definitions Signals D Q X Data In Data Out Clock H L V X Conditions High Low Valid No Longer Valid Timings Table 49. Serial Port AC Timing -Shift Register Mode; VDD= 2.7 to 5.5 V, TA= -40 to 85C 12 MHz Symbol TXLXL TQVXH TXHQX TXHDX TXHDV 16 MHz (1) Min 749 625 124 0 24 MHz (1) Unit Min 500 417 82 0 Parameter Min Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid 998 833 165 0 974 Max Max Max ns ns ns ns 482 ns 732 Note: 1. For high speed versions only. Waveforms TXLXL TXD TXHQX TQVXH RXD (Out) RXD (In) 0 TXHDV Valid Valid 1 2 TXHDX Valid Valid Valid Valid Valid 3 4 5 6 7 Set RI(1) Valid Set TI(1) Note: 1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit. Figure 24. Serial Port Waveforms - Shift Register Mode 44 Rev. C - October 14, 1998 TSC80251G1D 11.5. AC Characteristics - SSLC: I2C Interface Timings Table 50. I2C Interface AC Timing; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol Parameter Min INPUT Max Min 14xTCLCL (4) 16xTCLCL (4) 14xTCLCL (4) OUTPUT Max 4.0 s (1) 4.7 s (1) 4.0 s (1) A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A THD; STA TLOW Start condition hold time SCL low time THIGH TRC TFC SCL high time SCL rise time SCL fall time 1 s - (2) 0.3 s 0.3 s (3) TSU; DAT1 TSU; DAT2 TSU; DAT3 THD; DAT TSU; STA Data set-up time 250 ns 250 ns 250 ns 0 ns 20xTCLCL (4)- TRD 1 s (1) SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) Data hold time 8xTCLCL (4) 8xTCLCL (4) - TFC 4.7 s (1) 4.0 s (1) 4.7 s (1) Repeated START set-up time STOP condition set-up time Bus free time 14xTCLCL (4) 14xTCLCL (4) 14xTCLCL (4) TSU; STO TBUF TRD TFD SDA rise time SDA fall time 1 s - (2) 0.3 s 0.3 s (3) Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3xTCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC = one oscillator clock period. Waveforms START or repeated START condition TRD Repeated START condition START condition STOP condition TSU;STA SDA (INPUT/OUTPUT) TBUF TFD TRC TFC TSU;STO 0.7 VDD 0.3 VDD TSU;DAT3 THD;STA TLOW THIGH TSU;DAT1 THD;DAT TSU;DAT2 0.7 VDD 0.3 VDD SCL (INPUT/OUTPUT) Figure 25. I2C Waveforms Rev. C - October 14, 1998 45 AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAA A A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAA AAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Timings 46 TOHOL TOLOH TIHIL TILIH TSHSL TSHOX TSLOV TCLIX, TCHIX TIVCL, TIVCH TCLSH, TCHSH TCLOX, TCHOX TCLOV, TCHOV TCLIX, TCHIX TIVCL, TIVCH TSLCH, TSLCL TCLCX TCHCX TCHCH TSC80251G1D Definition of symbols 11.6. AC Characteristics - SSLC: SPI Interface Slave mode(1) Symbol S O I C Output Fall Time Output Rise time Input Fall Time Input Rise Time SS# High to SS# Low Output Data Hold after SS# High SS# Low to Output Data Valid Input Data Hold after Clock Edge Input Data Valid to Clock Edge SS# High after Clock Edge Output Data Hold Time after Clock Edge Output Data Valid after Clock Edge Input Data Hold after Clock Edge Input Data Valid to Clock Edge SS# Low to Clock edge Clock Low Time Clock High Time Clock Period Table 52. SPI Interface AC Timing; VDD= 2.7 to 5.5 V, TA= -40 to 85C SS# Data Out Data In Clock Signals Table 51. SPI Interface Timing Symbol Definitions Parameter Z X V L H Min 100 100 100 100 200 3.2 3.2 (2) 0 0 8 Floating No Longer Valid Valid Low High Conditions Max 100 100 130 130 100 Rev. C 2 2 - October 14, 1998 Unit TOSC TOSC TOSC s s ns ns ns ns ns ns ns ns ns ns ns ns TSC80251G1D AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A AA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Master mode(3) TCHCH TCHCX TCLCX Clock Period 4 TOSC TOSC TOSC ns ns ns ns Clock High Time Clock Low Time 1.6 1.6 50 50 TIVCL, TIVCH Input Data Valid to Clock Edge TCLIX, TCHIX Input Data Hold after Clock Edge TCLOV, TCHOV Output Data Valid after Clock Edge 65 TCLOX, TCHOX TILIH Output Data Hold Time after Clock Edge Input Data Rise Time Input Data Fall Time 0 2 2 s s ns ns TIHIL TOLOH Output Data Rise time 50 50 TOHOL Output Data Fall Time Notes: 1. Capacitive load on all pins= 200 pF in slave mode. 2. The value of this parameter depends on software. 3. Capacitive load on all pins= 100 pF in master mode. Symbol Parameter Min Max Unit Waveforms SS#(1) (output) SCK (SSCPOL=0) (output) SCK (SSCPOL=1) (output) TIVCH TCHIX TIVCL TCLIX TCHCH TCHCX TCLCX MISO (input) MSB IN BIT 6 TCLOV TCHOV LSB IN TCLOX TCHOX LSB OUT Port Data MOSI (output) Note: 1. SS# handled by software. Port Data MSB OUT BIT 6 Figure 26. SPI Master Waveforms (SSCPHA= 0) Rev. C - October 14, 1998 47 TSC80251G1D SS#(1) (output) SCK (SSCPOL=0) (output) SCK (SSCPOL=1) (output) TIVCH TCHIX TIVCL TCLIX TCHCH TCHCX TCLCX TCHCL TCLCH MISO (input) MSB IN TCHOV TCLOV BIT 6 TCHOX TCLOX BIT 6 LSB IN MOSI (output) Note: 1. SS# handled by software. Port Data MSB OUT LSB OUT Port Data Figure 27. SPI Master Waveforms (SSCPHA= 1) SS# (input) TSLCH TSLCL SCK (SSCPOL=0) (input) SCK (SSCPOL=1) (input) TCLOV TCHOV BIT 6 TCLOX TCHOX SLAVE LSB OUT (1) TCHCH TCLCH TCLSH TCHSH TSHSL TCHCX TCLCX TCHCL TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) TSHOX MSB IN BIT 6 LSB IN Note: 1. Not Defined but normally MSB of character just received. Figure 28. SPI Slave Waveforms (SSCPHA= 0) 48 Rev. C - October 14, 1998 TSC80251G1D SS# (input) TSLCH TSLCL SCK (SSCPOL=0) (input) SCK (SSCPOL=1) (input) TCHOV TCLOV BIT 6 TCLSH TCHSH TSHSL TCHCH TCLCH TCHCL TSLOV MISO (output) (1) TCHOX TCLOX SLAVE LSB OUT TSHOX SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN Note: 1. Not Defined but generally the LSB of the character which has just been received. Figure 29. SPI Slave Waveforms (SSCPHA= 1) Rev. C - October 14, 1998 49 TSC80251G1D 11.7. AC Characteristics - ROM Verifying Definition of symbols Table 53. ROM Verifying Timing Symbol Definitions Signals A E Q Address Enable: mode set on Port 0 Data Out H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Table 54. ROM Verifying AC timings; VDD= 4.5 to 5.5 V, TA= 0 to 40C Symbol TOSC TAVQV TAXQX TELQV TEHQZ Parameter XTAL1 Frequency Address to Data Valid Address to Data Invalid ENABLE low to Data Valid Data Float after ENABLE Min 82.5 Max 250 48xTOSC Unit ns ns ns 0 0 0 48xTOSC 48xTOSC ns ns Waveforms P0 Mode= 28h, 29h or 2Bh TELQV P1= A15:8 P3= A7:0 Address TAVQV P2= D7:0 Data TAXQX TEHQZ Figure 30. ROM Verifying Waveforms 50 Rev. C - October 14, 1998 TSC80251G1D 11.8. AC Characteristics - External Clock Drive and Logic Level References Definition of symbols Table 55. External Clock Timing Symbol Definitions Signals C Clock L H X Conditions Low High No Longer Valid Timings Table 56. External Clock AC Timings; VDD= 4.5 to 5.5 V, TA= -40 to +85C Symbol FOSC TCHCX TCLCX TCLCH TCHCL Oscillator Frequency High Time Low Time Rise Time Fall Time 10 10 3 3 Parameter Min Max 24 Unit MHz ns ns ns ns Waveforms TCLCH VDD - 0.5 0.45 V VIH1 TCLCX TCHCL TCLCL TCHCX VIL Figure 31. External Clock Waveform INPUTS VDD - 0.5 0.45 V 0.2 VDD + 0.9 0.2 VDD - 0.1 OUTPUTS VIH min VIL max Note: During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 32. AC Testing Input/Output Waveforms VLOAD + 0.1 V VLOAD - 0.1 V VOH - 0.1 V VOL + 0.1 V VLOAD Timing Reference Points Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH /VOL level occurs with IOL /IOH = 20 mA. Figure 33. Float Waveforms Rev. C - October 14, 1998 51 TSC80251G1D 12. Packages 12.1. List of Packages D PDIL 40 D PLCC 44 D VQFP 44 (1010) 12.2. PDIL 40 - Mechanical Outline Figure 34. Plastic Dual In Line Table 57. PDIL Package Size MM Min A A1 A2 B B1 C D E E1 e eA eB L D1 - 2.93 0.13 - 0.38 3.18 0.36 0.76 0.20 50.29 15.24 12.32 2.54 B.S.C. 15.24 B.S.C. 17.78 3.81 - - .115 .005 INCH Max 5.08 - 4.95 0.56 1.78 0.38 53.21 15.87 14.73 Min - .015 .125 .014 .030 .008 1.980 .600 .485 .100 B.S.C. .600 B.S.C. Max .200 - .195 .022 .070 .015 2.095 .625 .580 .700 .150 - 52 Rev. C - October 14, 1998 TSC80251G1D 12.3. PLCC 44 - Mechanical Outline Figure 35. Plastic Lead Chip Carrier Table 58. PLCC Package Size MM Min A A1 D D1 D2 E E1 E2 e G H J K Nd Ne 1.07 1.07 0.51 0.33 11 11 4.20 2.29 17.40 16.44 14.99 17.40 16.44 14.99 1.27 BSC 1.22 1.42 - 0.53 .042 .042 .020 .013 11 11 INCH Max 4.57 3.04 17.65 16.66 16.00 17.65 16.66 16.00 Min .165 .090 .685 .647 .590 .685 .647 .590 .050 BSC Max .180 .120 .695 .656 .630 .695 .656 .630 .048 .056 - .021 Rev. C - October 14, 1998 53 TSC80251G1D 12.4. VQFP 44 (1010) - Mechanical Outline Figure 36. Shrink Quad Flat Pack (Plastic) Table 59. VQFP Package Size MM Min A A1 A2 A3 D D1 E E1 J L e f 1.35 11.90 9.90 11.90 9.90 0.05 0.45 0.80 BSC 0.35 BSC - 0.64 REF 0.64 REF 1.45 12.10 10.10 12.10 10.10 - 0.75 .053 .468 .390 .468 .390 .002 .018 .0315 BSC .014 BSC INCH Max 1.60 Min - .025 REF .025REF Max .063 .057 .476 .398 .476 .398 6 .030 54 Rev. C - October 14, 1998 TSC80251G1D 13. Ordering Information 13.1. TSC80251G1D ROMless (Step D) High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TEMIC Part Number (2) TSC80251G1D-24CA TSC80251G1D-24CB TSC80251G1D-24CED TSC80251G1D-16CA TSC80251G1D-16CB TSC80251G1D-16CED TSC80251G1D-16IA TSC80251G1D-16IB ROM ROMless ROMless ROMless ROMless ROMless ROMless ROMless ROMless Description 24 MHz, Commercial 0 to 70C, PDIL 40 24 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, VQFP 44, Dry pack (1) 16 MHz, Commercial 0 to 70C, PDIL 40 16 MHz, Commercial 0 to 70C, PLCC 44 16 MHz, Commercial 0 to 70C, VQFP 44, Dry pack (1) 16 MHz, Industrial -40 to 85C, PDIL 40 16 MHz, Industrial -40 to 85C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TEMIC Part Number (2) TSC80251G1D-L12CB TSC80251G1D-L12CED ROM ROMless ROMless Description 12 MHz, Commercial, PLCC 44 12 MHz, Commercial, VQFP 44, Dry pack (1) 13.2. TSC83251G1D Mask ROM (Step D) High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TEMIC Part Number (2) TSC251G1Dxxx-24CA TSC251G1Dxxx-24CB TSC251G1Dxxx-24CED TSC251G1Dxxx-16CA TSC251G1Dxxx-16CB TSC251G1Dxxx-16CED TSC251G1Dxxx-16IA TSC251G1Dxxx-16IB ROM 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM Description 24 MHz, Commercial 0 to 70C, PDIL 40 24 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, VQFP 44, Dry pack (1) 16 MHz, Commercial 0 to 70C, PDIL 40 16 MHz, Commercial 0 to 70C, PLCC 44 16 MHz, Commercial 0 to 70C, VQFP 44, Dry pack (1) 16 MHz, Industrial -40 to 85C, PDIL 40 16 MHz, Industrial -40 to 85C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TEMIC Part Number (2) TSC251G1Dxxx-L12CB TSC251G1Dxxx-L12CED Notes: 1. Dry Pack mandatory for VQFP package. 2. xxx: means ROM code, is Cxxx in case of encrypted code. ROM 16K MaskROM 16K MaskROM Description 12 MHz, Commercial 0 to 70C, PLCC 44 12 MHz, Commercial 0 to 70C, VQFP 44, Dry pack (1) Rev. C - October 14, 1998 55 TSC80251G1D 13.3. TSC87251G1A OTP (Step A) High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TEMIC Part Number TSC87251G1A-16CA TSC87251G1A-16CB TSC87251G1A-16IA TSC87251G1A-16IB ROM 16K OTP ROM 16K OTP ROM 16K OTP ROM 16K OTP ROM Description 16 MHz, Commercial 0 to 70C, PDIL 40 16 MHz, Commercial 0 to 70C, PLCC 44 16 MHz, Industrial -40 to 85C, PDIL 40 16 MHz, Industrial -40 to 85C, PLCC 44 13.4. TSC87251G1A EPROM - UV Window package (Step A) High Speed Versions 4.5 to 5.5 V, Industrial TEMIC Part Number TSC87251G1A-16IC ROM 16K EPROM Description 16 MHz, Industrial -40 to 85C, window CQPJ 44 13.5. Options (Please consult TEMIC sales) G ROM code encryption G Tape & Real or Dry Pack G Known good dice G Ceramic packages G Extended temperature range: -55C to +125C 13.6. Starter Kit TEMIC Part Number TSC80251-SK Description TSC80251 Starter Kit 13.7. Product Marking Mask ROM versions TEMIC Customer Part number Temic Part number (R) INTEL'97 YYWW . Lot Number ROMless versions TEMIC Temic Part number (R) INTEL'97 YYWW . Lot Number OTP versions TEMIC Temic Part number (R) INTEL'95 YYWW . Lot Number 56 Rev. C - October 14, 1998 |
Price & Availability of TD251G1D
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |