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TAS5111
SLES049A - JULY 2003
DIGITAL AMPLIFIER POWER STAGE
FEATURES D 70-W RMS Power (BTL) Into 4 With Less
Than 0.2% THD+N
D 85-W RMS Power (BTL) Into 4 With Less
Than 10% THD+N (DKD)
APPLICATIONS D DVD Receiver D Home Theatre D Mini/Micro Component Systems D Internet Music Appliance DESCRIPTION
The TAS5111 is a high-performance digital amplifier power stage designed to drive a 4- speaker up to 70 W with 0.2% distortion plus noise. The device incorporates TI's Equibit technology and is used in conjunction with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, depending on the system design. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5111, safeguarding the device and speakers against fault conditions that could damage the system.
THD + NOISE vs FREQUENCY
1 THD+N - Total Harmonic Distortion + Noise - % RL = 4 TC = 75C
D 95-dB Dynamic Range (TDAA System With
TAS5026)
D Power Efficiency Greater Than 90% Into 4-
and 8- Loads - Smaller Power Supplies
D D D D
Self-Protecting Design 32-Pin TSSOP (DAD) PowerPAD Package 36-Pin PSOP3 (DKD) PowerPAD Package 3.3-V Digital Interface - Built-in Converter From 3.3V to PVDD Recommended System Design - Proven Design
THD + NOISE vs OUTPUT POWER
1
D EMI Compliant When Used With
THD+N - Total Harmonic Distortion + Noise - %
RL = 4 TC = 75C
0.1 PO = 1 W
PO = 70 W
0.1
0.01
PO = 10 W
0.01 100m
1
10
100
0.001 20
100
1k f - Frequency - Hz
10k 20k
PO - Output Power - W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Equibit and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
TAS5111
SLES049A - JULY 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5111 is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD) and 36-pin PSOP3 (DKD). The DAD and DKD packages have the thermal pad on top.
DAD PACKAGE (TOP VIEW)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) TAS5111 DVDD TO DGND GVDD TO GND PVDD_X TO GND (dc voltage) PVDD_X TO GND (spike voltage(2)) OUT_X TO GND (dc voltage) OUT_X TO GND (spike voltage(2)) BST_X TO GND (dc voltage) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BST_X TO GND (spike voltage(2)) GREG TO GND (3) PWM_XP, RESET, M1, M2, M3, SD, OTW Maximum operating junction temperature, TJ Storage temperature UNITS -0.3 V to 4.2 V 33.5 V 33.5 V 48 V 33.5 V 48 V 48 V 53 V 14.2 V -0.3 V to DVDD + 0.3 V -40C to 150C -40C to 125C
PWM_BP GND RESET DREG_RTN GREG M3 DREG DGND M1 M2 DVDD SD DGND OTW GND PWM_AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GVDD GND BST_B PVDD_B PVDD_B OUT_B OUT_B GND GND OUT_A OUT_A PVDD_A PVDD_A BST_A GND GVDD
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolutemaximum-ratedconditions for extended periods may affect device reliability. (2) The duration of voltage spike should be less than 100 ns. (3) GREG is treated as an input when the GREG pin is overdriven by GVDD of 12 V.
ORDERING INFORMATION
TA DKD PACKAGE (TOP VIEW) 0C t 70C to PACKAGE TAS5111DAD TAS5111DKD DESCRIPTION 32-pin small TSSOP
GND PWM_BP GND RESET DREG_RTN GREG M3 DREG DGND M1 M2 DVDD SD DGND OTW GND PWM_AP GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GREG GVDD GND BST_B PVDD_B PVDD_B OUT_B OUT_B GND GND OUT_A OUT_A PVDD_A PVDD_A BST_A GND GVDD GREG
36-pin large PSOP3 (1) For the most current specification and package information, refer to our web site at www.ti.com.
PACKAGE DISSIPATION RATINGS
PACKAGE 36-Pin DKD PSOP3 32-Pin DAD TSSOP RJC (C/W) 0.85 1.69 RJA (C/W) See Note 1
See Note 1 (1) Both versions of the TAS5111 package are thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the devices with the pad exposed to ambient air as the only heat sinking of the device. For this reason, RJA a system parameter that characterizes the thermal treatment provided in the application. An example and discussion of typical system RJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heat sinks if needed. Also, for additional general information on PowerPad packages, see TI (SLMA002).
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Terminal Functions
TERMINAL NAME BST_A BST_B DGND DREG DREG_RTN DVDD GND DKD 22 33 9, 14 8 5 12 1, 3, 16, 18, 21, 27, 28, 34 6, 19, 36 20, 35 10 11 7 15 25, 26 29, 30 23, 24 31, 32 17 2 4 DAD 19 30 8, 13 7 4 11 2,15, 18, 24, 25, 31 5 17, 32 9 10 6 14 22, 23 26, 27 20, 21 28, 29 16 1 3 FUNCTION(1) P P P P P P P DESCRIPTION HS bootstrap supply (BST), external capacitor to OUT_A required HS bootstrap supply (BST), external capacitor to OUT_B required I/O reference ground Digital supply voltage regulator decoupling pin, capacitor connected to DREG_RTN Decoupling return pin I/O reference supply input (3.3V): 100 to DREG Power ground
GREG GVDD M1 M2 M3 OTW OUT_A OUT_B PVDD_A PVDD_B PWM_AP PWM_BP RESET
P P I I I O O O P P I I I O
Gate drive voltage regulator decoupling pin, capacitor to GND Voltage supply to on-chip gate drive and digital supply voltage regulators Mode selection pin Mode selection pin Mode selection pin Overtemperature warning output, open drain with internal pullup Output, half-bridge A Output, half-bridge B Power supply input for half-bridge A Power supply input for half-bridge B Input signal, half-bridge A Input signal, half-bridge B Reset signal, active low Shutdown signal for half-bridges A and B
SD 13 12 (1) I = input, O = Output, P = Power
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FUNCTIONAL BLOCK DIAGRAM
BST_A GREG PVDD_A Gate Drive PWM_AP PWM Receiver Timing Control Gate Drive GND Protection A RESET GREG PVDD_B Protection B Gate Drive PWM_BP PWM Receiver Timing Control Gate Drive To Protection Blocks GND DREG DREG GVDD OTW OT Protection SD UVP DREG_RTN DREG_RTN GREG GREG DREG GREG GREG OUT_B BST_B OUT_A
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RECOMMENDED OPERATING CONDITIONS
MIN DVDD GVDD PVDD_x TJ Digital supply (1) Supply for internal gate drive and logic regulators Half-bridge supply Junction temperature Relative to DGND Relative to GND Relative to GND, RL= 4 to 8 3 16 0 0 TYP 3.3 29.5 29.5 MAX 3.6 30.5 30.5 125 UNIT V V V _C
(1) It is recommended for DVDD to be connected to DREG via a 100- resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD = 3.3 V, DVDD connected to DREG via a 100- resistor, RL = 4 , 8X fs = 384 kHz, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25C TA=25C OVER TEMPERATURE TCase= 75C TA=40C TO 85C UNITS MIN/TYP/ MAX
AC PERFORMANCE, BTL Mode, 1 kHz RL = 8 , THD = 0.2%, AES17 filter RL = 8 , THD = 10%, AES17 filter RL = 6 , THD = 0.2%, AES17 filter Po P Output O t t power RL = 6 , THD = 10%, AES17 filter RL = 4 , THD = 0.2%, AES17 filter RL = 4 , THD = 10%, AES17 filter Po = 1 W/ channel, RL = 4 , AES17 filter THD+N Total harmonic distortion + noise Po = 10 W/channel, RL = 4 , AES17 filter Po = 70 W/channel, RL = 4 , AES17 filter Noise SNR DR Output integrated noise Signal-to-noise ratio Dynamic range A-weighted, mute, RL = 4 , 20 Hz to 20 kHz, AES17 filter A-weighted f = 1 kHz, A-weighted 40 53 53 68 74 93 0.05% 0.03% 0.2% 295 95 95 V dB dB V 3.1 31 13.4 13 4 27 1 5 V V V mA mA W W W W W W Typ Typ Typ Typ Typ Typ Typ Typ Typ Max Typ Typ Min Max Min Max Max Max
INTERNAL VOLTAGE REGULATOR DREG GREG IVGDD IDVDd Voltage regulator Voltageregulator Voltage regulator Voltageregulator GVDD supply current, operating DVDD supply current, operating Io = 1 mA, PVDD = 18 V-30.5 V Io = 1.2 mA, PVDD = 18 V-30.5 V fS = 384 kHz, no load, 50% duty cycle fS = 384 kHz, no load
OUTPUT STAGE MOSFETs Ron,LS Ron,HS Forward on-resistance, LS Forward on-resistance, HS TJ = 25C TJ = 25C 110 110 132 132 m m Max Max 5
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ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD = 3.3 V, DVDD connected to DREG via a 100- resistor, RL = 4 , 8X fs = 384 kHz, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25C TA=25C OVER TEMPERATURE TCase= 75C TA=40C TO 85C UNITS MIN/TYP/ MAX
INPUT/OUTPUT PROTECTION Set the DUT in normal operation mode with all the protections enabled. Sweep GVDD up and down Monitor down. SD output. Record the GREG reading when SD is triggered. 6.9 7.4 74 7.9 125 150 See Note 1. 8 V C C A Max Typ Typ Typ V Min
Vuvp,G
Undervoltage protection rotection limit, GVDD
OTW OTE OC
Overtemperature warning Overtemperature error Overcurrent protection PWM_AP, PWM_BP, M1, M2, M3, SD, OTW
STATIC DIGITAL SPECIFICATION
2 VIH VIL Leakage High-level i Hi h l l input voltage t lt Low-level input voltage Input leakage current DVDD 0.8 -10 10 OTW/SHUTDOWN (SD) Internally pull up R from OTW/SD to DVDD 28 22
V V V A A
Min Max Max Min Max
k
Min
VOL Low level output voltage IO = 4 mA 0.4 V Max (1) To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See DemodulationFilter Design in the ApplicationInformation section of the data sheet and consider the recommended inductors and capacitors for optimalperformance. It is also important to consider PCB design and layout for optimum performance of the TAS5111. It is recommended to review the TAS5026-5111KEVM (S/N 001) design and layout documents as an example.
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SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
Gate-Drive Power Supply External Power Supply H-Bridge Power Supply 1000 F TAS5111DAD PWM_AP_1 PWM_AM_1 VALID_1 4 DREG_RTN 100 nF 100 nF PWM PROCESSOR TAS5026 5 GREG 6 M3 7 DREG 8 DGND 9 M1 100 10 11 12 100 nF 13 ERR_RCVY 14 15 GND 16 PWM_AP GND 17 GVDD 100 nF M2 DVDD SD DGND OTW GND 23 OUT_A 22 OUT_A 21 PVDD_A PVDD_A BST_A 20 19 18 1.5 33 nF 1.5 100 nF LPCB 10 k 10 H 100 nF 4.7 k GND 24 OUT_B 25 OUT_B 26 10 k 10 H 470 nF 100 nF 4.7 k PVDD_B PVDD_B 28 27 1 PWM_BP 2 GND 3 RESET BST_B 29 33 nF GND GVDD 31 30 1.5 100 nF 1.5 LPCB 100 nF 32
LPCB : TRACK IN THE PCB (1.0 mm wide and 50 mm long)
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
1 THD+N - Total Harmonic Distortion + Noise - % RL = 4 TC = 75C 0 -20 -40 0.1 PO = 1 W PO = 10 W PO = 70 W Noise Amplitude - dBr -60 -80 -100 -120 -140 0.001 20 -160 100 1k f - Frequency - Hz 10k 20k 0 2 4 6
NOISE AMPLITUDE vs FREQUENCY
FFT = -60 dB TC = 75C TAS5026 Front End Device
0.01
8
10
12
14
16
18
20
22
f - Frequency - kHz
Figure 1
Figure 2
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
1 THD+N - Total Harmonic Distortion + Noise - % RL = 4 TC = 75C 90 TA = 75C 80 70 PO - Output Power - W 60
OUTPUT POWER vs H-BRIDGE VOLTAGE
RL = 4 50 40 30 20 10 RL = 6 RL = 8
0.1
0.01 100m
0 1 10 100 0 4 8 12 16 20 24 28 32 PO - Output Power - W VDD - Supply Voltage - V
Figure 3
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Figure 4
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TAS5111
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SYSTEM OUTPUT STAGE EFFICIENCY vs OUTPUT POWER
100 - System Output Stage Efficiency - % 90 12 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 PO - Output Power - W f = 1 kHz RL = 4 TC = 75C Ptot - Power Loss - W 10 8 6 4 2 0 0 10 20 14 f = 1 kHz RL = 4 TC = 75C
POWER LOSS vs OUTPUT POWER
30
40
50
60
70
80
PO - Output Power - W
Figure 5
Figure 6
OUTPUT POWER vs CASE TEMPERATURE
90 PVDD = 29.5 V RL = 4 85 ron - On-State Resistance - m PO - Output Power - W 200 190 180 170 160 150 140 130 120 110 60 0 20 40 60 80 100 120 140 TC - Case Temperature - C 100 0
ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
80
75
70
65
25
50
75
100
125
TJ - Junction Temperature - C
Figure 7
Figure 8
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THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages, GVDD and PVDD_X. GVDD is the gate drive supply for the device, regulated internally down to approximately 12 V, and decoupled with regards to board GND on the GREG pins through an external capacitor. GREG powers both the low side and high side via a bootstrap step-up conversion. The bootstrap supply is charged after the first low-side turnon pulse. Internal digital core voltage DREG is also derived from GVDD and regulated down by internal LDRs to 3.3 V. The gate-driver LDR can be bypassed for reducing idle loss in the device by shorting GREG to GVDD and directly feeding in 12.0 V. This can be useful in an application where thermal conduction of heat from the device is difficult. Bypassing the LDR reduces dissipation by approximately 1 W at 30 V GVDD input. PVDD_X is the H-bridge power supply pin. Two power pins exists for each half-bridge to handle the current density. It is very important that the circuitry recommendations around the PVDD_X pins are followed very carefully both topologyand layout-wise. For topology recommendations, see the Typical System Configuration section. For layout recommendations, see the reference design layout for the TAS5111. Following these recommendations is important for parameters like EMI, reliability, and performance.
use of non-TI TDAA modulators it is recommended to use a 4-k pulldown resistor on each PWM output node to ground. This precharges the bootstrap supply capacitors and discharges the output filter capacitor (see the Typical TAS5111 Application Configuration section). After GVDD has been applied, it takes approximately 800 s to fully charge the BST capacitor. Within this time, RESET must be kept low. After approximately 1 ms, the back-end bootstrap capacitor is charged. RESET can now be released if the modulator is powered up and streaming valid PWM signals to the back-end PWM_xP. Valid means a switching PWM signal which complies with the frequency and duty cycle ranges stated in the Recommended Operating Conditions. A constant HIGH dc level on the PWM_xP is not permitted, because it would force the high-side MOSFET ON until it eventually ran out of BST capacitor energy and might damage the device. An unknown state of the PWM output signals from the modulator is illegal and should be avoided, which in practice means that the PWM processor must be powered up and initialized before RESET is de-asserted HIGH to the back end.
POWERING DOWN
For power down of the back end, an opposite approach is necessary. The RESET must be asserted LOW before the valid PWM signal is removed. When TI TDAA modulators are used in conjunction with TI TDAA back ends, the correct timing control of RESET and PWM_xP is performed by the modulator.
POWERING UP
> 1 ms > 1 ms
PRECAUTION
The TAS5111 must always start up in the high-impedance (Hi-Z) state. In this state, the bootstrap (BST) capacitor is precharged by a resistor on each PWM output node to ground. See the system configuration. This ensures that the back end is ready for receiving PWM pulses, indicating either HIGH- or LOW-side turnon after RESET is deasserted to the back end. With the following pulldown and BST capacitor size the charge time is:
RESET
GVDD
PVDD_X
PWM_xP
C = 33 nF, R = 4.7 k R x C x 5 = 775.5 s
After GVDD has been applied, it takes approximately 800 s to fully charge the BST capacitor. During this time, RESET must be kept low. After approximately 1 ms the back end BST is charged and are ready. RESET can now be released if the PWM modulator is ready and is streaming valid PWM signals to the back end. Valid PWM signals are switching PWM signals with a frequency
During power up when RESET is asserted LOW, all MOSFETs are turned off and the two internal half-bridges are in the high-impedance state (Hi-Z). The bootstrap capacitors supplying high-side gate drive are at this point not charged. To comply with the click and pop scheme and
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between 350-400 kHz. A constant HIGH level on the PWM+ would force the high side MOSFET ON until it eventually ran out of BST capacitor energy. Putting the device in this condition should be avoided. In practice this means that the DVDD-to-PWM processor (front-end) should be stable and initialization should be completed before RESET is deasserted to the back end. An opposite approach is necessary when powering the system down. RESET must be asserted LOW before the valid PWM signal is removed.
Chip Protection
The TAS5111 protection function is implemented in a closed loop with, for example, a system controller or other TI PWM processor (front-end) device. The TAS5111 contains three individual systems protecting the device against misuse. All of the error events covered result in the output stage being set in a high-impedance state (Hi-Z) for maximum protection of the device and connected equipment. The device can be recovered by toggling RESET low and then high, after all errors are cleared.
Overcurrent (OC) Protection
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller or other front-end device. The pin is open-drain with an internal pullup to DVDD. The logic output is, as shown in the following table, a combination of the device state and RESET input:
SD 0 0 1(1) 1 RESET 0 1 0 1 Not used Device in protection mode, i.e., UVP and/or OC and/or OT error Device set high-impedance (Hi-Z), SD forced high DESCRIPTION
The device has individual forward current protection on both high-side and low-side power stage FETs. The OC protection works only with the demodulation filter present at the output. See Filter Demodulation Design in the Application Information section of the data sheet for design constraints.
Overtemperature (OT) Protection
A dual temperature protection system asserts a warning signal when the device junction temperature exceeds 125C. The OT protection circuit is shared by all half-bridges.
Undervoltage (UV) Protection
Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system protects the device under power-up and power-down situations. The UV protection circuits are shared by all half-bridges.
Normal operation (1) SD is pulled high when RESET is asserted low independent of chip state (i.e., protection mode). This is desirable to maintain compatibility with some TI PWM front ends.
Reset Function
The function of the reset input is twofold:
Temperature Warning Pin: OTW
The OTW pin gives a temperature warning signal when temperature exceeds the set limit. The pin is of the open-drain type with an internal pullup to DVDD.
OTW 0 1 DESCRIPTION Junction temperature higher than 125C Junction temperature lower than 125C
D D
Reset is used for re-enabling operation after a latching error event (PMODE1). Reset is used for disabling output stage switching (mute function) (all PMODEs).
Overall Reporting
The SD pin, together with the OTW pin, gives chip state information as described in Table 1.
In PMODEs where the reset input functions as the means to re-enable operation after an error event, the error latch is cleared on the falling edge of reset and normal operation is resumed when reset goes high.
PROTECTION MODE
Latching Shutdown on All Errors (PMODE1)
In latching shutdown mode, all error situations result in a permanent shutdown (output stage Hi-Z). Re-enabling can be done by toggling the RESET pin.
Table 1. Error Signal Decoding
OTW 0 0 1 1 SD 0 1 0 1 DESCRIPTION Overtemperature error (OTE) Overtemperature warning (OTW) Overcurrent (OC) or undervoltage (UVP) error Normal operation, no errors/warnings
MODE Pins Selection
The protection mode is selected by shorting M1/M2 to DREG or DGND according to Table 2.
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Table 2. Protection Mode Selection
M1 0 0 1 1 M2 0 1 0 1 Reserved Latching shutdown on all errors (PMODE1) Reserved Reserved 10 9 L - Inductance - H DASL983XX-1023 8 7 6 5 4 0 5 10 I - Current - A 15 11 13mm DB PROTECTION MODE
INDUCTANCE vs CURRENT
The output configuration mode is selected by shorting the M3 pin to DREG or DGND according to Table 3.
Table 3. Output Mode Selection
M3 0 1 Reserved OUTPUT MODE Bridge-tied load output stage (BTL)
NOTE: When any of the RESET, MUTE, or ERROR_RECOVER pins is asserted, the speaker outputs are set to high impedance (Hi-Z).
APPLICATION INFORMATION
DEMODULATION FILTER DESIGN
Design of the demodulation filter affects the performance of the power amplifier significantly. As a result, to ensure proper operation of the overcurrent (OC) protection circuit and meet the device THD+N specifications, the selection of the inductors used in the output filter must be considered according to the following. The rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver at least 5 H of inductance at 15 A. If this rule is observed, the TAS5111 will not have distortion issues due to the output inductors and overcurrent conditions will not occur due to inductor saturation in the output filter. Another parameter to be considered is the idle current loss in the inductor. This can be measured or specified as inductor dissipation (D). The target specification for dissipation is less than 0.05. In general, 10-H inductors suffice for most applications. The frequency response of the amplifier is slightly altered by the change in output load resistance; however, unless very tight control of frequency response is necessary (better than 0.5 dB), it is not necessary to deviate from 10 H. The graphs in Figure 9 and NO TAG display the inductance vs current characteristics of two inductors that are recommended for use with the TAS5111.
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Figure 9. Inductance Saturation
The selection of the capacitor that is placed across the output of each inductor (Cload in Figure 12) is very simple. To complete the output filter, use a 0.47-F capacitor with a voltage rating at least twice the voltage applied to the output stage (PVDD). This capacitor should be a good quality polyester dielectric such as a Wima MKS2-047ufd/100/10 or equivalent. In order to minimize the EMI effect of unbalanced ripple loss in the inductors, 0.1-F 50-V SMD capacitors (X7R or better) should be added from the output of each inductor to ground.
GENERAL PRINCIPLES OF DEMODULATION FILTER DESIGN
The TDAA amplifier outputs are driven by heavy-duty DMOS transistors in an H-bridge configuration. These transistors are either off or fully on, which reduces the DMOS transistor on-state resistance, R(DMOSon), and the power dissipated in the device, thereby increasing efficiency. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal. For this application, EMI is considered important; therefore, the selected filter is the full-output type shown in Figure 10.
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TAS51xx Output A L R(Load)
The two half-circuit models are now combined to yield the actual bridge-tied load (BTL) circuit shown in Figure 12 and the capacitors and resistors are combined to provide the final BTL equations.
L(Half) L
C1A C2 C1B Output B L
C(Half)
R(Half) C(Load) R(Load)
C(Half) L(Half)
R(Half) L
Figure 10. Demodulation Filter
The main purpose of the output filter is to attenuate the high-frequency switching component of the TDAA amplifier while preserving the signals in the audio band. The first step in designing the filter is to construct the circuit and derive the transfer function, starting first with a half-circuit model and moving later to the full-bridge circuit. The half-circuit model of the Butterworth low-pass filter output is shown in Figure 11, with only one-half of the desired dc load resistance, R(load), of the speaker shown. The input signal, V(in), is the 352.8-kHz square-wave output of the TDAA amplifier, while the output, VO, is the voltage developed across the speaker.
L TDAA Output + V(in) - C(Half) + VO - R(Half)
Figure 12. Combination of the Two Half-Circuit Models
R(load) = 2R(half)
C
(load)
+
1 2 2 pR + f (load) co
2R L+L (half)
(load) 4pf co
The inductance value is the same for the half- and full-bridge circuits because there are two inductances in the BTL circuit. Based on these BTL component values, the -3-dB cutoff frequency for the LC filter is:
f co +
1 2p 2 L C
(load)
where the 2 in the denominator is the result of transposing the inductance and capacitance values from the half-circuit to the BTL full-circuit model. The capacitors labeled C1A and C1B in Figure 10 serve as high-frequency bypass capacitors acting as a commonmode filter and are empirically chosen to be approximately 10% of 2 x CL.
Figure 11. Butterworth Low-Pass Filter Half-Circuit Model
The transfer function for this half circuit is:
L H(s) + s2 ) R
1 C (half) (half)
THERMAL INFORMATION
The thermally augmented packages provided with the TAS5111 are designed to be interfaced directly to heat sinks using a thermal interface compound (for example, Wakefield Engineering type 126 thermal grease.) The heat sink then absorbs heat from the ICs and couples it to the local air. If the heatsink is carefully designed, this process can reach equilibrium and heat can be continually removed from the ICs. Because of the efficiency of the TAS5111, heat sinks will be smaller than those required for linear amplifiers of equivalent performance. RJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with roughly the following components:
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1 1 s) C L C (half) (half) (half) (half)
The component values are:
C
(half)
+
1 2 2 pf coR (half)
and
R L (half) +
(half)
2 pf co
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D D D
RJC (the thermal resistance from junction to case, or in this case the metal pad) Thermal grease thermal resistance Heat sink thermal resistance
36-Pin PSOP3 Ambient temperature Power to load Delta T inside package Delta T through thermal grease Required heat sink thermal resistance Junction temperature System RJA RJA * power dissipation 25C 70 W 5.5C 3.2C 11.0C/W 110C 12.3C/W 85C
32-Pin TSSOP 25C 70 W 12.3C 21.1C 8.2C/W 110C 13.2C/W 85C
RJC has been provided in the General Information section. The thermal grease thermal resistance can be calculated from the exposed pad area and the thermal grease manufacturer's area thermal resistance (expressed in C-in2/W). The area thermal resistance of the example thermal grease with a 0.001 inch thick layer is about 0.054 C-in2/W. The approximate exposed pad sizes are as follows: 36-pin PSOP3 32-pin TSSOP 0.116 in2 0.0164 in2
As an indication of the importance of keeping the thermal grease layer thin, if the thermal grease layer increases to 0.002 inches thick, the required heat sink thermal resistance changes to 5.2C/W for the PSOP3 package and to 2.4C/W for the TSSOP package.
Dividing the example thermal grease area resistance by the area of the pad gives the actual resistance through the thermal grease for both parts: 36-pin PSOP3 32-pin TSSOP 0.47 C/W 3.3 C/W
Thermal Pad 3,91 mm 3,31 mm
Note that both RJC and the thermal grease resistance are better for the PSOP3 package. The PSOP3 package should be used when output power is high and/or when the heat sink must be restricted in size. The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer. Pads should only be used with the PSOP3 package. Thermal tape has an even higher thermal resistance and should not be used at all with either of these two packages. Heat sink thermal resistance is generally predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus, for a single monaural IC, the system RJA = RJC + thermal grease resistance + heat sink resistance. The following table indicates modeled parameters for one TAS5111 IC on a heat sink. The junction temperature is set at 110C in both cases while delivering 70 W RMS into 4- loads with no clipping. It is assumed that the thermal grease is about 0.001 inch thick (this is critical).
14 4,11 mm 3,35 mm
CLICK AND POP REDUCTION
Going from non-switching to switching operation causes a spectral energy burst to occur within the audio bandwidth, which is heard in the speaker as an audible click, for instance, after having asserted RESET LH during a system start-up. To make this system work properly, the following design rules must be followed when using the TAS5111 back end:
D
The relative timing between the PWM_AP/M_x signals and their corresponding VALID_x signal
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TAS5111
SLES049A - JULY 2003
should not be skewed by inserting delays, because this increases the audible amplitude level of the click.
REFERENCES
D
The output stage must start switching from a fully discharged output filter capacitor. Because the output stage prior to operation is in the high-impedance state, this is done by having a passive pulldown resistor on each speaker output to GND (see Typical System Configuration).
1.
TAS5000 Digital Audio PWM Processor data manual - TI (SLAS270) True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet - TI (SLES009) True Digital Audio Amplifier TAS5010 Digital Audio PWM Processor data sheet - TI (SLAS328) True Digital Audio Amplifier TAS5012 Digital Audio PWM Processor data sheet - TI (SLES006) TAS5026 Six-Channel Digital Audio Processor data manual - TI (SLES041) TAS5036A Six-Channel Digital Audio Processor data manual - TI (SLES061) PWM
2.
Other things that can affect the audible click level:
3.
D
The spectrum of the click seems to follow the speaker impedance vs. frequency curve--the higher the impedance, the higher the click energy. Crossover filters used between woofer and tweeter in a speaker can have high impedance in the audio band, which should be avoided if possible.
4.
D
5.
Another way to look at it is that the speaker impulse response is a major contributor to how the click energy is shaped in the audio band and how audible the click will be. The following mode transitions feature click and pop reduction.
STATE Normal(1) Mute Normal(1) Error recovery Normal(1) Mute Normal(1) Error recovery (ERRCVY) Normal(1) Hard Reset Normal(1) CLICK AND POP REDUCED Yes Yes Yes Yes No Yes
6.
PWM
7.
TAS3103 Digital Audio Processor With 3D Effects data manual - TI - TI (SLES038) Digital Audio Measurements application report- TI (SLAA114) PowerPAD Thermally Enhanced technical brief - TI (SLMA002) Package
8.
9.
Hard Reset (1) Normal = switching
10. System Design Considerations for True Digital Audio Power Amplifiers application report - TI (SLAA117)
15
TAS5111
SLES049A - JULY 2003
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DAD (R-PDSO-G**)
38 PINS SHOWN 0,30 0,19 20
PowerPAD PLASTIC SMALL-OUTLINE (DIE DOWN)
0,65 38
0,13 M
Thermal Pad (See Note D)
6,20 NOM
8,40 7,80 0,15 NOM
Gage Plane 1 A 19 0- 8 0,75 0,50 0,25
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX A MIN
30 11,10 10,90
32 11,10 10,90
38 12,60 12,40 4073258/B 09/02
NOTES:A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusion. The package thermal performance may be enhanced by attaching an external heatsink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments. 16
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TAS5111
SLES049A - JULY 2003
DKD (R-PDSO-G36)
PLASTIC SMALL-OUTLINE
0,65 36
0,38 0,25
0,12 19 Thermal Pad (See Note D)
11,10 10,90
14,50 13,90 0,28 NOM
Gage Plane 1 16,00 15,80 0-8 1,10 0,80 18 0,30 0,10
Seating Plane 3,50 MAX 0,15 0,05 0,10
4204421/A 08/02 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-166 F. Falls within JEDEC MO-153
17
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