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512 Kbit / 1 Mbit / 2 Mbit (x8) Multi-Purpose Flash
SST39SF512 / SST39SF010 / SST39SF020
Data Sheet
FEATURES: * Organized as 64K x8 / 128K x8 / 256K x8 * Single 5.0V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 20 mA (typical) - Standby Current: 10 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Fast Read Access Time: - 70 and 90 ns * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time: 7 ms (typical) - Chip-Erase Time: 15 ms (typical) - Byte-Program Time: 20 s (typical) - Chip Rewrite Time: 2 seconds (typical) for SST39SF512 3 seconds (typical) for SST39SF010 5 seconds (typical) for SST39SF020 * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * TTL I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-Pin PDIP - 32-Pin PLCC - 32-Pin TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST39SF512/010/020 are CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The splitgate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF512/010/020 devices write (Program or Erase) with a 5.0V-only power supply. The SST39SF512/010/020 device conforms to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39SF512/010/020 devices provide a maximum ByteProgram time of 30 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39SF512/010/020 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39SF512/010/020 are offered in 32-pin TSOP and 32pin PLCC packages. A 600 mil, 32-pin PDIP is also available. See Figures 1, 2 and 3 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc. These specifications are subject to change without notice. 1
512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
Read The Read operation of the SST39SF512/010/020 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Byte-Program Operation The SST39SF512/010/020 are programmed on a byte-bybyte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 30 s. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse , while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The end of Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Chip-Erase Operation The SST39SF512/010/020 provide Chip-Erase operation, which allows the user to erase the entire memory array to the "1's" state. This is useful when the entire device must be quickly erased.
(c) 2000 Silicon Storage Technology, Inc.
The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored. Write Operation Status Detection The SST39SF512/010/020 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the program or erase cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39SF512/010/020 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program Operation. For sector or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e., toggling between 0 and 1. The Toggle Bit will begin with "1". When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising 2
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edge of fourth WE# (or CE#) pulse for Program operation. For Sector or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. Data Protection The SST39SF512/010/020 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39SF512/010/020 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF512 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The product identification mode identifies the device as the SST39SF512, SST39SF010 and SST39SF020 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST39SF512/010/020. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION TABLE Address Manufacturer's Code Device Code SST39SF512 SST39SF010 SST39SF020 0001H 0001H 0001H B4 H B5 H B6 H
394 PGM T1.0
1 2 3 4 5
Data BF H
0000H
6 7 8 9 10 11 12
Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM
EEPROM Cell Array
13 14
X-Decoder
Memory Address
Address Buffers & Latches Y-Decoder CE# OE# WE# DQ7 - DQ0
394 ILL B1.0
15 16
Control Logic
I/O Buffers and Data Latches
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SST39SF020 SST39SF010 SST39SF512 A11 A9 A8 A13 A14 A17 WE# VCC NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VCC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SST39SF512 SST39SF010 SST39SF020 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
394 ILL F01.1
Standard Pinout Top View Die Up
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP (8mm x 14mm)
SST39SF020 SST39SF010 SST39SF512
SST39SF512 SST39SF010 SST39SF020
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
394 ILL F02a.1
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PDIP
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SST39SF512 SST39SF010 SST39SF020
WE#
VCC
A12
A15
A16
A17
NC
1 2
WE#
VCC
A12
A15
A16
NC
NC
WE#
VCC
A12
A15
NC
NC
SST39SF020 SST39SF010 SST39SF512
NC
3
SST39SF512 SST39SF010 SST39SF020
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
SST39SF020 SST39SF010 SST39SF512
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
4 5 6 7
32-Pin PLCC Top View
21 14 15 16 17 18 19 20
DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
394 ILL F02b.2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
VSS
8 9 10 11 12 13 14 15 16
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PLCC
(c) 2000 Silicon Storage Technology, Inc.
DQ6
5
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
TABLE 2: PIN DESCRIPTION Symbol Pin Name AMS-A0 Address Inputs lines DQ7-DQ0 Data Input/output
CE# OE# WE# Vcc Vss NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Functions To provide memory addresses. During Sector-Erase AMS-A12 address will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide 5-volt supply ( 10%) Unconnected pins.
394 PGM T2.1
Note: AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
TABLE 3: OPERATION MODES SELECTION Mode CE# Read V IL Program VIL Erase VIL Standby Write Inhibit Product Identification Hardware Mode Software Mode VIH X X VIL VIL
OE# VIL VIH VIH X VIL X VIL VIL
WE# VIH VIL VIL X X VIH VIH VIH
A9 AIN AIN X X X X VH AIN
DQ DOUT DIN X High Z High Z/DOUT High Z/DOUT Manufacturer Code (BF) Device Code (1) ID Code
Address AIN AIN Sector address, XXh for Chip-Erase X X X AMS(2) - A1 = VIL, A0 = VIL AMS(2) - A1 = VIL, A0 = VIH See Table 4
394 PGM T3.0
Note: (1) Device Code = B4 for SST39SF512, B5 for SST39SF010 and B6 for SST39SF020 (2) AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence 1st Bus Write Cycle Addr(1) Data Byte-Program 5555H AAH Sector-Erase 5555H AAH Chip-Erase 5555H AAH Software ID Entry 5555H AAH Software ID Exit XXH F0H Software ID Exit 5555H AAH
Notes:
(1)
2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H
3rd Bus Write Cycle Addr(1) Data 5555H A0H 5555H 80H 5555H 80H 5555H 90H 5555H F0H
4th Bus Write Cycle Addr(1) Data BA(3) Data 5555H AAH 5555H AAH
5th Bus Write Cycle Addr(1) Data 2AAAH 2AAAH 55H 55H
6th Bus Write Cycle Addr(1) Data SAx(2) 30H 5555H 10H
1 2 3
394 PGM T4.0
(2)
(3) (4) (5)
(6)
Address format A14-A0 (Hex), Address A15 is a "Don't Care" for the Command sequence for SST39SF512. Address A16 and A15 are "Don't Care" for the Command sequence for SST39SF010. Address A15, A16 and A17 are "Don't Care" for the Command sequence for SST39SF020. SAx for Sector-Erase; uses AMS-A12 address lines AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020 BA = Program Byte address Both Software ID Exit operations are equivalent With AMS -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, SST39SF512 Device Code = B4 H, is read with A0 = 1. SST39SF010 Device Code = B5 H, is read with A0 = 1. SST39SF020 Device Code = B6 H, is read with A0 = 1. The device does not remain in Software Product ID Mode if powered down.
4 5 6 7 8
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ............................................................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
9 10 11 12 13 14 15 16
OPERATING RANGE Range Ambient Temp Commercial 0 C to +70 C Industrial -40 C to +85 C
AC CONDITIONS OF TEST VCC 5V10% 5V10% Input Rise/Fall Time ......... 10 ns Output Load ..................... CL = 100 pF for 90 ns Output Load ..................... CL = 30 pF for 70 ns See Figures 13 and 14
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
TABLE 5: DC OPERATING CHARACTERISTICS VCC = 5V10% Limits Symbol Parameter Min Max ICC Power Supply Current Read Write Standby VCC Current (TTL input) Standby VCC Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 pin Supervoltage Current for A9 pin 30 50 3 50 1 1 0.8 2.0 0.4 2.4 11.4 12.6 200
Units mA mA mA A A A V V V V V A
Test Conditions CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC Min., VCC=VCC Max CE#=WE#=VIL, OE#=VIH, VCC =VCC Max. CE#=VIH, VCC =VCC Max. CE#=VCC -0.3V. VCC = VCC Max. VIN =GND to VCC, VCC = VCC Max. VOUT =GND to VCC, VCC = VCC Max. VCC = VCC Min. VCC = VCC Max. IOL = 2.1 mA, VCC = VCC Min. IOH = -400A, VCC = VCC Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max.
394 PGM T5.0
ISB1 I SB2 ILI ILO VIL VIH VOL VOH VH IH
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ(1) TPU-WRITE(1) Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
394 PGM T6.0
TABLE 7: CAPACITANCE (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition CI/O CIN(1)
(1)
Maximum 12 pF 6 pF
394 PGM T7.0
I/O Pin Capacitance Input Capacitance
VI/O = 0V VIN = 0V
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND(1) TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1) Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
Minimum Specification 10,000 100 2000 200 100 + ICC
Units Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
394 PGM T8.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 2000 Silicon Storage Technology, Inc.
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AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VCC = 4.5-5.5V SST39SF512/010/020-70 Symbol Parameter Min Max TRC Read Cycle Time 70 TCE Chip Enable Access Time 70 TAA Address Access Time 70 TOE Output Enable Access Time 35 TCLZ(1) CE# Low to Active Output 0 TOLZ(1) OE# Low to Active Output 0 TCHZ(1) CE# High to High-Z Output 15 (1) OE# High to High-Z Output 15 TOHZ (1) TOH Output Hold from Address Change 0
Note: CL = 100 pF for 90 ns, CL = 30 pF for 70 ns
1
SST39SF512/010/020-90 Min Max 90 90 90 45 0 0 20 20 0 Units ns ns ns ns ns ns ns ns ns
394 PGM T9.0
2 3 4 5 6 7
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Byte-Program Time TAS Address Setup Time TAH Address Hold Time TCS WE# and CE# Setup Time TCH WE# and CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP CE# Pulse Width TWP WE# Pulse Width TWPH (1) WE# Pulse Width High TCPH (1) CE# Pulse Width High TDS Data Setup Time TDH (1) Data Hold Time TIDA (1) Software ID Access and Exit Time TSE Sector-Erase TSCE Chip-Erase
Note:
(1)This
Min 0 30 0 0 0 0 40 40 30 30 30 0
Max 30
150 10 20
Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
394 PGM T10.0
8 9 10 11 12 13 14 15 16
parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
TRC ADDRESS AMS-0
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
TOH DATA VALID
Note: AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
394 ILL F03.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
394 ILL F04.0
Note: AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
1 2 3 4 5 6
394 ILL F05.0
Note: AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
7 8 9
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
10 11 12 13
D D# D# D
DQ7
14
394 ILL F06.0
Note: AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
15 16
FIGURE 7: DATA# POLLING TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
Note
TWO READ CYCLES WITH SAME OUTPUTS Note: Toggle bit output is always high first. AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020 394 ILL F07.0
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX
TSE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
394 ILL F08.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
1 2 3
CE#
OE# TWP WE#
4
55 SW1 80 SW2 AA SW3 55 SW4 10 SW5
DQ7-0
AA SW0
5
394 ILL F17.0
6 7 8 9
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A15 for SST39SF512, A16 for SST39SF010 and A17 for SST39SF020
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
10 11
CE#
12
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2
394 ILL F09.1
TIDA
13
TAA BF Device ID
14 15 16
Device ID = B4 for SST39SF512, B5 for SST39SF010 and B6 for SST39SF020
FIGURE 11: SOFTWARE ID ENTRY AND READ
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# T WHP SW0 SW1 SW2
394 ILL F10.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
VIHT VHT
INPUT REFERENCE POINTS
1
VHT
OUTPUT
VLT VILT
VLT
2
394 ILL F11.0
3 4 5 6 7
AC test inputs are driven at VIHT (2.4 V) for a logic "1" and VILT (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% 90%) are <10 ns.
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE VCC TO TESTER RL HIGH
8 9 10
TO DUT CL RL LOW
11 12 13
394 ILL F12.0
14
FIGURE 14: A TEST LOAD EXAMPLE
15 16
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
Start
Load data: AA Address: 5555
Load data: 55 Address: 2AAA
Load data: A0 Address: 5555
Byte Address/Byte Data
Wait for end of Program (TBP' Data# Polling bit or Toggle bit operation) Program Completed
394 ILL F13.0
FIGURE 15: BYTE-PROGRAM ALGORITHM
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
1
Internal Timer Program/Erase Initiated Toggle Bit Byte-Program/ Sector Erase Initiated Data# Polling Byte-Program Initiated
2 3
Wait TBP, TSCE, or TSE
Read byte
Read DQ7
4 5
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
6 7 8 9 10
No
Does DQ6 match? Yes
Write Completed
Write Completed
394 ILL F14.0
11 12
FIGURE 16: WAIT OPTIONS
13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
Software Product ID Entry Command Sequence
Software Product ID Exit & Reset Command Sequence
Load data: AA Address: 5555
Load data: AA Address: 5555
Load data: F0 Address: XX
Load data: 55 Address: 2AAA
Load data: 55 Address: 2AAA
Wait TIDA
Load data: 90 Address: 5555
Load data: F0 Address: 5555
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
394 ILL F15.0
FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
Chip-Erase Command Sequence Load data: AA Address: 5555
Sector-Erase Command Sequence Load data: AA Address: 5555
1 2 3
Load data: 55 Address: 2AAA
Load data: 55 Address: 2AAA
4
Load data: 80 Address: 5555 Load data: 80 Address: 5555
5 6
Load data: AA Address: 5555
Load data: AA Address: 5555
7 8 9
Load data: 55 Address: 2AAA
Load data: 55 Address: 2AAA
Load data: 10 Address: 5555
Load data: 30 Address: SAX
10 11
Wait TSCE
Wait TSE
12
Chip-Erase to FFH Sector-Erase to FFH
13 14
394 ILL F16.0
15
FIGURE 18: ERASE COMMAND SEQUENCE
16
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
Device SST39SFxxx Speed Suffix1 Suffix2 - XXX XX XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (8mm x 14mm) U = Unencapsulated die Temperature Range C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns, 90 = 90 ns Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit SST39SF512 Valid combinations SST39SF512-70-4C-WH SST39SF512-70-4C-NH SST39SF512-90-4C-WH SST39SF512-90-4C-NH SST39SF512-90-4C-U3 SST39SF512-70-4I-WH SST39SF512-70-4I-NH SST39SF512-90-4I-WH SST39SF512-90-4I-NH SST39SF010 Valid combinations SST39SF010-70-4C-WH SST39SF010-70-4C-NH SST39SF010-90-4C-WH SST39SF010-90-4C-NH SST39SF010-90-4C-U4 SST39SF010-70-4I-WH SST39SF010-90-4I-WH SST39SF010-70-4I-NH SST39SF010-90-4I-NH SST39SF020-70-4C-PH SST39SF020-90-4C-PH SST39SF512-70-4C-PH SST39SF512-90-4C-PH
SST39SF010-70-4C-PH SST39SF010-90-4C-PH
SST39SF020 Valid combinations SST39SF020-70-4C-WH SST39SF020-70-4C-NH SST39SF020-90-4C-WH SST39SF020-90-4C-NH SST39SF020-90-4C-U4 SST39SF020-70-4I-WH SST39SF020-90-4I-WH SST39SF020-70-4I-NH SST39SF020-90-4I-NH
Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
PACKAGING DIAGRAMS
pin 1 index 1
1 2
C L
3
32
.600 .625 .530 .550 .065 .075 1.645 1.655 7 4 PLCS.
4 5
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600 BSC
0 15
6 7
.070 .080
.045 .065
.016 .022
.100 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.1
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
8 9
TOP VIEW
SIDE VIEW
BOTTOM VIEW
10
Optional Pin #1 Identifier .485 .495 .447 .453 .042 .048
2 1 32
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
11 12
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC .490 .530
13 14
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
15
32.PLCC.NH-ILL.1
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
16
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512 / SST39SF010 / SST39SF020
PIN # 1 IDENTIFIER
1.05 0.95 .50 BSC
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm.
32.TSOP-WH-ILL.3
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: WH
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 2000 Silicon Storage Technology, Inc.
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