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SPT5240
10-BIT, 400 MHz CURRENT OUTPUT D/A CONVERTER PRELIMINARY INFORMATION
DECEMBER 15, 2001
FEATURES
400 MWPS update rate Differential current output +3.3 V power supply Ultralow power dissipation: 140 mW (typ) @CLK = 400 MHz * Power-down mode draws less than 5 nA from AVDD and 200 A from DVDD with no clock or data * Excellent AC performance: SFDR = -57 dBc for CLK = 400 MHz and OUT = 1.27 MHz * Internal reference * * * *
APPLICATIONS
* * * * * * Battery-operated devices Portable RF devices Set top boxes Video displays Broadband RF High-speed test equipment
GENERAL DESCRIPTION
The SPT5240 is a 10-bit digital-to-analog converter that performs at an update rate of 400 M words per second. The part is implemented in a 0.25 m CMOS process. The architecture achieves excellent high-frequency performance with very low power dissipation. This makes it ideal
for all types of battery-operated equipment requiring highspeed digital-to-analog conversion. The SPT5240 operates over an extended industrial temperature range from -40 C to +85 C and is available in a 32-lead TQFP package.
BLOCK DIAGRAM
PWD
DVDD
AVDD
ISET VRNL
Reference Circuit
D0D9
10 Bits
10-Bit Current Output DAC
IOP ION
CLK
DGND
AGND
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 C
Supply Voltages AVDD ........................................................................ 3.7 V DVDD ........................................................................ 3.7 V A/D ground voltage differential ................................. 0.5 V Input Voltages DIN ................................................. -0.5 V to DVDD +0.5 V Clock ............................................. -0.5 V to DVDD +0.5 V Output Currents Bandgap reference output current (VRNL) ................. 1 A
Note: This is a No Load reference. Any load applied will cause a degradation at the output.
Temperature Operating temperature ............................... -40 to +85 C Junction temperature ............................................ 150 C Lead, soldering (10 seconds) ............................... 250 C Storage .................................................... -65 to +150 C
Note:
Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = 25 C, AVDD = DVDD = 3.3 V, OUT = 1.27 MHz, CLK = 400 MHz, Clock Duty Cycle = 50%, IOUT = 20 mA, RL = 50 , unless otherwise specified.
PARAMETERS DC Performance Resolution Differential Linearity Error (DLE) Integral Linearity Error (ILE) Max Offset Error Full-Scale Error Gain Error Maximum Full-Scale Output Current Output Compliance Voltage Minimum Output Impedance Gain Error Tempco
TEST CONDITIONS
TEST LEVEL
MIN
SPT5240 TYP 10 0.9 1.34 20 5 5 40 +1.25 250 100 400 2.23 104 1.22 1.36 802 656 57 -54 +2.1 +1.3 10 10 590 410 1 clk+4ns -29 +1.17
MAX
UNITS Bits LSB LSB nA % FS % FS mA V k ppm FS/C MWPS pV-s ns ns ns V/s V/s dBc dBc V V A A ps ps ns dBFS V
CLK=1 MHz CLK=1 MHz
V V V V V V V V V V V V V V V V V V V V V V V V V V V
AC Performance Maximum Output Update Rate Glitch Energy See figure 1 Settling Time (tsettling) Output Rise Time Output Fall Time Output Slew Rate Rising Edge Output Slew Rate Falling Edge Spurious Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Digital Data Input VIH Minimum VIL Maximum Logic "1" Current Logic "0" Current Input Setup Time (tS) Input Hold Time (tH) Output Delay Time (tD) Clock Feedthrough Reference Reference Voltage
See figure 1 See figure 1 See figure 1
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ELECTRICAL SPECIFICATIONS
TA = 25 C, AVDD = DVDD = 3.3 V, OUT = 1.27 MHz, CLK = 400 MHz, Clock Duty Cycle = 50%, IOUT = 20 mA, RL = 50 , unless otherwise specified.
PARAMETERS Power Supply Requirements Digital Supply Voltage Analog Supply Voltage Supply Current Sleep Mode AVDD DVDD AVDD DVDD PWD Pin Current Power Supply Rejection Ratio Power Dissipation Clock Input VIH Minimum VIL Maximum Input Current
TEST CONDITIONS
TEST LEVEL V V
MIN
SPT5240 TYP +3.3 +3.3 410 1 4 193 83 50 196 140 +1.5 +1.2 10
MAX
UNITS V V nA mA nA A A dB mW mW V V A
50 MHz Clock 50 MHz Clock Clock/Data Off Clock/Data Off Clock/Data Off 20 mA IOUT 12 mA IOUT
V V V V V V V V V V V
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
TYPICAL PERFORMANCE CHARACTERISTICS
THD and SFDR vs Input Frequency
60 58 56 54 52
SNR and SINAD vs Input Frequency
60 58 56 54 52
SFDR THD dBc
SNR
dBc
50 48 46 44 42 40 0 OUT = 1.27 MHz
50 48 46 44 42 OUT = 1.27 MHz
SINAD
100
Clock (MHz)
200
300
400
40
0
100
Clock (MHz)
200
300
400
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SPECIFICATION DEFINITIONS
DIFFERENTIAL LINEARITY ERROR (DLE) OR DIFFERENTIAL NONLINEARITY (DNL) In an ideal DAC, output transitions are 1 LSB apart. Differential Linearity Error is the maximum deviation, expressed in LSBs, from this ideal value. INTEGRAL LINEARITY ERROR (ILE) OR INTEGRAL NONLINEARITY (INL) The ideal transfer for a DAC is a straight line drawn between "zero-scale" output and "full-scale" output. ILE is the worst-case deviation of the output from the straight line. The deviation of the output at each code is measured and compared to the ideal output at that code. ILE may also be expressed as a sum of DLE starting from code 0...0 to the code that ILE measurement is desired. MONOTONIC A digital-to-analog converter is considered monotonic if the analog output never decreases as the code value at the input increases. A DLE of -1 would indicate a nonmonotonic DAC. OFFSET ERROR The deviation, from ideal, at the DAC output when set to zero-scale. In the current output DAC there should be no current flow at zero-scale. Therefore, Offset Error is the amount of current measured with the DAC set to zeroscale. FULL-SCALE ERROR The ideal maximum full-scale current output of the DAC is determined by the value of RSET. Full-scale error is the deviation of the output from ideal with the offset error included. GAIN ERROR The ideal maximum full-scale current output of the DAC is determined by the value of RSET. Gain error is the deviation of the output from ideal with the offset error removed. FULL-SCALE OUTPUT The maximum current output available for a given value of RSET. In the SPT5240 IOP is full-scale at code 1111111111 and ION is full-scale at code 0000000000. ZERO-SCALE OUTPUT The minimum current output, ideally zero amps. In the SPT5240 IOP is zero-scale at code 0000000000 and ION is zero-scale at code 1111111111. COMPLIANCE VOLTAGE The maximum terminal output voltage for which the device will provide the specified current output characteristics. HARMONIC 1. Of a sinusoidal wave, an integral multiple of the frequency of the wave. Note: The frequency of the sine wave is called the fundamental frequency or the first harmonic, the second harmonic is twice the fundamental frequency, the third harmonic is thrice the fundamental frequency, etc. 2. Of a periodic signal or other periodic phenomenon, such as an electromagnetic wave or a sound wave, a component frequency of the signal that is an integral multiple of the fundamental frequency. Note: The fundamental frequency is the reciprocal of the period of the periodic phenomenon. TOTAL HARMONIC DISTORTION (THD) The ratio of the sum of the power of first 9 harmonics above the fundamental frequency to the power of the fundamental frequency. Usually expressed in dBc. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal power to the power of the single largest harmonic or spurious signal within the range of the 9th harmonic. CLOCK FEEDTHROUGH The ratio of the full-scale output to the peak-to-peak noise generated at the DAC output by input clock transitions. Expressed in dBFS.
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Figure 1 - Timing Diagram
N CLK tS Digital Inputs VOP N-2 VON N-1 N tH
N+1
N+1 tD
N+2
N+3
1 LSB
N
N+1
1 LSB
tsettling
THEORY OF OPERATION
The SPT5240 is a 10-bit 400 MWPS digital-to-analog converter implemented in 0.25 m CMOS technology. It integrates a DAC core with a bandgap reference and operates from a +3.3-volt power supply. The DAC architecture is a compound differential current output DAC consisting of a 6-bit fully segmented DAC for the MSBs and a 4-bit fully segmented DAC for the LSBs. The input cell, followed by a master-slave latch, buffers the digital inputs. A 6:64 decoder decodes the digital data for
the MSBs, and a 4:16 decoder does so for the LSBs. The outputs of the decoders are latched using a second bank of master-slave latches whose outputs then drive differential current switches, which steer the appropriate current to the IOP or ION outputs. The analog (AVDD) and digital (DVDD) power supplies are separated on chip to allow flexibility in the interface board. The analog (AGND) and digital (DGND) are separated on chip. Circuit board ground planes should be separated and tied together with a ferrite bead.
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Figure 2 - Typical Interface Circuit
IOUT Adjust Reference Voltage Out Sleep Mode Select
Clock In CLK
RSET
ISET
VRNL
PWD IOP VOP
50
10-Bit Data Bus
D0D9 In
SPT5240
DGND AGND AVDD
ION
50
DVDD
VON
Notes: 1. FB = Ferrite bead across analog and digital ground planes. Place as close to DAC as feasible. 2. VRNL is a no-load output. Use for monitoring purposes only. 3. Minimum resistance (RSET) from ISET to ground results in maximum current output. 4. PWD pin has an internal pull-down resistor. Set pin high to initiate sleep mode. 5. Outputs (IOP and ION) require minimum 5 W load.
.01 F .1 F
FB
.01 F .1 F +
10 F + +D3.3 V
10 F
+A3.3 V
TYPICAL INTERFACE CIRCUIT
The SPT5240 requires few external components to achieve the stated performance. Figure 2 shows the typical interface requirements when used in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving optimal performance. DIGITAL INPUTS The SPT5240 has a 10-bit-wide parallel data input designed to work at +3.3 V CMOS levels. Fast edges and low transients provide for improved performance. CLOCK INPUT The SPT5240 is driven by a single-ended clock circuit. In order to achieve best performance at the highest throughput, a clock generation circuit should provide fast edges and low jitter. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit. This circuit provides robust ESD protection in excess
of 3,000 volts, in human body model, without sacrificing speed. POWER SUPPLIES AND GROUNDING The SPT5240 may be operated in the range of 2.8 to 3.6 volts. Normal operation is recommended to be separate analog and digital supplies operating at +3.3 volts. All power supply pins should be bypassed as close to the package as possible with the smallest capacitor closest to the device. Analog and digital ground planes should be connected together with a ferrite bead as shown in figure 2 and as close to the DAC as possible. SLEEP MODE To conserve power, the SPT5240 incorporates a powerdown function. This function is controlled by the signal on pin PWD. When PWD is set high, the SPT5240 enters the sleep mode. The analog outputs are both set to zero current output, resulting in less than 500 nA current draw from the analog supply. For minimum power dissipation, data and clock inputs should be removed.
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REFERENCES The SPT5240 utilizes an on-chip bandgap reference to set full-scale output current level. The current reference to the DAC circuitry is set by the external resistance value between the ISET pin and analog ground. An output of the bandgap reference voltage is available for monitoring purposes only at the VRNL pin. ANALOG OUTPUTS The SPT5240 provides differential current outputs which provide an output level based on the value of RSET at maximum output code (see Figure 3). The required value of RSET may be calculated using the formulas: LSB = IFS / 1023 Then: RSET = 1.1302 - (1000 * LSB) 4 * LSB
Figure 3 - RSET vs IOUT
35 30 25
IOUT (mA)
RSET Steps = 2.75 kW 20 15 10 5 0
60275
54825
49375
43925
38475
33025
27575
22125
16675
11225
RSET Value (Ohms)
Table I - Input Data Format
Input Code D9-D0 0000000000 1111111111 Sleep XXXXXXXXXX
X indicates either data state.
Where IFS is the desired full-scale current output. Each output requires a minimum 5-ohm load to analog ground. The typical circuit utilizes 50-ohm loads to develop voltage for the output transformer.
Analog Output ION IOP FS 0 0 FS 0 0
PACKAGE OUTLINE
32-Lead TQFP
A B GH
C
D
I J E F
SYMBOL A B C D E F G H I J K L
INCHES MIN MAX 0.346 0.362 0.272 0.280 0.346 0.362 0.272 0.280 0.031 typ 0.012 0.016 0.053 0.057 0.002 0.006 0.037 0.041 0.007 0 7 0.020 0.030
MILLIMETERS MIN MAX 8.80 9.20 6.90 7.10 8.80 9.20 6.90 7.10 0.80 BSC 0.30 0.40 1.35 1.45 0.05 0.15 0.95 1.05 0.17 0 7 0.50 0.75
K L
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PIN ASSIGNMENTS
DGND DVDD DVDD D5 D6 D3 D4 D7
PIN FUNCTIONS
ANALOG OUTPUTS IOP ION DAC current output. Full-scale output at 11...11 input code. Differential current output. Full-scale output at 00...00 input code. Digital Inputs (D0 is the LSB) Power down mode pin. Active high. Internally pulled down. Clock input pin. Data is latched on the rising edge. Voltage Reference - No Load Output. This pin is provided for monitoring purposes only. Full-scale Adjust Control. Connection for reference-current setting resistor. Analog Supply Ground. Digital Supply Ground. Analog +3.3 V supply. Digital +3.3 V supply.
31
29
32
28
30
27
26
D2 D1 DVDD D0 DGND CLK DGND AGND
25
1 2 3 4 5 6 7 8
10 12 13 14 15
24 23 22
D8 DGND D9 DGND PWD AVDD AGND ISET
DIGITAL INPUTS D0-D9 PWD CLK VRNL ISET POWER
32L TQFP
21 20 19 18 17
16
REFERENCE
11
AGND DGND AVDD DVDD
9
AGND
IOP
AGND
ORDERING INFORMATION
PART NUMBER SPT5240SIT TEMPERATURE RANGE -40 to +85 C PACKAGE 32L TQFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
AGND
AVDD
AVDD
VRNL
ION
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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