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ERRATA TO THE MSP50C6xx USER'S GUIDE
(TEXAS INSTRUMENTS LITERATURE NO. SPSU014, JANUARY 2000)
This document contains corrections and additions to information in the MSP50C6xx User's Guide (TI Literature Number SPSU014, January 2000). MSP50C6xx User's Guide Text Errors: 1. Page 2-39 of the user's guide, the 5th sentence is: Not that the reduced power mode... This should be: Note that the reduced power mode... (i.e., Not becomes Note) 2. Page 4-24, Table 4.11, Class 4, Subclass C, instruction description should be Memory references with long constant fields operating on Rx 3. Page 4-24, Table 4.11, Class 4, Subclass D, instruction description should be Memory references with R5 operating on Rx 4. On page 5-27, Section 5.6.5, know should be known MSP50C6xx User's Guide Table and Figure Errors: Errors INITZ X1 Page(s) A-7 1-11 1-12 7-3 A-7 B-8 C-6 X2 1-11 1-12 7-3 A-7 C-6 X2 (Pin#13) PLL (Pin#15) NC (Pin#31) GND1 (Pin#48) SCAN_OUT SCAN_IN SCAN_CLK PG0 OSCIN, OSCOUT B-8 B-8 B-8 B-8 A-7 B-8 B-8 B-8 B-4 1-10 Table(s) or Figure(s) Table A-1 Table 1-2 Figure 1-4 Table 7-1 Table A-1 Table B-1 Table 1 Table 1-2 Figure 1-4 Table 7-1 Table A-1 Table 1 Table B-1 Table B-1 Table B-1 Table B-1 Table A-1 Table B-1 Table B-1 Table B-1 Figure B-1 Table 1-1 SCANIN SCANCLK Replace Figure B-1 with Figure 1 in this document Exchange pad numbers (See Table 1 in this document) PLL OSCOUT VCC GND2 SCANOUT OSCOUT Correction RESET OSCIN
Printed in U.S.A.
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SPSS026B - MARCH 2000
FIGURE 1. Revised MSP50C604 Block Diagram
V SS 5 SCANIN SCANOUT SCANCLK SYNC TEST PGMPULSE (C604 only) (P614 only) INT vectors Break Point Emulation OTP Program Serial Comm. (EP) ROM Test-Area (reserved) User ROM 32k x (16 + 1) bit A port I/O 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF DATA Control G port I/0 DATA Control C port I/0 DATA Control 0x10 0x14 0x10 0x14 0x00 0x04 Scan Interface V DD 5 V PP
Power
(P614 only)
PG0 MASTER/SLAVE LOGIC
/8
PC0-7
DACP DACM RESET
DAC
0x30
Core Instr. Decoder
32 Ohm PDM Initialization Logic
PCU Prog. Counter Unit CU Computational Unit RTOTRIM Register 0x2F TIMER1 PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F
INRDY/PD0 OUTRDY/PD1 STROBE/PD2 R/WZ/PD3 PD4 PD5 PD6 PD7
OSC Reference Resistor Trimmed 32 kHz nominal
Comparator 1 bit: PD5 vs. PD4 + D port I/0 DATA Control 0x18 0x1C -
TIMER2
OSCIN OSCOUT
or or Crystal Referenced 32.768 kHz
DAC Data/Control ControlData 0x34 0x30 Clock Control 0x3D Gen. Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
8 Lines
PLL
PLL Filter
RAM 640 x 17 bit 0x0000 to (data) 0x027F
TABLE 1. Revised MSP50C6xx Pad Numbers
SIGNAL OSCOUT OSCIN PAD NUMBER 65 66 I/O Oscillator Reference Signals O I Resistor/crystal reference out Resistor/crystal reference in DESCRIPTION
2
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Missing Instruction Add this instruction between pages 4-132 and 4-133.
MULR
Syntax
[label]
Multiply (Rounded) With No Data Transfer
name
MULR
src
{adrs}
Clock, clk
Word, w
With RPT, clk Table 4-0-46
Class 5
Table 4-0-46
Execution
PH,PL MR * src PC PC + 1 TAG bit is set accordingly
Flags Affected Opcode
Instructions MULR [adrs]
16 1 x
15 1
14 0
13 1
12 1
11 1
10 0
9 1
8 0
7
6
5
4
3 adrs
2
1
0
dma16 (for direct) or offset16 (long relative) (see Section 4.13)
Description
Perform multiplication of multiply register (MR) and effective data memory value, add 08x00 to the product. The 16 MSBs of the 32-bit product are stored in the product high (PH) register. No status change. Round upper 16 bits. MULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MULAPL
See Also
Example MULR *R0++ Multiply MR with the content of data memory location pointed by R0 and store the rounded upper 16 bits of the result in PH. Increment R0 by 2.
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3
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Copyright (c) 2000, Texas Instruments Incorporated

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