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SP720MD-8, SP720MD, SP720MM-8, SP720MM
Data Sheet July 1999 File Number 3683.7
High Reliability Electronic Protection Array for ESD and Overvoltage Protection
The SP720 is a High Reliability Array of SCR/Diode bipolar structures for ESD and over-voltage protection to sensitive input circuits. The SP720 has 2 protection SCR/Diode device structures at each IN input. A total of 14 available IN inputs can be used to protect up to 14 external signal or bus lines. Over voltage protection is from the IN to V+ or V-. The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ or at a -VBE diode threshold below V-. From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input. The SP720MD and SP720MM are High Reliability Ceramic Packaged ICs. Refer to Application Note AN9304 for general application information and to AN9612 for further information on ESD and transient rating capabilities of the SP720.
Features
* The SP720MD-8 and SP720MM-8 are Harris Class Q "Equivalent" Parts and MIL-PRF-38535 Non-Compliant * ESD Interface Capability for HBM Standards - Modified MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . .15kV - MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV - IEC 1000-4-2, Direct Discharge, Single Input. . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2) Two Inputs in Parallel . . . . . . . . . . . . . . . . 8kV (Level 4) - IEC 1000-4-2, Air Discharge. . . . . . . . . . 15kV (Level 4) * High Peak Current Capability - IEC 1000-4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3A - Single Pulse, 100s Pulse Width . . . . . . . . . . . . . . 2A - Single Pulse, 4s Pulse Width . . . . . . . . . . . . . . . . 5A * Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to . . . . . . . . . . . . . . +30V - Differential Voltage Range to . . . . . . . . . . . . . . . . 15V * Fast Switching . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime * Low Input Leakages . . . . . . . . . . . . . . 1nA at 25oC Typical * Low Input Capacitance . . . . . . . . . . . . . . . . . . 3pF Typical * An Array of 14 SCR/Diode Pairs * Military Temperature Range . . . . . . . . . . . -55oC to 125oC
[ /Title (SP72 0MD8, SP720 MD, SP720 MM-8, SP720 MM) /Subject (High Reliability Electronic Protection Array for ESD and Overvoltage Protec-
Ordering Information
PART NO. SP720MD-8 SP720MD SP720MM-8 SP720MM TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld SBDIP 16 Ld SBDIP 20 Pad CLCC 20 Pad CLCC PKG. NO. D16.3 D16.3 J20.A J20.A
Applications
* Microprocessor/Logic Input Protection * Data Bus Protection * Analog Device Input Protection * Voltage Clamp
Pinouts
SP720MD (SBDIP) TOP VIEW
1 2 3 4 5 6 7 8 16 V+ 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 IN IN 8 9 V10 NC 11 NC 12 IN 13 IN 14 IN IN IN IN IN 4 5 6 7
Functional Block Diagram
SP720MM (CLCC) TOP VIEW
NC NC V+ IN IN V+ 16
(SP720MD)
IN IN IN IN IN IN IN V-
3
2
1
20
19 18 IN 17 IN 16 IN 15 IN V8 IN 1 IN 2
3-7 9 - 15 IN
9-11
NOTE: The design of the SP720MD-8, SP720MD, SP720MM-8, and SP720MM SCR/Diode ESD Diode Protection Arrays is covered by Harris patent 4567500. 1-800-4-HARRIS or 407-727-9207 | Copyright (c) Harris Corporation 1999
SP720MD-8, SP720MD, SP720MM-8, SP720MM
Absolute Maximum Ratings
Continuous Supply Voltage, [(V+) - (V-)] . . . . . . . . . . . . . . . . . +35V Max. DC Input Current, IIN . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA Input Peak Current, IIN (Refer to Figure 3) . . . . . . . . . . 2A, 100s ESD Capability, Refer to "ESD Capability" and Table 1, Figure 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 16 Ld SBDIP Package . . . . . . . . . . . . . 80 18 20 Pad CLCC Package . . . . . . . . . . . . 70 16 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC
Operating Conditions
Operating Voltage Range, Single Supply. . . . . . . . . . . . +2V to +30V Operating Voltage Range, Split Supply . . . . . . . . . . . . 1V to 15V Typical Quiescent Supply Current . . . . . . . . . . . . . . . . . . . . . . .50nA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Operating Voltage Range
TA = -55oC to 125oC, Unless Otherwise Specified SYMBOL VSUPPLY VIN - (V-) VIN - (V+) VIN - (V-) VIN - (V+) IIN IQUIESCENT TEST CONDITIONS VSUPPLY = [(V+) - (V-)] IIN = -1A (1ms Peak Pulse) IIN = +1A (1ms Peak Pulse) IIN = -100mA to VIIN = +100mA to V+ V- < VIN < V+, VSUPPLY = 30V V- < VIN < V+, VSUPPLY = 30V Note 3 VFWD/IFWD (Note 3) CIN tON MIN 0 TYP 2 to 30 MAX 35 UNITS V
Peak Forward/Reverse Voltage Drop IN to V- (with V- Reference) IN to V+ (with V+ Reference) DC Forward/Reverse Voltage Drop IN to V- (with V- Reference) IN to V+ (with V+ Reference) Input Leakage Current Quiescent Supply Current Equivalent SCR ON Threshold Equivalent SCR ON Resistance Input Capacitance Input Switching Speed NOTES: 2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01F or larger from the V+ and V- pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent "SCR ON Threshold" and "SCR ON Resistance". These characteristics are given here for thumb-rule information to determine peak current and dissipation under EOS conditions. -1.5 -15 5 50 1.1 1 3 2 +1.5 +15 150 V V nA nA V pF ns -2 +2 V V
R1 CHARGE SWITCH H.V. SUPPLY VD CD
RD DISCHARGE SWITCH IN DUT
TABLE 1. ESD TEST CONDITIONS STANDARD MIL STD 3015.7 IEC 1000-4-2 TYPE/MODE Modified HBM Standard HBM HBM, Air Discharge HBM, Direct Discharge HBM, Direct Discharge, Two Parallel Input Pins Machine Model RD CD 1.5k 100pF 1.5k 100pF 330 150pF 330 330 150pF 150pF VD 15kV 6kV 15kV (Level 4) 4kV (Level 2) 8kV (Level 4) 1kV
IEC 1000-4-2: R1 50 to 100M MIL STD 3015.7: R1 1 to 10M
FIGURE 1. ELECTROSTATIC DISCHARGE TEST EIAJ IC121
0k
200pF
9-12
SP720MD-8, SP720MD, SP720MM-8, SP720MM ESD Capability
ESD capability is dependent on the application and defined test standard. The evaluation results for various test standards and methods based on Figure 1 are shown in Table 1. For the "Modified" MIL-STD-3015.7 condition that is defined as an "in-circuit" method of ESD testing, the V+ and V- pins have a return path to ground and the SP720 ESD capability is typically greater than 15kV from 100pF through 1.5k. By strict definition of MIL-STD-3015.7 using "pin-to-pin" device testing, the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results were determined from AT&T ESD Test Lab measurements. The HBM capability to the IEC 1000-4-2 standard is greater than 15kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess of 8kV (Level 4). For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than 1kV from 200pF with no series resistance. The maximum peak input current capability is dependent on the V+ to V- voltage supply level, improving as the supply voltage is reduced. Values of 0, 5, 15 and 30 voltages are shown. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in Figure 3. When adjacent input pins are paralleled, the sustained peak current capability is increased to nearly twice that of a single pin. For comparison, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and 14+15. The overstress curve is shown in Figure 3 for a 15V supply condition. The dual pins are capable of 10A peak current for a 10s pulse and 4A peak current for a 1ms pulse. The complete curve for single pulse peak current vs. pulse width time ranging up to 1 second is shown in Figure 3.
VARIABLE TIME DURATION CURRENT PULSE GENERATOR CURRENT SENSE (-) (+) 1 IN 2 IN 3 IN 4 IN VOLTAGE PROBE V+ 16 IN 15 IN 14 IN 13 + C1
+ VX -
R1
Peak Transient Current Capability
The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP720's ability to withstand a wide range of transient current pulses. The test circuit shown in Figure 2 provides a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP720 `IN' input pin and the (+) current pulse input goes to the SP720 V- pin. The V+ to V- supply of the SP720 must be allowed to float (i.e., it is not tied to the ground reference of the current pulse generator). Figure 3 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits.
10 9 8 PEAK CURRENT (A) 7 6 5 4 3 2 1 0 0.001 0.01 0.1 1 PULSE WIDTH TIME (ms) 10 0V 5V 30V
5 IN SP720 IN 12 6 IN 7 IN IN 11 IN 10 IN 9
-
R1 ~ 10 TYPICAL VG ADJ. 10V/A TYPICAL C1 ~ 100F
8 V-
FIGURE 2. TYPICAL SP720 PEAK CURRENT TEST CIRCUIT WITH A VARIABLE PULSE WIDTH INPUT
CAUTION: SAFE OPERATING CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EACH CURVE. SINGLE PIN STRESS CURVES DUAL PIN STRESS CURVE
15V V+ TO V- SUPPLY
15V
100
1000
FIGURE 3. TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVERSTRESS IN AMPERES vs PULSE WIDTH TIME IN MILLISECONDS (TA = 25oC)
9-13
SP720MD-8, SP720MD, SP720MM-8, SP720MM
100 TA = 25oC SINGLE PULSE 80 FORWARD SCR CURRENT (mA) FORWARD SCR CURRENT (A) 2 2.5
TA = 25oC SINGLE PULSE
60
1.5
40
1 IFWD EQUIV. SAT. ON THRESHOLD ~1.1V .5 VFWD
20
0 600
0 800 1000 1200 0 1 2 3 FORWARD SCR VOLTAGE DROP (mV) FORWARD SCR VOLTAGE DROP (V)
FIGURE 4. LOW CURRENT SCR FORWARD VOLTAGE DROP CURVE
FIGURE 5. HIGH CURRENT SCR FORWARD VOLTAGE DROP CURVE
+VCC
+VCC
INPUT DRIVERS OR SIGNAL SOURCES
LINEAR OR DIGITAL IC INTERFACE
TO +VCC IN 1-7 IN 9-15 V+
SP720
SP720 INPUT PROTECTION CIRCUIT (1 OF 14 ON CHIP)
V-
FIGURE 6. TYPICAL APPLICATION OF THE SP720 AS AN INPUT CLAMP FOR OVERVOLTAGE, GREATER THAN 1VBE ABOVE V+ OR LESS THAN -1VBE BELOW V-. PINOUT SHOWN IS FOR THE SP720MD SBDIP PACKAGE
9-14
SP720MD-8, SP720MD, SP720MM-8, SP720MM Power Dissipation Derating Curves
1.0 MAX DISSIPATION
POWER DISSIPATION (W)
0.610W 0.5 MAX. DERATED DISSIPATION
93oC
82oC
0 0 50 100 AMBIENT TEMPERATURE (oC) 125 150 175
FIGURE 7. SP720MD DERATING CURVE FOR THE 82oC/W THERMAL RESISTANCE OF THE SIDEBRAZE 16 LEAD CERAMIC PACKAGE, DERATED 12.2mW/oC FROM A MAXIMUM PD OF 1.0W AT 93oC
MAX DISSIPATION 1
POWER DISSIPATION (W)
0.714W
0.5
MAX. DERATED DISSIPATION
105oC
70oC
0
50
100 AMBIENT TEMPERATURE (oC)
125
150
175
FIGURE 8. SP720MM DERATING CURVE FOR THE 70oC/W THERMAL RESISTANCE OF THE 20 PAD CERAMIC LCC PACKAGE, DERATED 14.3mW/oC FROM A MAXIMUM PD OF 1.0W AT 105oC
9-15
SP720MD-8, SP720MD, SP720MM-8, SP720MM SP720MD-8 and SP720MM-8 Dynamic Burn-In Circuits
16 LEAD CERAMIC SBDIP
VCC 1 INPUT SIGNAL FS 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C1
NOTES: 4. All resistors 1k 10%. 5. VCC = 30V 1%. 6. FS = 0V to 30V 1%, 50% Duty Cycle. 7. C1 = 22F Min Tantalum, 50WV (33WV at 125oC). 8. TAMB = 125oC. 20 PAD CLCC
VCC INPUT SIGNAL FS 4 5 6 7 8 9 10 11 12 13 3 2 1 20 19 18 17 16 15 14 C1
30V FS 0V
9-16
SP720MD-8, SP720MD, SP720MM-8, SP720MM Die Characteristics
DIE DIMENSIONS: 51 mils x 84 mils x 14 mils 1 mil METALLIZATION: Type: Al Thickness: 17.5kA 2.5kA PASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA SUBSTRATE POTENTIAL (POWERED UP): VWORST CASE CURRENT DENSITY: 9.18 x 104A/cm2 at 70mA PROCESS: Bipolar
Metallization Mask Layout
SP720MD-8, SP720MD, SP720MM-8, SP720MM
VCC (16)
9
1
(SBDIP PINOUT)
GND (8)
9-17
SP720MD-8, SP720MD, SP720MM-8, SP720MM Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C) 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES SYMBOL A b b1 b2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS
b3 c c1 eA e eA/2
c
D E e eA eA/2 L Q S1 S2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
9-18
SP720MD-8, SP720MD, SP720MM-8, SP720MM Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S D D3
J20.A
MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 B2 B3 D D1 D2 MIN 0.060 0.050 0.022 0.006 0.342 MAX 0.100 0.088 0.028 0.022 0.358 MILLIMETERS MIN 1.52 1.27 0.56 0.15 8.69 1.83 REF 0.56 9.09 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/18/94 NOTES:
j x 45o
B
E3
E
0.072 REF
0.200 BSC 0.100 BSC 0.342 0.358 0.358 -
5.08 BSC 2.54 BSC 9.09 9.09 5.08 BSC 2.54 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.91 0.08 5 5 20 1.40 1.40 2.41 0.38 9.09 1.27 BSC 8.69
h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1
D3 E E1 E2 E3 e e1 h j
0.007 M E F S H S B1
0.200 BSC 0.100 BSC 0.015 0.358 0.050 BSC 0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 5 5 20 0.055 0.055 0.095 0.015
-E-
L L1 L2 L3 ND NE N
e
L -HL3
-FE1 B3
E2
L2 B2
1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.
L1
e1
D1
D2
9-19

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