View SOES009A_1004112.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
D D D D D D
Contains 64-Bit Static Shift Register Contains Analog Buffer With Sample and Hold for Analog Output Over Full Clock Period Single-Supply Operation Operates With 500-kHz Shift Clock 8-Pin Clear Plastic DIP Package Advanced LinCMOSTM Technology
SI CLK AO VDD
(TOP VIEW) 1 2 3 4 8 7 6 5
VDD GND GND NC
NC - No internal connection
description
The TSL213 integrated opto sensor consists of 64 charge-mode pixels arranged in a 64 x 1 linear array. Each pixel measures 120 m x 70 m with 125-m center-to-center spacing. Operation is simplified by internal logic requiring only clock and start-integration-pulse signals. The TSL213 is intended for use in a wide variety of applications including linear and rotary encoding, linear positioning, edge and mark detection, and contact imaging. The TSL213 is supplied in an 8-pin dual-in-line clear plastic package.
functional block diagram
VDD 8
1
2
3
64 Pixels Sense Node
Pixel Buffer Pixel Buffer
Pixel Selector Switch S1 Reset S2 S3 S64
Dark Pixel Reference Generator
Differential Amplifier
Sample and Hold
Output Buffer
3 AO
Nonoverlapping Clock Generator
RL (external load)
Q1
Q2
Q3
Q64
CLK SI
2 1
64-Bit Shift Register
Clock Generator
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
Terminal Functions
PIN NAME AO CLK GND NC SI VDD NO. 3 2 6, 7 5 1 4, 8 Analog output Clock. The clock controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to the substrate. No internal connection Serial input. The serial input defines the end of the integration period and initiates the pixel output sequence. Supply voltages. These supply power to the analog and digital circuits. DESCRIPTION
detailed description
sensor elements The line of sensor elements, called pixels, consists of 64 discrete photosensing areas. Light energy striking a pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge accumulated in each element is directly proportional to the amount of incident light and the integration time. device operation Operation of the 64 x 1 array sensor consists of two time periods: an integration period during which charge is accumulated in the pixels and an output period during which signals are transferred to the output. The integration period is defined by the interval between serial-input (SI) pulses and includes the output period (see Figure 1). The required length of the integration period depends upon the amount of incident light and the desired output signal level. sense node On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense node under the control of the clock (CLK) and SI signals. The signal voltage generated at this node is directly proportional to the amount of charge and inversely proportional to the capacitance of the sense node. reset An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This voltage is used as a reference level for the differential signal amplifier. shift register The 64-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing signals for the NOCG. The SI signal provides the input to the shift register and is shifted under direct control of the clock. The output period is initiated by the presence of the SI input pulse coincident with a rising edge of CLK (see Figures 1 and 2). The analog output voltage corresponds to the level of the first pixel after settling time (ts) and remains constant for a minimum time, tv . A voltage corresponding to each succeeding pixel is available at each rising edge of the clock. The output period ends on the rising edge of the 65th clock cycle, at which time the output assumes the high-impedance state. The 65th clock cycle terminates the output of the last pixel and clears the shift register in preparation for the next SI pulse. To achieve minimum integration time, the SI pulse may be present on the 66th rising edge of the clock to immediately reinitiate the output phase. When the output period has been initiated by an SI pulse, the clock must be allowed to complete 65 positive-going transitions in order to reset the internal logic to a known state.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
sample and hold The sample-and-hold signal generated by the NOCG is used to hold the analog output voltage of each pixel constant until the next pixel is clocked out. The signal is sampled while CLK is high and held constant while CLK is low. nonoverlapping clock generators The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing. The signals are synchronous and are controlled by the outputs of the shift register. initialization Initialization of the sensor elements may be necessary on power up or during operation after any period of clock or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively performed output cycles and clears the pixels of any charge that may have accumulated during the inactive period. output enable The internally-generated output-enable signal enables the output stage of the sensor during the output period (64 clock cycles). During the remainder of the integration period, the output stage is in the high-impedance state that allows output interconnections of multiple devices without interference.
CLK 64 Cycles Clock Continues or Remains Low After 65th Cycle tint SI 64 Cycles
AO
Figure 1. Timing Waveforms
absolute maximum ratings, TA = 25C (unless otherwise noted) (see Note 1)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20 mA to 20 mA Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 10C to 85C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25C to 85C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to the network GND. 2. Case temperature is the surface temperature of the plastic package measured directly over the integrated circuit.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
CCCC CCCC
3
Analog Output Period
CCCCC CCCCC
TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
recommended operating conditions
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, Clock input frequency, fclock Pulse duration, CLK low, tw Sensor integration time, tint Setup time, SI before CLK, tsu(SI) Hold time, SI after CLK, th(SI) External resistive load, AO, RL Total number of TSL213 outputs connected together Operating free-air temperature, TA 0 50 50 330 10 70 C 10 1 5 4.5 0 VDD x 0.7 0 750 500 NOM MAX 5.5 VDD VDD VDD x 0.3 UNIT V V V V nm kHz s ms ns ns
electrical characteristics, VDD = 5 V, TA = 25C, fclock = 180 kHz, p = 565 nm, RL = 330 , CL = 330 pF, tint = 5 ms, Ee = 20 W/cm2 (unless otherwise noted) (see Note 3)
PARAMETER Analog output voltage saturation level Analog output voltage (white, average over 64 pixels) Analog output voltage (dark, each pixel) Output voltage (white) change with change in VDD Dispersion of analog output voltage Linearity of analog output voltage Pixel recovery time Supply current High-level input current Low-level input current Input capacitance Ee = 0 VDD = 5 V 5% See Note 4 See Note 5 See Note 6 IDD Avg VI = VDD VI = 0 5 0.85 25 4 TEST CONDITIONS Ee = 51 W/cm2 MIN 3 1.75 TYP 3.4 2 0.25 2% 10% 1.15 40 9 0.5 0.5 ms mA A A pF 0.4 MAX UNIT V V V
NOTES: 3. The input irradiance (Ee) is supplied by an LED array with p = 565 nm. 4. Dispersion of analog output voltage is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test. 5. Linearity of analog output voltage is calculated by averaging over 64 pixels and measuring the maximum deviation of the voltage at 2 ms and 3.5 ms from a line drawn between the voltage at 2.5 ms and the voltage at 5 ms. 6. Pixel recovery time is the time required for a pixel to go from the analog-output-voltage (white, average over 64 pixels) level to the analog-output-voltage (dark, each pixel) level or vice versa after a step change in light input.
operating characteristics, VDD = 5 V, TA = 25C, RL = 330 , CL = 330 pF, tint = 5 ms, Ee = 20 W/cm2, fclock = 500 kHz (unless otherwise noted)
PARAMETER ts tv Settling time Valid time TEST CONDITIONS See Figure 2 and Note 7 MIN TYP MAX 1 1/2 fclock UNIT s s
NOTE 7: Clock duty cycle is assumed to be 50%.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
PARAMETER MEASUREMENT INFORMATION
VDD 0.1 F 4 VDD SI CLK 1 2 SI CLK TSL213 8 VDD AO 3 RL = 330 AO
CL = 330 pF
GND 6
GND 7
Supply bypass capacitor with short leads should be placed as close to the device as possible. TEST CIRCUIT tw CLK tsu(SI) SI 50% th(SI) ts 90% Pixel 1 tv OPERATIONAL WAVEFORMS 90% Pixel 64 5V 0V 1 2 64 65 2.5 V 0V
5V
ts AO
Figure 2. Test Circuit and Operational Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
TYPICAL CHARACTERISTICS
INTEGRATION TIME vs IRRADIANCE FOR CONSTANT AVERAGE ANALOG OUTPUT VOLTAGE
10 9 f int - Integration Time - ms 0.4 Normalized Responsivity 8 7 6 5 4 3 2 0 5 10 15 20 25 30 35 40 Ee - Irradiance - W/cm2 45 50 VDD = 5 V p = 565 nm Analog Output Voltage (white, average over 64 pixels) = 2 V TA = 25C
NORMALIZED RESPONSIVITY vs WAVELENGTH OF INCIDENT LIGHT
1
0.1
0.04 VDD = 5 V TA = 25C tint = 3 ms 0.01 400 500 600 700 800 900 1000 1100 - Incident Wavelength - nm
Figure 3
ANALOG OUTPUT VOLTAGE (DARK) vs INTEGRATION TIME
300 1 0.9 Analog Output Voltage (dark) - mV Output Voltage Normalized to 2.2 V 250 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 4 7 10 20 40 70 100 0 2 3 VDD = 5 V TA = 25C
Figure 4
NORMALIZED OUTPUT VOLTAGE vs INTEGRATION TIME
Ee = 20 W/cm2
200
Ee = 10 W/cm2
150
100
Ee = 2 W/cm2
50
VDD = 5 V Ee = 0 TA = 25C 1 2
0 tint - Integration Time - ms
4 5 6 7 8 tint - Integration Time - ms
9
10
Figure 5
Figure 6
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL213 64 x 1 INTEGRATED OPTO SENSOR
SOES009A - NOVEMBER 1992 - REVISED AUGUST 1993
mechanical data
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated with an electrically nonconductive clear plastic compound.
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 SI CLK AO VDD NC GND GND VDD
6,60 (0.260) 6,10 (0.240) 1,91 (0.075) 1,02 (0.040) 15 TYP Pixel 1 is centered horizontally on Pin 1 10,92 (0.430) 9,40 (0.370) 8 5
9,53 (0.325) 7,62 (0.300) 0,32 (0.013) 1 4
C L
C (pixel) L
0,76 (0.030) D NOM
0,51 (0.020) R NOM 4 Places 7 MAX TYP 1,6 (0.063) 1,5 (0.059)
1,65 (0.065) 5,08 (0.200) 1,14 (0.045) 3,94 (0.155)
Seating Plane 0,51 (0.020) R MAX 4 Places 105 90 8 Places 7,62 (0.300) T.P. 0,30 (0.012) 0,20 (0.008) 1,27 (0.050) 0,51 (0.020) 1,52 (0.060) 0,38 (0.015) 1,65 (0.065) 1,14 (0.045) 3,81 (0.150) 3,18 (0.125) 0,56 (0.022) 0,36 (0.014) 2,54 (0.100) T.P.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SOES009A

	To Download SOES009A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .