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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
* * * * * * *
On-Board 64-Bit Static Shift Register Extendable Data I/O for Expanding the Number of Sensors Analog Buffer With Sample and Hold for Analog Output Over Full Clock Period Single-Supply Operation 500-kHz Shift Clock 14-Pin Clear Plastic Package Advanced LinCMOSTM Technology
VDD SI CLK AO GND SO VDD
(TOP VIEW)
*1
2 3 4 5 6 7
14 13 12 11 10 9 8
NC NC GND NC NC NC NC
NC - No internal connection
description
The TSL214 integrated opto sensor consists of 64 charge-mode pixels arranged in a 64 x 1 linear array. Each pixel measures 120 m x 70 m, with 125-m center-to-center spacing. Operation is simplified by internal logic requiring only clock and start-integration-pulse signals. The TSL214 is intended for use in a wide variety of applications including linear and rotary encoding, bar-code reading, edge detection and positioning, and contact imaging. The TSL214 is supplied in a 14-pin dual-in-line clear plastic package.
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994, Texas Instruments Incorporated
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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
functional block diagram
VDD 1, 7
1
2
3
64 Pixels Sense Node
Pixel Buffer Pixel Buffer
Pixel Selector Switch S1 Reset Q1 S2 S3 S64
Dark Pixel Reference Generator
Differential Amplifier
Sample and Hold
Output Buffer RL (external load)
4 AO
Nonoverlapping Clock Generator 6 SO
Q2
Q3
Q64
CLK 3 SI 2
64-Bit Shift Register
Clock Generator
Terminal Functions
TERMINAL NAME AO CLK GND NC SI SO VDD NO. 4 3 5, 12 8 - 11, 13, 14 2 6 1, 7 Analog output Clock input. CLK controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to the substrate. No internal connection Serial input. SI defines the end of the integration period and initiates the pixel output sequence. Serial output. SO provides a signal to drive the SI input of another TSL214 sensor for cascading. Supply voltage. VDD supplies power to the analog and digital circuits. DESCRIPTION
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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
detailed description
sensor elements The line of sensor elements, called pixels, consists of 64 discrete photosensing areas. Light energy striking a pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge accumulated in each element is directly proportional to the amount of incident light and the integration time. device operation Operation of the 64 x 1 array sensor consists of two time periods: an integration period during which charge is accumulated in the pixels and an output period during which signals are transferred to the output. The integration period is defined by the interval between serial-input (SI) pulses and includes the output period (see Figure 1). The required length of the integration period depends upon the amount of incident light and the desired output signal level. sense node On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense node under the control of the clock (CLK) and SI signals. The signal voltage generated at this node is directly proportional to the amount of charge and inversely proportional to the capacitance of the sense node. reset An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This voltage is used as a reference level for the differential signal amplifier. shift register The 64-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing signals for the NOCG. The SI signal provides the input to the shift register and is shifted under direct control of the clock. The input is shifted out to the serial output (SO) on the 64th clock cycle. This SO pulse can then be used as the SI pulse for another device for multiple-unit operation. The output period is initiated by the presence of the SI pulse coincident with a rising edge of the clock (Figures 1 and 2). The output voltage corresponds to the level of the first pixel after settling time (ts) and remains constant for a valid time (tv). A voltage corresponding to each succeeding pixel is available at each rising edge of the clock. The output period ends on the rising edge of the 65th clock cycle, at which time the output assumes a high-impedance state. The 65th clock cycle terminates the output of the last pixel and clears the shift register in preparation for the next SI pulse. To achieve minimum integration time, the SI pulse may be present on the 66th rising edge of the clock to immediately reinitiate the output phase. Once the output period is initiated by an SI pulse, the clock must be allowed to complete 65 positive-going transitions in order to reset the internal logic to a known state. sample-and-hold The sample-and-hold signal generated by the NOCG is used to hold analog output voltage of each pixel constant until the next pixel is clocked out. The signal is sampled while the clock is high and held constant while the clock is low. nonoverlapping clock generators The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing. The signals are synchronous and are controlled by the outputs of the shift register.
POST OFFICE BOX 655303
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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
initialization Initialization of the sensor elements may be necessary on power up or during operation after any period of clock or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively performed output cycles and clears the pixels of any charge that may have accumulated during the inactive period. multiple unit operation Multiple sensor devices may be connected together in a serial or parallel configuration. The serial connection is accomplished by connecting analog outputs (AO) together and connecting the SO terminal of each sensor device to the SI terminal of the next device. The SI signal is applied to the first device only, with each succeeding device receiving its SI from the SO of the preceding device. For n cascaded devices, the SI pulse is applied to the first device after every n*64 positive-going clock transitions. A common clock signal is applied to all the devices simultaneously. Parallel operation of multiple devices is accomplished by supplying clock and SI signals to all the devices simultaneously. The output of each device is then separately used for processing. output enable The internally generated output-enable signal enables the output stage of the sensor during the output period (64 clock cycles). During the remainder of the integration period, the output stage is in the high-impedance state, which allows output interconnections of multiple devices without interference.
CLK 64 Cycles Clock Continues or Remains Low After 65th Cycle tint SI 64 Cycles
SO Analog Output Period
AO
Figure 1. Timing Waveforms
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CCCC CCCC CCCC
CCCCC CCCCC CCCCC
TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (see Note 1)
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VDD +0.5 V Digital output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20 mA to 20 mA Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 10C to 85C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25C to 85C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to GND. 2. Case temperature is the surface temperature of the plastic measured directly over the integrated circuit.
recommended operating conditions
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, Clock input frequency, fclock Pulse duration, CLK low, tw(CLKL) Sensor integration time, tint (see Figures 1 and 2) Setup time, SI before CLK, tsu(SI) Hold time, SI after CLK, th(SI) External resistive load, AO, RL Total number of TSL214 outputs connected together Operating free-air temperature, TA 0 50 50 330 10 70 C 10 1 5 4.5 0 VDD x 0.7 0 750 500 NOM MAX 5.5 VDD VDD VDD x 0.3 UNIT V V V V nm kHz s ms ns ns
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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
electrical characteristics at VDD = 5 V, TA = 25C, fclock = 180 kHz, p = 565 nm, RL = 330 , CL = 330 pF, tint = 5 ms, Ee = 20 W/cm2 (unless otherwise noted) (see Note 3)
PARAMETER Low-level output voltage High-level output voltage Analog output voltage saturation level Analog output voltage (white, average over 64 pixels) Analog output voltage (dark, each pixel) Output voltage (white) change with change in VDD Dispersion of analog output voltage Linearity of analog output voltage Pixel recovery time Supply current High-level input current Low-level input current Input capacitance Ee = 0 VDD = 5 V 5% See Note 4 See Note 5 See Note 6 IDD (average) VI = VDD VI = 0 5 0.85 25 4 TEST CONDITIONS IO = 0 Ee = 60 W/cm2 MIN 4.4 3 1.75 3.4 2.2 0.25 2% 7.5% 1.15 40 9 0.5 0.5 ms mA A A pF 0.4 TYP MAX 0.1 UNIT V V V V V
NOTES: 3. The input irradiance (Ee) is supplied by an LED array with p = 565 nm. 4. Dispersion of analog-output voltage is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test. 5. Linearity of analog-output voltage is calculated by averaging over 64 pixels and measuring the maximum deviation of the voltage at 2 ms and 3.5 ms from a line drawn between the voltage at 2.5 ms and the voltage at 5 ms. 6. Pixel recovery time is the time required for a pixel to go from the analog-output voltage (white, average over 64 pixels) level to analog-output voltage (dark, each pixel) level or vice versa after a step change in light input.
operating characteristics, VDD = 5 V, TA = 25C, fclock = 500 kHz, RL = 330 , CL = 330 pF, tint = 5 ms, Ee = 20 W/cm2 (unless otherwise noted)
PARAMETER tr(SO) tf(SO) tpd(SO) ts Rise time, SO Fall time, SO Propagation delay time, SO Settling time See Figure 2 and Note 7 TEST CONDITIONS MIN TYP 25 25 70 1 1/2 fclock MAX UNIT ns ns ns s s
tv Valid time NOTE 7: Clock duty cycle is assumed to be 50%.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
VDD 0.1 F 1 VDD SI CLK 2 3 SI CLK TSL214 7 VDD AO 4 RL = 330 AO
CL = 330 pF
SO GND 5 GND 12
6
SO
Supply bypass capacitor with short leads should be placed as close to the device as possible. TEST CIRCUIT tw(CLKL) 1 CLK tsu(SI) 5V SI 50 % 0V th(SI) SO ts 90 % Pixel 1 tv OPERATIONAL WAVEFORMS 90 % Pixel 64 tpd(SO) 50 % 90 % 50 % 10 % tr(SO) tpd(SO) 10 % 90 % tf(SO) 2 64 65 2.5 V 0V 5V
ts AO
Figure 2. Test Circuit and Operational Waveforms
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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
TYPICAL CHARACTERISTICS
NORMALIZED RESPONSIVITY vs WAVELENGTH OF INCIDENT LIGHT
1 10 9 Normalized Responsivity f int - Integration Time - ms 0.4 8 7 6 5 4 3 2 500 600 700 800 900 1000 1100 - Incident Wavelength - nm 0 5 10 15 20 25 30 35 40 Ee - Irradiance - W/cm2 45 50 VDD = 5 V = 565 nm Analog Output Voltage (white, average over (64 pixels) = 2.2 V TA = 25C
INTEGRATION TIME vs IRRADIANCE, FOR CONSTANT AVERAGE ANALOG OUTPUT VOLTAGE
0.1
0.04 VDD = 5 V TA = 25 C tint = 3 ms 0.01 400
Figure 3
ANALOG OUTPUT VOLTAGE (DARK) vs INTEGRATION TIME
300 1 0.9 Analog Output Voltage (dark) - mV Output Voltage Normalized to 2.2 V 250 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 4 7 10 20 40 70 100 0 2 3 VDD = 5 V TA = 25C
Figure 4
OUTPUT VOLTAGE vs INTEGRATION TIME
Ee = 20 W/cm2
200
Ee = 10 W/cm2
150
100
50
VDD = 5 V Ee = 0 TA = 25C 1 2
Ee = 2 W/cm2
0 tint - Integration Time - ms
4 5 6 7 8 tint - Integration Time - ms
9
10
Figure 5
Figure 6
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
MECHANICAL DATA
This assembly consists of a sensor chip mounted on a printed circuit board in a clear molded plastic package. The distance between the top surface of the package and the surface of the sensor is nominally 1,0 mm (0.040 inch).
Designation per JEDEC Std. 30: PDIP-T14 10,67 (0.420) 9,65 (0.380) C L 1,91 (0.075) MAX Both Rows Bottom View
No. 1 Sensor Element
14 3,6 (0.142) NOM (first pixel location) 13 19,30 (0.760) 18,29 (0.720) 12 11 10 9 8 Sensor Center Line 3,94 (0.155) 3,68 (0.145) 3,43 (0.135) 2,79 (0.110) C L
1 2 3 4 5 6 7 2,54 (0.100) T.P. 12 Places (see Note A) 2,16 (0.085) MAX 4 Places
7,87 (0.310) 7,37 (0.290) C L
Seating Plane 4,6 (0.180) MIN
0,508 (0.020) 0,406 (0.016) Dia All Pins ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: The true-position spacing is 2,54 mm (0.100 inch) between lead centerlines. Each pin centerline is located within 0,25 mm (0.010 inch) of its true longitudinal positions.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL214 64 x 1 INTEGRATED OPTO SENSOR
SOES002E - JUNE 1991 - REVISED MARCH 1994
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
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Copyright (c) 1998, Texas Instruments Incorporated

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