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SN65CML100
SLLS547 - NOVEMBER 2002
1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER
FEATURES D Provides Level Translation From LVDS or
LVPECL to CML, Repeating From CML to CML
DESCRIPTION
This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- or 25- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA-644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion. The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-F capacitor and limit the current sourcing or sinking to 400 A. When not used, VBB should be left open. This device is characterized for operation from -40C to 85C.
D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives
Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
D Total Jitter < 70 ps D Low 100 ps (Max) Part-To-Part Skew D Wide Common-Mode Receiver Capability
Allows Direct Coupling of Input Signals
D 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
D Propagation Delay Times, 800 ps Maximum D 3.3-V Supply Operation D Available in SOIC and MSOP Packages APPLICATIONS D D D D D
Level Translation 622-MHz Central Office Clock Distribution High-Speed Network Routing Wireless Basestations Low Jitter Clock Repeater
FUNCTIONAL DIAGRAM
VCC A B 8 2 4 VBB
EYE PATTERN
7 6
1.5 Gbps 223-1 PRBS
Y Z
Vertical Scale = 500 mV/div
3
750 MHz
Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
SN65CML100
SLLS547 - NOVEMBER 2002
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER SN65CML100D SN65CML100DGK PART MARKING CML100 NWB PACKAGE SOIC MSOP STATUS Production Production
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage range,(2) VCC Sink/source, IBB Voltage range, (A, B, Y, Z) Human Body Model(3) Charged-Device Model(4) Continuous power dissipation Storage temperature range, Tstg A, B, Y, Z, and GND All pins All pins -0.5 V to 4 V 0.5 mA 0 V to 4.3 V 5 kV 2 kV 1500 V See Dissipation Rating Table -65C to 150C
Electrostatic discharge
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7. (4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VCC 3.3-V nominal supply at terminator Terminator su ly voltage, VTT supply Magnitude of differential input voltage |VID| Input voltage (any combination of common-mode or input signals) Output current, VBB Operating free-air temperature, TA -40 2.5-V nominal supply at terminator 1.8-V nominal supply at terminator 3 3 2.375 1.7 0.1 0 NOM 3.3 3.3 2.5 MAX UNIT 3.6 3.6 2.625 1.9 1 4 400 85 V V V V A C V
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SN65CML100
SLLS547 - NOVEMBER 2002
PACKAGE DISSIPATION RATINGS
PACKAGE DGK D TA 25C POWER RATING 425 mW 725 mW DERATING FACTOR(1) ABOVE TA = 25C 3.4 mW/C 5.8 mW/C TA = 85C POWER RATING 221 mW
377 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
DEVICE CHARACTERISTICS
PARAMETER ICC VBB Supply current, device only Switching reference voltage(1) 1890 MIN NOM 9 1950 MAX 12 2010 UNIT mA mV
(1) VBB parameter varies 1:1 with VCC
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ VIT- VID(HYS) II Positive-going differential input voltage threshold Negative-going differential input voltage threshold Differential input voltage hysteresis, VIT+ - VIT- Input current (A or B inputs) VI = 0 V or 2.4 V, Second input at 1.2 V VI = 4 V, Second input at 1.2 V VCC = 1.5 V, VI = 0 V or 2.4 V, Second input at 1.2 V VCC = 1.5 V, VI = 4 V, Second input at 1.2 V VIA = VIB, 0 VIA 4 V VI = 0.4 sin (4E6t) + 0.5 V VCC = 0 V -20 See Figure 1 and Table 1 -100 25 20 33 -20 20 33 -6 3 3 pF 6 A mV A A TEST CONDITIONS MIN TYP(1) MAX 100 mV UNIT
II(OFF) IIO Ci
Power off in ut current (A or B in uts) input inputs) Input offset current (|IIA - IIB|) Differential input capacitance
A
(1) All typical values are at 25C and with a 3.3-V supply.
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted) VOH VOL |VOD| VOH VOL |VOD| VOH VOL |VOD| VOH VOL |VOD| Co PARAMETER Output high voltage(2) Output low voltage(2) Differential output voltage magnitude Output high voltage(3) Output low voltage(3) Differential output voltage magnitude Output high voltage(2) Output low voltage(2) Differential output voltage magnitude Output high voltage(3) Output low voltage(3) Differential output voltage magnitude Differential output capacitance VI = 0.4 sin (4E6t) + 0.5 V VCC = 0 V TEST CONDITIONS RT = 50 VTT = 3 V to 3.6 V or , 36 VTT = 2.5 V 5%, See Figure 2 S Fi RT = 25 VTT = 3 V to 3.6 V or , 36 VTT = 2.5 V 5%, See Figure 2 S Fi RT = 50 , VTT = 1.8 V 5%, See Figure 2 MIN VTT-60 VTT-1100 640 VTT-60 VTT-550 320 VTT-170 VTT-1100 570 RT = 25 , VTT = 1.8 V 5%, See Figure 2 VTT-85 VTT-500 285 TYP(1) VTT-10 VTT-800 780 VTT-10 VTT-400 390 VTT-10 VTT-800 780 VTT-10 VTT-400 390 3 3 pF MAX VTT VTT-640 1000 VTT VTT-320 500 VTT VTT-640 1000 VTT VTT-320 500 UNIT mV mV mV mV mV mV mV mV mV mV mV mV
(1) All typical values are at 25C and with a 3.3-V supply. (2) Outputs are terminated through 50- resistors to VTT, CML level specifications are referenced to VTT and tracks 1:1 with variation of VTT. (3) Outputs are terminated through 25- resistors to VTT; CML level specifications are referenced to VTT and tracks 1:1 with variation of VTT. 3
SN65CML100
SLLS547 - NOVEMBER 2002
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted) PARAMETER tPLH tPHL tr tf tsk(p) tsk(pp) tjit(per) tjit(cc) Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Differential output signal rise time (20% - 80%) Differential output signal fall time (20% - 80%) Pulse skew (|tPHL - tPLH|)(2) Part-to-part skew(3) Period jitter, rms (1 standard deviation)(4) Cycle-to-cycle jitter (peak)(4) Peak-to-peak jitter(4) VID = 0.2 V 750 MHz clock input(5) 750 MHz clock input(6) 1.5 Gbps 223-1 PRBS input(7) 1.5 Gbps 27-1 PRBS input(8) RT = 50 or RT = 25 , See Figure 4 g TEST CONDITIONS MIN 250 250 NOM(1) MAX 800 800 300 300 0 1 8 50 100 5 27 UNIT ps ps ps ps ps ps ps ps
tjit(pp) 30 70 ps tjit(det) Deterministic jitter, peak-to-peak(4) 25 65 ps (1) All typical values are at 25C and with a 3.3-V supply. (2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) Jitter parameters are ensured by design and characterization. Measurements are made with a Tektronix TDS6604 oscilloscope running Tektronix TDSJIT3 software. Agilent E4862B stimulus system jitter 2 ps tjit(per), 16 ps tjit(cc), 25 ps tjit(pp), and 10 ps tjit(det) has been subtracted from the values. (5) VID = 200 mV, 50% duty cycle, VIC = 1.2 V, tr = tf 25 ns (20% to 80%), measured over 1000 samples. (6) VID = 200 mV, 50% duty cycle, VIC = 1.2 V, tr = tf 25 ns (20% to 80%). (7) VID = 200 mV, VIC = 1.2 V, tr = tf 0.25 ns (20% to 80%), measured over 100k samples. (8) VID = 200 mV, VIC = 1.2 V, tr = tf 0.25 ns (20% to 80%). Deterministic jitter is sum of pattern dependent jitter and pulse width distortion.
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SN65CML100
SLLS547 - NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
IIA A VIA VID B VIB IIB Z VOZ Y VOD VOY VOY+VOZ 2
VIA+VIB 2
VIC
Figure 1. Voltage and Current Definitions Table 1. Maximum Receiver Input Voltage Threshold
APPLIED VOLTAGES VIA 1.25 V 1.15 V 4.0 V 3.9 V 0.1 V 0.0 V 1.7 V 0.7 V 4.0 V 3.0 V 1.0 V 0.0 V VIB 1.15 V 1.25 V 3.9 V 4. 0 V 0.0 V 0.1 V 0.7 V 1.7 V 3.0 V 4.0 V 0.0 V 1.0 V RESULTING DIFFERENTIAL INPUT VOLTAGE VID 100 mV -100 mV 100 mV -100 mV 100 mV -100 mV 1000 mV -1000 mV 1000 mV -1000 mV 1000 mV -1000 mV RESULTING COMMONMODE INPUT VOLTAGE VIC 1.2 V 1.2 V 3.95 V 3.95 V 0.5 V 0.5 V 1.2 V 1.2 V 3.5 V 3.5 V 0.5 V 0.5 V OUTPUT
H L H L H L H L H L H L
H = high level, L = low level Y VOD Z VOY VOZ RT + _ VTT RT
Figure 2. Output Voltage Test Circuit
Y Driver Device Z RT1 VTT RT2 RT1 = RT2 = RT VOD Receiver Device
Figure 3. Typical Termination for Output Driver
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SN65CML100
SLLS547 - NOVEMBER 2002
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PARAMETER MEASUREMENT INFORMATION
RT1 A VIA VID B VIB Y 1 pF Z VOY R T2 VOZ VTT
VIA VIB
1.4 V 1V 0.4 V 0V -0.4 V tPHL 80% tPLH 100% 0V 0% tr
RT1 = RT2 = RT VID
VOY - VOZ tf
20%
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 0.25 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 4. Timing Test Circuit and Waveforms
PIN ASSIGNMENTS
D AND DGK PACKAGE (TOP VIEW)
NC A B VBB
1 2 3 4
8 7 6 5
VCC
Y Z GND
PIN DESCRIPTIONS PIN A, B Y, Z VBB VCC GND NC FUNCTION Differential inputs Differential outputs Reference voltage output Power supply Ground No connect FUNCTION TABLE DIFFERENTIAL INPUT VID = VA - VB VID 100 mV -100 mV < VID < 100 mV VID -100 mV Open OUTPUTS Y H ? L ? Z L ? H ?
H = high level, L = low level, ? = intermediate
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SN65CML100
SLLS547 - NOVEMBER 2002
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT VCC A VCC VCC B OUTPUT VCC
Y
Z
7V
7V 7V 7V
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SN65CML100
SLLS547 - NOVEMBER 2002
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREQUENCY
12 10 I CC - Supply Current - mA 12
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
V OD - Differential Output Voltage - mV
DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY
1000 VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 200 mV, RT = 50
I CC - Supply Current - mA
10
900
VTT = 3.3 V
8 6 4 2 0 VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 200 mV, RT = 50 , VTT = 2.5 V 0 250 500 750 1000
8 6 VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, f = 750 MHz, RT = 50 , VTT = 2.5 V -40 -20 0 20 40 60 80 100
800
700
4 2 0
VTT = 1.7 V
VTT = 2.5 V
600
500 100
200
f - Frequency - MHz
TA - Free-Air Temperature - C
300 400 500 600 f - Frequency - MHz
700
800
Figure 5 DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY
500 V OD - Differential Output Voltage - mV t pd - Propagation Delay Time - ps VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 200 mV, RT = 25
Figure 6 PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE
500 t pd - Propagation Delay Time - ps 475 VCC = 3.3 V, TA = 25C, VID = 200 mV f = 25 MHz, RT = 50 , VTT = 2.5 V 500 475
Figure 7 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, f = 25 MHz, RT = 50 , VTT = 2.5 V tPHL tPLH
450
VTT = 3.3 V
tPLH
450 425 400
450
400 VTT = 2.5 V VTT = 1.7 V
tPHL
425
350
400 375 350 -40
300
375 350
250 100
200
300 400 500 600 f - Frequency - MHz
700
800
0
0.5
1
1.5
2
2.5
3
3.5
4
-20
0
20
40
60
80
100
VIC - Common Mode Input Voltage - V
TA- Free-Air Temperature - C
Figure 8 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
30 VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, RT = 50 , VTT = 1.7 V, f = 25 MHz tPHL tPLH 25 Peak-To-Peak Jitter - ps 20 15 10
Figure 9 PEAK-TO-PEAK JITTER vs FREQUENCY
35 VCC = 3.3 V, TA = 25C, VIC = 1.2 V, RT = 50 , VTT = 2.5 V, Input = Clock 30 Peak-To-Peak Jitter - ps 25 20 15 10 5 0 200
Figure 10 PEAK-TO-PEAK JITTER vs DATA RATE
VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 0.8 V RT = 50 , VTT = 2.5 V Input = 223-1 PRBS VID = 0.5 V
650 t pd - Propagation Delay Time - ps 625 600 575 550 525 500 -40
VID = 0.3 V VID = 0.5 V VID = 0.8 V
5 0 100
VID = 0.3 V
-20
0
20
40
60
80
100
200
300
400
500
600
700
800
400
600
800
1000 1200 1400 1600
TA- Free-Air Temperature - C
f - Frequency - MHz
Data Rate - Mbps
Figure 11 8
Figure 12
Figure 13
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SN65CML100
SLLS547 - NOVEMBER 2002
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK JITTER vs COMMON MODE INPUT VOLTAGE
30 VCC = 3.3 V, TA = 25C, RT = 50 , VTT = 2.5 V Input = Clock VID = 0.8 V VID = 0.5 V 10 VID = 0.3 V
PEAK-TO-PEAK JITTER vs COMMON MODE INPUT VOLTAGE
60 VCC = 3.3 V, TA = 25C, RT = 50 , VTT = 2.5 V Input = 223-1 PRBS VID = 0.5 V VID = 0.8 V VID = 0.3 V Peak-To-Peak Jitter - ps 25 30
PEAK-TO-PEAK JITTER vs DATA RATE
VCC = 3.3 V, TA = 25C, VIC = 1.2 V, |VID| = 200 mV, Input = 223-1 PRBS, RT = 50
25 Peak-To-Peak Jitter - ps 20
50 Peak-To-Peak Jitter - ps 40 30
20
VTT = 1.7 V
15
15
20 10
VTT = 2.5 V VTT = 3.3 V
5 0 0 0.5 1 1.5 2
10
0 2.5 3 3.5 4 0 VIC - Common Mode Input Voltage - V 0.5 1 1.5 2 2.5 3 3.5 VIC - Common Mode Input Voltage - V 4
5 200
400
600
800
1000 1200 1400 1600
Data Rate - Mbps
Figure 14 PEAK-TO-PEAK JITTER vs DATA RATE
VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 200 mV, Input = 223-1 PRBS, RT = 25
Figure 15
Figure 16
25
Peak-To-Peak Jitter - ps
20
1.5 Gbps 223-1 PRBS
15
VTT = 1.7 V
Vertical Scale = 250 mV/div
10
VTT = 2.5 V
750 MHz
VTT = 3.3 V 5 200 400 600 800 1000 1200 1400 1600 Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 25
Data Rate - Mbps
Figure 17
Figure 18
1.5 Gbps 223-1 PRBS
1.5 Gbps 223-1 PRBS
Vertical Scale = 500 mV/div
Vertical Scale = 250 mV/div
750 MHz
750 MHz
Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 50
Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 25
Figure 19
Figure 20 9
SN65CML100
SLLS547 - NOVEMBER 2002
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TYPICAL CHARACTERISTICS
1.5 Gbps 223-1 PRBS
1.5 Gbps 223-1 PRBS
Vertical Scale = 500 mV/div
Vertical Scale = 250 mV/div
750 MHz
750 MHz
Horizoontal Scale = 200 ps/div VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 50
Horizoontal Scale = 200 ps/div VCC = 3.3 V, TA = 25C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 25
Figure 21
Figure 22
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SN65CML100
SLLS547 - NOVEMBER 2002
TYPICAL CHARACTERISTICS
Power Supply 1 + 3.3 V -
Power Supply 2
+ VTT - J3 DUT GND J4 J5 100 J2 EVM GND J1 VCC
J6 J7 DUT 50 Matched Cables SMA to SMA EVM Oscilloscope 50
Pattern Generator
Matched Cables SMA to SMA
Figure 23. Jitter Setup Connections for SN65CML100
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SN65CML100
SLLS547 - NOVEMBER 2002
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APPLICATION INFORMATION
For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. When VBB is used, decouple VBB via a 0.01-F capacitor and limit the current sourcing or sinking to 0.4 mA. When not used, VBB should be left open. TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, ETC.)
3.3 V or 5 V ECL B 50 50 50 VTT = VCC -2 V VTT 50 A 3.3 V SN65CML100
Figure 24. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V CML B 50 50 A 3.3 V SN65CML100
VTT
Figure 25. Current-Mode Logic (CML)
3.3 V 50 ECL 50 VTT 3.3 V A
VBB
SN65CML100
B VTT = VCC -2 V
Figure 26. Single-Ended (LVPECL)
3.3 V or 5 V LVDS 50 50 A 100 B 3.3 V SN65CML100
Figure 27. Low-Voltage Differential Signaling (LVDS)
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SN65CML100
SLLS547 - NOVEMBER 2002
MECHANICAL DATA
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES:A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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SN65CML100
SLLS547 - NOVEMBER 2002
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MECHANICAL DATA
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,08 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/C 08/01 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
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