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TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
D D D D D D D
Organization - TM16ER72HP-xx . . . 16 777216 x 72 Bits - TM16ER72LP-xx . . . 16 777216 x 72 Bits Single 3.3-V Power Supply (10% Tolerance) JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Buffer for Use With Socket TM16ER72xP-xx -- Uses 18 64M-Bit High-Speed (16M x 4-Bit) Dynamic RAMs High-Speed, Low-Noise LVTTL Interface High-Reliability 32-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGE Suffix) Intended for Workstation / Server Applications
D D D D D D
Long Refresh Periods: - TM16ER72HP: 64 ms (4 096 Cycles) - TM16ER72LP: 64 ms (8 192 Cycles) 3-State Output Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Ambient Temperature Range 0C to 70C Gold-Plated Contacts Performance Ranges
ACCESS TIME tRAC (MAX) 40 ns 50 ns 60 ns ACCESS ACCESS EDO TIME TIME CYCLE tCAC tAA tHPC (MAX) (MAX) (MIN) 11 ns 20 ns 16 ns 13 ns 25 ns 20 ns 15 ns 30 ns 25 ns
description
The TM16ER72HP is a 128M-byte, 168-pin, buffered dual-in-line memory module (DIMM). The DIMM is composed of eighteen TMS465409, 16 777 216 x 4-bit 4K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic thin small-outline package (TSOP) (DGE suffix), and two SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16ER72LP is a 128M-byte, 168-pin, buffered DIMM. The DIMM is composed of eighteen TMS464409, 16 777 216 x 4-bit 8K-refresh EDO DRAMs, each in a 400-mil, 32-pin plastic TSOP (DGE suffix), and two SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). These modules are intended for multimodule workstation / server applications where buffering is needed for address and control signals. Two copies of address 0 (A0 and B0) are defined to allow maximum performance for 4-byte applications that interleave between two 4-byte banks. A0 is common to the DRAMs used for DQ0-DQ31, while B0 is common to the DRAMs used for DQ32-DQ63.
operation
The TM16ER72xP operates as eighteen TMS46x409s that are connected as shown in the TM16ER72xP functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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1
PRODUCT PREVIEW
'16ER72xx-40 '16ER72xx-50 '16ER72xx-60
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM16ER72xP ( SIDE VIEW )
PIN NOMENCLATURE - TM16ER72HP A[0:11] A[0:11] B0 DQ[0:63] CB[0:7] CAS0 and CAS4 ID[0:1] RAS0 and RAS2 WE0 and WE2 OE0 and OE2 NC PD[1:8] PDE VDD VSS Row Address Inputs Column Address Inputs Addr0 for Bank 2 Devices Data In / Data Out Check Bit In / Check Bit Out Column-Address Strobe ID Pins Row-Address Strobe Write Enable Output Enable No-Connect Pin Presence Detect Presence Detect Enable 3.3-V Supply Ground
1
10 11
PRODUCT PREVIEW
PIN NOMENCLATURE - TM16ER72LP A[0:12] A[0:10] B0 DQ[0:63] CB[0:7] CAS0 and CAS4 ID[0:1] RAS0 and RAS2 WE0 and WE2 OE0 and OE2 NC PD[1:8] PDE VDD VSS Row Address Inputs Column Address Inputs Addr0 for Bank 2 Devices Data In / Data Out Check Bit In / Check Bit Out Column-Address Strobe ID Pins Row-Address Strobe Write Enable Output Enable No-Connect Pin Presence Detect Presence Detect Enable 3.3-V Supply Ground
40
41
PRESENCE DETECT PIN PD1 PD2 PD3 PD4 PD5 PD6 PD7 84 PD8 ID0 ID1 - 40 1 1 1 1 1 1 0 0 0 0 -50 1 1 1 1 1 0 0 0 0 0 - 60 1 1 1 1 1 1 1 0 0 0
2
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AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAA A AA AA A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAA
NO. 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN NAME RAS0 CAS0 DQ15 VDD DQ14 DQ13 DQ12 DQ10 DQ11 VDD WE0 VDD NC VDD DQ4 VSS DQ9 DQ8 DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VSS DQ0 VSS A0 OE0 VSS NC CB1 CB0 A12 A10 NC NC NC A8 A6 A4 A2 NO. 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
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PIN NAME
Pin Assignments
DQ31
DQ30
DQ29
VDD DQ28
DQ27
DQ26
DQ25
VSS DQ24
DQ17
VSS DQ16
CAS4
RAS2
WE2
VDD NC
VSS OE2
CB3
CB2
NC
NC
NO.
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PIN NAME
DQ42
VSS DQ41
DQ40
DQ39
DQ38
DQ37
VDD DQ36
DQ35
DQ34
DQ33
VSS DQ32
NO.
140
VSS 139AAAAAA DQ48
138
137
136
135
134
133
132
131
130AAAAAA NC
129
128
127
PIN NAME
DQ49
SMMS694 - AUGUST 1997
VDD NC
PDE
VSS NC
CB7
CB6
NC
NC
NC
PRODUCT PREVIEW
DQ23
DQ22
DQ21
VDD DQ20
DQ19
DQ18
VDD
VSS PD1
PD7
PD5
PD3
ID0
NC
NC
NC
NC
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126 125 124 123 122 121 120 109 108 107 106 105 104 103 102 101 100 119 118 117 116 115 114 113 112 110 111 99 DQ47 VDD DQ46 DQ45 DQ44 DQ43 VDD NC VDD NC VSS A1 VSS NC CB5 CB4 A11 NC NC NC NC NC NC B0 A9 A7 A5 A3 168 167 166 165 164 163 162 161 160 159 158 157 156AAAAAA DQ59 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 DQ63 DQ62 DQ61 VDD DQ60 DQ58 DQ57 VSS DQ56 DQ55 DQ54 DQ53 VDD DQ52 DQ51 DQ50 VDD VSS PD2 PD8 PD6 PD4 ID1 NC NC NC NC
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TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
buffered dual-in-line memory module and components
The buffered dual-in-line memory module and components include:
D D D
PC substrate: 1,27
" 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM16ER72xP
RAS0 WE0 OE0 CAS0 CAS DQ[0:3] DQ[0:3] CAS DQ[4:7] DQ[0:3] CAS DQ[8:11] DQ[0:3] CAS DQ[12:15] DQ[0:3] CAS CB[0:3] DQ[0:3] CAS DQ[16:19] DQ[0:3] CAS DQ[20:23] DQ[0:3] CAS DQ[24:27] DQ[0:3] CAS DQ[28:31] DQ[0:3] OE OE OE OE OE OE OE OE OE W U0 RAS DQ[32:35] RAS DQ[36:39] RAS DQ[40:43] RAS DQ[44:47] RAS CB[4:7] RAS DQ[48:51] RAS DQ[52:55] RAS DQ[56:59] RAS DQ[60:63] RAS2 WE2 OE2 CAS4 CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] CAS DQ[0:3] OE OE OE OE OE OE OE OE OE W RAS
UB0
PRODUCT PREVIEW
W U1
W
RAS
UB1
W U2
W
RAS
UB2
W U3
W
RAS
UB3
W U8
W
RAS
UB8
W U4
W
RAS
UB4
W U5
W
RAS
UB5
W U6
W
RAS
UB6
W U7
W
RAS
UB7
A0 B0 A[1:n]
U[0:8] UB[0:8] A[1:n]: U[0:8], UB[0:8]
VDD
U[0:8], UB[0:8] Two 0.1 F (Minimum) per DRAM
VSS
U[0:8], UB[0:8]
4
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TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM16ER72xP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
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PRODUCT PREVIEW
AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A
MIN 3 2 0 NOM MAX UNIT V V V V VDD VSS VIH VIL TA Supply voltage Supply voltage 3.3 0 3.6 High-level input voltage Low-level input voltage Ambient temperature - 0.3 VDD + 0.3 0.8 70 C
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
TM16ER72HP
PARAMETER VOH VOL II IO ICC1 High-level output g voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA LVTTL LVCMOS LVTTL '16ER72HP-40 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '16ER72HP-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '16ER72HP-60 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX UNIT V V A A
IOL = 100 A LVCMOS VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC VDD = 3.6 V, CASx high VDD = 3.6 V, VO = 0 V to VDD,
Minimum cycle
2 880
2 340
1 980
mA
PRODUCT PREVIEW
ICC2
Average standby g y current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
18
18
18
mA
9
9
9
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
2 880
2 340
1 980
mA
ICC4 ICC5
2 700 2 880
2 160 2 340
1 800 1 980
mA mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
6
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SMMS694 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM16ER72LP
PARAMETER VOH VOL II IO ICC1 High-level output g voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA LVTTL LVCMOS LVTTL '16ER72LP-40 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '16ER72LP-50 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX '16ER72LP-60 MIN 2.4 VDD - 0.2 0.4 0.2 20 20 MAX UNIT V V A A
IOL = 100 A LVCMOS VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC VDD = 3.6 V, CASx high VDD = 3.6 V, VO = 0 V to VDD,
Minimum cycle
2 250
1 800
1 620
mA
ICC2
Average standby g y current
VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
9
9
9
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
2 250
1 800
2 250
mA
ICC4 ICC5
2 520 2 880
1 980 2 340
1 620 1 980
mA mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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PRODUCT PREVIEW
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high
18
18
18
mA
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(A) Ci(OE) Ci(CAS) Ci(RAS) Ci(W) Co Input capacitance, A0 - A10 Input capacitance, OEx Input capacitance, CASx Input capacitance, RASx Input capacitance, WEx Output capacitance '16ER72xP MIN MAX 6 6 6 65 6 9 UNIT pF pF pF pF pF pF
NOTE 2: VDD = NOM supply voltage 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3)
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tREZ tCEZ tOEZ tWEZ Access time from column address (see Note 4) Access time from CASx (see Note 4) Access time from CASx precharge (see Note 4) Access time from RASx (see Note 4) Access time from OEx (see Note 4) Delay time, CASx to output in low impedance Output buffer turn off delay from RASx (see Note 5) Output buffer turn off delay from CASx (see Note 5) Output buffer turn off delay from OEx (see Note 5) Output buffer turn off delay from WEx (see Note 5) 2 3 5 5 3 11 16 16 11 '16ER72xP-40 MIN MAX 25 16 27 45 16 2 3 5 5 3 13 18 18 13 '16ER72xP-50 MIN MAX 30 18 33 50 18 2 3 5 5 3 15 20 20 15 '16ER72xP-60 MIN MAX 35 20 40 60 20 UNIT ns ns ns ns ns ns ns ns ns ns
PRODUCT PREVIEW
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in must not be driven until one of the applicable maximum values is satisfied.
EDO timing requirements
'16ER72xP-40 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tOCH tCP tOEP Cycle time, EDO page mode, read-write Cycle time, EDO read-write Delay time, RASx active to CASx precharge Hold time, OEx from CASx Hold time, output from CASx Pulse duration, CASx active Pulse duration, WEx active (output disable only) Setup time, OEx before CASx Pulse duration, CASx precharge Precharge time, OEx 16 45 34 5 5 6 5 5 6 5 10 000 MAX '16ER72xP-50 MIN 20 55 38 7 5 8 5 5 8 5 10 000 MAX '16ER72xP-60 MIN 25 64 46 10 5 10 5 5 10 5 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns
8
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TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
ac timing requirements (see Note 3)
'16ER72xP-40 MIN tRC tRWC tRASP tRAS tRP tWP tRASS tRPS tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tWTS tCSR tCAH tDH tRAH tRCH tRRH tWCH tROH tWRH tWTH tCHR tOEH tCHS tRHCP tAWD tCPW tCRP tCWD tOED tRAD Cycle time, random read or write Cycle time, read-write Pulse duration, RASx active, fast page mode (see Note 6) Pulse duration, RASx active, non-page mode (see Note 6) Pulse duration, RASx precharge Pulse duration, write command Pulse duration, RASx active, self-refresh (see Note 9) Pulse duration, RASx precharge after self-refresh Setup time, column address Setup time, row address Setup time, data in (see Note 7) Setup time, read command Setup time, write command before CASx precharge Setup time, write command before RASx precharge Setup time, write command before CASx active (early-write only) Setup time, WEx high before RAS low (CBR refresh only) Setup time, WEx low before RAS low (test mode only) Setup time, CASx referenced to RASx ( CBR refresh only ) Hold time, column address Hold time, data in (see Note 7) Hold time, row address Hold time, read command referenced to CASx (see Note 8) Hold time, read command referenced to RASx (see Note 8) Hold time, write command during CASx active ( early-write only ) Hold time, RASx referenced to OEx Hold time, WEx high after RAS low (CBR refresh) Hold time, WEx low after RAS low (test mode only) Hold time, CASx referenced to RASx ( CBR refresh only ) Hold time, OEx command Hold time, CASx active after RASx precharge (self-refresh) Hold time, RASx active from CASx precharge Delay time, column address to write command ( read-write only ) Delay time, WEx low after CASx precharge (read-write only) Delay time, CASx precharge to RASx Delay time, CASx to write command ( read-write only ) Delay time, OEx to data in Delay time, RASx to column address (see Note 9) With ac parameters, it is assumed that tT = 2 ns. In a read-write cycle, tRWD and tRWL must be observed. Referenced to the later of CASx or WEx in write operations Either tRCH or tRRH must be satisfied for a read cycle. The maximum value is specified only to ensure access time. 69 97 40 100 000 40 25 7 7 7 0 5 5 0 7 8 0 7 7 3 12 11 4 0 -2 7 6 8 8 4 12 12 27 34 37 3 31 13 12 30 10 000 MAX '16ER72xP-50 MIN 84 116 50 100 000 50 30 9 9 9 0 5 5 0 9 10 0 7 7 3 8 13 6 0 -2 9 8 10 10 6 14 14 33 41 45 3 35 15 8 20 10 000 MAX '16ER72xP-60 MIN 104 140 60 100 000 60 40 11 11 11 0 5 5 0 11 12 0 7 7 3 10 15 8 0 -2 11 10 12 12 8 16 16 40 48 54 3 39 17 10 25 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 3. 6. 7. 8. 9.
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9
PRODUCT PREVIEW
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
ac timing requirements (see Note 3) (continued)
'16ER72xP-40 MIN tRAL tCAL tRCD tRPC tRSH tRWD tTAA tTCPA tTRAC tREF Delay time, column address to RASx precharge Delay time, column address to CASx precharge Delay time, RASx to CASx ( see Note 9) Delay time, RASx precharge to CASx Delay time, CASx active to RASx precharge Delay time, RASx to write command (read-write only) Access time from address (test mode) Access time from column precharge (test mode) Access time from RASx (test mode) Refresh time interval 2 25 14 12 3 16 92 30 35 17 32 30 2 31 MAX '16ER72xP-50 MIN 30 17 10 3 18 67 35 40 55 32 30 2 39 MAX '16ER72xP-60 MIN 35 23 12 3 20 79 40 45 65 32 30 20 47 MAX UNIT ns ns ns ns ns ns ns ns ns ms ns
tT Transition time NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 9. The maximum value is specified only to ensure access time.
PRODUCT PREVIEW
10
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TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
device symbolization (TM16ER72HP illustrated)
TM16ER72HP Buffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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PRODUCT PREVIEW
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
MECHANICAL DATA
BU (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.255 (31,88) 1.245 (31,62) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088183/A 07/97
PRODUCT PREVIEW
0.125 (3,18) 0.118 (3,00) DIA 2 Places
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM16ER72HP 16777216 BY 72-BIT TM16ER72LP 16777216 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES
SMMS694 - AUGUST 1997
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
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PRODUCT PREVIEW
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Copyright (c) 1998, Texas Instruments Incorporated

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