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Designing Low Cost Buck Regulators Using The TL5001A
TL5001AEVM - 108/109/110
User's Guide
June 1999
Mixed-Signal Products
SLVU014
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated
Information About Cautions and Warnings
Preface
Read This First
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
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iii
iv
Running Title--Attribute Reference
Contents
1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5 Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.6 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.7 Test Results (SLVP108) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Design Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Duty Cycle Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Snubber Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-2 2-3 2-3 2-3 2-4 2-4 2-5 2-5 2-6
2
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 2-1 2-2 2-3 2-4 2-5 Typical Buck Converter Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 SLVP108/109/110 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Bottom Layer (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Silk Screen (Top Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Drill Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Top Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 VDRAIN-To-GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Power Switch Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Power Switch Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Control Loop Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Uncompensated Open-Loop Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Error-Amplifier Compensation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Error-Amplifier Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 System Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Tables
1-1 2-1 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
vi
Chapter 1
Hardware
The TL5001AEVM-108, TL5001AEVM-109, and TL5001AEVM-110 (SLVP108, SLVP109, and SLVP110) Buck Regulator DC/DC Converter Modules provide the user with a cost-effective solution for providing power to a high performance DSP such as the Texas Instruments TMS320C6201. The SLVP108 is a nominal 5-V input to 3.3-V output regulator. The SLVP109 is a 5-V to 2.5-V regulator, and the SLVP110 is a 5-V to 1.8-V regulator, all rated for up to 3-A output current. The SLVP108/109/110 converters provide a lowercost replacement for the SLVP101/102/103 converters at the expense of 3% output voltage tolerance instead of the 1% for the latter modules. This chapter includes the following topics:
Topic
1.1 1.2 1.3 1.4 1.5 1.6 1.7
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Test Results (SLVP108) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Hardware
1-1
Introduction
1.1 Introduction
Low cost and simplicity of design make buck converters popular solutions in dc/dc step-down applications where lack of isolation from the input source is not a concern. Figure 1-1 shows a diagram of a typical buck converter. The converter passes a duty-cycle modulated pulse waveform through a low-pass output filter (L1, C2) to produce a dc voltage. An error amplifier senses the output voltage, compares it to a reference voltage and adjusts the width of the power switch (Q1) on time, to maintain the desired output voltage. A commutating diode (CR1) provides a path for inductor current to continue to flow when the power switch is turned off.
Figure 1-1. Typical Buck Converter Schematic Diagram
Q1 VI + R3 C1 Controller CR1 R1 FB R2 + C2 L1 VO
These Converter Modules are designed to provide I/O power (3.3 V) and Internal Core power (2.5 V, 1.8 V for Rev. 3 devices) to the Texas Instruments TMS320C6201 DSP. These modules satisfy all of the requirements for powering this high performance DSP such as low cost, low parts count, good transient response and excellent output voltage accuracy. The TMS320C6201 DSP requires 3.3 V for I/O power and 2.5 V (1.8 V for Rev. 3) for Internal Core power. In order to provide power to this device, separate supplies must be used for each of the two voltages and proper power sequencing to the device must be provided. Both power supplies should always be brought up simultaneously to protect the device. If this is not possible, then the I/O supply (DVdd) must not exceed the core supply (CVdd) by more than 2 V, and CVdd must not exceed DVdd by more than 0.5 V. Both power supplies should achieve 95% of their voltage level within a 25-ms window, and should be able to handle an output current of 3 A (maximum consumption by the device). In order to implement this modular approach to generating the required supply voltages, external circuitry must be added to insure that the sequencing requirements of the previous paragraph are met. The SLVP108, SLVP109, and SLVP110 buck converters use the Texas Instruments TL5001A PWM controller to give power supply outputs of 3.3 V,
1-2
Introduction
2.5 V, and 1.8 V at 0-A to 3-A with a 3% output voltage tolerance. Also featured in this design is the TPS2817 MOSFET driver IC. These converters operate over an input voltage range of 4.5-V to 6-V with typical efficiencies of 90% for 3.3 V out and 80% for 1.8 V out. Chapter 2 lists full design specifications. The TL5001A controller IC provides the oscillator, the PWM comparator, undervoltage lock-out, and short circuit protection for the power supply. The oscillator sets the switching frequency. The PWM comparator compares the error amplifier output to a ramp voltage to produce the required pulse width for output voltage regulation. Undervoltage lock-out prevents the power supply from attempting to run when the input voltage is not sufficient for proper operation. Short circuit protection prevents accidental short circuits applied to the output from destroying the power supply. Note: The short circuit protection circuit provides protection from short circuits only. If the output load current is increased beyond the rated value, damage may occur to the power supply, i.e., short circuit protection does not imply overload protection.
Hardware
1-3
Vo 0 - 3A Vo Vo 0.1 F 12 C3 11
9 10 1 2 3
MBRS340T3
1-4
P1 VSENSE Vin 4.5 - 6 V Vin Vin GND GND GND GND D1 C6 2200 pF GND 8 7 U1 TPS2817DBV 6 R2 4.7 + C7 100 F 5 4 5 4 C2 0.1 F 3 + C1 100 F 2 1 Q1 IRF7404 R6 4.7 L1 0.10 H L2 10 H C9 10 F C12 0.1 F U2 TL5001 2 VCC 6 DTC R1 1 K C4 0.1 F 1 Note 1 SLVP108 (3.3V) R8 = 432 SLVP109 (2.5V) R8 = 665 SLVP110 (1.8V) R8 = 1.24 k C5 0.1 F 5 COMP OUT FB 3 4 R7 1.00 K C8 1500 pF R4 620 C11 0.056 F R9 300 C13 0.022 F 7 SCP RT GND R3 8 13.7 K C10 R5 27.4 K 0.01 F R8 Note 1
1.2 Schematic
Schematic
Figure 1-2. SLVP108/109/110 Schematic Diagram
Hardware
Test Setup
1.3 Test Setup
For initial power up of the SLVP108, the following steps should be followed: 1) If necessary for improved load transient response, connect an external electrolytic capacitor of at least 100 F from the SLVP108 output to ground. The external capacitor is not necessary for proper operation. 2) Connect an electronic load adjusted to draw approximately 1 A at 3.3 V. The exact current is not critical; any nominal current is sufficient. A fixed resistor can also be used in place of the electronic load. The output current 3.3 V where R is the value of the load drawn by the resistor is I O R (3.3) 2 resistor. The power rating of the resistor, PR should be at least 2. R
+
3) Connect a lab power supply to the input of the SLVP108. Make sure that the current limit is set for at least 2 A. Turn the voltage up to 5 V. 4) Now verify that the SLVP108 output voltage (measured at the module output pins) is 3.3 V 0.10 V. 5) For subsequent testing, make sure the lab supply output current capacity and current limit are at least 3.5 A so that the SLVP108 can be operated at maximum load of 3 A. 6) Refer to Section 1.6 for selected typical waveforms and operating conditions for verification of proper module operation. For initial power up of the other converters, simply replace any reference to 3.3 V in the above discussion with a reference to the appropriate output voltage. Figure 1-3 shows the SLVP108 test setup.
1-5
Test Setup
Figure 1-3. Test Setup
Power Supply
-
+
Supply+ Supply- Load- Remote Sense + Load - Load+
1-6
Board Layout
1.4 Board Layout
Figure 1-4. Top Layer
Figure 1-5. Bottom Layer (Top View)
Figure 1-6. Silk Screen (Top Layer)
1-7
Assembly Drawing
Figure 1-7. Drill Drawing
Drill Table Hole Dia (inch) 0.016 0.038 Symbol Quantity 34 12 Plated Yes Yes
+
X
1.5 Assembly Drawing
Figure 1-8. Top Assembly Drawing
1-8
Bill of Materials
1.6 Bill of Materials
Table 1-1. Bill of Materials
Ref Des Part Number
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 L1 L2 P1 Q1 R1 R2 R3 R4 R5 R6 R7 R8A R8B R8C R9 U1 U2 TPS2817DBV TL5001AD 10TPB100M GRM42-6X7R104M016A GRM42-6X7R104M016A GRM42-6X7R104M016A GRM42-6X7R104M016A GRM39X7R222M050A 10TPB100M GRM39X7R152K050A GRM235Y5V106Z016A GRM42-6X7R103M050A GRM40X7R563K050A GRM442-6X7R104M016A GRM40X7R223K050A MBRS340T3 S1008-101K DO3316P-103 PTC36SBBN IRF7404
Description
Capacitor, POSCAP, 100 F, 10 V 20% Capacitor, Ceramic, 0.1 F, 16 V, X7R, 20% Capacitor, Ceramic, 0.1 F, 16 V, X7R, 20% Capacitor, Ceramic, 0.1 F, 16 V, X7R, 20% Capacitor, Ceramic, 0.1 F, 16 V, X7R, 20% Capacitor, Ceramic, 2200 pF, 50 V, X7R, 20% Capacitor, POSCAP, 100 F, 10 V 20% Capacitor, Ceramic, 1500 pF, 50 V, X7R, 10% Capacitor, Ceramic, 10 F, 16 V, Y5V, 80 -20% Capacitor, Ceramic, 0.01 F, 50 V, X7R, 20% Capacitor, Ceramic, 0.056 F, 50 V, X7R, 10% Capacitor, Ceramic, 0.1 F, 16 V, X7R, 20% Capacitor, Ceramic, 0.022 F, 50 V, X7R, 10% Diode, Schottky, 3 A, 40 V Inductor, SM, Shielded, 0.1 H, 2.13 A, 25 m Inductor, 10 H, 3.9 A, 0.025 m Header, Right Angle, 12-pin, 0.1 ctrs, 0.2 pins MOSFET, P-ch, 20 V, 6.8 A, 40 m Resistor, SMD, MF, 1.0 K, 1/16 W, 5% Resistor, SMD, MF, 4.7 , 1/16 W, 5% Resistor, SMD, MF, 13.7 K, 1/16 W, 1% Resistor, SMD, MF, 620 , 1/16 W, 5% Resistor, SMD, MF, 27.4 K, 1/16 W, 1% Resistor, SMD, MF, 4.7 , 1/16 W, 5% Resistor, SMD, MF, 1.00 K, 1/16 W, 1% Resistor, SMD, MF, 432 , 1/16 W, 1% (SLVP108 Only) Resistor, SMD, MF, 665 , 1/16 W, 1% (SLVP109 Only) Resistor, SMD, MF, 1.24 K, 1/16 W, 1% (SLVP110 Only) Resistor, SMD, MF, 300 , 1/16 W, 5% IC, MOSFET Driver, Single Ch, 2 A IC, PWM Controller
Size
D 1206 1206 1206 1206 603 D 603 1210 1206 805 1206 805 SMC 1008 0.51x0.37 0.1 SO-8 603 603 603 603 603 603 603 603 603 603 603 SOT25 SO-8
MFG
Sanyo muRata muRata muRata muRata muRata Sanyo muRata muRata muRata muRata muRata muRata Mot Delevan Coilcraft Sullins IR
TI TI
1-9
Test Results (SLVP108)
1.7 Test Results (SLVP108)
Figure 1-9. Load Regulation
LOAD REGULATION
16.5 V O - Delta Output Voltage - mV V O - Delta Output Voltage - % Delta 4.5 5.0 5.5 6.0 VI - Input Voltage - V V O - Delta Output Voltage - % Delta 13.2 9.9 6.6 3.3 0.0 -3.3 -6.6 -9.9 -13.2 -16.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 -0.1 -0.2 -0.3 -0.4 -0.5 VI = 5 V
Delta
IO - Output Current - A
Figure 1-10. Line Regulation
LINE REGULATION
16.5 V O - Delta Output Voltage - mV 13.2 9.9 6.6 3.3 0.0 -3.3 -6.6 -9.9 -13.2 -16.5 IO = 1.5 A 0.5 0.4 0.3 0.2 0.1 0
1-10
Delta
Test Results (SLVP108)
Figure 1-11. Efficiency
EFFICIENCY 100 90 80 70 Efficiency - % 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Io - Output Current - A VI = 5 V
Figure 1-12. VDRAIN-To-GND Voltage
0
VI = 5 V IO = 1.5 A
1-11
Test Results (SLVP108)
Figure 1-13. Power Switch Rise Time
0
VI = 5 V IO = 2.5 A
Figure 1-14. Power Switch Fall Time
0
VI = 5 V IO = 2.5 A
1-12
Test Results (SLVP108)
Figure 1-15. Output Voltage Ripple
VI = 5 V IO = 3 A
Figure 1-16. Load Transient Response
Output Current - A
1 40
20 Output Voltage - mV 0 -20 -40 VI = 5 V IO = 1 A
0
-60
1-13
1-14
Chapter 2
Design Procedure
The SLVP108, SLVP109, and SLVP110 Buck Regulator DC/DC Converter Modules provide a method for evaluating the performance of the TPS2817 MOSFET driver and the TL5001A PWM controller. The TPS2817 contains all of the circuitry necessary to drive large power MOSFET transistors and includes a voltage regulator for higher voltage applications. This section explains how to construct basic power conversion circuits including the design of the control chip functions and the basic loop. This chapter includes the following topics:
Topic
2.1 2.2 2.3
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Design procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Design Procedure
2-1
Introduction
2.1 Introduction
The SLVP108, SLVP109, and SLVP110 are dc-dc buck converter modules that provide a regulated output voltage at up to 3.0 A with an input voltage range of 4.5 V to 6 V. The controller is a TL5001A PWM operating at a nominal frequency of 400 kHz. The TL5001A is configured for a maximum duty cycle of 100 percent and has soft-start and short-circuit protection built in. The output voltage has a 3% tolerance. Using the procedure given below, the user can modify this design for any similar application.
2.2 Operating Specifications
Table 2-1 lists the operating specifications for the SLVP108, SLVP109, and SLVP110.
Table 2-1. Operating Specifications
Specification Input voltage range SLVP108 Static voltage tolerance (see Note 1) SLVP109 SLVP110 Line regulation (see Note 2) Load regulation (see Note 3) Transient response (see Note 4) res onse 100 Output current range (see Note 5) Current limit (see Note 6) Operating frequency Output ripple SLVP108 Efficiency, 3 A load SLVP109 SLVP110 SLVP108 Efficiency, 1.5 A load SLVP109 SLVP110
Unless otherwise specified, all test conditions are TA = 25C, VI = 5 V, IO = 3 A, VO = nominal. Notes: 1) VI = 5 V, IO = 1.5 A. 2) IO = 1.5 A. 3) VI = 5 V 4) VI = 5 V, IO stepped repetitively from 0.1 A to 1.1 A 5) Output current rating is limited by thermal considerations. Load currents above this rating may cause damage to the power supply.
Min 4.5 3.2 2.4 1.7
Typ
Max 6
Units V
3.3 2.5 1.8 4 15 100
3.4 2.6 1.9 mV mV mVpk sec 3 A V
0 NA 400 20 78% 75% 70% 88% 82% 77%
NA kHz mVp-p
2-2
Design Procedures
2.3 Design Procedures
Detailed steps in the design of a buck topology converter may be found in Designing With the TL5001C PWM Controller (literature number SLVA034) from Texas Instruments. This section shows the basic steps involved in this design, for a nominal 3.3-V output.
2.3.1
Duty Cycle Estimate
The duty cycle, D, is the ratio of the power switch conduction time to the period of one switching cycle. An estimate of the duty cycle is used frequently in the following sections. The duty cycle for a continuous mode step-down converter is approximately:
D
+ VVO ) VD *V
I
SAT
From the manufacturer's data sheet for the commutating diode, the forward voltage is VD = 0.45 V at 3-A forward current. Similarly, from the IFR7404 data sheet, the switch ON voltage, VSAT, can be estimated by multiplying the drain-source on resistance, RDS(on), of 40 m by the on state drain current, ID, of 3 A giving 0.12 V. The duty cycle for VI = 4.5, 5, and 6 V is 0.86, 0.77, and 0.64, respectively.
2.3.2
Output Filter
A buck converter uses a single-stage LC filter. Choose an inductor to maintain continuous-mode operation down to 15 percent of the rated output load (This value can range from 5% to 15%):
DIO + 2
0.15
IO
+2
0.15
3
+ 0.9 A
The inductor value needed is :
L
+
VI
* VSAT * VO
DIO
D
t
using a temperature-adjusted VSAT of 0.12 x 1.3 = 0.156:
L
+ (9 * 0.156 * 3.3) 0.90.64
2.5
10 -6
+ 9.86 mH
The two criteria for selecting the output capacitor are the amount of capacitance needed and the capacitor's equivalent series resistance, ESR. After the capacitance and ESR requirements are determined, the capacitor can be selected. Assuming that all of the inductor ripple current flows through the capacitor and the effective series resistance (ESR) is zero, the capacitance needed is:
C
+
8
DIO f DVO
+8
0.45 400 10 3
0.03
+ 4.69 mF
2-3
Design Procedure
Design Procedures
Now, assuming the capacitance is very large, the ESR needed to limit the ripple to 30 mV is:
ESR
+ DVO + 0.03 + 0.033 W 0.9 DI
O
To provide margin, the output filter capacitor should be rated greater than the calculated capacitance and have lower ESR than calculated. Due to available volume, this design uses a 100-F electrolytic in parallel with a 10-F ceramic capacitor. This capacitance provides adequate filtering with good load transient response.
2.3.3
Power Switch
The design uses a p-channel MOSFET to simplify the drive-circuit design and minimize component count. The IRF7404 p-channel power MOSFET is selected for it's low rDS(on) of 40 m and drain-to-source breakdown voltage of 20 V. Power dissipation, which includes both conduction and switching losses, is given by:
PD
+
I O2
r DS(ON)
D
)
0.5
VI
IO
t r)f
f
An example power MOSFET power dissipation calculation follows with the following assumptions: The total switching time, tr+f = 100 ns, An rDS(ON) high temperature adjustment factor = 1.3, A 55C maximum ambient temperature, VI = 5 V and IO = 3 A then :
PD
+ 3.02 (0.040 1.3) + 0.36 ) 0.30 + 0.66 W
TJ
0.77
)
0.5
5
3
100
10 -9
400 kHZ
The thermal impedance, RJA = 90C/W for FR-4 with 2-oz. copper and a one-inch-square pattern, thus:
+ TA )
R qJA
PD
+ 55 ) (90
0.66)
+ 114.4C
Conduction losses are nearly equal to switching losses in this application but may not be in others. It is good practice to check dissipation at the extreme limits of input voltage to find the worst case.
2.3.4
Rectifier
The catch rectifier conducts during the time interval when the MOSFET is off. The MRBS340T3 is a 3-A, 40-V rectifier in a surface-mount SMC package. For the same operating conditions as above, the rectifier power dissipation is:
PD
+ IO
VD
(1-D)
+3
0.45
0.23
+ 0.31 W
2-4
Design Procedures
2.3.5
Snubber Network
A snubber network is usually needed to suppress the ringing at the node where the power switch drain, output inductor, and the rectifier connect. The snubber design is very dependent on PWB layout and component parasitics, but as a starting point, select a snubber capacitor with a value that is 4 to 10 times larger than the estimated capacitance of the catch rectifier. The power dissipated in the snubber resistor is directly proportional to this capacitor value, so this value should be chosen with care. The MBRS340T3 has a capacitance of about 150 pF at a reverse voltage of 5 V. For this design, a capacitor value of 2200 pF was selected. A resistor value of 4.7 was then selected. The resistor value selection is often a trial and error sequence of steps, but it should be chosen so that the snubber RC time constant times 3 is less than the minimum ON time of the power switch. This allows the snubber capacitor to fully charge and discharge during each portion of the switching period.
2.3.6
Controller Functions
The TL5001A controller functions, oscillator frequency, soft-start, dead-time control, and short-circuit protection, are discussed in this section. The oscillator frequency is set by selecting the resistance value from the graph in Figure 6 of the TL5001A data sheet. For 400 kHz, a value of 13.7 k is selected. Dead-time control provides a minimum off-time for the power switch in each cycle. Set this time by connecting a resistor between DTC and GND. For this design, a maximum duty cycle of 100% is chosen. Then R is calculated as:
R DT
+ ROSC ) 1.25 kW + (13.7 kW ) 1.25 kW)
D
[1
* VOSC(0%) ) VOSC(0%) (1.5 * 0.5) ) 0.5] + 22.4 kW
V OSC(100%)
Any value higher than the calculated value will be satisfactory since the duty cycle limit is 100%. A value of 27.4 k is used in this design. Soft-start is added to reduce power-up transients. This is implemented by adding a capacitor across the dead-time resistor. In this design, a soft-start time of 100 s is used:
C
+ 3R
tR
DT
+3
100 10 -6 27.4 kW
+ 0.011 mF a 0.01 mF
The TL5001A has short circuit protection (SCP) instead of a current sense circuit. If not used, the SCP terminal must be connected to ground to allow the converter to start up. If used, a timing capacitor is connected to SCP that should have a time constant that is at least 10 times greater than the soft-start time constant. This time constant is chosen to be 10 ms:
C(mF)
+ 12.46
t SCP
+ 12.46
0.01 s
+ 0.125 mF a 0.1 mF
It should be emphasized here that the power supply is rated for a maximum output current of 3 A. This limit is due to thermal considerations. Although the
Design Procedure
2-5
Design Procedures
power supply has short circuit protection, it does not have overload protection. If a load current in excess of 3 A is applied, the power supply may fail or have a reduced lifetime. In addition, if a short circuit is applied to the power supply, the short-circuit protection internal to the TL5001A will latch the power supply into an OFF state. To reset the latch, power must be removed from the input of the power supply and reapplied after the output short circuit is removed.
2.3.7
Loop Compensation
The control loop for this converter consists of three gains: the power stage (GPS), the error amplifier (GE/A), and the internal TL5001A PWM modulator (GPWM). Figure 2-1 shows a simplified block diagram of the control loop. Negative feedback stabilizes the output voltage against changes in line or load without destroying the control-loop's ability to respond to line and/or load transients. To maintain good performance and stability, it is necessary to tailor the open-loop frequency response of the converter. The frequency response of the error amplifier is shaped by judicious selection of external components to obtain a desired overall open-loop response. This tailoring of the converter frequency response is called loop compensation. A detailed treatment of dc-to-dc converter stability analysis and design is beyond the scope of this report; however, several references on the subject are available.
Figure 2-1. Control Loop Simplified Block Diagram
VI Power Stage Duty Cycle VO
Pulse Width Modulator Error Amplifier Vref
Comp
The following is a simplified approach to designing networks to stabilize continuous mode buck converters that works well when the open-loop gain is below unity at a frequency at least one-half of the switching frequency of the power supply. Before the error-amplifier frequency response can be designed, the frequency response of the rest of the control loop must be determined. As mentioned above, this consists of the power stage gain and phase and the pulse width modulator gain and phase. The first component of the control loop to be determined is the power stage. A gain block and a damped LC filter with a double complex pole can approximate the frequency response of the buck power stage operating in continuous conduction mode. There is also a zero due to the ESR of the
2-6
Design Procedures
external output capacitance. The low frequency magnitude of the gain is the change in output voltage divided by the change in the duty cycle. Without going through the detailed derivation, a simplified expression for the gain of this continuous-mode buck power stage is:
G PS(s)
+ DVO + VI DD
1
R
) RL
R
1
)s
RC
CO L CO
1
)s
RC
CO
L ) R ) s2
) RRC
1 Where:
)s
1
C CER
R RC R)R C
R = load resistance = 1.1 CO = 110-F total output capacitance RC = ESR of aluminum electrolytic capacitance 75 m CCER = 10-F internal ceramic capacitance L = 10-H internal output inductor value RL = equivalent resistance of internal inductor and FET RDS(on) 65 m. The double pole from the LC filter is at a frequency of : 1 2
p
L
CO
1
)
RC R
+ 4.64 kHz
The zero due to the output capacitance and its ESR is at a frequency of : 2
p
1 RC
CO
+ 19.3 kHz
The second component of the control loop to be determined is the pulse width modulator. The response of a voltage-mode pulse-width modulator can be modeled as a simple gain block. The magnitude of the gain is the change in power supply output voltage for a change in the pulse-width-modulator input voltage (error-amplifier COMP voltage). From the TL5001A Data Sheet, Figure 11, PWM Triangle Wave Amplitude vs Frequency, the maximum triangle wave voltage at 400 kHz is approximately 1.5 V and the minimum is 0.5 V. As the error-amplifier voltage swings from 0.5 V to 1.5 V, the power supply output voltage changes from 0 V to 5 V. Thus, the gain, GPWM, is: 5-0 + DV DVO + 1.5-0.5 + 5.0 a 14 dB
O(COMP)
G PWM
Design Procedure
2-7
Design Procedures
The product (sum in dB) of the gains of these two control loop components, the power stage gain, GPS, and the pulsewidth-modulator gain, GPWM, makes up the uncompensated open-loop response. Figure 2-2 is a gain (solid line) and phase (dashed line) graph of the uncompensated open-loop response of the converter obtained from a MathCad analysis. The operating conditions for the graph below are: VI = 5 V, IO = 3 A, CO = 110 F, and RC = 0.075 .
Figure 2-2. Uncompensated Open-Loop Response
50.0 40.0 30.0 20.0 Gain 10.0 Phase 0.0 -10.0 -20.0 -30.0 10 100 1000 Frequency 10000 -225 -270 -315 -360 100000 0 -45 -90 -135 -180 Phase
Gain
Now that the known parts of the control loop are determined, the error-amplifier frequency response can be designed. Unless the designer is trying to meet an unusual requirement, such as very wideband response, many of the decisions regarding gains, compensation pole and zero locations, and unity-gain bandwidth are at the discretion of the designer. Generally, the total open-loop response favored for stability is a 20-dB-per-decade rolloff with a desired phase margin of at least 30 degrees for all conditions. High gain at low frequencies is desired to minimize error in the output voltage and sufficient bandwidth must be designed into the circuit to assure that the converter has good transient response. These requirements can be met by adding compensation components around the error amplifier to modify the total loop response. Therefore, the error amplifier design should provide the following:
-
A pole at dc to give high low frequency gain Two zeroes near the filter poles to correct for phase shift due to the power stage frequency response Two additional poles to roll off high frequency gain
The compensation circuit shown in Figure 2-3 is used to implement the above functions.
2-8
Design Procedures
Figure 2-3. Error-Amplifier Compensation Network
C8
C13 C11 R9 VO R7 VREF - + COMP R4
The first step in the design of the error-amplifier frequency response is the design of the output sense divider. This sets the output voltage, and the top resistor, R7, determines the relative impedance of the rest of the compensation design. A 1-k resistor for the top of the divider gives a divider current of 2.3 mA for an output setting of 3.3 V and a Vref of 1 V. The bottom of the divider (omitted from Figure 2-3 for clarity) is calculated as:
R
+ Vref
R7 V O-V ref
+1 V
1.00 kW V O-1
+ 435 W a 432 W
For 2.5-V operation, this resistor would be 665 and for 1.8-V operation, it would be 1.24 k. The advantage of changing the bottom resistor instead of the top divider resistor is that the compensation does not change with output voltage changes. The disadvantage is that divider current changes with changes in the output voltage and should be sufficient at the lowest voltage to make the error amplifier input bias current insignificant. The transfer function for the circuit in Figure 2-3 is:
V COMP VO
+ (-1) + (-1)
f Z1 f P1 f P2
f Z2 f P3
[1
[s
R7
) s C13 (R7 ) R9)] [1 ) s C11 (C8 ) C11)] [1 ) s R9 C13] 1)s
R4] R4
(C8 C11) (C8)C11)
These poles and zeros must be calculated to adjust the total loop response and desired gain-bandwidth. With R7 already selected, the next step is to calculate the pole at dc (the integrator) in order to give the correct crossover frequency. The capacitance C8 + C11 along with R7 provides this pole and also positions the gain at low frequencies. A crossover frequency of 30 kHz is selected. The higher the crossover, the better the transient response (assuming that the crossover frequency is much less than the operating frequency). At 30 kHz, the gain of the modulator stage, as shown in Figure 2-2, is -11 dB. The sum of this gain, the integrator gain, and the two zeros must equal zero at 30 kHz. The zeros will be positioned around the LC filter poles (~ 4.64 kHz) and will have a gain of: 2 20
Log 30 kHz 4.64 kHz
+ 32.4 dB
Design Procedure
2-9
Design Procedures
Therefore, the required gain due to the integrator is 0 - (11 +32.4) = -21.4 dB, or a voltage gain of 0.0851. The integrator capacitance can now be calculated. In practice, C8 is much smaller than C11 and can usually be ignored:
C11
+2 +2
p
1
f CO
R7
0.0851
+ 0.062 mF a 0.056 mF
The frequency of the first error amplifier zero, fZ1, is used to compensate for one of the LC filter poles (4.64 kHz). Assuming a value for R9 of about 1/3 of R7, then C13 is:
C13
p p
1
f Z1
(R7
) R9) + 0.026 mF a 0.022 mF
The second error amplifier zero, fZ2, also is 4.64 kHz:
R4
+2 +2
1 f Z2
C11
+ 612 W a 650 W
The two high frequency poles are placed well after the crossover frequency but less than the switching frequency. The first one kills the effect of the ESR zero at 19.3 kHz:
R9
p
1 f ESR
C13
+ 375 W a 300 W
The second is an optional high-frequency roll-off filter positioned about half of the operating frequency. Assuming that C8 is much smaller than C11, then the series combination of these capacitors is approximately equal to C8, therefore:
C8
+2
p
1 f P3
R4
+ 1280 pF a 1500 pF
A graph of the error-amplifier response is given in Figure 2-4. The solid line is the gain and the dashed line is the phase.
Figure 2-4. Error-Amplifier Frequency Response
60.0 90 70 50.0 50 Phase - Degrees 40.0 Gain - dB Gain 30.0 -10 Phase 20.0 -30 -50 10.0 -70 0.0 10 100 1000 10000 Frequency - Hz -90 100000 30 10
2-10
Design Procedures
The overall open-loop frequency response of the converter is the product of the uncompensated open-loop response (Figure 2-2) and the error amplifier response (Figure 2-4). A Bode plot of the overall open loop frequency response of the converter is shown below in Figure 2-5. Again, the solid line is the gain and the dashed line is the phase. As seen in the graph, the gain crosses 0 dB in the vicinity of 20 kHz and the phase margin is approximately 100 degrees. It should be emphasized that the power stage gain and hence the overall loop gain is dependent on input voltage, output voltage, output load resistance, and parasitic resistances present in the power stage and external components. The graph below represents a typical operating condition. However, it is good design practice to check for stability at the line voltage extremes and limits of output voltage settings and loads to ensure that variations do not cause problems.
Figure 2-5. System Frequency Response
70 60 50 40 Gain - dB 30 20 10 0 -315 -10 -20 -30 10 100 1000 10000 Frequency - Hz -360 100000 -270 Gain -225 Phase - Degrees Phase -180
Design Procedure
2-11
2-12

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