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Designing with the TL1454 PWM Controller
User's Guide
1998
Mixed Signal Products
Printed in U.S.A. 11/98
SLVU012
Designing with the TL1454 PWM Controller User's Guide
Literature Number: SLVU012 November 1998
Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated
Trademarks
Preface
Read This First
About This Manual
This user's guide reviews the design of two 500 kHz dc-to-dc converters. The first is a 3.3-V, 1.5-A buck converter, and the other is a 12-V, 0.2-A boost converter. Both converters operate from a 4.5-V to 7-V power source. The user's guide also provides a schematic, parts list, measured performance data, and typical waveforms.
How to Use This Manual
This document contains the following chapters:
Trademarks
Chapter 1 Designing with the TL1454 PWM Controller Chapter 2 3.3-V Step-Down Regulator Chapter 3 12-V Step-Up Regulator Chapter 4 Test Results Chapter 5 EVM Documentation
Related Documentation From Texas Instruments
TL1454 Dual-Channel PWM controller data sheet (literature number SLVS086) TPS1110 Single P-Channel Logic Level MOSFETs data sheet (literature number SLVS100) Designing with the TL5001 (literature number SLVA034A)
TI is a trademark of Texas Instruments Incorporated.
Read This First
iii
iv
Running Title--Attribute Reference
Contents
1 Designing with the TL1454 PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Buck Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Boost Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Short Circuit Protection (SCP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-4 1-5 1-6 1-7 1-7 1-7
2
3.3-V Step-Down Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Duty-Cycle Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Output Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Power-Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.1 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.2 Catch Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.4.3 Catch-Rectifier Snubber Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5 Dead-Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.6 Soft-Start Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.7 Output Sense Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.8 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.8.1 Buck Power Stage and Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.8.2 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 12-V Step-Up Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Duty Cycle Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Power-Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.2 Output Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.3 Output-Rectifier Snubber Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5 Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.6 Soft-Start Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.7 Output Sense Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.8 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.8.1 Boost Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.8.2 Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.8.3 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3
Chapter Title--Attribute Reference
v
Contents
4
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 EVM Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 5-3 5-5
5
vi
Running Title--Attribute Reference
Figures
1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 5-1 5-2 5-3 Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 TL1454 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Typical Buck Converter Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Typical Boost Converter Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 PWM Triangle Wave Amplitude vs. Timing Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Buck Uncompensated Loop Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Buck Compensation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Buck Compensated Open Loop Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Control Loop Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Boost Uncompensated Loop Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Boost Compensation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Boost Compensated Open Loop Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 SLVP085 Measured Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 SLVP085 Measured Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 SLVP085 Measured Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 SLVP085 CR2-Cathode Switching Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 SLVP085 3.3-V Output Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 SLVP085 3.3-V Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 SLVP085 3.3-V Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 SLVP085 Q1 VDS Switching Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 SLVP085 12-V Output Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 SLVP085 12-V Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 SLVP085 12-V Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Dual Regulator EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 EVM Board Layout Component Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 EVM Board Layout Solder Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Contents
vii
Running Title--Attribute Reference
Tables
1-1 4-1 4-2 5-1 Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V Measured Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-V Measured Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 4-4 4-4 5-3
viii
Chapter 1
Designing with the TL1454 PWM Controller
With the trend in electronics of downsizing, both in hardware and power, the pulse-width-modulation (PWM) method is frequently used in power supply circuits. High-frequency operation enables an increase in efficiency and a reduction in size and cost of switching power supplies. The TL1454 is a dual-channel PWM control IC that incorporates all the functions required to control two high-frequency dc-to-dc converters. The TL1454 internally provides undervoltage lockout, short-circuit protection, independent dead time controls, adjustable oscillator, voltage reference, error amplifiers, and drivers for power MOSFET switches in a compact 16-pin package. This user's guide reviews the design of two 500-kHz, dc-to-dc converters, both operating from a 4.5-V to 7-V power source. This user's guide provides a schematic diagram, a parts list, performance data, and typical waveforms. A detailed description of the TL1454 is found in the Power Supply Circuits Data Book, Texas Instruments Literature Number SLVD002. A more detailed explanation of step-down converter design and component selection is available in a related document, Designing with the TL5001, Texas Instruments Literature Number SLVA034A.
Topic
1.1 1.2 1.3 1.4 1.5
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Buck Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Boost Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Designing with the TL1454 PWM Controller
1-1
Introduction
1.1 Introduction
The dual dc-to-dc converter provides a simple power supply solution for applications requiring two independently regulated output voltages, where one of the required voltages is less than the input supply and the other output voltage is higher than the input. The user will save in cost and board space because the power supply and control functions are incorporated in a single IC. Design simplicity and low component count make step-down (buck) converters popular solutions where the regulated output voltage is lower than the input and isolation is not a requirement. Similarly, step-up (boost) converters are popular solutions where the regulated output voltage is higher than the input and isolation is not a requirement. The TL1454 controller provides the following features:
-
3.6-V to 20-V operating input-voltage range 50-kHz to 2-MHz oscillator-frequency range 3.5-mA typical current consumption MOSFET drive outputs for each channel 1.25-V reference voltage Input undervoltage lock out protection Short circuit protection 0% to 100% dead time adjustment range
The TL1454 is available in the D, N, or PW package. The package layout is shown in Figure 1-1.
Figure 1-1. Package Layout
D, N OR PW PACKAGE (TOP VIEW)
CT RT DTC1 IN1 + IN1 - COMP1 GND OUT1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
REF SCP DTC2 IN2 + IN2 - COMP2 VCC OUT2
A functional block diagram of the TL1454 is shown in Figure 1-2. In the TL1454 controller, channel 1 is configured to drive n-channel MOSFETs in boost or flyback converters, and channel 2 is configured to drive p-channel MOSFETs in step-down or inverting converters. The operating frequency is set with an external resistor and an external capacitor, and dead time for each channel is
1-2
Designing with the TL1454 PWM Controller
Introduction
continuously adjustable from 0% to 100% duty cycle with a resistive divider network. Adding a capacitor to the dead-time control (DTC) network provides a soft start capability. The error-amplifier common-mode input range includes ground, which allows the TL1454 to function in ground-sensing battery chargers as well as voltage converters.
Figure 1-2. TL1454 Functional Block Diagram
VCC 10 Voltage REF GND COMP1 IN1 + IN1 - 7 6 4 5 + _ Error Amplifier 1 COMP2 11 13 + IN2 + 12 _ IN2 - Error Amplifier 2 PWM Comparator 2 VCC 1.25 V 2.5 V To Internal Circuitry OSC PWM Comparator 1 RT CT 21 1.8 V 1.2 V VCC 16
REF
8
OUT1
SCP Comparator 2 SCP Comparator 1 1V
UVLO and SCP Latch
9
OUT2
0.65 V
0.65 V 1.25 V
1V
15 SCP
3 DTC1
14 DTC2
Designing with the TL1454 PWM Controller
1-3
Specification Summary
1.2 Specification Summary
When used in the EVM board, the two converter designs in this user's guide meet the performance specifications summarized in Table 1-1. Since the design requires no input-to-output isolation, a discontinuous-mode, step-up (boost) converter is used for the 12-V output. A continuous mode, step-down (buck) converter is used for the 3.3-V output. Both converters operate at a frequency of 500 kHz. In Table 1-1, VO1 is the 12-V boost converter output and is controlled by channel 1 of the TL1454. VO2 is the 3.3-V buck converter output and is controlled by channel 2 of the TL1454.
Table 1-1. Specification Summary
MIN
Input voltage range Ambient temperature range, TA Efficiency Output voltage, VO1 Output current, IO1 Output ripple voltage, VO1(PP) Regulation (VO1) Output voltage, VO2 Output current, IO2 Output ripple voltage, VO2(PP) Regulation (VO2) 0 33 4% 0 120 4% 3.3 1.5 V A mV 4.5 0 80% 12 200 V mA mV
TYP
MAX UNITS
7 55 V C
The design uses surface-mount packages wherever feasible to minimize size and simplify assembly.
1-4
Designing with the TL1454 PWM Controller
Buck Regulator Circuit Operation
1.3 Buck Regulator Circuit Operation
The basic circuit can be represented by an output filter, a controller, and a MOSFET switch and commutating diode providing the switching function. The schematic diagram in Figure 1-3 provides a simplified circuit representation of the buck converter.
Figure 1-3. Typical Buck Converter Schematic Diagram
Q1 VI + C1 FB R2 Controller R3 CR1 R1 + C2 L1 VO
The buck converter passes a duty-cycle-modulated waveform through a lowpass output filter (L1, C2). A controller senses the output voltage, compares it to an internal reference voltage, and adjusts the duty cycle of the power switch (Q1) to maintain the desired output voltage. A commutating diode (CR1) maintains continuous current through the inductor when the power switch is turned off.
Designing with the TL1454 PWM Controller
1-5
Boost Regulator Circuit Operation
1.4 Boost Regulator Circuit Operation
The boost converter circuit can simply be represented by an output filter, a controller, and a MOSFET switch and diode providing the switching function. Figure 1-4 provides a simplified circuit representation of the boost converter.
Figure 1-4. Typical Boost Converter Schematic Diagram
L1 VI + C1 Controller FB R2 Q1 R1 + C2 CR1 VO
The power switch (Q1) turns on to apply the input voltage across the inductor (L1) storing energy in the inductor. When Q1 turns off, the energy in L1 is delivered to the load and output capacitor through the output diode CR1. The controller senses the output voltage, compares it to an internal reference voltage, and adjusts the duty cycle of the power switch (Q1) to maintain the desired output voltage.
1-6
Designing with the TL1454 PWM Controller
Controller Functions
1.5 Controller Functions
The following functions set by the controller govern the operation of both converters. Reference designators refer to components on the Evaluation Module TL1454EVM-085 (EVM), and a schematic for the EVM is given in Figure 5-1.
1.5.1
Oscillator Frequency
Using Figure 6 in the TL1454 data sheet, choose R4 = 10 k and C5 = 120 pF to set the oscillator frequency to fs = 500 kHz (Ts = 2 s). R4 is connected between the RT terminal and ground, and C5 is connected between the CT terminal and ground. Tight tolerance, temperature stable components are recommended for both R4 and C5 to minimize the oscillator frequency variation. R4 is a 1%, metal-film device and C5 is a 10%, or better, NPO ceramic.
1.5.2
Short Circuit Protection (SCP) Timing
In normal operation, the TL1454 SCP terminal (15) is held low at approximately 185 mV. If the switching power supply becomes short-circuited, the protection-enable capacitor (C7) connected externally from the SCP terminal to ground will begin charging. If the voltage across C7 reaches 1 V, the SCP latch is activated and the converter is shut down. The value of C7 is chosen to insure that SCP will not trip during start-up. Selecting a time constant 10 times the output start-up rise time will insure that the short-circuit protection circuit is disabled long enough for the output to come into regulation. The time constant is selected to be 120 ms. The expression to calculate C7 is:
C7
t PE 0.120 + 80300 + 80300 + 1.49 mF 1.5 mF
Designing with the TL1454 PWM Controller
1-7
1-8
Designing with the TL1454 PWM Controller
Chapter 2
3.3-V Step-Down Regulator
The following sections describe the design procedures for this 3.3-V stepdown (buck) regulator. Selection and/or design guidelines for the external power components are given. As stated in the TL1454 data sheet, channel 2 of the controller is configured to control and provide drive signals for a stepdown regulator using a p-channel power MOSFET.
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
Page
Duty-Cycle Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Output Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Power-Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Soft-Start Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Output Sense Network
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
3.3-V Step-Down Regulator
2-1
Duty-Cycle Estimates
2.1 Duty-Cycle Estimates
Before starting the detailed design, the designer should estimate the duty cycle (D) for various input voltages. Duty cycle is the ratio of the power-switch conduction time to the period of the operating frequency. The duty cycle for a step-down converter operating in continuous-mode is stated as:
D
) + VO-V Vd V
I sat
Where: Vd = Catch rectifier conduction voltage (assume 0.6 V) Vsat = Power switch conduction voltage (assume 0.1 V). The duty cycles for VI = 4.5 V, 5 V, and 7 V are 0.89, 0.80, and 0.57, respectively.
2-2
3.3-V Step-Down Regulator
Output Inductor
2.2 Output Inductor
Choose the inductance value to maintain continuous-mode operation down to approximately 10% to 15% of the rated output current. The average of the inductor current is equal to the output current. Since inductor current is triangular in shape, the peak-to-peak value of the current for a load of 10% of rated load will be:
DIL2 + 2(0.1)
I O(Max)
+ 2(0.1) (1.5) + 0.3 A p-p
Worst case ripple current occurs at maximum input voltage. Calculate the inductor value using:
L2
+ I satDI O L2 + 14 mH 10 mH
V -V -V
(D) t s
+ (7-0.1-3.3)(0.57) 2 0.3
10 -6
Use an inexpensive 10-H, 0.052-, 2.6-A surface-mount inductor from Sumida (or equivalent) for this design.
3.3-V Step-Down Regulator
2-3
Output Capacitor
2.3 Output Capacitor
Select the output capacitor to limit the output ripple voltage to the level required by the specification (See Table 1-1). The three elements of a capacitor that contribute to ripple are equivalent series resistance (ESR), equivalent series inductance (ESL), and capacitance. It is necessary to provide a great deal of capacitance to get ESR to acceptable levels. ESL can be a problem at high frequencies. Control ESL by choosing low ESL capacitors, limiting lead length (PCB and capacitor), and replacing one large device with several smaller ones connected in parallel. Assuming that all the inductor ripple current flows through the filter capacitor and ESR is zero, the capacitance needed to limit the ripple voltage to 33 mV p-p is:
C
+
DIL2
8 f s DV O
+ 8 500
0.3 10 3 33
10 -3
+ 2.3 mF
Assuming that the capacitance is very large and does not contribute to ripple, the ESR needed to limit the ripple to 33 mV p-p is:
ESR (max)
+ DVO + DI
L2
33
10 -3 0.3
+ 110 mW
Capacitor ripple current is seldom a problem in low-voltage converters. However, the following formula calculates the rms ripple current:
I C RMS
+ DIL2 63 + DIL2(0.289) + 0.3(0.289) + 86 mARMS
The capacitance and ESR requirements are met with a single 10-F multilayer ceramic capacitor with an ESR less than 10 m. The output inductor, L2, and the capacitor, C17, make up a very high-Q output filter. In order to reduce the Q of the filter, add a larger electrolytic capacitor, C13, and series resistance, R17, in parallel with C17. This reduces the resonant peaking and slows the phase transition of the output filter. C13 is a 100-F, 100-m tantalum capacitor from AVX. R17 is made up of four 1- resistors in parallel. The resulting filter response, offset by the gain of the pulse-width modulator and the dc gain of the power stage, is shown as the buck uncompensated loop response in Figure 2-2.
2-4
3.3-V Step-Down Regulator
2.4 Power-Stage Design
The power-stage design includes selecting the power switch, the catch rectifier, and the rectifier snubbing network (if needed). Also, the design includes calculating the power dissipations, calculating the junction temperatures, and ensuring that the semiconductors have adequate heatsinking.
2.4.1
Power Switch
The power switch uses a P-channel MOSFET that simplifies the drive circuit design and minimizes component count. To meet the preliminary duty cycle estimate, the MOSFET rDS(on) should be less than 0.1 V / 1.5 A = 67 m with a 5 V gate drive and a drain-to-source breakdown voltage rating appropriate for a 7-V supply. The TPS1110 meets these requirements. It is a -7 V P-channel power MOSFET in an SO-8 package with rDS(on) = 65 m typical at VGS = -4.5 V (The voltages are negative because this is a P-channel MOSFET). Power dissipation, which includes both conduction and switching losses, is given by:
PD
+
I O2 r DS(on) (D)
)
0.5 V I I O t (r)f)
fs
where rDS(on) is adjusted for junction temperature and t(r+f) = total MOSFET switching time (turn-on and turn-off) Assuming that the drive circuit is adequate for t(r+f) = 100 ns, and the junction temperature is 100C with a 55C ambient, the rDS(on) of the TPS1110 increases approximately 35%. At 4.5 V input:
PD
+ ) + )
1.5 2 (1.35
0.065)(0.89) 10 -6 500 10 3
0.5(4.5)(1.5) 0.1
+ 345 mW
At 7 V input:
PD
1.5 2 (1.35 0.5(7)(1.5) 0.1
0.065)(0.57) 10 -6 500 10 3
+ 375 mW
The junction temperature can be estimated using a value of 100C/W for the junction-to-ambient thermal impedance, Using the worst case power dissipation from above, the junction temperature is approximately:
TJ
+ TA ) RqJA
PD
+ 55 ) (100)(0.375) + 93C
3.3-V Step-Down Regulator
2-5
The original assumptions turned out to be conservative because the calculated junction temperature is 93C instead of the assumed 100C. Also, the worst case for power dissipation occurs at the maximum input voltage in this application but may not be in others. It is recommended to check dissipation at the extreme limits of input voltage to find the worst case.
2.4.2
Catch Rectifier
When the transistor turns off, the catch rectifier conducts and provides a path for the inductor current. Important criteria for selecting the rectifier include: fast switching, breakdown voltage, current capability, low forward voltage drop, and appropriate packaging. Typically, derating a diode to 50% of its current rating will achieve the proper derating of the junction temperature. Unless the application justifies the expense and complexity of a synchronous rectifier, the best solution for low-voltage outputs is usually a Schottky rectifier. CR2 is an SS32 surface-mount Schottky rectifier with a 20-V breakdown voltage and 3-A current rating. The maximum power dissipation occurs at minimum duty cycle (maximum rectifier conduction time).
PD
+
V d I O (1-D)
+ (0.5)(1.5)(1-0.57) + 323 mW + 55 ) (55)(0.323) + 73C
Junction temperature for this diode may be estimated using a thermal resistance of 55C/W (printed circuit board mounted with 0.55 x 0.55 copper pad area):
TJ
+ TA ) RqJA
PD
2.4.3
Catch-Rectifier Snubber Network
Step-down converters usually suffer from ringing on the voltage waveform at the node where the power switch, output inductor, and catch-rectifier cathode connect. The ringing, which results from driving parasitic inductances and capacitances with fast rise-time waveforms, ranges in severity from objectionable to unacceptable depending on component selection and printed circuit board layout. An RC snubber damping network in parallel with the catch rectifier is by far the simplest way to minimize or eliminate the problem. Since deleting components from a printed-circuit layout is usually easier than adding them, it is best to include the network in the initial design and delete the components if they prove unnecessary.
2-6
3.3-V Step-Down Regulator
The initial design is straightforward, but the printed circuit board layout may require component-value adjustments during the prototype phase. The capacitor value chosen is 2 to 5 times the rectifier junction capacitance; higher values improve the snubbing but dissipate more power. The SS32 has a typical junction capacitance of approximately 500 pF, so a snubber capacitor value should be at least 1000 pF, and C11 is 1500 pF. Rectifiers normally ring in the range from 1 to 50 MHz. Choose the snubber resistor, R11, so that the snubber-capacitor can fully charge during the ringing. So, for a 15-nS ringing time constant, choose R11 as:
R11
+ 3 Ringing + 3 C11
t
15 10 -9 1500 10 -12
+ 3.3 W 2.7 W + 37 mW
Because the snubber is charged and discharged during each cycle, the power dissipation in R11 is:
P R11
+ 2(C11) VI2
f 2
+ 2 1500
10 -12 7 2
500 2
10 3
3.3-V Step-Down Regulator
2-7
Dead-Time Control
2.5 Dead-Time Control
Dead-time control provides a minimum period of time during each cycle when the power switch cannot be on: that is, it limits the duty cycle to some value less than 100%. Even though dead-time is not necessary in this application, a small amount of dead time would minimize the surge current that would result from a short circuit while the protection circuit is timing out. Referring to Figure 2-1 below (Figure 9 in the TL1454 data sheet), for a timing capacitor value of 120 pF, the duty cycle of the power switch is 100% when VDT, the dead-time control voltage, is less than approximately 1.1 V (VO(min)) and 0% when VDT is greater than 1.75 V (VO(max)).
Figure 2-1. PWM Triangle Wave Amplitude vs. Timing Capacitance
2 1.9 PWM Triangle Waveform Amplitude - V 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 10 0 VCC = 6 V RT = 5.1 k TA = 25C 10 1 10 2 10 3 10 4 VO(min) VO(max)
Timing Capacitance - pF
The following expression is used to set VDT, where D = maximum allowed duty cycle:
V DT
+ VO(max) -D VO(max)-VO(min) - 0.65 V DT + 1.75-1(1.75-1.1) - 0.65 + 0.45 V
This is the maximum voltage allowed to guarantee 100% duty cycle; grounding DTC2 will suffice for this application.
2-8
3.3-V Step-Down Regulator
Soft-Start Timing
2.6 Soft-Start Timing
Soft start can be accomplished by adding a capacitor in parallel with the upper dead-time divider resistor. This design has a dead time of 0% which requires no divider. A lower resistor must be added for soft-start timing purposes. This design uses an output rise time of 5 ms. Selecting the lower resistor to be 47 k as recommended in the data sheet, capacitor C13 can be calculated as:
C15
5 SS + tR3 + 47
10 -3 10 3
+ 0.11 mF 0.1 mF
3.3-V Step-Down Regulator
2-9
Output Sense Network
2.7 Output Sense Network
The output sense network is a resistive divider connected between the converter output and ground with the output connected to the TL1454 IN2+ terminal (13) of channel 2 (see Figure 5-1). The divider ratio was chosen for a 1.25-V output (the TL1454 reference voltage) when the converter output is at the desired value. Establishing the proper divider ratio is critical: selecting values for the sense network can affect operation. Choosing values that are too high can result in converter-output voltage-accuracy problems because the error-amplifier input-bias current loads the network. Values that are too low may dissipate too much power, drain too much power from limited power sources such as batteries, or result in loop-compensation capacitor values that are too high to be practical. The dc-source resistance of the error-amplifier inputs should be 10 k and approximately matched to minimize output voltage errors caused by the input-bias current. A simple procedure for determining appropriate values for the resistors is to choose a convenient value for R1 (10 k in this case) and calculate R6 and R8 using:
R6 R8
+ R1 -VVO + 10 kW 3.3 VV + 16.1 kW 16.2 kW V 3.3 V-1.25
O ref
+
R1
VO
V ref
3.3 + 10 kW V V + 26.4 kW 26.7 kW 1.25
Resistors with 1% tolerance with low and/or reasonably well matched temperature coefficients are recommended to minimize output voltage errors. A device with a 5% tolerance is suitable for R1.
2-10
3.3-V Step-Down Regulator
Loop Compensation
2.8 Loop Compensation
The loop compensation design consists of shaping the error amplifier frequency response with external components to stabilize the feedback of the dc-to-dc converter control loop without destroying the control loop's ability to respond to line and/or load transients. The following is a network design approach to stabilize continuous-mode step-down converters. This approach works well as long as the open loop gain is below unity at a frequency much less than the power supply switching frequency. Notice that the equations given in this section are applicable to buck converters only. The procedure and applicable equations for loop compensation of discontinuous-mode step-up (boost) converters are given in another part of this user's guide.
2.8.1
Buck Power Stage and Pulse-Width Modulator
Disregarding the error-amplifier frequency response, the combined response of the pulse-width modulator and buck power stage operating in continuous mode can be modeled as a simple gain block followed by an LC-filter transfer function. The magnitude of the gain is the change in output voltage for a change in the pulse-width-modulator input voltage (error-amplifier COMP2 terminal voltage). For this design, decreasing the COMP2 voltage from 1.75 V to 1.1 V increases the duty cycle from 0% to 100%, and the output voltage from 0 V to approximately 5 V (= VI) at the nominal input voltage. The gain, GC-VO , is:
G C-VO
5-0 + DVDVO + 1.75-1.1 + 7.69 17.7 dB.
COMP
Similarly, the gain is 16.9 dB at low line (4.5-V input) and 20.6 dB at high line (7-V input). For converters with wider input ranges, 2:1 or more, the designer should check for stability at several line voltages to insure that gain variation does not cause a problem. The phase shift associated with GC-VO is -180 because a decrease in COMP2 voltage causes an increase in output voltage. This is a function of the TL1454 controller.
3.3-V Step-Down Regulator
2-11
Loop Compensation
The output filter response is a two-pole low-pass filter that includes an underdamped complex pole pair near the filter's resonant frequency, fp , and the capacitor ESR which adds a zero, fz1 . The complex poles are located at:
fp
+
2
1
p p
L2
C 13
1
1
) RRC
1
+
2
(10
mH)
(100
mF)
)
0.35 2.2
+ 4.67 kHz
mF + 4.55 kHz.
The capacitor ESR zero is located at:
f z1
+2
p
1 RC
C 13
+2
p
1 0.35 W
100
Combining the two equations above and including the effects of the damping due to ESR, provides an expression for the output filter response.
G FIL(s)
+ Vi
1
R
) RL
R
1 1
1
)s
RC
C 13 L2 C 13
1
)s
RC
C 13
) LR2 ) s2
) RRC
)s
C 17
R RC R)R C
Where: = 2 .2 1 .5 A C13 = Output capacitance = 100 F RC = Capacitor ESR + R17 = 0.35 L2 = Output inductance = 10 H RL = Equivalent resistance of Inductor and FET RDS(on) C17 = Ceramic capacitance = 10 F
R = Load resistance =
3 .3 V
The uncompensated loop response for this buck converter is the product of the gain, GC-VO, and the output filter gain, GFIL. Figure 2-2 includes the gain and phase plots of the open loop response (error amplifier not included) obtained from a simple Mathcad analysis. The graph is for the case where maximum gain occurs (at maximum input voltage of 7 V). The presence of the complex pole pair is evident from the resonant peaking in the gain at 5 kHz and the rapid phase transition in the vicinity of 5 kHz.
2-12
3.3-V Step-Down Regulator
Loop Compensation
Figure 2-2. Buck Uncompensated Loop Response
40 30 Gain 20 10 Gain - dB Phase 0 -10 -20 -30 -40 10 100 1k f - Frequency - Hz 10 k -180 -225 -270 -315 -360 100 k -90 -135 Phase - Degrees 0 -45
2.8.2
Error Amplifier
Unless the designer is trying to meet an unusual requirement, such as very wide band response, many of the decisions regarding gains, compensation pole and zero locations, and loop unity-gain bandwidth are largely arbitrary. Generally, the loop gain at low frequencies is very high, to minimize any dc error in the output voltage. Compensation zeros are added to correct for the sharp change in phase encountered near the filter's resonant frequency. An open loop unity gain frequency is selected higher than the filter resonant frequency, but 10% or less than the converter operating frequency. In this instance, choose an open loop unity gain frequency of 40 kHz to provide good transient response. The compensation network shown in Figure 2-3 is picked for this design.
Figure 2-3. Buck Compensation Circuit
C3 Error IN- _ AMP IN+ +
R1 VREF VO R8 C9
COMP
To PWM
R6
3.3-V Step-Down Regulator
2-13
Loop Compensation
Assuming an ideal amplifier, the transfer function (from VO to COMP) for this noninverting error-amplifier configuration is:
A ea(s)
+
R6 R6
) R8
1
)s
1
)s
R8 C9 R6 R8 C9 R6)R8
1
)s
s
R1 C3 R1 C3
The transfer function is made up of two independent transfer functions. The first one is the voltage sense divider (R6, R8, and C9). This represents the transfer function from the output voltage VO to the noninverting amplifier input, IN+. The second transfer function, made up of R1 and C3, provides high dc gain and can be referred to as the integrator gain. The compensation component selection begins with the voltage sense divider. Other than sensing the output voltage, this network consisting of R6, R8, and C9, produces one zero and one pole. The zero is located at a frequency of:
fz
+2 +
2
p
1 C9
R8
Similarly, the pole is located at a frequency of:
fp
1
p
C9
R6 R8 R6)R8
Since R6 and R8 are already determined, it is necessary to choose capacitor C9. Choose C9 to provide a zero at approximately the same frequency as the filter resonance. Capacitor C9 is calculated to be 1200 pF. The zero associated with this network is positioned at approximately 5 kHz:
fz
+2
p
p
1 C9
R8
+2
p
p
1200
1 10 -12
26.7
10 3
+ 5 kHz
The pole associated with this network is positioned at approximately 13.3 kHz:
fp
+2
1 C9
R8 R6
o
+2
1200
1 10 -12
10
10 3
+ 13.3 kHz
For an open loop unity gain frequency of 40 kHz, the sum (in dB) of the gains of the modulator, LC filter, and error amplifier must be 0 dB at 40 kHz. The gain of the modulator/LC filter at 40 kHz may be obtained by any number of analysis methods, and for this design, the gain at 40 kHz is about 0 dB, as shown in Figure 2-2. The gain of the voltage sense network (R6, R8, and C9 ) is found to be approximately 0 dB at 40 kHz. Therefore, the integrator gain should be 0 dB at 40 kHz for an overall loop unity-gain frequency of 40 kHz. The next step is to calculate integrator components. R1 was chosen to be 10 k. C3 is chosen to provide a zero at approximately 5 kHz giving unity gain (from the integrator portion of the error amplifier circuit) above 10 kHz. C3 is calculated to produce a zero at 5 kHz:
C3
+2
p
1
f
R1
+2
p
5
1 10 3
10
10 3
+ 3185 pF 3300 pF
2-14
3.3-V Step-Down Regulator
Loop Compensation
Figure 2-4 shows the total open loop frequency response of the buck regulator (at maximum input voltage). The figure shows the results of adding the compensation network to the system response shown in Figure 2-2. The design goals are clearly met: high gain at low frequency, gradual phase shift around the filter resonant frequency, and unity gain frequency of 40 kHz (above filter resonance of 5 kHz and less than 10% of switching frequency of 500 kHz). In addition, the phase margin is about 50 indicating a stable system.
Figure 2-4. Buck Compensated Open Loop Response
80 60 Gain 40 Gain - dB 0 Phase - Degrees 180 90
20 0 Phase -20 -40 -60 10 100 1k f - Frequency - Hz 10 k
-90
-180 -270
-360
100 k
3.3-V Step-Down Regulator
2-15
2-16
3.3-V Step-Down Regulator
Chapter 3
12-V Step-Up Regulator
The following sections describe the design procedure for this 12-V step-up (or boost) regulator. Selection and/or design guidelines are given for the external power components. As stated in the TL1454 data sheet, channel 1 of the controller is configured to control and provide drive signals for a step-up regulator using an n-channel power MOSFET.
Topic
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Page
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Duty Cycle Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Soft-Start Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Output Sense Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
12-V Step-Up Regulator
3-1
Inductor Selection
3.1 Inductor Selection
The boost inductor, converter switching frequency, input and output voltages, and output power determine a boost converter's operating mode. This converter operates in the discontinuous-conduction mode (DCM). In discontinuous mode, the current in the inductor starts at zero and returns to zero in each switching cycle. To keep the converter in discontinuous mode, the inductor must be less than a computed maximum value. However, for a specified output power level, the smaller the inductance, the higher the peak and rms current in Q1 and CR1. Therefore, the value of inductance is not critical and can be left to the needs of the designer. Discontinuous mode is desirable because the power-stage frequency response is stable and has a dc gain and a single pole. Continuous-mode boost converters have a dc gain, a complex pole pair, and a right-half-plane zero, making feedback loop stabilization difficult. The maximum value of inductance L, can be calculated as a function of M, R, and TS where M is defined as the converter voltage gain from input to output, R is the load resistance and TS is the period of one switching cycle.
L
vR
TS
2
M -1 M3
M is defined as:
M
+ VO V
I
For this example, with M = 2.7, VO = 12 V, VI = 4.5 V, and R = 60 the calculated value of L is:
L
v 60
2 10 -6 2
2.7-1 2.7 3
+ 5.2 mH 2.7 mH
Allowing for startup transients and additional output current to charge the output filter capacitor, and since the exact value is not critical, a smaller standard-value inductor is chosen.
3-2
12-V Step-Up Regulator
Duty Cycle Estimates
3.2 Duty Cycle Estimates
The duty cycle (D) is the ratio of the power switch conduction time to the period of one switching cycle. The duty cycle for a boost converter is calculated as:
D
+
K
M
(M-1)
Where K is:
K
+ R2
L TS
For this example, assuming VI = 5 V, VO = 12 V, R = 60 , corresponding to 200 mA output current, we get a duty cycle estimate of:
D
+
2 2.7 60 2
10 -6 10 -6
12 5
12 -1 5
+ 0.39
For VI = 5 V, VO = 12 V, R = 600 , corresponding to 20 mA output current, we get a duty cycle estimate of:
D
+
2 2.7 600 2
10 -6 10 -6
12 5
12 -1 5
+ 0.12
12-V Step-Up Regulator
3-3
Output Capacitor
3.3 Output Capacitor
The peak inductor current must be calculated to determine the amount of output capacitance needed. The expression for the peak inductor current, IPK , is:
I PK
+ VI L
D
TS
The peak inductor current occurs when the converter is driving its maximum load of 200 mA and the input voltage is at the minimum of 4.5 V. Using the duty cycle calculated for VI = 4.5 V and for a 200-mA load gives:
I PK
+ 2.7 4.510-6
(0.45)
2
10 -6
+ 1.5 A
The two criteria for selecting the output capacitor are the amount of capacitance needed and the capacitor's equivalent series resistance (ESR). After the capacitance and ESR requirements are determined, the capacitor can be selected. The voltage variation due to the inductor current flow in the output capacitor is approximately:
DVO +
I2
2
PK
L V O-V I
C
The above equation is based on the assumption that all inductor ripple current flows through the capacitor and the ESR is zero. If the desired output ripple voltage is 120 mV, then the capacitance needed is:
C
+ (2) +
(1.5)
2
2.7 (0.12)
10 -6 (12-5)
+ 3.6 mF
Now, given that the capacitance is very large, the ESR needed to limit the ripple to 120 mV is:
ESR
DVO 0.12 DIO + 1.5 +
80 mW
The actual output filter capacitor should be rated at greater than the calculated capacitance and lower than the calculated ESR. This design used one 22-F multilayer ceramic capacitor. With this ceramic capacitor, the ESR is significantly less than the calculated ESR requirement.
3-4
12-V Step-Up Regulator
Power-Stage Design
3.4 Power-Stage Design
The power-stage design includes selecting the power switch, the output rectifier, and the rectifier snubbing network (if needed), calculating the power dissipations and junction temperatures, and verifying that the semiconductors have adequate heatsinking.
3.4.1
Power Switch
The output drive of the TL1454 for this channel (OUT1) is set up to drive an N-channel MOSFET that is ideal for boost converters. In choosing the proper power switch, important criteria include: maximum switch current, peak switch voltage, rDS(on) , power dissipation, and gate-drive voltage. The peak drain current is the inductor current during the on time. This current was calculated previously as 1.5 A. The peak drain voltage is calculated as follows:
V PK
+ VO ) Vd + 12 ) 0.5 + 12.5 V
The maximum allowable rDS(on) is calculated from an assumed VSat-pk of 0.5 V and adjusted for temperature. Assume a temperature adjustment (K) of 1.4:
r DS(on)
0.5 v I Sat-pk + (1.5) (1.4) + 0.24 W K
V
PK
The gate-drive voltage will range from approximately 4.5 V to 7.0 V, thus a MOSFET with low-level drive capability is required. The transistor chosen is the IRLL014. This device is a 60-V, 2.7-A MOSFET with a maximum rDS(on) of 0.20 at a 5-V gate drive. The transistor's turn-off time (tfall) is 26 ns. The surface-mount SOT-223 package has a thermal resistance of 60C/W when mounted on a 1 square pcb. The conduction and switching losses for this device are calculated as follows (where D = duty cycle = ton x f and K = 1.4):
PD
+
r DS(on)
K
I2 L(rms)
)
1V PK I L(PK) t fall (f ) 2
and IL(rms) is:
I L(rms)
+ IPK
D 3
At 4.5 Vin, the power dissipation is:
PD
+ )
2
(0.2)
(1.4)
(1.5)
0.45 3 10 -9 500 10 3
1 (12.5) (1.5) 26 2
+ 217 mW
3-5
12-V Step-Up Regulator
Power-Stage Design
Worst-case junction temperature is calculated as:
TJ
+ TA )
R qJA
PD
+ 55 ) (60
0.217)
+ 68C
3.4.2
Output Rectifier
For low-voltage applications, a Schottky diode is recommended. This design uses an SS12 Schottky rectifier with a 1-A current rating, a 20-V reverse voltage rating, and a maximum forward drop of 0.5 V. Power dissipation for CR1 is:
P CR1
+
VD IO
+ (0.5) (0.2) + 100 mW + 55 ) (88 + 64C
Junction temperature for this diode may be estimated using a thermal resistance of 88C/W:
TJ
+ TA )
R QJA
PCR1
0.1)
3.4.3
Output-Rectifier Snubber Network
An RC snubber is placed across the diode to prevent ringing of the output diode due to parasitic inductances. Select a capacitor value that is 2 to 5 times the diode junction capacitance. With a diode junction capacitance of 200 pF, a reasonable capacitor value to use is 1000 pF. Assuming a ringing period of 30 ns, then choose the snubber resistor, R10, so that the snubber capacitor can fully charge during the ringing period. So, for a 30-ns ringing time constant, choose R10 as
R10
+ 3Ringing + 3 C10
t V2 PK f 2
30 10 -9 1000 10 -12
+ 10 W
500 2 10 3
The power dissipation for the resistor is:
P R10
+ 2(C10)
+ 2 1000
10 -12 12.5 2
+ 78 mW
3-6
12-V Step-Up Regulator
Dead Time Control
3.5 Dead Time Control
Unlike step-down converters where 100% duty-cycle operation is acceptable, the duty cycle of step-up converters must be limited below 100%. The maximum duty cycle for this design was calculated at approximately 0.5. Allowing for tolerances, the actual limit value should be somewhat higher. We chose a maximum duty cycle of 0.70. Using Figure 2-1 and the equation below, to determine the DTC input voltage required:
V DT
+ 1.75-0.7(1.75-1.1)-0.65 + 0.65 V
A voltage divider, R12/R13, connected from the reference voltage to ground, sets the dead time control voltage. The input bias current of the DTC1 pin is 10 A maximum. Although a divider current of 1000 times the input current is preferred, this would excessively load the reference supply. The divider current will be set at 200 A. The bottom divider resistor is calculated:
R13
DT + VI) + 2000.65 -6 + 3250 W 3.32 kW 10
Using 3320 , the divider current is 196 A. R12 is now calculated as:
R12
-V 1.25-0.65 + VREF) DT + 196 10-6 + 3261 W 3.01 kW I
With the new calculated values, the actual dead-time voltage and duty cycle are:
V DT
+ VREF R12R13R13 + 1.25 301033203320 + 0.65 V ) ) +
V O(max)- 0.65 -V DT V O(max)-V O(min) - 0.65 - + 1.751.75 - 1.10.65 + 0.69
D max
12-V Step-Up Regulator
3-7
Soft-Start Timing
3.6 Soft-Start Timing
Soft start is achieved by adding a capacitor in parallel with the upper resistor of the dead-time control circuit. If dead-time control is not being used, soft start can still be implemented by using a capacitor in series with a resistor connected to DTC. The SCP time period of 120 ms was set in section 1.4.2. A good standard for the soft-start timing is no more than 1/10 of the SCP time period. Using 5 ms, the soft-start capacitor is calculated as:
C14
5 + R12 ot R13 + 3010 o10-3 + 3.2 mF 3.3 mF 3320
3-8
12-V Step-Up Regulator
Output Sense Network
3.7 Output Sense Network
Using the same approach as in the 3.3-V design:
R5
+ R2 -VVO + 10 kW 12 VV + 11.2 kW 11 kW V 12 V-1.25
O ref
R7
+ R2V
VO
ref
12 + 10 kW V V + 96 kW 95.3 kW 1.25
Precision resistors are used in this divider, not so much for the actual resistance value, but for the drift characteristics of the values.
12-V Step-Up Regulator
3-9
Loop Compensation
3.8 Loop Compensation
The control loop for this converter consists of three gains: the power stage gain (GPS), the error amplifier gain (GE/A), and the internal TL1454 PWM modulator gain (GPWM). For this converter, the pulse-width modulator and power stage frequency responses are computed separately as opposed to calculating the pulse-width modulator and power stage frequency response together as it was previously done with the buck converter above. Figure 3-1 shows a simplified block diagram of the control loop.
Figure 3-1. Control Loop Simplified Block Diagram
VI Power Stage Duty Cycle Pulse Width Modulator Error Amplifier Vref VO
Comp Internal to TL1454
The loop-compensation design procedure consists of shaping the erroramplifier frequency response with external components to stabilize the dc-to-dc converter. The following is a simplified approach to designing networks to stabilize discontinuous mode boost converters that works well when the open-loop gain is below unity at a frequency much lower than the frequency of operation. Before the error-amplifier frequency response can be designed, the frequency response of the rest of the loop must be determined. This consists of determining the power stage gain and phase, and the pulse width modulator gain and phase.
3.8.1
Boost Power Stage
The response of the boost power stage operating in discontinuous mode can be modeled as a simple gain block with a single real pole. The magnitude of the gain is the change in the output voltage divided by the change in the duty cycle. The gain of the discontinuous boost power stage is:
G PS(s)
+ DVO + GOD DD
1
) wsP
12-V Step-Up Regulator
1
3-10
Loop Compensation
where,
G OD
+ (22
VO M)-1 M)-1 M-1
M-1 KM
1
wP + (2
R
C
and K and M are the same as previously defined. For this example, with VI = 5 V and IO = 200 mA, the dc gain, GOD , is given by:
G OD
+
2 2
12 12 -1 5
12 -1 5 2 2.7 10 -6 60 2 10 -6
12 5
+ 22.7 27.1 dB
and, the single real pole is given by:
wP +
2
12 -1 5 12 -1 5
60
1 22
10 -6
+ 2056 Rad sec 327 Hz
This power stage gain is dependent on input voltage and output load resistance. For this circuit, the lowest gain occurs when the input voltage is at its maximum of 7 V and the output load resistance is at its minimum of 60 (corresponding to 200 mA load current). This condition gives a minimum phase margin. It is good design practice to check for stability at the line voltage extremes, and at the limits of output loads to ensure that the gain and phase variations do not cause problems.
3.8.2
Pulse-Width Modulator
The response of the pulse-width modulator can be modeled as a simple gain block. The magnitude of the gain is the change in PWM output duty cycle for a change in the pulse-width-modulator input voltage (error-amplifier COMP voltage). Looking in Figure 2-1, the maximum PWM triangle wave amplitude is 1.75 V and its minimum is 1.1 V for this application. Even though the maximum duty cycle is limited to 0.69, if the duty cycle were allowed to attain 100%, the duty cycle output would change from 100% to 0% for COMP voltage changes from 1.1 to 1.75. Therefore, the gain, GPWM , is:
G PWM
+ DV
DD
O (COMP)
1 -0 + 1.75-1.1 + 1.54 3.7 dB
The product (sum in dB) of the gains of the power stage, GPS , and the pulsewidth-modulator, GPWM makes up the uncompensated open loop response. Figure 3-2 is a gain and phase plot of the uncompensated open loop response of this converter obtained from a Mathcad analysis. The presence of the single real pole is evident from the phase in the region of 327 Hz and the total phase shift is only 90 degrees.
12-V Step-Up Regulator
3-11
Loop Compensation
Figure 3-2. Boost Uncompensated Loop Response
60 90
40
0 Phase - Degrees
Gain Gain - dB 20 -90
0 Phase
-180
-20
-270
-40 10 100 1k f - Frequency - Hz 10 k
-360 100 k
3.8.3
Error Amplifier
Unless the design needs to meet an unusual requirement, (i.e., very wideband response) many of the decisions regarding gains, compensation pole and zero locations, and unity gain bandwidth are largely arbitrary. Generally, the gain at low frequencies is very high to minimize error in the output voltage. Compensation zero(s) are added near the filter pole(s) to correct for the change in phase encountered near the filter's pole frequency. An open loop unity gain frequency is selected beyond the filter's pole frequency, but 10% or less than the converter operating frequency. In this instance, choose a unity gain frequency of approximately 10 kHz to provide good transient response. The compensation network is shown in Figure 3-3.
Figure 3-3. Boost Compensation Circuit
C8 R15 Error IN- _ AMP IN+ + R5 C4
R2 VREF VO R7
COMP
To PWM
For an ideal amplifier, the error amplifier transfer function is:
A ea(s)
+ R5 ) R7
R5
1
)s
C4 (R2 R15) s C4 R2
)
1
) s C8 R2 R15 R2)R15 1 ) s C8 R15
12-V Step-Up Regulator
3-12
Loop Compensation
This amplifier has a pole at dc, a zero positioned to approximately cancel the pole from the power stage, and a high frequency pole to prevent noise from upsetting the control loop. The unity gain frequency is selected to be approximately 10 kHz. From the gain-phase plot of the uncompensated open loop response of the converter (Figure 3-2), the gain is approximately 0 dB, and the phase is -90 degrees at 10 kHz. Therefore, the amplifier needs to provide a gain of 0 dB at 10 kHz. The gain is approximated by the ratio of R15 to R2 and the R5 - R7 voltage divider because the zero provided by C4 and R2 + R15 is located much lower in frequency than the desired crossover frequency. The gain at 10 kHz can be approximated by the following:
G ea(10 kHz)
+ R5 R5 R7 )
G ea(10 kHz)
R2
) R15 +
R2
11 kW 11 kW 95.3 kW
)
10 kW 91 kW 10 kW
)
+ 1.04
Expressed in dB, the gain is:
+ 0.34 dB
The zero provided by C4 and R2+ R15 is given by:
fZ
+2
p
1
C4
(R2
) R15) + 2
p
1 C8
p
R15
1 (2200 pF) (10 kW
) 91 kW) + 717 Hz
(91 kW)
And finally, the high frequency pole is calculated as:
f P-HF
+2
+2
p
1 (22 pF)
+ 80 kHz
The overall open loop frequency response of the converter is the product of the uncompensated open loop response and the error amplifier response. A Bode plot of the overall open loop frequency response of the converter is shown in Figure 3-4. The gain crosses 0 dB in the vicinity of 10 kHz and the phase margin is near 80 degrees.
Figure 3-4. Boost Compensated Open Loop Response
80 60 Gain 40 Gain - dB 20 0 -20 -40 -60 10 100 1k f - Frequency - Hz 10 k 100 k Phase 0 -90 Phase - Degrees 180 90
-180
-270
-360
12-V Step-Up Regulator
3-13
3-14
12-V Step-Up Regulator
Chapter 4
Test Results
The following sections describe the procedure for test setup of the TL1454-EVM-085 Evaluation Module (EVM), and the test results. These results represent the typical performance of the EVM.
Topic
4.1 4.2
Page
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Test Results
4-1
Test Setup
4.1 Test Setup
For initial powerup of the TL1454EVM-085 (SLVP085) evaluation board, perform the following steps: 1) Connect an electronic load from the 3.3-V output to GND (P2-1 and 2 to P2-3 and 4) adjusted to draw approximately 0.5 A at 3.3 V. Connect an electronic load from the 12-V output to GND (P2-5 to P2-3 and 4) adjusted to draw approximately 100 mA at 12 V. The exact current levels are not critical; any nominal current is sufficient. A fixed resistor may be used in place of the electronic load. The output current drawn by the resistor is
IO =
VO Amps where R is the value of the load resistor and VO R
is the output voltage. The power rating of the resistor, PR should be at least:
PR
w VO2 R
2 Watts
2) Connect a 5-V lab power supply from the VI input to RTN (P1-1 and 2 to P1-3 and 4) of the SLVP085. A set current limit of 1.5 A should be adequate for the input power requirements. 3) Turn on the 5-V supply and ramp the input voltage up to 5 V. 4) Verify that the EVM output voltages (measured at the module output pins) are 3.3 V 0.17 V, and 12 V 0.6 V. 5) For subsequent testing, ensure the lab supply output current capacity and current limit are at least 3 A so that the SLVP085 can be operated at maximum loads on both outputs. 6) See Section 4.2 for selected typical waveforms and operating conditions for verification of proper module operation.
4-2
Test Results
Test Setup
Figure 4-1. Test Setup
Power Supply
-
+
L2 C1 C18 CR2 P1 C14 + C5 R4 R2 R5 R15 C8 C4 R7 C5 R6 C3 R16 C9 R8 TEXAS INSTRUMENTS TL1454 EVAL BOARD CR1 SLVP085 R9 R12 C2 R13 C15 U1 1 C7 R3 R1 L1 C11 C17 C16 R14 C10 R10 Q1 R18 C12 1 JMP1 Q2 R17B R17C R11 R17A R17 D P2 JMP2
C13
60 5W
-
LOAD
+
Test Results
4-3
Test Results
4.2 Test Results
Figures 4-2 to 4-12 and Tables 4-1 and 4-2 show test results for the SLVP085 evaluation board.
Table 4-1. 3.3 V Measured Test Results
Parameter Load regulation Line regulation Output ripple Transient response Efficiency VI = 5 V, VI = 5 V, Test Conditions IO(12 V) = 200 mA IO(12 V) = 200 mA IO(3.3 V) = 1.5 A, IO(12 V) = 200 mA VI = 5 V, IO(12 V) = 200 mA, IO(3.3 V) pulsed from 1.5 A to 3 A VI = 5 V, IO(3.3 V) = 1.5 A IO(12 V) = 0 mA Measurement 0.1 Max 0.1 Max 25 50 90 Unit % % mV mV pk %
Table 4-2. 12 V Measured Test Results
Parameter Load regulation Line regulation Output ripple Transient response Efficiency VI = 5 V,
IO(3.3 V) = 1.5 A,
Test Conditions IO(3.3 V) = 1.5 mA
IO(12 V) = 200 mA
Measurement 0 0 35 20 83
Unit % % mV mV pk %
VI = 5 V,
IO(3.3 V) = 1.5 mA
VI = 5 V, IO(3.3 V) = 3 A, IO(12 V) pulsed from 100 mA to 200 mA VI = 5 V, IO(3.3 V) = 0 A IO(12 V) = 200 mA
Figure 4-2. SLVP085 Measured Efficiency
95 3.3 V 90 Combined 85 Efficency - % 12 V 80
75
70
65 0 20 40 60 80 100 Percent of Rated Load
4-4
Test Results
Test Results
Figure 4-3. SLVP085 Measured Line Regulation
0.20 0.15 0.10 Line Regulation - % 3.3 V 0.05 0 -0.05 -0.10 -0.15 -0.20 4.5 4.75 IO (3.3 V) = 1.5 A IO (12 V) = 200 mA
12 V
5
5.25 5.5 5.75
6
6.25 6.5 6.75
7
Input Voltage - V
Figure 4-4. SLVP085 Measured Load Regulation
0.20 0.15 0.10 Load Regulation - % 0.05 0 -0.05 -0.10 -0.15 -0.20 0 10 20 30 40 50 60 70 80 90 100 Percent Full Load - % 3.3 V 12 V VI = 5 V
Test Results
4-5
Test Results
Figure 4-5. SLVP085 CR2-Cathode Switching Waveform
VI = 5 V IO (3.3 V) = 1.5 A
Voltage 2 V/div 0V
500 ns/div
Figure 4-6. SLVP085 3.3-V Output Start-Up
VI (5 V) 2 V/div 0V
VO (3.3 V) IO = 1.5 A 1 V/div 0V
1 ms/div
4-6
Test Results
Test Results
Figure 4-7. SLVP085 3.3-V Output Voltage Ripple
VI = 5 V IO (3.3 V) = 1.5 A
Voltage 20 mV/div
500 ns/div
Figure 4-8. SLVP085 3.3-V Load Transient Response
VI = 5 V IO (12 V) = 200 mA 1 VO (3.3 V) 50 mV/div AC Coupled
IO (3.3 V) 500 mA/div 2
100 s/div
Test Results
4-7
Test Results
Figure 4-9. SLVP085 Q1 VDS Switching Waveform
VI = 5 V IO (12 V) = 200 mA
Voltage 2 V/div 0V
500 ns/div
Figure 4-10. SLVP085 12-V Output Start-Up
VI (5 V) 2 V/div 0V VO (12 V) IO = 200 mA 2 V/div
0V
2 ms/div
4-8
Test Results
Test Results
Figure 4-11. SLVP085 12-V Output Voltage Ripple
VI = 5 V IO (12 V) = 200 mA
Voltage 20 mV/div
500 ns/div
Figure 4-12. SLVP085 12-V Load Transient Response
VO (12 V) 20 mV/div AC Coupled 1 VI = 5 V IO (3.3 V) = 1.5 A
IO (12 V) 50 mA/div
2 200 s/div
Test Results
4-9
4-10
Test Results
Chapter 5
EVM Documentation
The schematic, board layout, and bill of materials are provided to document the SLVP085 EVM dual regulator assembly.
Topic
5.1 5.2 5.3
Page
EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
EVM Documentation
5-1
EVM Schematic
5-2
P1 V IN V IN RTN RTN 4 C6 0.1 F R11 2.7 R17 0.25 R16 100 1 2 3 4 + C14 3.3 F 16 V C15 ref 0.1 F C10 14 OUT2 9 L1 2.7 H R12 3.01 k V CC R2 10 k R1 10 k U1 TL1454CD 18 R10 5 10 k CR2 SS32 C17 10 F R9 C1 10 F C11 1500 pF C13 100 F C18 10 F + 1 2 3 4.5 V to 7 V Q2 TPS1110D L2 10 H P2 3.3 V/1.5 A 3.3 V/1.5 A GND GND 12 V/200 mA C3 1000 pF 10 CR1 SS12 8 OUT1 R14 10 k SCP GND R4 10 k C5 120 pF 7 15 + Q1 IRLL014 C12 22 F C16 0.47 F R18 1 C8 R15 91 k C4 3 DTC1 2200 pF 6 COMP1 5 IN1- 4 IN1+ 2 RT 1 CT 22 pF DTC2 3300 pF 11 COMP2 12 IN2- 13 IN2+ R5 11 k R7 95.3 k + C7 1.5 F
5.1 EVM Schematic
Figure 5-1. Dual Regulator EVM Schematic
C2 0.1 F
R3 47 k
C9 1200 pF
R8 26.7 k
R6 16.2 k
R13 3.32 k
EVM Documentation
EVM Bill of Materials
5.2 EVM Bill of Materials
Table 5-1. EVM Bill of Materials
APPROVED VENDOR TDK
ITEM 1
QTY 3
REF. DES./COMM C1,C17,C18
PART NO. C3225Y5V1C106Z
PART DESCRIPTION CAP, CER, 10 F,10 V (Dist #: CC1210CY5V106Z) CAP, TANT, 100 F, 10 V, D CASE CAP, CER, 0.1 F, 1206, X7R CAP, CER, 3300 pF, 0805, X7R CAP, CER, 2200 pF, 0805, NPO CAP, CER, 120 pF, 0805, NPO CAP, TANT, 1.5 F, 16 V, A CASE CAP, CER, 22 pF, 0805, NPO CAP, CER, 1200 pF, 0805, X7R CAP, CER, 1000 pF, 0805, X7R CAP, CER, 1500 pF, 0805, X7R CAP, CER, 22 F, 25 V, 2220, Y5V CAP, TANT, 100 F, 16 V, E CASE CAP, TANT, 100 F, 10 V, D CASE CAP, TANT, 3.3 F, 16 V, A CASE CAP, CER, 0.47 F, 1210, Z5U RES, 10 K, 0805, 5% RES, 47 K, 0805, 5% RES, 10.0 K, 0805, 1% RES, 11.0 K, 0805, 1% RES, 16.2 K, 0805, 1% RES, 95.3 K, 0805, 1% RES, 26.7 K, 0805, 1% RES, 2.7 , 0805, 5% RES, 10 ,, 0805, 5% RES, 15 ,, 0805, 5% RES, 3.01 K, 0805, 1% RES, 3.32 K, 0805, 1% RES, 91 K, 0805, 5%
ALT 2 3 4 5 6 7 8 9 10 11 ALT 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 1 1 1 1 1
0 3 1 1 1 1 1 1 1 1 1 0 1 1 1 4 1 1 1 1 1 1
Alt. part for item 1 C2,C6,C15 C3 C4 C5 C7 C8 C9 C10 C11 C12 Alt. part for item 11 C13 C14 C16 R1,R2,R9,R14 R3 R4 R5 R6 R7 R8 R11 R10 R16 R12 R13 R15
TPSD107M010R0100 STANDARD STANDARD STANDARD STANDARD ECS-T1CY155R STANDARD STANDARD STANDARD STANDARD THCR60E1E226Z TPSE107M016R0100 TPSD107M010R0100 ECS-T1CY335R STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD
AVX MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE PANASONIC MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MARCON/TOSHIBA AVX AVX PANASONIC MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE MULTI. SOURCE
EVM Documentation
5-3
EVM Bill of Materials
Table 5-1. EVM Bill of Materials (Continued)
ITEM 28 QTY 4 REF. DES./COMM R17A,R17B,R17C, R17D R18 U1 CR1 PART NO. STANDARD PART DESCRIPTION (4 PARALLEL RES) RES, 1 , 0805, 5% RES, 1 , 0805, 5%, See Item 28 IC, DUAL PWM Controller, SOIC-16 DIO, RECT, SCHOTTKY, 1A, 20 V, DO-214 AC APPROVED VENDOR MULTI. SOURCE
29 30 31
1 1 1
STANDARD TL1454CD SS12
MULTI. SOURCE TI GI
ALT 32
0 1
Alt. part for item 31 CR2
SK12 SS32 DIO, RECT, SCHOTTKY, 3A, 20 V, DO-214 AB
DI GI
ALT 33
0 1
Alt. part for item 32 Q1
SK32 IRLL014 FET, MOS, N-Channel, 0.2 60 V, 2.7 A, SOT-223 FET, MOS, P-Channel, 0.06 , 12 V, 6A, SOIC-8 IND, PWR, 2.7 H, 0.052 , 2.43 A IND, PWR, 10 H, 0.06 , 2.6 A HEADER, 4P, 0.100 Center, Straignt HEADER, 5P, 0.100 Center, Straight FAB, PCB JUMPER, #22 Bus wire
DI IR
34
1
Q2
TPS1110D
TI
35 36 37
1 1 1
L1 L2 P1
CD43-2R7MC CD105-100MC TSW-104-14-G-S
SUMIDA SUMIDA SAMTEC
38
1
P2
TSW-105-14-G-S
SAMTEC
39 40
1 2 JMP1,JMP2
STANDARD
MULTI. SOURCE MULTI. SOURCE
5-4
EVM Documentation
EVM Board Layout
5.3 EVM Board Layout
Figure 5-2. EVM Board Layout Component Side
L2 C1 C18 CR2 JMP2
P1 C14+ C5 R4 R2 R5 R15 C8 C4 R7
SLVP085 R12R13C2 C15 U1 1 C7 R3 R1 L1 R6 C3 R14 C5 R16 C9 R8 TEXAS INSTRUMENTS TL1454 EVAL BOARD CR1 C10 R10 Q1 R18 C12 C11 C17 C16 R9 JMP1 1 Q2 R17B R17C R11 R17A
C13
R17D P2
Component Side
EVM Documentation
5-5
EVM Board Layout
Figure 5-3. EVM Board Layout Solder Side
Solder Side (Top View)
5-6
EVM Documentation

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