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| TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 D D D D D D D D D D Over Voltage Protection and Lock Out for 12 V, 5 V, 3.3 V Under Voltage Protection and Lock Out for 5 V and 3.3 V Fault Protection Output With Open-Drain Output Stage Open-Drain Power Good Output Signal for Power Good Input, 3.3 V and 5 V 300-ms Power Good Delay 75-ms Delay for 5-V and 3.3-V Power Supply Short-Circuit Turnon Protection 2.3-ms PSON Control to FPO Turnoff Delay 38-ms PSON Control Debounce 73-s Width Noise Deglitches Wide Supply Voltage Range From 4 V to 15 V D OR P PACKAGE (TOP VIEW) PGI GND FPO PSON 1 2 3 4 8 7 6 5 PGO VDD VS5 VS33 description The TPS3510 is designed to minimize external components of personal-computer switching power supply systems. It provides protection circuits, power good indicator, fault protection output (FPO) and PSON control. Over voltage protection (OVP) monitors 3.3 V, 5 V, and 12 V (12-V signal detects via VDD pin). Under voltage protection (UVP) monitors 3.3 V and 5 V. When an OV or UV condition is detected, the power good output (PGO) is set to low and FPO is latched high. PSON from low to high resets the protection latch. UVP function is enabled 75 ms after PSON is set low and debounced. Furthermore, there is a 2.3-ms delay (and an additional 38-ms debounce) at turnoff. There is no delay during turnon. Power good feature monitors PGI, 3.3 V and 5 V and issues a power good signal when the output is ready. The TPS3510 is characterized for operation from -40C to 85C. typical application 5 VSB PGI PGO 12 V 1 8 PGO PGI 2 7 VDD GND 3 6 VS5 FPO 4 5 PSON VS33 0.5 V Drop VSB 5V 3.3 V PSON (From Motherboard) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 FUNCTION TABLE PGI <0.95 V <0.95 V <0.95 V 0.95 V x = don't care FPO = L means: fault IS NOT latched FPO = H means: fault IS latched PGO = L means: fault PGO = H means: NO fault 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 functional block diagram VDD 12 V OV + _ POR VS5 R 5 V OV + _ 73-s Debounce S Q FPO VS33 73-s Debounce 2.3-ms Delay VDD 3.3 V OV + _ 38-ms Debounce PSON 3.3 V UV + _ 5 V UV + _ + _ PGI1 150-s Debounce 75-ms Delay VDD PGO 300-ms Delay Band-Gap Reference 1.15 V PGI PGI2 + _ Band-Gap Reference 0.95 V 150-s Debounce and 4.8-ms Delay POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 timing diagram VDD PSON FPO PGI 3.3 V, 5 V 12 V PGO td1 tb td1 td2 Protect Occur PSON On PSON Off PSON On AC Off td1 PG OFF Delay 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 Terminal Functions TERMINAL NAME FPO GND PGI PGO PSON VDD VS33 VS5 NO. 3 2 1 8 4 7 5 6 I O I I I I I/O O DESCRIPTION Inverted fault protection output, open drain output stage Ground Power good input Power good output, open drain output stage ON/OFF control Supply voltage/12 V over-voltage protection input pin 3.3 V over/under-voltage protection 5 V over/under-voltage protection detailed description power good and power good delay A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that the 5-V and 3.3-V outputs are above the under-voltage threshold limit. At this time the converter should be able to provide enough power to ensure continuous operation within the specification. Conversely, when either the 5-V or the 3.3-V output voltages fall below the under-voltage threshold, or when ac power has been removed for a time sufficiently long so that power supply operation is no longer ensured, PGO should be de-asserted to a low state. Figure 1 represents the timing characteristics of the power good (PGO), dc enable (PSON), and the 5 V/3.3 V supply rails. PSON On Off 75% 5-V/3.3-V Output PGO t5 t3 t2 t4 10% Figure 1. Timing of PSON and PGO Although there is no requirement to meet specific timing parameters, the following signal timings are recommended: 2ms t2 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 10 ms Furthermore motherboards should be designed to comply with the previously recommended timing. If timings other than these are implemented or required, this information should be clearly specified. The TPS3510 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a 300-ms power-good delay. If the voltage signals at PGI, VS33, and VS5 rise above the under-voltage threshold, the POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 open-drain power-good output (PGO) goes high after a delay of 300 ms. When the PGI voltage or either the 3.3-V and 5-V power rails drops below the under-voltage threshold, PGO is disabled immediately (after 150-s debounce). power supply remote on/off (PSON) and fault protect output (FPO) Since the latest personal computer generation focuses on easy turnon and power saving functions, the PC power supply requires two characteristics. One is a dc power supply remote on/off function, the other is standby voltage to achieve very low power consumption of the PC system. Thus the main power needs to be shut down. The power supply remote on/off (PSON) is an active low signal that turns on all of the main power rails including 3.3 V, 5 V, -5 V, 12 V, and -12 V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver current and should be held at 0 V. When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs of the main power rails should not deliver current but are held at 0 V. Toggling the power supply remote on/off (PSON) from low to high resets the fault-protection latch. During this fault condition only the standby power is not affected. When PSON goes from high to low or low to high, the 38-ms debounce block is active to avoid a glitch on the input that disables/enables the FPO output. During this period the under-voltage function is disabled for 75 ms to prevent turnon failure. At turnoff, there is an additional delay of 2.3 ms from PSON to FPO. Power should be delivered to the rails only if the PSON signal is held at ground potential, thus FPO is active-low. The FPO pin can be connected to 5 V (or up to 15 V) through a pullup resistor. under-voltage protection The TPS3510 provides under-voltage protection (UVP) for the 3.3-V and 5-V rails. When an under voltage condition appears at either one of the 3.3-V (VS33) or 5-V (VS5) input pins for more than 146 s, the FPO output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or VDD is removed. The need for under voltage protection is often overlooked in off-line switching power supply system design. But it is very important in battery-powered or hand-held equipment since the TTL or CMOS logic often results in malfunction. In flyback or forward-type off-line switching power supplies, usually designed for low power, the over-load protection design is very simple. Most of these types of power supplies are only sensing the input current for an overload condition. The trigger point needs to be set much higher than the maximum load in order to prevent false turnon. However, this causes one critical problem. If the connected load is larger than the maximum allowable load but smaller than the trigger point, the system always becomes overheated with failure and damage occurring. over-voltage protection The over voltage protection (OVP) of TPS3510 monitors 3.3 V, 5 V, and 12 V (12 V is sensed via the VDD pin). When an over-voltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 s, the FPO output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or VDD is removed. During fault conditions, most power supplies have the potential to deliver higher output voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages to be high enough to cause internal or external damage of the system. To protect the system under these abnormal conditions, it is common practice to provide over-voltage protection within the power supply. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 Because TTL and CMOS circuits are very vulnerable to over-voltages, it is becoming industry standard to provide overvoltage protection on all 3.3-V and 5-V outputs. However, not only the 3.3-V and 5-V rails for the logic circuits on the motherboard need to be protected, but also the 12-V peripheral devices such as the hard disk, floppy disk, and CD-ROM players etc., need to be protected. short-circuit power supply turnon During safety testing the power supply might have tied the output voltage direct to ground. If this happens during the normal operating, this is called a short-circuit or over-current condition. When it happens before the power supply turns on, this is called a short-circuit power supply turn on. It can happen during the design period, in the production line, at quality control inspection or at the end user. The TPS3510 provides an under-voltage protection function with a 75-ms delay after PSON is set low. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Output voltage VO: FPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V PGO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40_C to 85_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE P D TA 25C POWER RATING 1092 mW 730 mW DERATING FACTOR ABOVE TA = 25C 8.74 mW/C 5.84 mW/C TA = 70C POWER RATING 699 mW 467 mW TA = 85C POWER RATING 568 mW 379 mW recommended operating conditions at specified temperature range MIN Supply voltage, VDD PSON, VS5, VS33 Input voltage, VI PGI FPO PGO FPO PGO See Note 2 1 -40 85 4 NOM MAX 15 7 VDD + 0.3 V (max = 7 V) 15 7 20 10 V UNIT V Output voltage, VO voltage Output sink current, IO,sink current O i k Supply voltage rising time, tr Operating free-air temperature range, TA V mA ms C NOTE 2: VDD rising and falling slew rate must be less than 14 V/ms. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) over-voltage protection PARAMETER VS33 Over-voltage threshold ILKG VOL Leakage current (FPO) Low-level output voltage (FPO) Noise deglitch time OVP VS5 VDD V(FPO) = 5 V VDD = 5 V, VDD = 5 V Isink = 20 mA 35 73 TEST CONDITIONS MIN 3.7 5.7 13.2 TYP 3.9 6.1 13.8 MAX 4.1 6.5 14.4 5 0.7 110 A V s V UNIT PGI and PGO PARAMETER VPGI VIT ILKG VOL Input threshold voltage (PGI) Under-voltage Under voltage threshold Leakage current (PGO) Low-level output voltage (PGO) Short-circuit protection delay td1 Delay time 3.3 V, 5 V PGI to PGO PGI to FPO PGI to PGO Noise deglitch time PGI to FPO UVP to FPO VDD = 5 V VDD = 5 V PGI1 PGI2 VS33 VS5 PGO = 5 V VDD = 4 V, Isink = 10 mA 49 200 3.2 88 180 82 75 300 4.8 150 296 146 TEST CONDITIONS MIN 1.1 0.9 2 3.3 TYP 1.15 0.95 2.2 3.5 MAX 1.2 1 2.4 3.7 5 0.4 114 450 7.2 225 445 220 s UNIT V V A V ms ms PSON control PARAMETER II VIH VIL tb td2 Input pullup current High-level input voltage Low-level input voltage Debounce time (PSON) Delay time (PSON to FPO) VDD = 5 V VDD = 5 V 24 tb+1.1 38 tb+2.3 TEST CONDITIONS PSON = 0 V 2.4 1.2 57 tb+4 MIN TYP 120 MAX UNIT A V V ms ms total device PARAMETER IDD Supply current TEST CONDITIONS PSON = 5 V MIN TYP MAX 1 UNIT mA 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 400 TA = -40C 300 I DD - Supply Current - A 0 -20 -40 -60 -80 -100 -200 -300 0 2.5 5 7.5 10 12.5 15 VDD - Supply Voltage - V PGI = 1.4 V PSON = 5 V -120 -140 20 VDD = 4 V INPUT CURRENT (PSON) vs INPUT VOLTAGE (PSON) 200 100 TA = 0C 0 I I - Input Current - A TA = 85C TA = 25C -100 TA = -40C TA = 0C TA = 25C TA = 85C 0 1 2 3 4 5 6 7 VI - Input Voltage - V Figure 2 LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) 4 VDD = 4 V PSON = GND 800 VOL- Low-Level Output Voltage - mV 700 600 500 400 300 TA = 25C 200 100 0 0 40 60 80 100 IOL - Low-Level Output Current - mA 20 120 0 0 Figure 3 LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) VDD = 4 V PSON = GND Exploded View TA = 85C VOL - Low-Level Output Voltage - V 3 TA = 85C 2 TA = 25C 1 TA = 0C TA = -40C TA = -40C TA = 0C 5 10 15 20 IOL - Low-Level Output Current - mA 25 Figure 4 Figure 5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) 4 VOL - Low-Level Output Voltage - mV VDD = 4 V PSON = GND VOL - Low-Level Output Voltage - V TA = 85C 3 600 LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) VDD = 4 V PSON = GND Exploded View 500 400 TA = 85C 300 2 TA = -40C TA = 25C 1 TA = 0C 200 TA = 25C TA = -40C 100 TA = 0C 0 0 50 75 100 125 IOL - Low-Level Output Current - mA 25 150 0 0 5 10 15 IOL - Low-Level Output Current - mA 20 Figure 6 NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD 1.001 VDD = 4 V PSON = GND 1 0.999 Figure 7 Normalized Input Threshold Voltage - VIT(TA)/VIT(25 C ) 0.998 0.997 0.996 0.995 0.994 -40 60 -15 10 35 TA - Free-Air Temperature - C 85 Figure 8 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 MECHANICAL DATA D (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M Gage Plane 0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 - JULY 2000 MECHANICAL DATA P (R-PDIP-T8) 0.400 (10,60) 0.355 (9,02) 8 5 PLASTIC DUAL-IN-LINE 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane 0.020 (0,51) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.430 (10,92) MAX 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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