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TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS290 - APRIL 2000
D D D D D D D D D D
Dual Supervisory Circuits With Power-Fail for DSP and Processor-Based Systems Voltage Monitor for Power-Fail or Low-Battery Warning Watchdog Timer With 0.8 Second Time-Out Power-On Reset Generator With Integrated 100 ms Delay Time Open-Drain Reset and Power-Fail Output Supply Current of 15 A (TYP.) Supply Voltage Range . . . 2.7 V to 6 V Defined RESET Output From VDD 1.1 V MSOP-8 and SO-8 Packages Temperature Range . . . - 40C to 85C
D
Applications Include - Multivoltage DSPs and Processors - Portable Battery-Powered Equipment - Embedded Control Systems - Intelligent Instruments - Automotive Systems
D OR DGK PACKAGE (TOP VIEW)
SENSE1 SENSE2 PFI GND
1 2 3 4
8 7 6 5
VDD WDI PFO RESET
description
The TPS3306 family is a series of supervisory circuits designed for circuit initialization which require two supply voltages, primarily in DSP and processor-based systems. The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of 3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V.
TYPICAL OPERATING CIRCUIT 3.3 V 1.5 V AVDD TPS3306-15 SENSE1 R1 1% SENSE2 PFI R2 1% GND VDD WDI PFO RESET R3 R4 CVDD DVDD B_XF A_XF RESET VSS VSSA TMS320 VC5441
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS290 - APRIL 2000
description (continued)
The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the following supply voltage monitoring table.
SUPPLY VOLTAGE MONITORING DEVICE TPS3306-15 TPS3306-18 TPS3306-20 TPS3306-25 TPS3306-33 NOMINAL SUPERVISED VOLTAGE SENSE1 3.3 V 3.3 V 3.3 V 3.3 V 5V SENSE2 1.5 V 1.8 V 2V 2.5 V 3.3 V THRESHOLD VOLTAGE (TYP) SENSE1 2.93 V 2.93 V 2.93 V 2.93 V 4.55 V SENSE2 1.4 V 1.68 V 1.85 V 2.25 V 2.93 V
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below the threshold voltage VIT. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td(typ) = 100 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage VIT. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT, the output becomes active (low) again. The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply. The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, tt(out) = 0.50 s, RESET becomes active for the time period td . This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. The TPS3306-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages. The TPS3306-xx family is characterized for operation over a temperature range of - 40C to 85C.
AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE (D) TPS3305-15D TPS3305-18D -40_C to 85_C TPS3305-20D TPS3305-25D TPS3305-33D -SMALL OUTLINE (DGK) TPS3306-15DGK TPS3306-18DGK TPS3306-20DGK TPS3306-25DGK TPS3306-33DGK MARKING DGK PACKAGE TIAIC TIAID TIAIE TIAIF TIAIG
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TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS290 - APRIL 2000
description (continued)
FUNCTION/TRUTH TABLES SENSE1>VIT1 0 0 1 1 SENSE2>VIT2 0 1 0 1 FUNCTION/TRUTH TABLES PFI>VIT 01 10 PFO LH HL TYPICAL DELAY 0.5 s 0.5 s RESET L L L H
functional block diagram
SENSE 1 R1 + _ R2 R3 + _ RESET Logic + Timer TPS3306 VDD
SENSE 2
RESET
R4 GND Reference Voltage of 1.25 V PFI
Oscillator PFO _ +
WDI
Transition Detection 40 k
Watchdog Logic + Timer
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TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS290 - APRIL 2000
timing diagram
SENSEn V(nom) VIT 1.1 V t WDI 1 tt(out) 0 RESET 1 Undefined Behavior 0 td td td t RESET Because of Power-Down RESET Because of WDI RESET Because of a Power Drop Below VIT- RESET Because of Power-Up Undefined Behavior t
Terminal Functions
TERMINAL NAME GND PFI PFO RESET SENSE1 SENSE2 WDI VDD NO. 4 3 6 5 1 2 7 8 I/O I I O O I I I I Ground Power-fail comparator input Power-fail comparator output, open-drain Active-low reset output, open-drain Sense voltage input 1 Sense voltage input 2 Watchdog timer input Supply voltage DESCRIPTION
detailed description
watchdog In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to typically toggle the watchdog input within 0.8 s to avoid a time out occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected or tied with a high impedance driver, the watchdog is disabled and will be retriggered internally.
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SLVS290 - APRIL 2000
detailed description (continued)
saving current while using the watchdog The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the time-out period, a current of 5 V/40 k 125 A can flow into WDI.
VDD VIT
WDI
t
t(tout)
RESET
t
td
td
t
Figure 1. Watchdog Timing power-fail comparator (PFI & PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input (PFI) will be compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold (VPFI) of typ. 1.25 V, the power-fail output (PFO) goes low. If it goes above 1.25 V plus about 10 mV hysteresis, the output returns to high. By connecting 2 external resistors, it is possible to supervise any voltages above 1.25 V. The sum of both resistors should be about 1 M, to minimize power consumption and also to assure that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected.
VPFI,trip = 1.25 V x R1 + R2 R2 V(SENSE) R1 1% PFI R2 1%
VCC PFO TPS3306 GND
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TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL
SLVS290 - APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h continuously. DISSIPATION RATING TABLE PACKAGE DGK D TA 25C POWER RATING 424 mW 725 mW DERATING FACTOR ABOVE TA = 25C 3.4 mW/C 5.8 mW/C TA = 70C POWER RATING 271 mW 464 mW TA = 85C POWER RATING 220 mW 377 mW
recommended operating conditions at specified temperature range
MIN Supply voltage, VDD Input voltage at WDI and PFI, VI Input voltage at SENSE1 and SENSE2, VI High-level input voltage at WDI, VIH Low-level input voltage at WDI, VIL Operating free-air temperature range, TA -40 2.7 0 0 0.7xVDD 0.3xVDD 85 MAX 6 VDD+0.3 (VDD+0.3)VIT/1.25 V UNIT V V V V V C
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SLVS290 - APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VDD = 2.7 V to 6 V, IOL = 20 A VOL Low-level output voltage RESET, PFO VDD = 3.3 V, VDD = 6 V, Power-up reset voltage (see Note 2) VDD 1.1 V, IOL = 2 mA IOL = 3 mA IOL = 20 A 1.37 1.64 VSENSE1, VSENSE2 1.81 VDD = 2 7 V to 6 V 2.7 V, TA = 0C to 85C 2.20 2.86 4.46 VIT Negative-going input threshold voltage g gg g (see Note 3) PFI 1.22 1.37 1.64 VSENSE1, VSENSE2 1.81 VDD = 2 7 V to 6 V 2.7 V, TA = -40C to 85C 2.20 2.86 4.46 PFI PFI VIT = 1.25 V VIT = 1.40 V VIT = 1.68 V VIT = 1.86 V VIT = 2.25 V VIT = 2.93 V VIT = 4.55 V WDI = VDD = 6 V Time average (dc = 88%) WDI = 0 V, VDD = 6 V, Time average (dc = 12%) WDI = VDD = 6 V, VSENSE1 = VDD = 6 V VSENSE2 = VDD = 6 V VDD, = 6 V VDD = 6 V, 0 V VI VDD WDI = 0 V, -25 15 1.22 1.40 1.68 1.85 2.25 2.93 4.55 1.25 1.40 1.68 1.85 2.25 2.93 4.55 1.25 10 15 15 20 20 30 40 100 -15 120 5 6 -120 150 A -20 170 8 9 -170 25 40 A nA A A mV MIN TYP MAX 0.2 0.4 0.4 0.4 1.43 1.72 1.89 2.30 3 4.64 1.28 1.44 1.73 1.90 2.32 3.02 4.67 1.29 V V V V UNIT
Vhys y
Hysteresis
VSENSEn
IH(AV) IL(AV)
Average high-level input current WDI Average low-level input current WDI
IH IL II IDD Ci
High-level input current Low-level input current Input current Supply current Input capacitance
SENSE1 SENSE2 WDI PFI
VI = 0 V to VDD 10 pF NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD 15 s/V. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 F) should be placed close to the supply terminals.
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SLVS290 - APRIL 2000
timing requirements at VDD = 2.7 V to 6 V, RL = 1 M, CL = 50 pF, TA = 25C
PARAMETER tw Pulse width SENSEn WDI TEST CONDITIONS VSENSEnL = VIT -0.2 V, VIH = 0.7 x VDD, VSENSEnH = VIT +0.2 V VIL = 0.3 x VDD MIN 6 100 TYP MAX UNIT s ns
switching characteristics at VDD = 2.7 V to 6 V, RL = 1 M, CL = 50 pF, TA = 25C
PARAMETER tt(out) td tPHL tPHL tPLH Watchdog time out Delay time Propagation (delay) time, high-to-low level output Propagation (delay) time, high-to-low level output Propagation (delay) time, low-to-high level output PFI to PFO SENSEn to RESET TEST CONDITIONS VI(SENSEn) VIT + 0.2 V, See timing diagram VI(SENSEn) VIT + 0.2 V, See timing diagram VIH = VIT +0.2 V, VIL = VIT -0.2 V MIN 0.5 70 TYP 0.8 100 1 MAX 1.2 140 5 UNIT s ms s
05 0.5
1
s
TYPICAL CHARACTERISTICS
NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD
1.005 1.004 1.003 I DD - Supply Current - A 1.002 1.001 1 0.999 0.998 0.997 0.996 0.995 -40 60 -15 10 35 TA - Free-Air Temperature - C 85 VDD = 6 V 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 SENSEn = VDD TA = 25C TPS3306-33
Normalized Input Threshold Voltage - VIT(TA), VIT(25 C)
SUPPLY CURRENT vs SUPPLY VOLTAGE
-8 -10 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VDD - Supply Voltage - V
Figure 2
Figure 3
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SLVS290 - APRIL 2000
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
2.8 VDD = 2.7 V VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - V 2.4 2 1.6 1.2 0.8 -40C 0.4 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 IOL - Low-Level Output Current - mA 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 IOL - Low-Level Output Current - mA -40C 85C VDD = 6 V
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
85C
Figure 4
MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE
10 tw - Minimum Pulse Duration at Vsense - s 9 8 7 6 5 4 3 2 1 0 0 VDD = 6 V
Figure 5
100 200 300 400 500 600 700 800 900 1000 SENSE - Threshold Overdrive - mV
Figure 6
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SLVS290 - APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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SLVS290 - APRIL 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,25 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
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Copyright (c) 2000, Texas Instruments Incorporated

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