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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
D D D D D D D D D D D D
Open Drain Power-On Reset With 220-ms Delay (TPS773xx) Open Drain Power-Good (PG) Status Output (TPS774xx) 250-mA Low-Dropout Voltage Regulator Available in 1.8-V, 2.7-V, 2.8-V, 3.3-V, Fixed Output and Adjustable Versions Dropout Voltage Typically 200 mV at 250 mA (TPS77333, TPS77433) Ultralow 92-A Quiescent Current (Typ) 8-Pin MSOP (DGK) Package Low Noise (55 Vrms) Without an External Filter (Bypass) Capacitor (TPS77318, TPS77418) 2% Tolerance Over Specified Conditions For Fixed-Output Versions Fast Transient Response Thermal Shutdown Protection See the TPS779xx Family of Devices for Active High Enable
TPS773xx DGK PACKAGE (TOP VIEW)
FB/SENSE RESET EN GND
1 2 3 4
8 7 6 5
OUT OUT IN IN
TPS774xx DGK PACKAGE (TOP VIEW)
FB/SENSE PG EN GND
1 2 3 4
8 7 6 5
OUT OUT IN IN
TPS77x33
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
300
description
The TPS773xx and TPS774xx are low-dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 250 mA of output current with a dropout of 200 mV (TPS77333, TPS77433). Quiescent current is 92 A at full load dropping down to 1 A when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10 F) or low capacitance (1 F) tantalum capacitors. These devices have extremely low noise output performance (55 Vrms) without using any added filter capacitors. TPS773xx and TPS774xx are designed to have fast transient response for larger load current changes.
VDO - Dropout Voltage - mV
250
IO = 250 mA
200
150
100 IO = 10 mA 50 0 -40 IO = 0 A
120 0 40 80 TJ - Junction Temperature - C
140
The TPS773xx or TPS774xx is offered in 1.8-V, 2.7-V, 2.8-V and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS773xx and TPS774xx families are available in 8-pin MSOP (DGK) packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV at an output current of 250 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 A over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 A at TJ = 25C. The TPS773xx features an integrated power-on reset, commonly used as an supply voltage supervisor (SVS), or reset output voltage. The RESET output of the TPS773xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS773xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after a 220 ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage. For the TPS774xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS774xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage.
AVAILABLE OPTIONS OUTPUT VOLTAGE (V) TYP 3.3 2.8 - 40 C to 125C 40C 125 C 2.7 1.8 Adjustable 1.5 V to 5.5 V TPS77333DGK TPS77328DGK TPS77327DGK TPS77318DGK TPS77301DGK PACKAGED DEVICES MSOP (DGK) TPS77433DGK TPS77428DGK TPS77427DGK TPS77418DGK TPS77401DGK
TJ
NOTE: The TPS77301 and TPS77401 are programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77301DGKR).
VI
5 6
IN IN
OUT OUT SENSE
7 8 1 2 +
VO
0.1 F
3 EN
PG or RESET GND
PG or RESET Output 10 F
4
Figure 1. Typical Application Configuration (For Fixed Output Options)
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
functional block diagrams
adjustable version
IN EN PG or RESET _ + OUT
+ _ Vref = 1.1834 V
220 ms Delay (for TPS773xx Option) FB/SENSE
R1
R2
GND
External to the Device
fixed-voltage version
IN EN PG or RESET _ + OUT SENSE R1
+ _ Vref = 1.1834 V
220 ms Delay (for TPS773xx Option)
R2
GND
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
Terminal Functions
TERMINAL NAME TPS773XX FB/SENSE RESET EN GND IN OUT TPS774XX FB/SENSE PG EN GND IN OUT 1 2 3 4 5, 6 7, 8 I O I O I Feedback input voltage for adjustable device (sense input for fixed options) Power good Enable input Regulator ground Input voltage Regulated output voltage 1 2 3 4 5, 6 7, 8 I O I O I Feedback input voltage for adjustable device (sense input for fixed options) Reset output Enable input Regulator ground Input voltage Regulated output voltage NO. I/O DESCRIPTION
TPS773xx RESET timing diagram
VI
Vres t VO Threshold Voltage VIT - VIT - t RESET Output 220 ms Delay 220 ms Delay VIT + VIT +
Vres
Output Undefined
Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VIT - Trip voltage is typically 5% lower than the output voltage (95%VO) VIT- to VIT+ is the hysteresis voltage.
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II II II II
t
II II II II
Output Undefined
TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TPS774xx PG timing diagram
VI
Vres t VO Threshold Voltage VIT - VIT - t PG Output VIT + VIT +
Vres
Output Undefined
Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VIT - Trip voltage is typically 18% lower than the output voltage (82%VO) VIT- to VIT+ is the hysteresis voltage.
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II II II II
t
II II II II
Output Undefined
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 13.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16.5 V Maximum RESET voltage (TPS773xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Maximum PG voltage (TPS774xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE - FREE-AIR TEMPERATURES PACKAGE AIR FLOW (CFM) 0 DGK 150 250 JA (C/W) 266.2 255.2 242.8 JC (C/W) 3.84 3.92 4.21 TA < 25C POWER RATING 376 mW 392 mW 412 mW DERATING FACTOR ABOVE TA = 25C 3.76 mW/C 3.92 mW/C 4.12 mW/C TA = 70C POWER RATING 207 mW 216 mW 227 mW TA = 85C POWER RATING 150 mW 157 mW 165 mW
recommended operating conditions
MIN Input voltage, VI Output voltage range, VO Output current, IO (see Note 1) 2.7 1.5 0 MAX 10 5.5 250 UNIT V V mA
Operating virtual junction temperature, TJ (see Note 1) - 40 125 C To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
electrical characteristics over recommended operating junction temperature range (TJ = -40C to 125C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 F (unless otherwise noted)
PARAMETER Adjustable j voltage 1 8 V Output 1.8 Output voltage (see Notes 2 and 4) 2.7 2 7 V Output 2.8 2 8 V Output 3.3 3 3 V Output Quiescent current (GND current) (see Notes 2 and 4) Output voltage line regulation (VO/VO)(see Note 3) Load regulation Output noise voltage Output current limit Peak output current Thermal shutdown junction temperature Standby current FB input current High level enable input voltage Low level enable input voltage Enable input current Power supply ripple rejection (TPS77318, TPS77418) Minimum input voltage for valid PG Trip threshold voltage PG (TPS774xx) Hysteresis voltage Output low voltage f = 1 kHz, I(PG) = 300 A VO decreasing Measured at VO VI = 2.7 V, I(PG) = 1 mA TJ = 25C V(PG) 0.8 V 79 0.5 0.15 0.4 -1 55 1.1 85 Adjustable voltage EN = VI, EN = VI FB = 1.5 V 2 0.7 1 TJ = 25C TEST CONDITIONS 1.5 V VO 5.5 V, 1.5 V VO 5.5 V TJ = 25C, 2.8 V < VIN < 10 V TJ = 25C, 3.7 V < VIN < 10 V TJ = 25C, 3.8 V < VIN < 10 V TJ = 25C, 4.3 V < VIN < 10 V TJ = 25C VO + 1 V < VI 10 V, TJ = 25C VO + 1 V < VI 10 V TJ = 25C BW = 300 Hz to 100 kHz, TJ = 25C, TPS77318, TPS77418 VO = 0 V 2 ms pulse width, 2.8 V < VIN < 10 V 1.764 3.7 V < VIN < 10 V 2.646 3.8 V < VIN < 10 V 2.744 4.3 V < VIN < 10 V 3.234 92 125 0.005 0.05 1 55 0.9 50% duty cycle 400 144 1 3 1 1.3 3.3 3.366 A %/V %/V mV Vrms A mA C A A A V V A dB V %VO %VO V 2.8 2.856 2.7 2.754 TJ = 25C 0.98VO 1.8 1.836 V MIN TYP VO 1.02VO MAX UNIT
Leakage current V(PG) = 5 V 1 A NOTES: 2. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output current 1 mA. 3. If VO < 1.8 V then VI(max) = 10 V, VI(min) = 2.7 V: Line regulation (mV)
+ +
V %V
O
V
I(max) 100
* 2.7 V *
V
1000
If VO > 2.5 V then VI(max) = 10 V, VI(min) = Vo + 1 V: V %V Line regulation (mV) 4. IO = 1 mA to 250 mA O V
I(max) 100
O
)1
1000
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
electrical characteristics over recommended operating junction temperature range (TJ = -40C to 125C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 F (unless otherwise noted) (continued)
PARAMETER Minimum input voltage for valid RESET Trip threshold voltage Reset (TPS773xx) Hysteresis voltage Output low voltage Leakage current RESET time-out delay 2.8 V Output VDO Dropout voltage (see Note 5) 3.3 V Output IO = 250 mA, IO = 250 mA IO = 250 mA, IO = 250 mA TJ = 25C TJ = 25C TEST CONDITIONS I(RESET) = 300 A VO decreasing Measured at VO VI = 2.7 V, V(RESET) = 5 V I(RESET) = 1 mA MIN 92 0.5 0.15 220 270 475 200 330 mV 0.4 1 TYP 1.1 98 MAX UNIT V %VO %VO V A ms
NOTE 5: IN voltage equals VO(Typ) - 100 mV; 1.8 V, and 2.7 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage needs to drop to 3.2 V for purpose of this test).
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE VO Output voltage Ground current Power supply rejection ratio Output spectral noise density Zo VDO Output impedance Dropout voltage Line transient response Load transient response Output voltage and enable pulse Equivalent series resistance (ESR) vs Time vs Output current vs Output current vs Junction temperature vs Junction temperature vs Frequency vs Frequency vs Frequency vs Input voltage vs Junction temperature 2, 3 4, 5 6 7 8 9 10 11 12, 14 13, 15 16 18 - 21
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS77x33 TPS77x18
OUTPUT VOLTAGE vs OUTPUT CURRENT
3.302 1.802
OUTPUT VOLTAGE vs OUTPUT CURRENT
VO - Output Voltage - V
VO - Output Voltage - V
3.301
1.801
3.3
1.800
3.299
1.799
3.298 0 50 100 150 200 IO - Output Current - mA 250
1.798 0 50 100 150 200 IO - Output Current - mA 250
Figure 2
TPS77x33
Figure 3
TPS77x18
OUTPUT VOLTAGE vs JUNCTION TEMPERATURE
3.35 VI = 4.3 V 3.33 VO - Output Voltage - V IO = 250 mA 3.31 VO - Output Voltage - V 1.84 1.86
OUTPUT VOLTAGE vs JUNCTION TEMPERATURE
VI = 2.8 V
1.82
1.80 IO = 1 mA IO = 50 mA IO = 250 mA
3.29
1.78
3.27
3.25 -40
120 0 40 80 TJ - Junction Temperature - C
140
1.77 -40
0
40
80
120
140
TJ - Junction Temperature - C
Figure 4
Figure 5
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS77xxx
GROUND CURRENT vs JUNCTION TEMPERATURE
115 110 105
Ground Current - A
100 IO = 1 mA 95
90 85 IO = 250 mA 80 -40 10 60 110 140
TJ - Junction Temperature - C
Figure 6
TPS77x33 TPS77x33
POWER SUPPLY REJECTION RATIO vs FREQUENCY
100 PSRR - Power Supply Rejection Ratio - dB Output Spectral Noise Density - V Hz 90 80 70 60 50 40 30 20 10 0 10 100 1k 10k 100k 1M 10M f - Frequency - Hz IO = 250 mA IO = 1 mA CO = 10 F TJ = 25 C 10
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
CO = 10 F TJ = 25 C IO = 250 mA 1 IO = 1 mA
0.1
0.01 100
1k f - Frequency - Hz
10k
100k
Figure 7
Figure 8
10
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS77x33
OUTPUT IMPEDANCE vs FREQUENCY
10 TJ = 25 C IO = 1 mA Zo - Output Impedance - 1
0.1 IO = 250 mA
0.01 10
100
1k 10k 100k f - Frequency - Hz
1M
10M
Figure 9
TPS77x01 TPS77x33
DROPOUT VOLTAGE vs INPUT VOLTAGE
400 IO = 250 mA 350 VDO - Dropout Voltage - mV 300 250 200 150 100 50 0 2.7 TJ = 125 C VDO - Dropout Voltage - mV TJ = 25 C TJ = -40 C 250 300
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
IO = 250 mA
200
150
100 IO = 10 mA 50 0 -40 IO = 0 A
3.2
3.7 4.2 VI - Input Voltage - V
4.7
120 0 40 80 TJ - Junction Temperature - C
140
Figure 10
Figure 11
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS77x18 TPS77x18
LINE TRANSIENT RESPONSE
IO - Output Current - mA VI - Input Voltage - V
LOAD TRANSIENT RESPONSE
3.8 2.8
250 0 +50
10 VO - Change in Output Voltage - mV 0 -10 VO - Change in Output Voltage - mV 0 -50 CO = 10 F TJ = 25 C IO = 250 mA 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t - Time - ms 1.8 2
CO = 10 F TJ = 25 C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t - Time - ms 0.9 1
Figure 12
TPS77x33
Figure 13
TPS77x33
LINE TRANSIENT RESPONSE
IO - Output Current - mA VI - Input Voltage - V
LOAD TRANSIENT RESPONSE
5.3 4.3
250 0
10 VO - Change in Output Voltage - mV VO - Change in Output Voltage - mV 0 -10 0 -50 -100 CO = 10 F TJ = 25 C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t - Time - ms 0.9 1
CO = 10 F TJ = 25 C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t - Time - ms 0.9 1
Figure 14
Figure 15
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS77x33
OUTPUT VOLTAGE AND ENABLE PULSE vs TIME (AT STARTUP)
Enable Pulse - V CO = 10 F TJ = 25 C
EN 0
VO - Output Voltage - V
0
0
0.2 0.4
0.6
0.8 1.0 1.2 1.4 t - Time - ms
1.6 1.8
2.0
Figure 16
VI
IN OUT + EN
To Load
CO GND ESR
RL
Figure 17. Test Circuit for Typical Regions of Stability (Figures 25 through 28) (Fixed Output Options)
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT
10 Region of Instability VO = 3.3 V CO = 1 F VI = 4.3 V TJ = 25C 1 ESR - Equivalent Series Resistance - ESR - Equivalent Series Resistance - 10
EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT
Region of Instability
1
Region of Stability
Region of Stability
0.1 VO = 3.3 V CO = 10 F VI = 4.3 V TJ = 25C Region of Instability 0.01
Region of Instability 0.1 0 50 100 150 200 250 IO - Output Current - mA 0 50 100
150
200
250
IO - Output Current - mA
Figure 18
TYPICAL REGION OF STABILITY
Figure 19
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT
10 Region of Instability VO = 3.3 V CO = 1 F VI = 4.3 V TJ = 125 C 1 ESR - Equivalent Series Resistance - ESR - Equivalent Series Resistance - 10
EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT
Region of Instability
1
Region of Stability
Region of Stability
0.1 VO = 3.3 V CO = 10 F VI = 4.3 V TJ = 125C Region of Instability 0.01
Region of Instability 0.1 0 50 100 150 200 250 IO - Output Current - mA 0 50 100
150
200
250
IO - Output Current - mA
Figure 20
Figure 21
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.
14
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TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
APPLICATION INFORMATION pin functions
enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. power good (PG) (TPS774xx) The PG terminal is an open drain, active high output that indicates the status of Vout (output of the LDO). When Vout reaches 82% of the regulated voltage, PG will go to a high-impedance state. It will go to a low-impedance state when Vout falls below 82% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. reset (RESET) (TPS773xx) The RESET terminal is an open drain, active low output that indicates the status of Vout. When Vout reaches 95% of the regulated voltage, RESET will go to a low-impedance state after a 220-ms delay. RESET will go to a high-impedance state when Vout is below 95% of the regulated voltage. The open-drain output of the RESET terminal requires a pullup resistor.
external capacitor requirements
An input capacitor is not usually required; however, a bypass capacitor (0.047 F or larger) improves load transient response and noise rejection if the TPS773xx or TPS774xx is located more than a few inches from the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board space. The TPS773xx and TPS774xx have very low noise specification requirements without using any external components. Like all low dropout regulators, the TPS773xx or TPS774xx requires an output capacitor connected between OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum recommended capacitance value is 1 F provided the ESR meets the requirement in Figures 19 and 21. In addition, a low-ESR capacitor can be used if the capacitance is at least 10 F and the ESR meets the requirements in Figures 18 and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
APPLICATION INFORMATION external capacitor requirements (continued)
Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature; therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the requirement specified in Figures 18 - 21. Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
IO LDO
-
VESR
+
RESR
+
VI
RLOAD
VO
-
CO
Figure 22. - LDO Output Stage With Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (VCout = Vout). This means no current is flowing into the Cout branch. If Iout suddenly increases (transient condition), the following occurs:
D D
The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 23). Therefore, capacitor Cout provides the current for the new load condition (dashed arrow). Cout now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 22. When Cout is conducting current to the load, initial voltage at the load will be Vout = VCout - VESR. Due to the discharge of Cout, the output voltage Vout will drop continuously until the response time t1 of the LDO is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 23.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn:
D D
The higher the ESR, the larger the droop at the beginning of load transient. The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period.
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
APPLICATION INFORMATION
conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement.
Iout
Vout 1 2 3 ESR 1 ESR 2 ESR 3
t1
t2
Figure 23. - Correlation of Different ESRs and Their Influence to the Regulation of Vout at a Load Step From Low-to-High Output Current
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
APPLICATION INFORMATION programming the TPS77x01 adjustable LDO regulator
The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as shown in Figure 28. The output voltage is calculated using: V Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50-A divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 50 A and then calculate R1 using: R1 O
+ Vref
1
) R1 R2
(1)
+
V V
O
ref
*1
R2
OUTPUT VOLTAGE PROGRAMMING GUIDE OUTPUT VOLTAGE 2.5 V 3.3 V VO R1 FB/SENSE GND CO 3.6 V R1 33.3 53.6 61.9 R2 30.1 30.1 30.1 UNIT k k k
(2)
TPS77x01 VI IN PG or RESET OUT PG or RESET Output 250 k EN
0.1 F
R2
NOTE: To reduce noise and prevent oscillation, R1 and R2 need to be as close as possible to the FB/SENSE terminal.
Figure 24. TPS77x01 Adjustable LDO Regulator Programming
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
APPLICATION INFORMATION regulator protection
The TPS773xx or TPS774xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS773xx or TPS774xx also features internal current limiting and thermal protection. During normal operation, the TPS773xx or TPS774xx limits output current to approximately 0.9 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130C(typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125C; the maximum junction temperature should be restricted to 125C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P Where: TJmax is the maximum allowable junction temperature. RJA is the thermal resistance junction-to-ambient for the package, i.e., 266.2C/W for the 8-terminal MSOP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: P D D(max)
+ TJmax * TA R
qJA
+ VI * VO
I
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
19
TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG
SLVS281B - FEBRUARY 2000 - REVISED JUNE 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,25 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
20
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 2000, Texas Instruments Incorporated

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