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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
D D D D D D D D D D D D D D D
Fully Integrated xVCC and xVPP Switching xVPP Programmed Independent of xVCC 3.3-V, 5-V, and/or 12-V Power Distribution Low rDS(on) (60-m 3.3-V xVCC Switch and 140-m 5-V xVCC Switch Typical) Short Circuit and Thermal Protection 150-A (Maximum) Quiescent Current Standby Mode: 50-mA Current Limit (Typ) 12-V Supply Can Be Disabled 3.3-V Low-Voltage Mode Ambient Temperature . . . - 40C to 70C Meets PC CardTM Standards TTL-Logic Compatible Inputs Available in 24-Pin and 30-Pin SSOP (DB), and 32-Pin TSSOP (DAP) Packages Break-Before-Make Switching Internal Power-On Reset
TPS2214A DB PACKAGE (TOP VIEW)
5V 5V DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC GND RESET
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
5V NC MODE NC 12V BVPP BVCC BVCC STBY OC 3.3V 3.3V
NC - No internal connection
PINOUTS FOR TPS2216A DAP AND DB PACKAGES ARE PROVIDED ON PAGE 2.
description
The TPS2214A and TPS2216A PC Card power-interface switches provide an integrated power-management solution for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on single integrated circuits. These low-cost devices allow the distribution of 3.3-V, 5-V, and/or 12-V power to the card. The current-limiting feature eliminates the need for fuses. Current-limit reporting can help the user isolate a system fault. The TPS2214A and TPS2216A feature a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5-V power. This feature facilitates low-power system designs such as sleep modes where only 3.3 V is available. These devices also have the ability to program the xVPP outputs independent of the xVCC outputs. A standby mode that changes all output-current limits to 50 mA (typical) has been incorporated. End-equipment applications for these products include: notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras, and bar-code scanners. The TPS2216A is backward-compatible with the TPS2202A, TPS2206, and TPS2216. The TPS2214A is backward-compatible with the TPS2214.
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC SMALL OUTLINE (DB) PowerPAD PLASTIC SMALL OUTLINETM (DAP)
- 40C to 70C TPS2214ADB(R), TPS2216ADB(R) TPS2216ADAP(R) The DB and DAP packages are available in tubes and left-end taped and reeled. Add R suffix to device type (e.g., TPS2216ADBR) for taped and reeled.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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1
TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TPS2216A DAP PACKAGE (TOP VIEW)
TPS2216A DB PACKAGE (TOP VIEW)
5V 5V NC DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC AVCC GND RESET NC 3.3V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
5V NC MODE NC NC NC NC 12V BVPP BVCC BVCC BVCC OC STBY 3.3V 3.3V
5V 5V DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
5V MODE NC NC NC NC 12V BVPP BVCC BVCC BVCC STBY OC 3.3V 3.3V
NC - No internal connection
Terminal Functions
TERMINAL NO. NAME 3.3V 5V 12V AVCC AVPP BVCC BVPP GND MODE TPS2214 DB-24 13, 14 1, 2, 24 7, 20 9, 10 8 17, 18 19 11 22 TPS2216 DB-30 15, 16, 17 1, 2, 30 7, 24 9, 10, 11 8 20, 21, 22 23 12 29 DAP 16, 17, 18 1, 2, 32 8, 25 10, 11, 12 9 21, 22, 23 24 13 30 I I I I O O O O 3.3-V input for card power and/or chip power if 5 V is not present 5-V input for card power and/or chip power 12-V Vpp input card power VCC output: 3.3-V, 5-V, GND or high impedance to card VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card VCC output: 3.3-V, 5-V, GND or high impedance to card VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card Ground TPS2206 operation when floating or pulled low; must be pulled high externally for TPS2216A operation. MODE is internally pulled low with a 150-k pulldown resistor. Logic-level output that goes low when an overcurrent or overtemperature condition exists. Logic-level reset input active high. Do not connect if RESET pin is used. RESET is internally pulled low with a 150-k pulldown resistor. Logic-level reset input active low. Do not connect if RESET pin is used. The pin is internally pulled high with a 150-k pullup resistor. Logic-level active low input sets the TPS2216 to standby mode and sets all current limits to 50 mA. The pin is internally pulled high with a 150-k pullup resistor. Logic-level clock for serial data word Logic-level serial data word Logic-level latch for serial data word No internal connection I/O DESCRIPTION
OC RESET RESET STBY CLOCK DATA LATCH NC
15 6 12 16 4 3 5 21, 23
18 6 14 19 4 3 5 13, 25, 26, 27, 28
20 7 14 19 5 4 6 3, 15, 26, 27, 28, 29, 31
O I I I I I I
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
functional block diagram (pin numbers refer to 30-pin DB package)
TPS2216A 3.3V 3.3V 3.3V 15 16 17 S2 CS S3 CS S8 CS S9 CS S10 5V 5V 5V 1 2 30 S5 CS S6 CS S12 CS 7 S13 CS S14 CS S11 23 S4 CS 20 21 22 S7 8 AVPP S1 9 10 11 AVCC AVCC AVCC
BVCC BVCC BVCC
BVPP
12V
12V
24
Internal Current Monitor 29 19 3 4 5 6 14 18 MODE STBY DATA CLOCK LATCH RESET RESET OC GND 12 Thermal
Both 12V pins must be connected together.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
absolute maximum ratings over operating virtual free-air temperature (unless otherwise noted)
Input voltage range for card power: VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 6 V VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 6 V VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 14 V Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 6 V Output voltage range: VO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 6 V VO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 14 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output current: IO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited IO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE TA 25C DERATING FACTOR TA = 70C POWER RATING POWER RATING ABOVE TA = 25C 1095 mW 4255 mW 10.99 mW/C 42.55 mW/C 602 mW 2340 mW
PACKAGE DB DAP
TA = 85C POWER RATING 438 mW 1702 mW
These devices are mounted on an JEDEC low-k board (2 oz. traces on surface), 1-W power applied.
recommended operating conditions
MIN Input voltage, VI VI(3.3V) VI(5V) VI(12V) IO(VCC) at TA = 70C IO(VPP) at TA = 70C Data Pulse duration Data hold time Data setup time Latch delay time Clock delay time Operating virtual junction temperature, TJ Refer to Figures 2 and 3. Latch Clock 200 250 100 100 100 100 250 - 40 100 ns ns ns ns C ns 2.7 2.7 2.7 MAX 5.25 5.25 13.5 750 200 2.5 UNIT V V V mA mA MHz
Output current, IO current Clock frequency
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
electrical characteristics, TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, STBY floating, all outputs unloaded (unless otherwise noted)
power switch
PARAMETER 3.3 V to xVCC, with one or two switches on 5 V to xVCC, with one or two switches on Switch resistance 3.3 3 3 V/5 V/12 V to xVPP 3 3 V/5 V to xVCC 3.3 3.3 3 3 V/5 V/12 V to xVPP Clamp low voltage VO(xVCC) VO(xVPP) IO(xVCC) high-impedance g state Ilkg lk Leakage current IO(xVPP) high-impedance g state IO(xVCC) IO(xVPP) Standby mode, IO(xVCC) Standby mode, IO(xVPP) Current limit response time xVCC switch xVPP switch II(3.3V) II(5V) II(12V) II(3.3V) II(5V) II(12V) Shutdown mode Trip point, TJ Hysteresis II(3.3V) II(5V) II(12V) Thermal shutdown 155 10 TJ = 25C, TJ = 85C, TJ = 25C, TJ = 85C, TJ = 25C, TJ = 85C, TJ = 25C, TJ = 85C, TJ = 25C, TJ = 85C, TEST CONDITIONS VI(5V) = 0 or 5, VI(5V) = 0 or 5, IO = 750 mA IO = 750 mA IO = 50 mA IO = 50 mA STBY = low, STBY = low, STBY = low, STBY = low, IO = 30 mA IO = 30 mA IO = 30 mA IO = 30 mA IO = 750 mA IO = 750 mA MIN TYP 60 90 140 160 0.7 1.4 1.4 2 5 10 0.275 0.275 1 2 1 2 1 250 35 30 100 16 0.01 VO(xVCC) = VO(xVPP) = 5 V ( ) ( ) 100 6 100 VI(5V) = 0, 0 VO(xVCC) = 3.3 V, 33V VO(xVPP) = 12 V 0 22 30 1 VO(xVCC) = Hi-Z, VO(xVPP) = Hi-Z ( ) ( ) 1 1 C A 2 120 10 120 A A MAX 105 140 185 200 1.5 2.5 2 3 7 16 0.8 0.8 10 50 10 50 2.5 500 65 mA 60 s A mA A V m UNIT
IO(xVCC) at 10 mA, After reset IO(xVPP) at 10 mA, After reset TJ = 25C TJ = 85C TJ = 25C TJ = 85C TJ = 85C, Output powered into a short to GND TJ = 85C, Out ut owered Output powered into a short to GND GND, STBY = 0 V 100 m short circuit 100-m
IOS
Short-circuit Short circuit output current limit
Normal operation N l ti and in reset mode II Input current
Pulse-testing techniques maintain junction temperature close to ambient temperature (250-s-wide pulse, less than 0.5% duty cycle); thermal effects must be taken into account separately. Specified by design, not tested in production. Input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inactive. NOTE: VI(3.3V) or VI(5V) must be biased for switches to function.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
electrical characteristics, TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, STBY floating, all outputs unloaded (unless otherwise noted) (continued)
logic section (CLOCK, DATA, LATCH, MODE, RESET, RESET, STBY, OC)
PARAMETER II(RESET) or II(RESET) II(MODE) II(STBY) II(CLOCK) or II(DATA) or II(LATCH) Logic input high level Logic input low level Logic output high level, OC level VI(5V) = 5 V, VI(5V) = 0 V, IO = 1 mA IO = 1 mA VI(5V)-0.4 VI(3.3V)-0.4 0.4 VI(5V) = 5 V VI(5V) = 0 V 2 2 0.8 TEST CONDITIONS VI(RESET) = 5 V or VI(RESET) = 0 V VI(RESET) = 0 V or VI(RESET) = 5 V VI(MODE) = 5 V VI(MODE) = 0 V VI(STBY) = 5 V VI(STBY) = 0 V MIN TYP 30 30 MAX 50 1 50 1 1 30 50 1 V V V V A UNIT
Logic input current
Logic output low level, OC IO = 1 mA RESET and MODE have internal 150-k pulldown resistors; RESET and STBY have internal 150-k pullup resistors.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
switching characteristics
PARAMETER LOAD CONDITION CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 , F, IO(xVCC) = 0, IO(xVPP) = 0 CL(xVCC) = 150 F, F, CL(xVPP) = 10 , IO(xVCC) = 1 A, IO(xVPP) = 50 mA CL(xVCC) = 0.1 F, CL(xVPP) = 0.1 , F, IO(xVCC) = 0, IO(xVPP) = 0 CL(xVCC) = 150 F, CL(xVPP) = 10 , F, IO(xVCC) = 1 A, IO(xVPP) = 50 mA VO(xVCC) VO(xVPP) VO(xVCC) VO(xVPP) VO(xVCC) VO(xVPP) VO(xVCC) VO(xVPP) Latch to xVPP (12 V) Latch to xVPP (5 V) Latch to xVPP (3 3 V), VI(5V) = 5 V (3.3 V) Latch to xVPP (3 3 V), VI(5V) = 0 V (3.3 V) Latch to xVCC (5 V) Latch to xVCC (3 3 V) VI(5V) = 5 V (3.3 V), Latch to xVCC (3 3 V) VI(5V) = 0 V (3.3 V), ( ) tpd d Propagation delay Latch to xVPP (12 V) Latch to xVPP (5 V) Latch to xVPP (3 3 V), VI(5V) = 5 V (3.3 V) Latch to xVPP (3 3 V), VI(5V) = 0 V (3.3 V) Latch to xVCC (5 V) Latch to xVCC (3 3 V) VI(5V) = 5 V (3.3 V), Latch to xVCC (3 3 V) VI(5V) = 0 V (3.3 V), Refer to Parameter Measurement Information Specified by design: not tested in production. No card inserted, assumes 0.1-F recommended output capacitor (see Figure 32). tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) TEST CONDITIONS MIN TYP 1 0.8 ms 1.2 2.5 0.01 0.01 ms 3 8 3 25 0.6 8.5 0.6 9 1.4 9 0.3 15 0.2 15 0.4 15 4.5 13 3.3 8 3 9 3 9 1 12 0.6 12 1 12 ms MAX UNIT
tr
Output rise times
tf
Output fall times
CL(xVCC) = 0 1 F, 0.1 F CL(xVPP) = 0.1 , F, IO(xVCC) = 0, IO(xVPP) = 0
CL(xVCC) = 150 F F, CL(xVPP) = 10 , F, IO(xVCC) = 1 A, IO(xVPP) = 50 mA A
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
xVPP IO(xVPP) LOAD CIRCUITS xVCC IO(xVCC)
LATCH
50% tpd(off) 90% 10%
VDD GND
LATCH
50% tpd(off) 90% 10%
VDD GND
tpd(on) VO(xVPP)
tpd(on) VO(xVCC) GND
GND
Propagation Delay (xVPP) tf 90% 10% Rise/Fall Time (xVPP) GND
Propagation Delay (xVCC) tf 90% 10% Rise/Fall Time (xVCC) GND
tr VO(xVPP)
tr VO(xVCC)
LATCH
50% toff 90% 10% Turn On/Off Time (xVPP)
VDD GND
50% toff 90% 10% Turn On/Off Time (xVCC) VOLTAGE WAVEFORMS
VDD GND
ton VO(xVPP)
ton VO(xVCC) GND
GND
Figure 1. Test Circuits and Voltage Waveforms
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
DATA D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data Setup Time LATCH
Data Hold Time
Latch Delay Time Clock Delay Time
CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for Independent xVPP Switching When MODE = 5 V or 3.3 V
DATA
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Setup Time Data Hold Time LATCH
Latch Delay Time
Clock Delay Time CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D8, see the control logic table.
Figure 3. Serial-Interface Timing When MODE = 0 V or Floating
Table of Timing Diagrams
FIGURE Short-circuit current response, short applied to powered-on 5-V xVCC switch output Short-circuit current response, short applied to powered-on 12-V xVPP switch output OC response with ramped load on 5-V xVCC switch output 4 5 6
OC response with ramped load on 12-V xVPP switch output 7 Timing tests are conducted at free-air temperature, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, CL = 0.1 F on each output, STBY floating.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
VO(OC) 5 V/div
VO(OC) 5 V/div
IO(VCC) 5 A/div 0 200 400 600 800 1000
IO(VPP) 5 A/div 0 200 400 600 800 1000
t - Time - s
t - Time - s
Figure 4. Short-Circuit Response, Short Applied to Powered-on 5-V xVCC-Switch Output
Figure 5. Short-Circuit Response, Short Applied to Powered-on 12-V xVPP-Switch Output
VO(OC) 5 V/div
VO(OC) 5 V/div
IO(VCC) 1 A/div 0 10 20 30 40 50
IO(VPP) 0.2 A/div 0 4 8 12 16 20
t - Time - ms
t - Time - ms
Figure 6. OC Response With Ramped Load on 5-V xVCC-Switch Output
Figure 7. OC Response With Ramped Load on 12-V xVPP-Switch Output
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE tpd(on) tpd(off) tpd(on) tpd(off) tpd(on) tpd(off) tr tf tr tf tr tf II Turnon propagation delay time, 3.3-V xVCC switch Turnoff propagation delay time, 3.3-V xVCC switch Turnon propagation delay time, 5-V xVCC switch Turnoff propagation delay time, 5-V xVCC switch Turnon propagation delay time, 12-V xVPP switch Turnoff propagation delay time dc, 12-V xVPP switch Rise time, 3.3-V xVCC switch Fall time, 3.3-V xVCC switch Rise time, 5-V xVCC switch Fall time, 5-V xVCC switch Rise time, 12-V xVPP switch Fall time, 12-V xVPP switch Input current at VI(xVCC) = VI(xVPP) =3.3 V Input current at VI(xVCC) = VI(xVPP) =5 V Input current at VI(xVCC) = 5 V, VI(xVPP) =12 V Static drain-source on-state resistance, 3.3-V xVCC switch rDS(on) () Static drain-source on-state resistance, 5-V xVCC switch Static drain-source on-state resistance, 12-V xVPP switch VIO( VCC) IO(xVCC) VIO(xVPP) IOS DC input-to-output voltage (drop), 3.3-V xVCC switch DC input-to-output voltage (drop), 5-V xVCC switch DC input-to-output voltage (drop), 12-V xVPP switch Short-circuit current limit, 3.3-V xVCC switch Short-circuit current limit, 5-V xVCC switch Short-circuit current limit, 12-V xVPP switch vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Load capacitance vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Load current vs Load current vs Load current vs Junction temperature vs Junction temperature vs Junction temperature 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
NOTE: Electrical characteristics tests are conducted at VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, CL = 0.1 F on each output, STBY floating (unless otherwise noted on Figures).
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
TURNON PROPAGATION DELAY TIME, 3.3-V xVCC SWITCH vs LOAD CAPACITANCE
14 t pd(off) - Turnoff Propagation Delay Time - ms
1.4 t pd(on) - Turnon Propagation Delay Time - ms
TURNOFF PROPAGATION DELAY TIME, 3.3-V xVCC SWITCH vs LOAD CAPACITANCE
1.2 TJ = 85C
12
1
TJ = 25C
0.8
TJ = 85C 10 TJ = 25C TJ = -40C
0.6
TJ = -40C
8
0.4 dc Load = 1 A 0.2 0.1 1 10 100 CL - Load Capacitance - F 1000
dc Load = 1 A 6 0.1 1 10 100 CL - Load Capacitance - F 1000
Figure 8
TURNON PROPAGATION DELAY TIME, 5-V xVCC SWITCH vs LOAD CAPACITANCE
14 t pd(off) - Turnoff Propagation Delay Time - ms
Figure 9
TURNOFF PROPAGATION DELAY TIME, 5-V xVCC SWITCH vs LOAD CAPACITANCE
1.6 t pd(on) - Turnon Propagation Delay Time - ms 1.4 1.2 1 0.8 0.6 0.4
12
TJ = 85C TJ = 25C
TJ = 25C 10 TJ = 85C
TJ = -40C
TJ = -40C
8
dc Load = 1 A 0.2 0.1 1 10 100 CL - Load Capacitance - F 1000
dc Load = 1 A 6 0.1 1 10 100 CL - Load Capacitance - F 1000
Figure 10
Figure 11
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
TURNON PROPAGATION DELAY TIME, 12-V xVPP SWITCH vs LOAD CAPACITANCE
t pd(off)- Turnoff Propagation Delay Time dc - ms 6 t pd(on) - Turnon Propagation Delay Time - ms 16
TURNOFF PROPAGATION DELAY TIME dc 12-V xVPP SWITCH vs LOAD CAPACITANCE
5 TJ = 85C 4
14
12
TJ = -40C
3 TJ = 25C TJ = -40C 2
TJ = 25C 10 TJ = 85C
1 dc Load = 50 mA 0 0.1 1 10 100 CL - Load Capacitance - F 1000
8 dc Load = 50 mA 6 0.1 1 10 100 CL - Load Capacitance - F 1000
Figure 12
RISE TIME, 3.3-V xVCC SWITCH vs LOAD CAPACITANCE
2 1.8 3 1.6 TJ = 25C 1.4 t f - Fall Time - ms t r - Rise Time - ms 1.2 1 0.8 0.6 0.4 0.5 0.2 dc Load = 1 A 0 0.1 1 10 100 CL - Load Capacitance - F 1000 0 0.1 TJ = -40C TJ = 85C 2.5 3.5
Figure 13
FALL TIME, 3.3-V xVCC SWITCH vs LOAD CAPACITANCE
TJ = 85C 2 TJ = 25C TJ = -40C
1.5
1
dc Load = 1 A 1 10 100 CL - Load Capacitance - F 1000
Figure 14
Figure 15
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
RISE TIME, 5-V xVCC SWITCH vs LOAD CAPACITANCE
1.8 1.6 TJ = 85C 1.4 t r - Rise Time - ms t f - Fall Time - ms 1.2 1 0.8 0.6 0.4 0.2 dc Load = 1 A 0 0.1 1 10 100 CL - Load Capacitance - F 1000 0 0.1 1 10 100 CL - Load Capacitance - F 1000 TJ = 25C 3 2.5 TJ = 85C 2 1.5 1 0.5 dc Load = 1 A TJ = 25C TJ = -40C 4 3.5
FALL TIME, 5-V xVCC SWITCH vs LOAD CAPACITANCE
TJ = -40C
Figure 16
RISE TIME, 12-V xVPP SWITCH vs LOAD CAPACITANCE
5 4.5 4 3.5 t r - Rise Time - ms t f - Fall Time - ms 3 2.5 2 1.5 TJ = 85C 1 .5 dc Load = 50 mA 0 0.1 1 10 100 CL - Load Capacitance - F 1000 0 0.1 TJ = 25C TJ = -40C 20 18 16 14 12 10 8 6 4 2
Figure 17
FALL TIME, 12-V xVPP SWITCH vs LOAD CAPACITANCE
TJ = 85C TJ = 25C
TJ = -40C
dc Load = 50 mA 1 10 100 CL - Load Capacitance - F 1000
Figure 18
Figure 19
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
INPUT CURRENT AT VI(xVCC) = VI(xVPP) = 3.3 V vs JUNCTION TEMPERATURE
100 90 80 I I - Input Current - A I I - Input Current - A 70 60 50 40 30 20 10 0 -50 II(12V) 0 50 TJ - Junction Temperature - C 100 II(3.3V) II(5V)
INPUT CURRENT AT VI(xVCC) = VI(xVPP) = 5 V vs JUNCTION TEMPERATURE
120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -50 II(12V) II(3.3V) 0 50 TJ - Junction Temperature - C II(5V)
100
Figure 20
Figure 21
STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3-V xVCC SWITCH vs JUNCTION TEMPERATURE
0.08 dc Load = 0.75 A 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 -50
120 110 100 90 80 I I - Input Current - A 70 60 50 40 30 20 10 0 -10 -50 0 50 TJ - Junction Temperature - C 100 II(3.3V) II(12V) II(5V)
rDS(on) - Static Drain-Source On-State Resistance -
INPUT CURRENT AT VI(xVCC) = 5 V, VI(xVPP) = 12 V vs JUNCTION TEMPERATURE
0 50 TJ - Junction Temperature - C
100
Figure 22
Figure 23
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 5-V xVCC SWITCH vs JUNCTION TEMPERATURE
0.2 dc Load = 0.75 A 0.16
rDS(on) - Static Drain-Source On-State Resistance -
rDS(on) - Static Drain-Source On-State Resistance -
STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 12-V xVPP SWITCH vs JUNCTION TEMPERATURE
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 0 50 TJ - Junction Temperature - C 100 dc Load = 50 mA
0.12
0.08
0.04
0 -50 50 0 TJ - Junction Temperature - C 100
Figure 24
DC INPUT-TO-OUTPUT VOLTAGE (DROP), 3.3-V xVCC SWITCH vs LOAD CURRENT
0.06 dc Input-to-Output Voltage (Drop) - V dc Input-to-Output Voltage (Drop) - V
Figure 25
DC INPUT-TO-OUTPUT VOLTAGE (DROP), 5-V xVCC SWITCH vs LOAD CURRENT
0.16 0.14 0.12
0.05
0.04 85C 25C 0.03
85C 0.1 25C 0.08 0.06 -40C 0.04 0.02 0
0.02
-40C
0.01
0
0
0.2
0.4 0.6 IL - Load Current - A
0.8
0
0.2 0.4 0.6 IL - Load Current - A
0.8
Figure 26
Figure 27
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
DC INPUT-TO-OUTPUT VOLTAGE (DROP), 12-V xVPP SWITCH vs LOAD CURRENT
0.06 dc Input-to-Output Voltage (Drop) - V
1.9
SHORT-CIRCUIT CURRENT LIMIT, 3.3-V xVCC SWITCH vs JUNCTION TEMPERATURE
0.05
I OS - Short-Circuit Current Limit - A
85C 25C
1.85
0.04 -40C
1.8
0.03
1.75
0.02
1.7
0.01
1.65
0 0 0.01 0.02 0.03 IL - Load Current - A 0.04 0.05
1.6 -50
0 50 TJ - Junction Temperature - C
100
Figure 28
SHORT-CIRCUIT CURRENT LIMIT, 5-V xVCC SWITCH vs JUNCTION TEMPERATURE
Figure 29
SHORT-CIRCUIT CURRENT LIMIT, 12-V xVPP SWITCH vs JUNCTION TEMPERATURE
0.4 I OS - Short-Circuit Current Limit - A
2.36 I OS - Short-Circuit Current Limit - A
2.32
0.38
2.28
0.36
2.24
0.34
2.2
2.16
0.32
2.12 -50 10 40 -20 70 TJ - Junction Temperature - C 100
0.3 -50 0 50 TJ - Junction Temperature - C 100
Figure 30
Figure 31
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning Satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association), comprising members from leading computer, software, PC Card, and semiconductor manufacturers, was established. One key goal was to realize the plug-and-play concept. Cards and hosts from different vendors should be compatible or able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector terminal and line resistance. The two Vpp terminals were originally specified as separate signals, but are commonly tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals.
designing for voltage regulation
The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card will result from resistive losses, VPCB, in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2214A or TPS2216A would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V DS
+ VO(reg)-VPS(reg)-VPCB
Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for output voltage regulation of the 3.3-V output is 300 mV; so, using the same equation by deducting the voltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the TPS2214A or TPS2216A. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the IC, divided by the output-switch resistance. I max O V DS + rDS(on)
The xVCC outputs can deliver 1 A continuously at 5 V and 3.3 V within regulation over the operating temperature range. The xVPP outputs of the IC can deliver 200 mA continuously.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION designing for voltage regulation (continued)
overcurrent and overtemperature protection PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that could lead to power-supply or PCB trace damage. Even systems robust enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection. However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2214A and TPS2216A take a two-pronged approach to overcurrent protection, which is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 250 mA to 500 mA, typically around 375 mA. Second, when an overcurrent condition is detected, these devices assert an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates. This shuts down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. 12-V supply not required Many PC Card switches use the externally supplied 12 V to power gate drive and other chip functions; this requires that power be present at all times. The TPS2214A and TPS2216A offer considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the 5-V or 3.3-V power supplies. Therefore, the external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery lifetime. Additional power savings are realized by the IC during shutdown mode, in which quiescent current drops to a maximum of 1 A. 3.3-V low-voltage mode The TPS2214A and TPS2216A will operate in 3.3-V low-voltage mode when 3.3 V is the only available input voltage (VI(5V) = 0, VI(12V) = 0). This feature allows host and PC Cards to be operated in low-power 3.3-V-only modes such as sleep modes. Note that in this operation mode, the IC will derive its bias current from the 3.3-V input pin and can only provide 3.3 V to the outputs. voltage transitioning requirement PC Cards are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2214A and TPS2216A meet all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The TPS2214A and TPS2216A include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION designing for voltage regulation (continued)
shutdown mode In the shutdown mode, which can be controlled by bit D8 of the input serial DATA word, each of the xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is limited to 1 A or less to conserve battery power. standby mode The TPS2214A and TPS2216A can be put in standby mode by pulling STBY low to conserve power during low-power operation. In this mode, all of the power outputs (xVCC and xVPP) will have a nominal current limit of 50 mA. STBY has an internal 150-k pullup resistor. The output-switch status of the device must be set, allowing the output capacitors to charge, prior to enabling the standby mode. Changing the setting of the output switches with the device in standby mode may cause an overcurrent response to be generated. mode The mode pin programs the switches in either TPS2214A/ TPS2216A or TPS2206 mode. An internal 150-k pulldown resistor is connected to the pin. Floating or pulling the mode pin low sets the switches in TPS2206 mode; pulling the mode pin high sets the switches in TPS2214A/ TPS2216A mode. In TPS2206 mode, xVPP outputs are dependent on xVCC outputs. In TPS2214A/ TPS2216A mode, xVPP is programmed independent of xVCC. Refer to TPS2214A/TPS2216A control-logic tables for more information. power-supply considerations The TPS2214A and TPS2216A have multiple pins for each of its 3.3-V and 5-V power inputs and for the switched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and less power. It is recommended that all input and output power pins be paralleled for optimum operation. Because the two 12-V pins are not internally connected, they must be tied together externally. To increase the noise immunity of the TPS2214A and TPS2216A, the power-supply inputs should be bypassed with a 1-F electrolytic or tantalum capacitor paralleled by a 0.047-F to 0.1-F ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-F (or larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the IC and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken, or allowed to fall, below -0.3 V.
RESET and RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying low impedance paths from xVCC and xVPP terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active-high RESET or active low RESET input will close internal switches S1, S4, S7, and S11 with all other switches left open. The TPS2214A and TPS2216A remain in the low-impedance output state until the signal is deasserted and further data is clocked in and latched. The input serial data can not be latched during reset mode. RESET and RESET are provided for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. The RESET pin has an internal 150-k pulldown resistor and the RESET pin has an internal 150-k pullup resistor. The device will be reset automatically when powered up.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION calculating junction temperature
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 23 through 25, using an initial temperature estimate about 50C above ambient. Then calculate the power dissipation for each switch, using the formula: P D
+ rDS(on) +
P D
I2
Next, sum the power dissipation of all switches and calculate the junction temperature: T J R
qJA
) TA
Where: RJA is the inverse of the derating factor given in the dissipation rating table. Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic inputs and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figures 2 and 3). The 11-bit (D0-D10) serial data word is loaded during the positive edge of the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs. The TPS2216 serial interfaces are compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards. An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the xVCC and xVPP outputs as previously discussed.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION TPS2214A/TPS2216A control logic
TPS2214A/TPS2216A mode (MODE pulled high)
xVPP
AVPP CONTROL SIGNALS D8 (SHDN) 1 1 1 1 1 0 D0 0 0 0 1 1 X D1 0 1 1 0 1 X D9 X 0 1 X X X OUTPUT V_AVPP 0V 3.3 V 5V 12 V Hi-Z Hi-Z BVPP CONTROL SIGNALS D8 (SHDN) 1 1 1 1 1 0 D4 0 0 0 1 1 X D5 0 1 1 0 1 X D10 X 0 1 X X X OUTPUT V_BVPP 0V 3.3 V 5V 12 V Hi-Z Hi-Z
xVCC
AVCC CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D3 0 0 1 1 X D2 0 1 0 1 X OUTPUT V_AVCC 0V 3.3 V 5V 0V Hi-Z BVCC CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D6 0 0 1 1 X D7 0 1 0 1 X OUTPUT V_BVCC 0V 3.3 V 5V 0V Hi-Z
TPS2206 mode (MODE floating or pulled low)
xVPP
AVPP CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D0 0 0 1 1 X D1 0 1 0 1 X OUTPUT V_AVPP 0V V_AVCC 12 V Hi-Z Hi-Z BVPP CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D4 0 0 1 1 X D5 0 1 0 1 X OUTPUT V_BVPP 0V V_BVCC 12 V Hi-Z Hi-Z
xVCC
AVCC CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D3 0 0 1 1 X D2 0 1 0 1 X OUTPUT V_AVCC 0V 3.3 V 5V 0V Hi-Z BVCC CONTROL SIGNALS D8 (SHDN) 1 1 1 1 0 D6 0 0 1 1 X D7 0 1 0 1 X OUTPUT V_BVCC 0V 3.3 V 5V 0V Hi-Z
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION ESD protections (see Figure 32)
All TPS2214A and TPS2216A inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-F capacitors protects the devices from discharges up to 10 kV.
TPS2216A AVCC 0.1 F AVCC AVCC AVPP 0.1 F VCC VCC PC Card Connector A Vpp1 Vpp2
12V
10 F
0.1 F
12V 12V 5V 5V 5V
BVCC 0.1 F BVCC BVCC BVPP 0.1 F
VCC VCC PC Card Connector B Vpp1 Vpp2
5V 33 F 0.1 F
3.3V
33 F
0.1 F
3.3V 3.3V 3.3V DATA CLOCK LATCH MODE STBY RESET RESET OC From PCI or System RST GPI/O Controller DATA CLOCK LATCH
Maximum recommended output capacitance for xVCC is 220 F and for xVPP is 10 F without OC glitch when switches are powered on.
Figure 32. Detailed Interconnections and Capacitor Recommendations
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
APPLICATION INFORMATION 12-V flash memory supply
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 33, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 A when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7- MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127).
TPS2216A 3.3V or 5V ENABLE (see Note A) R1 10 k TPS6734 EN REF SS COMP VCC FB OUT GND AVCC AVCC 8 7 6 5 D1 33 F, 20 V + C1 L1 18 H AVCC AVPP
1 2
C1 33 F 20V
+
3 4
C2 0.01 F
12 V 0.1 F
12V 12V BVCC BVCC
C4 0.001 F
5V 33 F 0.1 F
5V 5V 5V
BVCC BVPP
3.3 V
33 F
0.1 F
3.3V 3.3V 3.3V DATA CLOCK LATCH MODE STBY RESET RESET OC
NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.
Figure 33. TPS2216A with TPS6734 12-V, 120-mA Supply
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
MECHANICAL DATA
DAP (R-PDSO-G**)
38-PIN SHOWN
PowerPADTM PLASTIC SMALL-OUTLINE PACKAGE
0,65 38
0,30 0,19 20
0,13 M
Thermal Pad (see Note D)
6,20 NOM
8,40 7,80 0,15 NOM
Gage Plane 1 A 19 0- 8 0,75 0,50 0,25
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
30
32
38
11,10
11,10
12,60
A MIN
10,90
10,90
12,40
4073257/B 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
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TPS2214A, TPS2216A DUAL-SLOT PC CARD POWER SWITCHES FOR SERIAL PCMCIA CONTROLLERS
SLVS267B - DECEMBER 1999 - REVISED AUGUST 2000
MECHANICAL DATA
DB (R-PDSO-G**)
28 PIN SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE PACKAGE
0,15 NOM 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 1,03 0,63
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 / D 02/98
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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