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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
D D D D D D D D D D D
Fully Integrated VCC and Vpp Switching for Dual-Slot PC CardTM Interface P2CTM 3-Lead Serial Interface Compatible With CardBusTM Controllers 3.3 V Low-Voltage Mode Meets PC Card Standards RESET for System Initialization of PC Cards 12-V Supply Can Be Disabled Except During 12-V Flash Programming Short Circuit and Thermal Protection 30-Pin SSOP (DB) and 32-Pin TSSOP (DAP) Compatible With 3.3-V, 5-V and 12-V PC Cards Low rDS(on) (140-m 5-V VCC Switch; 110-m 3.3-V VCC Switch) Break-Before-Make Switching
DB OR DF PACKAGE (TOP VIEW)
5V 5V DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V
description
The TPS2206 PC Card power-interface switch provides an integrated power-management solution for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit (IC), using the Texas Instruments LinBiCMOSTM process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power by means of the P2C (PCMCIA Peripheral-Control) Texas Instruments nonproprietary serial interface. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. The TPS2206 is backward compatible with the TPS2202 and TPS2202A, except that there is no VDD connection. Bias current is derived from either the 3.3-V input pin or the 5-V input pin. The TPS2206 also eliminates the APWR_GOOD and BPWR_GOOD pins of the TPS2202 and TPS2202A.
5V 5V NC DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC AVCC GND RESET NC 3.3V
DAP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
5V NC NC NC NC NC NC 12V BVPP BVCC BVCC BVCC OC NC 3.3V 3.3V
NC - No internal connection
The TPS2206 features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS and P2C are trademarks of Texas Instruments. PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
description (continued)
The TPS2206 incorporates a reset function, selectable by one of two inputs, to help alleviate system errors. The reset function enables PC Card initialization concurrent with host platform initialization, allowing a system reset. Reset is accomplished by grounding the VCC and Vpp (flash-memory programming voltage) outputs, which discharges residual card voltage. End equipment for the TPS2206 includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras and bar-code scanners.
AVAILABLE OPTIONS TA - 40C to 85C PACKAGED DEVICES PLASTIC SMALL OUTLINE (DB) TPS2206IDBLE PLASTIC SMALL OUTLINE (DF) TPS2206IDFLE TSSOP (DAP) TPS2206IDAPR CHIP FORM (Y) TPS2206Y
The DB package and the DF package are only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS2206IDBLE). The DAP package is only available taped and reeled (indicated by the R suffix on the device type; e.g., TPS2206IDAPR).
typical PC card power-distribution application
Power Supply 12 V 5V 3.3 V Supervisor 3 PCMCIA Controller 12V 5V 3.3V RESET RESET Serial Interface OC TPS2206 AVPP AVCC AVCC AVCC BVPP BVCC BVCC BVCC Vpp1 Vpp2 VCC VCC Vpp1 Vpp2 VCC VCC PC Card A
PC Card B
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
TPS2206Y chip information
This chip, when properly assembled, displays characteristics similar to those of the TPS2206. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS 5V 4 3 1 5V DATA 5 2 23 CLOCK LATCH 6 RESET 12V 7 22 AVPP AVCC 8 144 9 20 21 AVCC AVCC GND 1 2 3 4 5 6 7 8 9 10 11 12 TPS2206Y 23 22 21 20 19 18 17 16 15 14 13 5V 12V BVPP BVCC BVCC BVCC OC 3.3V 3.3V 3.3V RESET
CHIP THICKNESS: 15 TYPICAL 10 11 12 13 15 14 16 17 19 18 BONDING PADS: 4 x 4 MINIMUM TJ max = 150C TOLERANCES ARE 10%. ALL DIMENSIONS ARE IN MILS. 142
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
Terminal Functions
TERMINAL NAME DB, DF 3.3V 5V 12V AVCC AVPP BVCC BVPP CLOCK DATA GND LATCH NC 15, 16, 17 1, 2, 30 7, 24 9, 10, 11 8 20, 21, 22 23 4 3 12 5 13, 19, 25, 26, 27, 28, 29 18 6 14 NO. DAP 16, 17, 18 1, 2, 32 8, 25 10, 11, 12 9 21, 22, 23 24 5 4 13 6 3, 19, 26, 27, 28, 29, 30, 31 20 7 14 O I I I I I I O O O O I I 3.3-V VCC input for card power 5-V VCC input for card power and/or chip power 12-V Vpp input for card power Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance to card Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance Logic-level clock for serial data word Logic-level serial data word Ground Logic-level latch for serial data word No internal connection I/O DESCRIPTION
OC RESET RESET
Logic-level overcurrent. OC reports output that goes low when an overcurrent condition exists Logic-level RESET input active high. Do not connect if terminal 14 is used. Logic-level RESET input active low. Do not connect if terminal 6 is used.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range for card power: VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 14 V Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output current (each card): IO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited IO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE DB DF DAP No backplane Backplane TA 25C POWER RATING 1024 mW 1158 mW 1625 mW DERATING FACTOR ABOVE TA = 25C 8.2 mW/C 9.26 mW/C 13 mW/C TA = 70C POWER RATING 655 mW 741 mW 1040 mW TA = 85C POWER RATING 532 mW 602 mW 845 mW
6044 mW 48.36 mW/C 3869 mW 3143 mW These devices are mounted on an FR4 board with no special thermal considerations. 2-oz backplane with 2-oz traces; 5.2-mm x 11-mm thermal pad with 6-mil solder; 0.18-mm diameter vias in a 3x6 array.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
recommended operating conditions
MIN Input voltage range, VI VI(5V) VI(3.3V) VI(12V) IO(xVCC) at 25C IO(xVPP) at 25C 0 - 40 0 0 0 MAX 5.25 5.25 13.5 1 150 2.5 125 UNIT V V V A mA MHz C
Output current Clock frequency
Operating virtual junction temperature, TJ
electrical characteristics, TA = 25C, VI(5V) = 5 V (unless otherwise noted)
dc characteristics
PARAMETER 5 V to xVCC 3.3 V to xVCC Switch resistances 3.3 V to xVCC 5 V to xVPP 3.3 V to xVPP 12 V to xVPP VO(xVPP) VO(xVCC) Clamp low voltage Clamp low voltage Ipp high impedance state high-impedance Ilkg lk Leakage current ICC high impedance state high-impedance VI(5V) = 5 V II Input current VI(5V) = 0, VI(3.3V) = 3.3 V Shutdown mode IOS Short-circuit output-current limit IO(xVCC) IO(xVPP) Ipp at 10 mA ICC at 10 mA TA = 25C TA = 85C TA = 25C TA = 85C VO(AVCC) = VO(BVCC) = 5 V, VO(AVPP) = VO(BVPP) = 12 V VO(AVCC) = VO(BVCC) = 3.3 V, VO(AVPP) = VO(BVPP) = 0 VO(BVCC) = VO(AVCC) = VO(AVPP) = VO(BVPP) = Hi-Z TJ = 85C, Output powered up into a short to GND 1 120 1 1 VI(5V) = 5 V, VI(5V) = 0, VI(3.3 V) = 3.3 V VI(3.3V) = 3.3 V TEST CONDITIONS TPS2206 MIN TYP 103 69 96 MAX 140 110 180 6 6 1 0.8 0.8 10 50 10 50 117 131 150 A 150 1 2.2 400 A A mA A V V m UNIT
Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
logic section
PARAMETER Logic input current Logic input high level Logic input low level VI(5V)= 5 V, Logic output high level Logic output low level VI(5V)= 0, VI(3.3V) = 3.3 V IO = 1mA IO = 1mA IO = 1mA, VI(5V)-0.4 VI(3.3V)-0.4 0.4 V V 2 0.8 TEST CONDITIONS TPS2206 MIN MAX 1 UNIT A V V
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
switching characteristics
PARAMETER tr tf Output rise time Output fall time VO(xVCC) VO(xVPP) VO(xVCC) VO(xVPP) LATCH to VO( ) O(xVPP) LATCH to VO( CC) (3 3 V) VI(5V) = 5 V O(xVCC) (3.3 V), ( ) tpd d Propagation delay (see Figure 1) LATCH to VO( VCC) (5 V) O(xVCC) LATCH to VO( VCC) (3 3 V) VI(5V) = 0 O(xVCC) (3.3 V), Refer to Parameter Measurement Information Switching Characteristics are with CL = 150 F. ton toff ton toff ton toff ton toff TEST CONDITIONS TPS2206 MIN TYP 1.2 5 10 14 4.4 18 6.5 20 5.7 25 6.6 21 ms ms ms ms ms ms ms ms ms MAX UNIT
electrical characteristics, TA = 25C, VI(5V) = 5 V (unless otherwise noted)
dc characteristics
PARAMETER 5 V to xVCC 3.3 V to xVCC Switch resistances 3.3 V to xVCC 5 V to xVPP 3.3 V to xVPP 12 V to xVPP VO(xVPP) VO(xVCC) Ilkg lk Clamp low voltage Clamp low voltage Leakage current Ipp High-impedance state ICC High-impedance state VI(5V) = 5 V II Input current VI(5V) = 0, VI(3.3V) = 3.3 V Ipp at 10 mA ICC at 10 mA TA = 25C TA = 25C VO(AVCC) = VO(BVCC) = 5 V, VO(AVPP) = VO(BVPP) = 12 V VO(AVCC) = VO(BVCC) = 3.3 V, VO(AVPP) = VO(BVPP) = 0 VI(5V) = 5 V, VI(5V) = 0, VI(3.3 V) = 3.3 V VI(3.3V) = 3.3 V TEST CONDITIONS TPS2206Y MIN TYP 103 69 96 4.74 4.74 0.724 0.275 0.275 1 1 117 A 131 V V A m MAX UNIT
Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
switching characteristics
PARAMETER tr tf Output rise time Output fall time VO(xVCC) VO(xVPP) VO(xVCC) VO(xVPP) LATCH to VO( VPP) O(xVPP) LATCH to VO( CC) (3.3 V), VI(5V) = 5 V O(xVCC) (3 3 V) ( ) tpd d Propagation delay (see Figure 1) LATCH to VO( VCC) (5 V) O(xVCC) LATCH to VO( VCC) (3.3 V), VI(5V) = 0 O(xVCC) (3 3 V) Refer to Parameter Measurement Information Switching Characteristics are with CL = 150 F. ton toff ton toff ton toff ton toff TEST CONDITIONS TPS2206Y MIN TYP 1.2 5 10 14 4.4 18 6.5 20 5.7 25 6.6 21 ms ms ms ms ms ms ms ms ms MAX UNIT
PARAMETER MEASUREMENT INFORMATION
Vpp CL VCC CL
LOAD CIRCUIT VDD LATCH 50% GND toff ton 90% VO(xVPP) VOLTAGE WAVEFORMS 10% VI(12V) VO(xVCC) GND ton LATCH
LOAD CIRCUIT VDD 50% GND toff VI(5V) 10% VOLTAGE WAVEFORMS GND
90%
Figure 1. Test Circuits and Voltage Waveforms
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
Table of Timing Diagrams
FIGURE Serial-Interface Timing xVCC Propagation Delay and Rise Time With 1-F Load, 3.3-V Switch, VI(5V) = 5 V xVCC Propagation Delay and Fall Time With 1-F Load, 3.3-V Switch, VI(5V) = 5 V xVCC Propagation Delay and Rise Time With 150-F Load, 3.3-V Switch, VI(5V) = 5 V xVCC Propagation Delay and Fall Time With 150-F Load, 3.3-V Switch, VI(5V) = 5 V xVCC Propagation Delay and Rise Time With 1-F Load, 3.3-V Switch, VI(5V) = 0 xVCC Propagation Delay and Fall Time With 1-F Load, 3.3-V Switch, VI(5V) = 0 xVCC Propagation Delay and Rise Time With 150-F Load, 3.3-V Switch, VI(5V) = 0 xVCC Propagation Delay and Fall Time With 150-F Load, 3.3-V Switch, VI(5V) = 0 xVCC Propagation Delay and Rise Time With 1-F Load, 5-V Switch xVCC Propagation Delay and Fall Time With 1-F Load, 5-V Switch xVCC Propagation Delay and Rise Time With 150-F Load, 5-V Switch xVCC Propagation Delay and Fall Time With 150-F Load, 5-V Switch xVPP Propagation Delay and Rise Time With 1-F Load, 12-V Switch xVPP Propagation Delay and Fall Time With 1-F Load, 12-V Switch xVPP Propagation Delay and Rise Time With 150-F Load, 12-V Switch xVPP Propagation Delay and Fall Time With 150-F Load, 12-V Switch 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
DATA
D8
D7
D6
D5
D4
D3
D2
D1
D0
LATCH
CLOCK NOTE A: Data is clocked in on the positive leading edge of the clock. The latch should occur before the next positive leading edge of the clock. For definition of D0 to D8, see the control logic table.
Figure 2. Serial-Interface Timing
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
45
t - Time - ms
t - Time - ms
Figure 3. xVCC Propagation Delay and Rise Time With 1-F Load, 3.3-V Switch, (VI(5 V) = 5 V)
Figure 4. xVCC Propagation Delay and Fall Time With 1-F Load, 3.3-V Switch, (VI(5 V) = 5 V)
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
45
t - Time - ms
t - Time - ms
Figure 5. xVCC Propagation Delay and Rise Time With 150-F Load, 3.3-V Switch, VI(5 V) = 5 V
Figure 6. xVCC Propagation Delay and Fall Time With 150-F Load, 3.3-V Switch, VI(5 V) = 5 V
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
45
t - Time - ms
t - Time - ms
Figure 7. xVCC Propagation Delay and Rise Time With 1-F Load, 3.3-V Switch, VI(5 V) = 0
Figure 8. xVCC Propagation Delay and Fall Time With 1-F Load, 3.3-V Switch, VI(5 V) = 0
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
45
t - Time - ms
t - Time - ms
Figure 9. xVCC Propagation Delay and Rise Time With 150-F Load, 3.3-V Switch, VI(5 V) = 0
Figure 10. xVCC Propagation Delay and Fall Time With 150-F Load, 3.3-V Switch, VI(5 V) = 0
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2 t - Time - ms
3
4
0
5
10
15
20
25
30
35
40
45
t - Time - ms
Figure 11. xVCC Propagation Delay and Rise Time With 1-F Load, 5-V Switch
Figure 12. xVCC Propagation Delay and Fall Time With 1-F Load, 5-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div) 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 40 45
t - Time - ms
t - Time - ms
Figure 13. xVCC Propagation Delay and Rise Time With 150-F Load, 5-V Switch
Figure 14. xVCC Propagation Delay and Fall Time With 150-F Load, 5-V Switch
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
0.2
0.4 0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
1
2
3
4
5
6
7
8
9
t - Time - ms
t - Time - ms
Figure 15. xVPP Propagation Delay and Rise Time With 1-F Load, 12-V Switch
Figure 16. xVPP Propagation Delay and Fall Time With 1-F Load, 12-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVPP (5 V/div) xVPP (5 V/div) 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 40 45
t - Time - ms
t - Time - ms
Figure 17. xVPP Propagation Delay and Rise Time With 150-F Load, 12-V Switch
Figure 18. xVPP Propagation Delay and Fall Time With 150-F Load, 12-V Switch
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE IDD IDD rDS(on) rDS(on) rDS(on) rDS(on) VO(xVCC) VO(xVCC) VO(xVCC) VO(xVPP) IOS(xVCC) IOS(xVCC) IOS(xVPP) Supply current, VI(5V) = 5 V Supply current, VI(5V) = 0 Static drain-source on-state resistance, 3.3-V switch, VI(5V) = 5 V Static drain-source on-state resistance, 3.3-V switch, VI(5V) = 0 Static drain-source on-state resistance, 5-V switch Static drain-source on-state resistance, 12-V switch Output voltage, 5-V switch Output voltage, 3.3-V switch, VI(5V) = 5 V Output voltage, 3.3-V switch, VI(5V) = 0 Output voltage, 12-V switch Short-circuit current, 5-V switch Short-circuit current, 3.3-V switch Short-circuit current, 12-V switch vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Junction temperature vs Output current vs Output current vs Output current vs Output current vs Junction temperature vs Junction temperature vs Junction temperature 19 20 21 22 23 24 25 26 27 28 29 30 31
SUPPLY CURRENT vs JUNCTION TEMPERATURE
155 150 I CC - Supply Current - A 145 140 135 130 125 120 115 - 25 0 25 50 75 100 125 VO(AVCC) = VO(BVCC) = 5 V VO(AVPP) = VO(BVPP) = 12 V No load I CC - Supply Current - A 155 150 145 140 135 130 125 120 115 110 - 50 - 25
SUPPLY CURRENT vs JUNCTION TEMPERATURE
VO(AVCC) = VO(BVCC) = 3.3 V VO(AVPP) = VO(BVPP) = 0 V VI(5V) = 0 No load
110 - 50
TJ - Junction Temperature - C
Figure 19
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AA AA
AA AA
0
25
50
75
100
125
TJ - Junction Temperature - C
Figure 20
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
3.3-V SWITCH 3.3-V SWITCH
r DS(on) - Static Drain-Source On-State Resistance - m
220 200 180 160 140 120 100 80 60 - 50 VI(5 V) = 5 V VI(3.3V) = 3.3 V VCC = 3.3 V
r DS(on) - Static Drain-Source On-State Resistance - m
STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
220 200 180 160 140 120 100 80 60 - 50 VI(5 V) = 0 VI(3.3V) = 3.3 V VCC = 3.3 V
- 25
0
25
50
75
100
125
- 25
0
25
50
75
100
125
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 21
5-V SWITCH
Figure 22
12-V SWITCH
r DS(on) - Static Drain-Source On-State Resistance - m
r DS(on) - Static Drain-Source On-State Resistance - m
STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
240 220 200 180 160 140 120 100 80 60 - 50 VI(5 V) = 5 V VCC = 5 V
STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
1100 VI(5 V) = 5 V Vpp = 12 V
1000
900
800
700
600
- 25
0
25
50
75
100
125
500 - 50
- 25
0
25
50
75
100
125
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 23
Figure 24
14
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
5-V SWITCH 3.3-V SWITCH
OUTPUT VOLTAGE vs OUTPUT CURRENT
5 25C 3.27 VO(xVCC) - Output Voltage - V - 40C 85C 4.9 VO(xVCC) - Output Voltage - V 4.95 3.3
OUTPUT VOLTAGE vs OUTPUT CURRENT
- 40C 25C 85C 3.24 125C 3.21
125C
4.85 VI(5V) = 5 V VCC = 5 V 4.8 0 0.2 0.4 0.6 0.8 IO(xVCC) - Output Current - A 1
3.18
VI(5V) = 5 V VI(3.3V) = 3.3 V VCC = 3.3 V 0 0.2 0.4 0.6 0.8 IO(xVCC) - Output Current - A 1
3.15
Figure 25
3.3-V SWITCH
Figure 26
12-V SWITCH
OUTPUT VOLTAGE vs OUTPUT CURRENT
3.3 - 40C 25C 85C 3.2 11.98 VO(xVPP) - Output Voltage - V 12
OUTPUT VOLTAGE vs OUTPUT CURRENT
- 40C 25C
VO(xVCC) - Output Voltage - V
3.25
11.96
85C
125C
11.94
125C
3.15 VI(5 V) = 0 V VCC = 3.3 V 3.1 0 0.2 0.8 0.6 IO(xVCC) - Output Current - A 0.4 1
11.92 VI(5 V) = 5 V VPP = 12 V 11.9 0 0.03 0.06 0.09 IO(xVPP) - Output Current - A 0.12
Figure 27
Figure 28
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
5-V SWITCH 3.3-V SWITCH
SHORT-CIRCUIT CURRENT vs JUNCTION TEMPERATURE
2 I OS(xVCC) - Short-Circuit Current - A I OS(xVCC) - Short-Circuit Current - A VI(5 V) = 5 V VCC = 5 V 1.8 2
SHORT-CIRCUIT CURRENT vs JUNCTION TEMPERATURE
VI(5V) = 0 VI(3.3V) = 3.3 V VCC = 3.3 V
1.8
1.6
1.6
1.4
1.4
1.2
1.2
1
1
0.8 - 50
0 25 75 - 25 50 100 TJ - Junction Temperature - C
125
0.8 - 50
- 25 0 25 50 75 100 TJ - Junction Temperature - C
125
Figure 29
12-V SWITCH
Figure 30
SHORT-CIRCUIT CURRENT vs JUNCTION TEMPERATURE
0.32 I OS(xVPP) - Short-Circuit Current - A VI(5 V) = 5 V VPP = 12 V 0.3
0.28
0.26
0.24
0.22
0.2 - 50
- 25
50 100 0 25 75 TJ - Junction Temperature - C
125
Figure 31
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited on-board memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning Satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA was established, comprised of members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept. Cards and hosts from different vendors should be compatible--able to communicate with one another transparently. PC Card power specification System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals. designing for voltage regulation The current PCMCIA specification for output-voltage regulation (VO(reg)) of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation (VPS(reg)) of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card will result from resistive losses (VPCB) in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop (VDS) for the TPS2206 would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V DS
+ VO reg -VPS reg -VPCB
(1)
Typically, this would leave 100 mV for the allowable voltage drop across the TPS2206. The voltage drop is the output current multiplied by the switch resistance of the TPS2206. Therefore, the maximum output current that can be delivered to the PC Card in regulation is the allowable voltage drop across the TPS2206 divided by the output switch resistance. I max O V DS + rDS on (2)
The xVCC outputs have been designed to deliver 700 mA at 5 V within regulation over the operating temperature range. Current proposals for the PCMCIA specifications are to limit the power dissipated in the PCMCIA slot to 3 W. With an input voltage of 5 V, 700 mA continuous is the maximum current that can be delivered to the PC Card. The TPS2206 is capable of delivering up to 1 A continuously, but during worst-case conditions the output may not be within regulation. This is generally acceptable because the majority of PC Cards require less than 700 mA continuous. Some cards require higher peak currents (disk drives during initial platter spin-up), but it is generally acceptable for small voltage sags to occur during these peak currents. The xVCC outputs have been designed to deliver 1 A continuously at 3.3 V within regulation over the operating temperature range. The PCMCIA specification for output voltage regulation of the 3.3-V output is 300 mV. Using the voltage drop percentages (2%) for power supply regulation and PCB resistive loss (1%), the allowable voltage drop for the 3.3 V switch is 200 mV. The xVPP outputs have been designed to deliver 150 mA continuously at 12 V.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION
overcurrent and over-temperature protection PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems robust enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection. However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2206 takes a two-pronged approach to overcurrent protection. First, instead of fuses, sense FETs monitor each of the power outputs. Excessive current generates an error signal that linearly limits the output current, preventing host damage or failure. Sense FETs, unlike sense resistors or polyfuses, have an added advantage in that they do not add to the series resistance of the switch and thus produce no additional voltage losses. Second, when an overcurrent condition is detected, the TPS2206 asserts a signal at OC that can be monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region. 12-V supply not required Most PC Card switches use the externally supplied 12-V Vpp power for switch-gate drive and other chip functions, which requires that power be present at all times. The TPS2206 offers considerable power savings by using an internal charge pump to generate the required higher voltages from the 5-V or 3.3-V input; therefore, the external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery lifetime. Do not ground the 12-V input if the 12-V input is not used. Additional power savings are realized by the TPS2206 during a software shutdown in which quiescent current drops to a maximum of 1 A.
backward compatibility and 3.3-V low-voltage mode
The TPS2206 is backward compatible with the TPS2202 AND TPS2202A products, with the following considerations. Pin 25 (VDD on TPS2202/TPS2202A) is a no connect because bias current is derived from either the 3.3-V input pin or the 5-V input pin. Also, the TPS2206 does not have the APWR_GOOD or BPWR_GOOD VPP reporting outputs. These are left as no connects. The TPS2206 operates in 3.3-V low-voltage mode when 3.3 volts is the only available input voltage (VI(5V)=0). This allows host and PC Cards to be operated in low-power 3.3-V-only modes such as sleep modes or pager modes. Note that in this operation mode, the TPS2206 derives its bias current from the 3.3-V input pin and only 3.3 V can be delivered to the PC Card. The 3.3-V switch resistance increases, but the added switch resistance should not be critical, because only a small amount of current is delivered in this mode. If 6% (198 mV) is allowed for the 3.3-V switch voltage drop, a 500 m switch could deliver over 350 mA to the PC Card. voltage transitioning requirement PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2206 is designed to meet all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The TPS2206 offers a selectable VCC and Vpp ground state, in accordance with PCMCIA 3.3-V/5-V switching specifications, to fully discharge the card capacitors while switching between VCC voltages.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION
output ground switches Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These devices do not meet the PC Card specification requiring a discharge of VCC within 100 ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. A method commonly shown to alleviate this problem is to add to the switch output an external 100-k resistor in parallel with the PC Card. Considering that this is the only discharge path to ground, a timing analysis shows that the RC time constant delays the required discharge time to more than 2 seconds. The only way to ensure timing compatibility with PC Card standards is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add an external ground FET to each of the output lines with the control logic necessary to select it. In summary, the TPS2206 is a complete single-chip dual-slot PC Card power interface. It meets all currently defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial control interface. The TPS2206 offers functionality, power savings, overcurrent and thermal protection, and fault reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power supply considerations
The TPS2206 has multiple pins for each of its 3.3-V, 5-V, and 12-V power inputs and for the switched VCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. Both 12-V inputs must be connected for proper Vpp switching; it is recommended that all input and output power pins be paralleled for optimum operation. Although the TPS2206 is fairly immune to power input fluctuations and noise, it is generally considered good design practice to bypass power supplies typically with a 1-F electrolytic or tantalum capacitor paralleled by a 0.047-F to 0.1-F ceramic capacitor. It is strongly recommended that the switched VCC and Vpp outputs be bypassed with a 0.1-F or larger capacitor; doing so improves the immunity of the TPS2206 to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2206 and the load. High switching currents can produce large negative-voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similary, no pin should be taken below - 0.3 V.
RESET or RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying a low impedance to the VCC and Vpp terminals. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The RESET or RESET input closes internal switches S1, S4, S7, and S10 with all other switches left open (see TPS2206 control-logic table). The TPS2206 remains in the low-impedance output state until the signal is deasserted and further data is clocked in and latched. RESET or RESET is provided for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. The unused pin is internally pulled up or down and should be left unconnected.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION overcurrent and thermal protection
The TPS2206 uses sense FETs to check for overcurrent conditions in each of the VCC and Vpp outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected, providing for initiation of system diagnostics and/or sending a warning message to the user. During power up, the TPS2206 controls the rise time of the VCC and Vpp outputs and limits the current into a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply. In extreme cases, as much as 10 A to 15 A may flow into the short before the current limiting of the TPS2206 engages. If the VCC or Vpp outputs are driven below ground, the TPS2206 may latch nondestructively in an off state. Cycling power will reestablish normal operation. Overcurrent limiting for the VCC outputs is designed to activate, if powered up, into a short in the range of 1 A to 2.2 A, typically at about 1.6 A. The Vpp outputs limit from 120 mA to 400 mA, typically around 280 mA. The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full shutdown of the supply. Shutdown occurs only during thermal limiting. Thermal limiting prevents destruction of the IC from overheating if the package power-dissipation ratings are exceeded. Thermal limiting disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 21, 22, 23, and 24 using an initial temperature estimate about 50C above ambient. Then calculate the power dissipation for each switch, using the formula: P D
+ rDS(on)
S PD
I2
(3)
Next, sum the power dissipation and calculate the junction temperature: T J
+
R
qJA
) TA,
R
qJA + 108 C
W
(4)
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic input and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading edge of the clock (see Figure 2). The 9-bit (D0 through D8) serial data word is loaded during the positive edge of the latch signal. The latch signal should occur before the next positive leading edge of the clock. The shutdown bit of the data word places all VCC and Vpp outputs in a high-impedance state and reduces chip quiescent current to 1 A to conserve battery power. The TPS2206 serial interface is designed to be compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards. An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the VCC or Vpp outputs as previously discussed.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION
TPS2206 S7 S1 S2 3.3V 3.3V 3.3V S4 CS S5 S6 5V S11 5V S12 5V 12V 12V Internal Current Monitor Supervisor RESET RESET Thermal Controller DATA CLOCK LATCH Serial Interface CS Vpp2 Vpp1 S10 S3 CS See Note A CS Card B VCC VCC S8 S9 VCC VCC Card A Vpp1 Vpp2
See Note A
CPU
OC
GND
NOTE A: MOSFET switches S9 and S12 have a back-gate diode from the source to the drain. Unused switch inputs should never be grounded.
Figure 32. Internal Switching Matrix
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION TPS2206 control logic
AVPP
CONTROL SIGNALS D8 SHDN 1 1 1 1 0 D0 A_VPP_PGM 0 0 1 1 X D1 A_VPP_VCC 0 1 0 1 X S7 CLOSED OPEN OPEN OPEN OPEN INTERNAL SWITCH SETTINGS S8 OPEN CLOSED OPEN OPEN OPEN S9 OPEN OPEN CLOSED OPEN OPEN OUTPUT VAVPP 0V VCC VPP(12 V) Hi-Z Hi-Z
BVPP
CONTROL SIGNALS D8 SHDN 1 1 1 1 0 D4 B_VPP_PGM 0 0 1 1 X D5 B_VPP_VCC 0 1 0 1 X S10 CLOSED OPEN OPEN OPEN OPEN INTERNAL SWITCH SETTINGS S11 OPEN CLOSED OPEN OPEN OPEN S12 OPEN OPEN CLOSED OPEN OPEN OUTPUT VBVPP 0V VCC VPP(12 V) Hi-Z Hi-Z
AVCC
CONTROL SIGNALS D8 SHDN 1 1 1 1 0 D3 A_VCC3 0 0 1 1 X D2 A_VCC5 0 1 0 1 X S1 CLOSED OPEN OPEN CLOSED OPEN INTERNAL SWITCH SETTINGS S2 OPEN CLOSED OPEN OPEN OPEN S3 OPEN OPEN CLOSED OPEN OPEN OUTPUT VAVCC 0V 3.3 V 5V 0V Hi-Z
BVCC
CONTROL SIGNALS D8 SHDN 1 1 1 1 0 Output depends on AVCC Output depends on BVCC D6 B_VCC3 0 0 1 1 X D7 B_VCC5 0 1 0 1 X S4 CLOSED OPEN OPEN CLOSED OPEN INTERNAL SWITCH SETTINGS S5 OPEN CLOSED OPEN OPEN OPEN S6 OPEN OPEN CLOSED OPEN OPEN OUTPUT VBVCC 0V 3.3 V 5V 0V Hi-Z
ESD protection
All TPS2206 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The VCC and Vpp outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-F capacitors protects the devices from discharges up to 10 kV.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION
AVCC AVCC 12 V 0.1 F + 12V 10 F 12V BVCC BVCC BVCC TPS2206 AVPP 5V 0.1 F + 5V 33 F 5V 5V 3.3 V 0.1 F + 3.3V 33 F 3.3V 3.3V BVPP BVPP DATA CLOCK LATCH RESET RESET System Voltage Supervisor or PCI Bus Reset To CPU 0.1 F AVPP 0.1 F 0.1 F AVCC 0.1 F
VCC VCC Vpp1 Vpp2
PC Card Connector A
VCC VCC Vpp1 Vpp2
PC Card Connector B
DATA CLOCK LATCH PCMCIA Controller
OC GND
CS Shutdown Signal From CPU
Figure 33. Detailed Interconnections and Capacitor Recommendations
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
APPLICATION INFORMATION 12-V flash memory supply
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 1, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 A when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM ( pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7- MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127).
3.3 V or 5 V R1 10 k ENABLE (see Note A) C1 33 F, 20 V + 2 REF 3 4 COMP C2 0.01 F C4 0.001 F GND SS U1 OUT 6 5 TPS6734 1 EN VCC 8 L1 18 H D1 C5 + 33 F, 20 V 12V TPS2206 AVPP AVPP 12 V 12V AVCC AVCC AVCC
FB
7
BVCC BVCC BVCC
BVPP 5V 0.1 F 33 F 5V 5V 5V 3.3 V 0.1 F 33 F 3.3V 3.3V 3.3V RESET RESET BVPP DATA CLOCK LATCH
OC GND
To CPU
NOTE A: The enable terminal can be tied to a generall purpose I/O terminal on the PCMCIA controller or tied high.
Figure 34. TPS2206 with TPS6734 12-V, 120-mA Supply
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
MECHANICAL DATA
DB (R-PDSO-G**)
28 PIN SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE PACKAGE
0,15 NOM 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 1,03 0,63
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
30
38
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 / C 10/95
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
MECHANICAL DATA
DF (R-PDSO-G30)
0,80 30 16 0,45 0,25 0,12 M
PLASTIC SMALL-OUTLINE PACKAGE
7,80 7,20
10,80 10,00 0,15 NOM
1 13,10 12,50
15 Gage Plane 0,25 0- 8 0,84 0,76
Seating Plane 2,65 MAX 0,10 MIN 0,10 4040038 / B 02/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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TPS2206 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS138C - MAY 1996 - REVISED JUNE 2000
MECHANICAL DATA
DAP (R-PDSO-G**)
38-PIN SHOWN
PowerPADTM PLASTIC SMALL-OUTLINE PACKAGE
0,65 38
0,30 0,19 20
0,13 M
Thermal Pad (see Note D)
6,20 NOM
8,40 7,80 0,15 NOM
Gage Plane 1 A 19 0- 8 0,75 0,50 0,25
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
28
30
32
38
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40 4073257/A 07/96
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This solderable pad is electrically and thermally connected to the backside of the die and possiblly selected leads. The maximum pad size on the printed circult board should be equal to the package body size (2,0 mm).
PowerPAD is a trademark of Texas Instruments.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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