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UCC5629
Multimode SCSI 14 Line Terminator
FEATURES
* Auto Selection Single Ended (SE) or Low Voltage Differential (LVD) Termination * Meets SCSI-1, SCSI-2, SCSI-3, SPI, Ultra (Fast-20), Ultra2 (SPI-2 LVD) and Ultra3 Standards * 2.7V to 5.25V Operation * Differential Failsafe Bias * Thermal packaging for low junction temperature and better MTBF. * Reversed Polarity Disconnect
DESCRIPTION
The UCC5629 Multimode SCSI Terminator provides a smooth transition into the next generation of the SCSI Parallel Interface (SPI-2). It automatically senses the bus, via DIFFB, and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which type of devices are connected to the bus. The UCC5629 can not be used on a HVD, EIA485, differential SCSI bus. If the UCC5629 detects a HVD SCSI device, it switches to a high impedance state. The Multimode terminator contains all functions required to terminate and auto detect and switch modes for SPI-2 bus architectures. Single Ended and Differential impedances and currents are trimmed for maximum effectiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus type detection circuitry is integrated into the terminator to provide automatic switching of termination between single ended and LVD SCSI and a high impedance for HVD SCSI. The multimode function provides all the performance analog functions necessary to implement SPI-2 termination in a single monolithic device. The UCC5629 is offered in a 48 pin LQFP package for a temperature range of 0C to 70C.
BLOCK DIAGRAM
(NOISE LOAD) 1.3V
HPD
2.15V
-15mA ISOURCE -5mA 50A ISINK 200A
REF 1.3V
35
DIFFSEN
DIFFB
34
0.6V
27
26
LVD
SE
REF 2.7V
110
SOURCE/SINK REGULATOR
124
56mV -+ 56mV
52.5
12
52.5
11
REF 1.25V
ALL SWITCHES MODE UP SE DOWN LVD OPEN DISCNCT
L1-
+-
L1+
10A
SE GND SWITCH
110
124
DISCNCT 36
56mV -+ 56mV
+-
52.5
2
52.5
1
L14-
L14+
TRMPWR
3
SE GND SWITCH
HS/GND
HS/GND
25 GND
4-9
28-33
10
REG 4.7F .
UDG-99156
SLUS444 - NOVEMBER 1999
UCC5629
ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR Package Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C Recommended Operating Conditions . . . . . . . . . 2.7V to 5.25V
CONNECTION DIAGRAMS
(TOP VIEW) FQP Package
HS/GND HS/GND HS/GND REG L1+ L1- HS/GND HS/GND HS/GND TRMPWR L14- L14+
Currents are positive into negative out of the specified terminal. Note: Consult Packaging Section of Databook for thermal limitations and considerations of package.
12 11 L2+ L2- L3+ 13 14 15 16 17 18 19 20 21 22 23 24 25 26
10
9
8
7
6
5
4
3
2
1 48 47 46 45 44 43 42 41 40 39 38 37 L13- L13+ L12- L12+ L11- L11+ L10- L10+ L9- L9+ L8- L8+
RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
L3- L4+ L4- L5+ L5- L6+ L6- L7+ L7-
27
28
29 30
31
32
33 34
35
36
GND SE LVD HS/GND HS/GND HS/GND
DISCNCT DIFFSENS DIFFB HS/GND HS/GND HS/GND
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = 0C to 70C,
TRMPWR = 3.3V. PARAMETER TRMPWR Supply Current Section TRMPWR Supply Current LVD Mode SE Mode Disabled Terminator Regulator Section 1.25V Regulator 1.25V Regulator Source Current 1.25V Regulator Sink Current 1.3V Regulator 1.3V Regulator Source Current 1.3V Regulator Sink Current 2.7V Regulator 2.7V Regulator Source Current 2.7V Regulator Sink Current Differential Termination Section Differential Impedance Common Mode Impedence Differential Bias Voltage Common Mode Bias Output Capacitance Single Ended Measurement to Ground (Note 1) (Note 2) 100 110 100 1.15 1.25 105 150 110 165 125 1.35 3 mV V pF LVD Mode VREG= 0V VREG= 3.3V Diff Sense VREG= 0V VREG= 3.3V SE Mode VREG= 0V VREG= 3.3V 1.15 -375 170 1.2 -15 50 2.5 -375 170 2.7 -700 300 1.25 -700 300 1.3 1.35 -1000 700 1.4 -5 200 3.0 -1000 700 V mA mA V mA A V mA mA 20 1.6 250 25 10 400 mA mA A TEST CONDITIONS MIN TYP MAX UNITS
2
UCC5629
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = 0C to 70C,
TRMPWR = 3.3V. PARAMETER Single Ended Termination Section Impedance TEST CONDITIONS MIN 102.3 TYP 110 MAX UNITS 117.7
Z=
(VLX - 0 . 2V )
ILX
, (Note 3) -21 -18 -24 -25.4 -22.4 400 3 20 0.8 10 0.5 1.9 -10 60 2.0 30 0.7 2.4 10 -6 5 V A V V A mA mA mA mA nA pF
Termination Current Output Leakage Output Capacitance Single Ended GND SE Impedance Disconnect and Diff Buffer Input Section DISCNCT Threshold DISCNCT Input Current Diff Buffer Single Ended to LVD Threshold Diff Buffer LVD to HPD Threshold DIFFB Input Current Status Bits (SE, LVD) Output Section ISOURCE ISINK
Signal Level 0.2V, All Lines Low Signal Level 0.5V Single Ended Measurement to Ground (Note 1) I= 10mA
VLOAD = 2.4V VLOAD = 0.4V
-4 2
Note 1: Guaranteed by design. Not 100% tested in production. Note 2: Z CM =
[
1. 2V
I(VCM + 0. 6V ) - I(VCM - 0. 6V )
]
where VCM=voltage measured with L+ tied to L- and zero current applied
Note 3: VLX= Output voltage for each terminator minus output pin (L1- through L14-) with each pin unloaded. ILX = Output current for each terminator minus output pin (L1- through L14-) with the minus output pin forced to 0.2V.
PIN DESCRIPTIONS
DIFFB: Diff sense filter pin should be connected at a 0.1 F capacitor. DIFFSENS: The SCSI bus Diff Sense line to detect what types of devices are connected to the SCSI bus. DISCNCT: Disconnect pin shuts down the terminator when it is not at the end of the bus. The disconnect pin high enables the terminator. LINEn-: Signal line active line for single ended or negative line in differential applications for the SCSI bus. LINEn+: Ground line for single ended or positive line for differential applications for the SCSI bus. LVD: TTL Compatible status bit indicating that the device has detected the bus in LVD mode. If the terminator is connected it is in LVD mode. REG: Regulator bypass pin, must be connected to a F capacitor. SE: TTL Compatible status bit indicating that the device has detected the bus in single ended mode. If the terminator is connected it is in single ended mode. TRMPWR: VIN 2.7V to 5.25V supply.
3
UCC5629
APPLICATION INFORMATION
The ucc5629 is a Multi-mode active terminator with selectable single ended (SE) and low voltage differential (LVD) SCSI termination integrated into a monolithic component. Mode selection is accomplished with the "diff sense" signal. The diff sense signal is a three level signal, which is driven at each end of the bus by one active terminator. A LVD or multi-mode terminator drives the diff sense line to 1.3 V. If diff sense is at 1.3 V, then bus is in LVD mode. If a single ended SCSI device is plugged into the bus, the diff sense line is shorted to ground. With diff sense shorted to ground, the terminator changes to single ended mode to accommodate the SE device. If a HVD device is plugged in to the bus, the diff sense line is pulled high and the terminator shuts down. The diff sense line is driven and monitored by the terminator through a 50Hz noise filter at the DIFFB input pin. A set of comparators, that allow for ground shifts, determine the bus status as follows. Any diff sense signal below 0.5V is single ended, between 0.7V and 1.9V is LVD and above 2.2V is HVD. In the single ended mode, a multi-mode terminator has a 110 terminating resistor connected to a 2.7V termination voltage regulator. The 2.7V regulator is used on all Unitrode terminators designed for 3.3V systems. This requires the terminator to operate in specification down to 2.7V TRMPWR voltage to allow for the 3.3V supply tolerance, an unidirectional fusing device and cable drop. At each L+ pin, a ground driver drives the pin to ground, while in single ended mode. The ground driver is specially designed so it will not effect the capacitive balance of the bus when the device is in LVD or disconnect mode. The device requirements call for 1.5pF balance on the lines of a differential pair. The terminator capacitance has to be a small part of the capacitance imbalance. Layout is very critical for Ultra2 and Ultra3 systems. Multi-layer boards need to adhere to the 120 impedance standard, including connector and feed-through. This is normally done on the outer layers with 4 mil etch and 4 mil spacing between the runs within a pair, and a minimum of 8 mil spacing to the next pair. This spacing between the pairs reduces potential crosstalk. Beware of feed-throughs and each through hole connection adds a lot of capacitance. Standard power and ground plane spacing yields about 1pF to each plane. Each feedthrough will add about 2.5pF to 3.5pF.Enlarging the clearance holes on both power and ground planes can reduce the capacitance and opening up the power and ground planes under the connector can reduce the capacitance for through hole connector applications. Microstrip technology is normally too low of impedance and should not be used. It is designed for 50 rather than 120 differential systems. Capacitance balance is critical for Ultra2 and Ultra3. The balance capacitance standard is 0.5pF per line with the balance between pairs of 2pF. The components are designed with very tight balance, typically 0.1pF between pins in a pair and 0.3pF between pairs. Layout balance is critical, feed-throughs and etch length must be balanced, preferably no feed-throughs would be used. Capacitance for devices should be measured in the typical application, material and components above and below the circuit board effect the capacitance. Multi-mode terminators need to consider power dissipation; the ucc5629 is offered in a power package with heat sink ground pins. These heat sink/ground pins are directly connected to the die mount paddle under the die and conduct heat from the die to reduce the junction temperature. These pins need to be connected to etch area or a feed-through per pin connecting to the ground plane layer on a multi-layer board. In 3.3V TRMPWR systems, the UCC3912 should be used to replace the fuse and diode. This reduces the voltage drop, allowing for cable drop to the far end terminator. 3.3V battery systems normally have a 10% tolerance. The UCC3912 is 150mV drop under LVD loads, allowing 150mV drop in the cable system. All Unitrode LVD and multi-mode terminators are designed for 3.3V systems, operating down to 2.7V.
4
UCC5629
TYPICAL APPLICATION
L1+ L1- TERMPWR 3 TRMPWR L9+ L9- CONTROL LINES (9) L9+ L9- L1+ L1- TRMPWR 3 TRMPWR
L10+ L10- 4 BITS OF THE HIGH BYTE L13+ L13- 36 DISCNCT DIFFSENSE 35 REG 10 DIFF B 34 20k 0.1F . 20k
L10+ L10-
L13+ L13- DISCNCT 36 35 DIFFSENSE DIFF B 34 REG 10
4.7F .
220k
0.1F .
4.7F 4.7F .
4.7F L1+ L1- DATA LINES (15) L9+ L9- LOW BYTE 8+ PARITY L9+ L9- L1+ L1- DATA LINES (15)
3
TRMPWR L10+ L10- HIGH BYTE 4 BITS PLUS PARITY L14+ L14+ L14- L10+ L10-
TRMPWR
3
36 DISCNCT
L14-
DISCNCT 36
REG 10
DIFF B 34
DIFF B 34
REG 10
4.7F .
4.7F
SCSI CONTROLLER DIFFSENS
UDG-99157
Note: A 220k resistor is added to ground to insure the transceivers will come up in single-ended mode when no terminator is enabled. The controller DIFFSENS ties to the DIFFB pin on the terminators, only one RC network should be on a device.
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
5
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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