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UCC5640
Low Voltage Differential (LVD) SCSI 9 Line Terminator
FEATURES
* First LVD only Active Terminator * Meets SCSI SPI-2 Ultra2 (Fast-40) and Ultra3 / Ultra160 (Fast-80) Standards * 2.7V to 5.25V Operation * Differential Failsafe Bias
DESCRIPTION
The UCC5640 is an active terminator for Low Voltage Differential (LVD) SCSI networks. This LVD only design allows the user to reach peak bus performance while reducing system cost. The device is designed as an active Y-terminator to improve the frequency response of the LVD Bus. Designed with a 1.5pF channel capacitance, the UCC5640 allows for minimal bus loading for a maximum number of peripherals. With the UCC5640, the designer will be able to comply with the Fast-40 SPI-2 and Fast-80 SPI-3 specifications. The UCC5640 also provides a much-needed system migration path for ever improving SCSI system standards. This device is available in the 24 pin TSSOP and 28 pin TSSOP for ease of layout use. The UCC5640 is not designed for use in single ended or high voltage differential systems.
BLOCK DIAGRAM
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATIONS OPEN CIRCUIT ON POWER OFF OR OPEN CIRCUIT IN A DISABLED TERMINATOR MODE 12 1.3V 0.1V HIGH POWER DIFFERENTIAL DIFSENS
TRMPWR 28
2.7V to 5.25V
SOURCE 5-15mA SINK 200A MAXIMUM (NOISE LOAD) REF 1.3V
2.4V > 1.9V DIFFB 20k 11 0.1F HIGH IMPEDANCE RECEIVER EVEN WITH POWER OFF 0.7V > 0.5V SOURCE/SINK REGULATOR LOW FREQUENCY FILTER 50Hz - 60Hz REF 1.25V 124
27
LVD*
SINGLE ENDED 56mV - + 56mV + - 124 56mV - + 56mV + - 52 4 52 3 52 26 52 25 L9+ L9- L1+ L1-
10A
DISCNCT 15
14
GND
1
REG
4.7F
* 28 pin package only
UDG-98181
SLUS314A - JANUARY 2000
UCC5640
CONNECTION DIAGRAMS
TSSOP-24 (Top View) PW24 Package
REG L1+ L1- L2+ L2- L3+ L3- L4+ L4- DIFFB DIFSENS GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 TRMPWR
REG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TRMPWR LVD L9- L9+ L8- L8+ L7- L7+ L6- L6+ L5- L5+ N/C DISCNCT
TSSOP-28 (Top View) PW28 Package
L9-
N/C
L9+
L1+
L8- L8+ L7- L7+ L6- L6+ L5- L5+ DISCNCT
L1- L2+ L2- L3+ L3- L4+ L4- DIFFB DIFSENS N/C GND
ABSOLUTE MAXIMUM RATINGS
TERMPWR Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3.6V Package Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C
Currents are positive into negative out of the specified terminal. consult Packaging Section of Databook for thermal limitations and considerations of package.
RECOMMENDED OPERATING CONDITIONS
TERMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications apply for TA = 0C to 70C,
TRMPWR = 3.3V. TA = TJ. PARAMETER TRMPWR Supply Current Section TRMPWR Supply Current TRMPWR Voltage No Load Disabled Terminator 2.7 25 400 5.25 mA A V TEST CONDITIONS MIN TYP MAX UNITS
2
UCC5640
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications apply for TA = 0C to 70C,
TRMPWR = 3.3V. TA = TJ. PARAMETER Regulator Section 1.25V Regulator 1.25V Regulator Source Current 1.25V Regulator Sink Current 1.3V Regulator 1.3V Regulator Source Current 1.3V Sink Current Differential Termination Section Differential Impedance Common Mode Impedance Differential Bias Voltage Common Mode Bias Output Leakage, Disconnect Output Capacitance ISOURCE ISINK DISCNCT Threshold Input Current Differential Sense SE to LVD Threshold Differential Sense LVD to HPD Threshold At 0V and 3.3V DISCNCT, TRMPWR = 0 to 5.25V, VLINE = 0.2 to 5.25V Single ended measurement to ground (Note 1) VLOAD = 2.4V VLOAD = 0.4V 2 0.8 -30 0.5 1.9 -10 0.7 2.4 -6 5 2 -2.5mA to 4.5mA L+ connected to L- No load, L+ or L- 100 110 100 1.15 1.25 10 105 150 110 165 125 1.35 400 3 -4 mV V nA pF mA mA V A V V DIFSENS connected to DIFFB DIFSENS connected to DIFFB DIFSENS connected to DIFFB DIFFB connected to GND DIFSENS to GND DIFSENS to 3.3V 80 1.2 -15 50 1.15 1.25 -100 100 1.3 1.4 -5 200 1.35 -80 V mA mA V mA A TEST CONDITIONS MIN TYP MAX UNITS
Low Voltage Differential (LVD) Status Bit Section
Disconnect & Differential Sense Input Section
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTION
DIFFB: Differential sense filter pin should be connected to a 0.1F capacitor and 20k resistor to Diff Sense. DIFSENS: The SCSI bus differential sense line to detect what type of devices are connected to the SCSI Bus. DISCNCT: Disconnect pin shuts down the terminator when it is not at the end of the bus. GND: Ground. Ln -: Negative line in differential applications for the SCSI Bus. Ln +: Positive line for differential applications for the SCSI Bus. LVD: (28 pin package only) Indicates that the bus is in LVD mode. REG: Regulator bypass; must be connected to a 4.7 F capacitor to ground. TRMPWR: VIN 2.7V to 5.25V power supply.
3
UCC5640
APPLICATION INFORMATION
UCC5640PW28 Termpower 28 TRMPWR L1+ L1- 27 LVD L9+ L9- 25 26 DIFF SENSE 3 4 CONTROL LINES (9) 22 23 L9+ L9- DISCNCT 13 2 3 UCC5640PW24 L1+ L1- TRMPWR 24 Termpower
15
DISCNCT
REG 1 4.7F
DIFFB 11
12 20k
11 20k
DIFFB 10
REG 1 4.7F
0.1F
0.1F
UCC5640PW28 L1+ L1- 3 4 DATA LINES (9) 4.7F 15 DISCNCT L9+ L9- REG 1 4.7F DIFFB 11 25 26 22 23 2 3
UCC5640PW24 L1+ L1-
28
TRMPWR
TRMPWR 24
L9+ L9- DIFFB 10 DISCNCT 13 REG 1 4.7F
4.7F
UCC5640PW28 L1+ L1- 3 4 DATA LINES (9) 15 DISCNCT L9+ L9- REG S1* 1 4.7F DIFFB 11 25 26 22 23 2 3
UCC5640PW24 L1+ L1-
28
TRMPWR
TRMPWR 24
L9+ L9- DIFFB 10 DISCNCT 13 REG 1 S2* 4.7F
* CLOSE S1 AND S2 TO CONNECT TERMINATORS
UDG-98180
Figure 1. Application diagram.
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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