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UCC1917 UCC2917 UCC3917
Positive Floating Hot Swap Power Manager
FEATURES
* Manages Hot Swap of 15V and Above * Precision Fault Threshold * Programmable Average Power Limiting * Programmable Linear Current Control * Programmable Overcurrent Limit * Programmable Fault Time * Internal Charge Pump to Control External NMOS Device * Fault Output and Catastrophic Fault Indication * Fault Mode Programmable to Latch or Retry * Shutdown Control * Undervoltage Lockout
DESCRIPTION
The UCC3917 family of positive floating hot swap managers provides complete power management, hot swap, and fault handling capability. The voltage limitation of the application is only restricted by the external component voltage limitations. The IC provides its own supply voltage via a charge pump off of VOUT. The onboard 10V shunt regulator protects the IC from excess voltage. The IC also has catastrophic fault indication to alert the user that the ability to shut off the output NMOS has been bypassed. All control and housekeeping functions are integrated and externally programmable. These include the fault current level, maximum output sourcing current, maximum fault time, soft start time, and average NMOS power limiting. The fault level across the current sense amplifier is fixed at 50mV to minimize total drop out. Once 50mV is exceeded across the current sense resistor, the fault timer will start. The maximum allowable sourcing current is programmed with a voltage divider from the VREF/CATFLT pin to generate a fixed voltage on the MAXI pin. The current level at which the output appears as a current source is equal to VMAXI divided by the current sense resistor. If desired, a controlled current startup can be programmed with a capacitor on MAXI. When the output current is below the fault level, the output device is switched on with full gate drive. When the output current exceeds the fault level, but is less than maximum allowable sourcing level programmed by MAXI, the output remains switched on, and the fault timer starts charging CT. Once CT charges to 2.5V, the output device is turned off and attempts either a retry sometime later or waits for the state on the LATCH pin to change if in latch mode. When the output current reaches the maximum sourcing current level, the output device appears as a current source.
VDD 13 VDD 40A UVLO >10V=ENABLE < 6V=DISABLE LATCH 16 1 VDD 40A 5V VDD DISABLE VOUT VOUT OUTPUT LOW 3 OUTPUT PLIM
BLOCK DIAGRAM
SHTDWN 12
VOUT
FLTOUT 11 C1P 8 5V REFERENCE LOGIC SUPPLY
OVER CURRENT COMPARATOR ON-TIME DELAY
50mV + 2 4 SENSE VOUT
C1N
7
C2P
6 + 4V
10 CT
C2N
5
200mV
9 VSS
15 VREF/CATFLT
14
UDG-99055
MAXI
SLUS203A - AUGUST 1999
UCC1917 UCC2917 UCC3917 ABSOLUTE MAXIMUM RATINGS
IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA SHTDWN Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -500A LATCH Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -500A VREF Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -500A PLIM Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA MAXI Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3V Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAM
DIL-16, SOIC-16 (Top View) J or N Package, D Package
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0C to 70C for the UCC3917, -40C to 85 for the UCC2917 and -55C to 125C for the UCC1917, CT = 4.7nF. TA = TJ. All voltages are with respect to VOUT. Current is positive into and negative out of the specified terminal.
PARAMETER VDD Section IDD UVLO Turn On Threshold UVLO Off Voltage VSS Regulator Voltage Fault Timing Section Overcurrent Threshold Overcurrent Input Bias CT Charge Current CT Catastrophic Fault Threshold CT Fault Threshold CT Reset Threshold Output Duty Cycle Output Section Output High Voltage Output Low Voltage IOUT = 0 IOUT = -500A IOUT = 0 IOUT = 500A IOUT = 1mA Linear Current Section Sense Control Votlage Input Bias SHUTDOWN Section Shutdown Threshold Input Current Shutdown Delay SHTDWN = 0V 2.0 24 2.4 40 100 2.8 60 500 V A ns MAXI = 100mV MAXI = 400mV MAXI = 200mV 85 370 100 400 50 115 430 500 mV mV nA 6 5 8 7 0 0.1 0.5 10 9 0.05 0.5 0.9 V V V V V Fault Condition VCT = 1V -78 3.4 2.25 0.32 1.7 2.5 0.5 2.7 TA = 25C Over Operating Temperature 47.5 46 50 50 50 -50 53 54 500 -28 4.5 2.75 0.62 3.7 mV mV nA A V V V % From VOUT (Note 1) 3.0 7.9 5.5 -6 5 8.8 6.5 -5 11 9.7 7.5 -4 mA V V V TEST CONDITIONS MIN TYP MAX UNITS
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UCC1917 UCC2917 UCC3917 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0C to 70C for the UCC3917, -40C to 85 for the UCC2917 and -55C to 125C for the UCC1917, CT = 4.7nF. TA = TJ. All voltages are with respect to VOUT. Current is positive into and negative out of the specified terminal.
PARAMETER LATCH Section Latch Threshold Input Current Fault Out Section Fault Output High Fault Output Low Power Limiting Section VSENSE Regulator Voltage Duty Cycle Control VREF/CATFLT Section VREF Regulator Voltage Fault Output Low Output Sink Current Overload Comparator Threshold IVREF/CATFLT = 5mA VCT = 5V, VVREF/CATFLT = 5V Relative to MAXI 15 110 4.5 5 0.22 40 200 5.5 0.50 70 290 V V mA mV IPLIMIT = 64A IPLIMIT = 64A IPLIMIT = 1mA 4.5 0.6 0.045 5 1.2 0.1 5.5 1.7 0.2 V % % 6 8 0.01 10 0.05 V V LATCH = 0V 1.7 24 2 40 2.3 60 V A TEST CONDITIONS MIN TYP MAX UNITS
Note 1: Set by user with RSS.
PIN DESCRIPTIONS
C1N: Negative side of the upper charge pump capacitor. C1P: Positive side of the upper charge pump capacitor. C2N: Negative side of the lower charge pump capacitor. C2P: Positive side of lower charge pump capacitor. CT: A capacitor is connected to this pin to set the fault time. The fault time must be more than the time to charge the external load capacitance (see Application Information). FLTOUT: This pin provides fault output indication. Interface to this pin is usually performed through level shift transistors. Under a non-fault condition, FLTOUT will pull to a high state. When a fault is detected by the fault timer or the under voltage lockout, this pin will drive to a low state, indicating the output NMOS is in the off state. LATCH: Pulling this pin low causes a fault to latch until this pin is brought high or a power on reset is attempted. However, pulling this pin high before the reset time is reached will not clear the fault until the reset time is reached. Keeping LATCH high will result in normal operation of the fault timer. Users should note there will be an RC delay dependent upon the external capacitor at this pin. MAXI: This pin programs the maximum allowable sourcing current. Since VREF/CATFLT is a regulated voltage, a voltage divider can be derived to generate the program level for MAXI. The current level at which the output appears as a current source is equal to the volt3 age on MAXI divided by the current sense resistor. If desired, a controlled current start up can be programmed with a capacitor on MAXI (to VOUT), and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an RC network. OUTPUT: Gate drive to the NMOS pass element. PLIM: This feature ensures that the average external NMOS power dissipation is controlled. A resistor is connected from this pin to the drain of the external NMOS pass element. When the voltage across the NMOS exceeds 5V, current will flow into PLIM which adds to the fault timer charge current, reducing the duty cycle from the 3% level. SENSE: Input voltage from the current sense resistor. When there is greater than 50mV across this pin with respect to VOUT, a fault is sensed, and CT starts to charge. SHTDWN: This pin provides shutdown control. Interface to this pin is usually performed through level shift transistors. When shutdown is driven low, the output disables the NMOS pass device. VDD: Power to the I.C. Is supplied by an external current limiting resistor on initial power-up or if the load is shorted. As the load voltages rises (VOUT), a small amount of power is drawn from VOUT by an internal charge pump. The charge pump's input voltage is regulated by an on-chip 5V zener. Power to VDD is supplied
UCC1917 UCC2917 UCC3917 PIN DESCRIPTIONS (cont.)
by the charge pump under normal operation (i.e., external FET is on). VOUT: Ground reference for the IC. VREF/CATFLT: This pin primarily provides an output reference for the programming of MAXI. Secondarily, it provides catastrophic fault indication. In a catastrophic fault, when the IC unsuccessfully attempts to shutdown the NMOS pass device, this pin pulls to a low state when CT charges about the catastrophic fault thershold. A possible application for this pin is to trigger the shutdown of an auxilliaty FET in series with the main FET for redundency. VSS: Negative reference out of the chip. Normally current fed via a resistor to ground.
UDG-96265-1
Figure 1. Fault timing circuitry for the UCC3917, including power limit and overload.
APPLICATION INFORMATION
Fault Timing Fig. 1 shows the detailed circuitry for the fault timing function of the UCC3917. For simplicity, we first consider a typical fault mode where the overload comparator and the current source I3 do not come into play. A typical fault occurs once the voltage across the current sense resistor, RS, exceeds 50mV. This causes the over current comparator to trip and the timing capacitor to charge with current source I1 plus the current from the power limiting amplifier, or PLIM amplifier. The PLIM amplifier is designed to only source current into the CT pin once the voltage across the output FET exceeds 5V. The current IPL is related to the voltage across the FET with the following expression: IPL = (VIN - VOUT) - 5V R PL 4 Note that under normal fault conditions where the output current is just above the fault level, VOUT VIN, IPL = 0, and the CT charging current is just I1. During a fault, CT will charge at a rate determined by the internal charging current and the external timing capacitor, CT. Once CT charges to 2.5V, the fault comparator switches and sets the fault latch. Setting the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with current source I2 until 0.5V is reached. Once the voltage at CT reaches 0.5V, the fault latch resets (assuming LATCH is high, otherwise the fault latch will not reset until the LATCH pin is brought high or a power-on reset occurs) which re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the overcurrent comparator will close the charging switch causing the cycle to repeat. Under a constant fault the duty cycle is given by:
UCC1917 UCC2917 UCC3917 APPLICATION INFORMATION (cont.)
Duty Cycle = 15A . I2 I PL + I 1 I PL + 50A PFET AVG = (VIN - VOUT) * IMAX * Duty Cycle = (VIN - VOUT) * IMAX * 1.5 A IPL + 50A
where IPL is 0A under normal operations (see Fig. 2). However, under large transients, average power dissipation can be limited using the PLIM pin. A proof follows, average dissipation in the pass element is given by: VIN - VOUT R PL
Where (VIN - VOUT) >> 5V, IPL
IOUT IMAX IFAULT IO(nom) OUTPUT CURRENT
t
VCT 2.5V
CT VOLTAGE (WITH RESPECT TO VOUT) 0.5V 0V VOUT VIN OUTPUT VOLTAGE (WITH RESPECT TO GND) 0V
t
t t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
UDG-99147
t0: Safe condition - output current is nominal, output voltage is at the positive rail, VIN. t1: Fault control reached - output current rises above the programmed fault value, CT begins to charge with 50A. t2: Maximum current reached - output current reaches the programmed maximum level and becomes a constant current with value IMAX. t3: Fault occurs - CT has charged to 2.5V, fault output goes low, the FET turns off allowing no output current to flow, VOUT discharges to ground. t4: Retry - CT has discharged to 0.5V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT rises to VIN.
t5 = t3: Illustrates 3% duty cycle. t6 = t4: t7: Output short circuit - if VOUT is short circuited to ground, CT charges at a higher rate depending upon the values for VIN and RPL. t8: Fault occurs - output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted. t9 = t4: Output short circuit released, still in fault mode. t10 = t0: Fault released, safe condition - return to normal operation of the circuit breaker. Note that t6 - t5 36 * (t5 - t4).
Figure 2. Nominal timing diagram.
5
UCC1917 UCC2917 UCC3917 APPLICATION INFORMATION (cont.)
and where IPL >> 50A, the duty cycle can be approximated as: 1.5 A * R PL . V IN - VOUT Therefore the average power dissipation in the MOSFET can be approximated by: PFET AVG = (VIN - VOUT) * IMAX * = IMAX * 1.5 A * R PL Notice that since (VIN - VOUT) cancels, average power dissipation is limited in the NMOS pass element (see Fig. 3). Also, a value for RPL can be roughly determined from this approximation. R PL = PFET AVG IMAX * I.5 A 1.5 A * R PL VIN - VOUT
IOVERLOAD = I MAX + 200mV / R S
Once the overcurrent comparator trips the UCC3917 will enter programmed fault mode (hiccup or latched). It should be noted that on subsequent retries during Hiccup mode or if a short should occur when the UCC3917 is actively limiting the current, the output current will not exceed IMAX. In the event that the external FET does not respond during a fault the UCC3917 will set the VREF/CATFLT pin low to indicate a catastrophic failure. Selecting the Minimum Timing Capacitance To ensure that the IC will startup correctly the designer must ensure that the fault time programmed by CT exceeds the startup time of the load. The startup time (TSTART) is a function of several components; load resistance and load capacitance, soft start components R1, R2 and CSS, the power limit current contribution determined by RPL, and CIN. For a parallel capacitor-constant current load: (1)
RPL = INF
T START =
C LOAD * VIN I MAX - I LOAD
IMAX = 4A
For a parallel R-C load :
RPL = 10M
T START = V IN - R LOAD * C LOAD * ln 1 - I MAX * R LOAD
(2)
PAVG
RPL = 5M
RPL = 2M RPL = 1M RPL = 200k RPL =500k
If the power limit function is not be used then CT(min) can be easily found:
CT (min) =
ICH * T START dVCT
(3)
Figure 3. Plot of average power vs. FET voltage for increasing values of RPL.
Overload Comparator The overload comparator provides protection against a shorted load during normal operation when the external N-channel FET is fully enhanced. Once the FET is fully enhanced the linear current amplifier essentially saturates and the system is in effect operating open loop. Once the FET is fully enhanced the linear current amplifier requires a finite amount of time to respond to a shorted output possibly destroying the external FET. The overload comparator is provided to quickly shutdown the external MOSFET in the case of a shorted output (if the FET is fully enhanced). During an output short CT is charged by I3 at ~ 1mA. The current threshold for the overload comparator is a function of IMAX and a fixed offset and is defined as:
where dVCT is the hysteresis on the fault detection circuitry. During operation in the latched fault mode configuration dVCT = 2.5V. When the UCC3917 is configured for the hiccup or retry mode of fault operation dVCT=2.0V. If the power limit function is used the CT charging current becomes a function of ICH + IPL. And CT(min) is found from:
6
UCC1917 UCC2917 UCC3917 APPLICATION INFORMATION (cont.)
CT (min)
-t VIN - I MAX * R LOAD * 1 - e R LOAD *C LOAD ICH + R PL dt * dVCT
(4)
Please note that the actual on-time if hiccup mode threshold current 60A. For example, in the minimum when operating into a short is defined by:
T (on) =
CT * dVCT seconds ICH + I PL ( pk )
(8)
where dVCT ~2.0V and
I PL ( pk ) =
VIN A R PL
(9)
Selecting Other External Components Other external components are necessary for correct operation of the IC. Referring to the application diagram at the back of the data sheet, resistors RSENSE, RSS, R1, R2 and R3 are required and follow certain equations with a brief description following where applicable: R SENSE = R SS = GND) 50mV (Sense Resistor) IFAULT
IPL(PK) IPL VIN-V PL VOUT
VIN - 5V (Connected between VSS and 5mA
TSTART
Figure 4. Relationship between IPL, VOUT and TSTART.
Since IPL is a function of the output voltage, VOUT, which varies over time, equation 4 must be integrated to solve for CT(min). However equation 4 can be easily approximated if the output voltage slews. If the output voltage slews linearly then the CT charge current contribution from the power limit circuitry is shown to be at a peak when VOUT = 0V and at 0A when VOUT=VIN-VPL, where VPL is the power limit voltage threshold. IPL is shown in Fig. 4 below. Where IPL is defined as:
VIN - 10 (Used in series with a diode to 5mA connect VIN to VDD) R3 = (R1 + R2) > 20k (Current limit out of VREF) Lastly, the external capacitors used for the charge pump are required and need to equal 0.1F, i.e. CIN = CH = C1 = C2 = 0.1F. LEVEL Shift Circuitry (Optional) The UCC3917 can be used in many systems without logic command or diagnostic feedback. If a system requires control from low-voltage logic or feedback to low-voltage logic, then level shifting circuits are required. The level shift circuits in Fig. 5A and Fig. 5B show ways to interface to LATCH and SHTDWN and the level shift circuits in Fig. 6 show ways of interfacing from FLTOUT to low-voltage logic. In Fig. 5A, resistor R limits the level shift current. Select R so that the current in the level shift circuit never exceeds the absolute maximum current in the logic command inputs, 500A. For example, if the maximum supply voltage for the system is 75V, select
I PL
(VIN
- VOUT - V PL )
(5)
R PL
The average IPL current for the interval (0, TSTART) from Fig. 4 is defined as:
I PL ( AVG )
(VIN
- V PL )
2
(6)
2 * R PL * VIN
Equation 4 can now be simplified to:
R>
(7)
CT (min)
ICH + I PL ( AVG ) dVCT
75V = 150 k . 500 A
* T START
R must also be chosen so that the minimum current in the level shift circuit exceeds the worst case logic 7
UCC1917 UCC2917 UCC3917 APPLICATION INFORMATION (cont.)
R TO UCC3917 C SHTDWN OR LATCH (A) TO UCC3917 SHTDWN OR LATCH R C
supply voltage for the system is 25V, choose
R>
25V = 416 k . 60 A
VOUT
The capacitor C shown on the output of this circuit is useful to filter the level shift output and prevent false triggering from noise. The minimum recommended capacitor value is 100pF. Larger capacitors will result in better noise immunity and longer delay to logic command. The circuit in Fig. 5B accomplished the same function as the circuit in Fig. 5A, using different components. In this circuit, select resistor R so that the transistor draws enough current to exceed the 60A logic threshold but doesn't exceed the 500A maximum logic input current. For example, if the input circuit is 5V logic, then
VOUT
(B)
UDG-99148
Figure 5. Potential level shift circuitry to interface to LATCH and SHTDWN on the
VDD 13 R1 LOCAL VDD 11 LOCAL FAULT R2 FLTOUT LOCAL FAULT LOCAL VDD R1
VDD 13
VDD 13
11 FLTOUT
LOCAL VDD R1 LOCAL FAULT
11
FLTOUT
R2
R2
(A)
(B)
(C)
Figure 6. Potential level shift circuitry to interface to FLTOUT on the UCC3917.
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UCC1917 UCC2917 UCC3917 APPLICATION INFORMATION (cont.)
VIN D1 LATCH 16 UVLO >10V=ENABLE < 6V=DISABLE 1 VDD 40A SHTDWN 12 VOUT VOUT FLTOUT 11 C1P C1 C1N 7 8 10V SHUNT REGULATOR LOGIC SUPPLY 5V REFERENCE OUTPUT LOW 5V VDD DISABLE 3 OUTPUT PLIM RPL R3
VDD 13 VDD 40A
VOUT
CIN
OVER CURRENT COMPARATOR ON-TIME DELAY
50mV + 2
SENSE VOUT RSENSE CT
C2P C2 C2N
4 CT
6 4V 10 200mV +
5
9 VSS VREF/CATFLT
15
14 MAXI R1 R2 CSS CH
RSS
OUTPUT
UDG-99056
Figure 7. Positive floating hot swap power manager UCC1917, UCC2917 and UCC3917.
SAFETY RECOMMENDATIONS
Although the UCC3917 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3917 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the power device. The UCC3917 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device.
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460
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Copyright (c) 2000, Texas Instruments Incorporated

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