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| HIP2060 April 1998 60V, 10A Half Bridge Power MOSFET Array Description The HIP2060 is a power half-bridge MOSFET array that consists of two matched N-Channel enhancement-mode MOS transistors. The advanced Intersil PASIC2 process technology used in this product utilizes efficient geometries that provides outstanding device performance and ruggedness. The HIP2060 is designed to integrate two power devices in one chip thus providing board layout area and heat sink savings for applications such as Motor Controls, Uninterruptable Power Supplies, Switch Mode Power Supplies, Voice Coil Motors, and Class D Power Amplifier. Features * Two 10A Power MOS N-Channel Transistors * Output Voltage to 60V * rDS(ON) . . . . . 0.135 Max Per Transistor at VGS = 15V * rDS(ON) . . . . . . 0.15 Max Per Transistor at VGS = 10V * Pulsed Current . . . . . . . . . . . . . . . . 25A Each Transistor * Avalanche Energy . . . . . . . . . . 100mJ Each Transistor * Grounded Tab Eliminates Heat Sink Isolation Ordering Information PART NUMBER HIP2060AS1 HIP2060AS2 HIP2060AS3 TEMP. RANGE (oC) -40 to 125 -40 to 125 -40 to 125 PACKAGE 5 Ld SIP 5 Ld Gullwing SIP 5 Ld SIP PKG. NO. Z5.067C Z5.067A Z5.067B GATE1 1 SOURCE1 = DRAIN2 4 GATE2 2 Z2 Z1 D1 Symbol DRAIN1 5 NOTE: When ordering use the entire part number. SOURCE2 3, TAB Packages JEDEC TS-001AA (ALTERNATE VERSION) HIP2060 AS1 54 3 2 JEDEC MO-169 HIP2060 AS2 1 1 GATE1 2 GATE2 3 SOURCE2 4 SOURCE1-DRAIN2 5 DRAIN1 (TAB) Z5.067B (SIP) HIP2060 AS3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 3983.5 1 HIP2060 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified HIP2060 60 60 20 10 25 10 100 46 0.37 60 -40 to 125 -40 to 150 300 60 UNITS V V V A A A mJ W W/oC oC/W oC oC oC Continuous Drain-Source Voltage Over Operating Junction and Case Temperature Range. . . . . . VDS Drain-Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Source-Drain Diode Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ISD Pulsed Drain Current, each Output, all Outputs on (Notes 1, 2) . . . . . . . . . . . . . . . . . . . . . . . IDM Continuous Drain Current, each Output, all Outputs on (Note 2) . . . . . . . . . . . . . . . . . . . . . . . .IDS Single Pulse Avalanche Energy (Note 3) Refer to UIS Curve . . . . . . . . . . . . . . . . . . . . . . . . . EAS Continuous Power Dissipation at TC = 25oC (Infinite Heatsink). . . . . . . . . . . . . . . . . . . . . . . . . PD Continuous Power Dissipation, Derate above TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA Operating Case Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC Junction and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (For Soldering, 10s)(Lead Tips Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Continuous Drain1-Source2 Voltage Over Operating Junction Temperature Range. . . . . . VD1S2 NOTES: 1. Pulse width limited by maximum junction temperature. 2. Drain current limited by package construction. 3. VDD = 25V, Start TJ = 25oC, L = 1.5mH, RGS = 50, R = 0. See Figures 2, 12, and 13. V Electrical Specifications PARAMETER Drain-Source Breakdown Voltage TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS TEST CONDITIONS ID = 100A, VGS = 0V TC = -40oC to 125oC TC = 25oC MIN 60 TYP MAX UNITS V 1.5 70 2.3 105 2.7 - V V V A A A V V nA Gate Threshold Voltage Drain1-Source2 Breakdown Voltage (Across D1) Zero Gate Voltage Drain Current VGS(TH) BVD1S2 IDSS ID1S2 VGS = VDS, ID = 250A ID1S2 = 1A, VG1S1, VG2S2 = 0V VDS = 60V VGS = 0V TC = 25oC TC = 25oC - - - 1 Drain1-Source2 Current (Through D1) VD1S2 = 60V TC = 25oC VG1S1 = 0V, VG2S2 = 0V TC = 125oC ID = 10A, VGS = 15V ID = 10A, VGS = 10V - 0.3 1 0.9 1.1 - 1 1.25 1.5 100 Drain-Source On-State Voltage (Note 4) Forward Gate Current, Drain Short Circuited to Source Reverse Gate Current, Drain Short Circuited to Source Drain-Source On Resistance (Note 4) VDS(ON) IGSSF IGSSR rDS(ON) VDS = 0V, VGS = 20V VDS = 0V, VGS = -20V VGS = 15V, ID = 10A VGS = 15V, ID = 10A VGS = 10V, ID = 10A VGS = 10V, ID = 10A TC = 25oC TC = 125oC TC = 25oC TC = 125oC - - -100 nA S - 0.09 0.15 0.11 0.19 4.5 0.135 0.21 0.15 0.25 - Forward Transconductance (Note 4) gfs VDS = 15V, ID = 5A 2 HIP2060 Electrical Specifications PARAMETER Turn-On Delay Time (Note 5) Rise Time (Note 5) Turn-Off Delay Time (Note 5) Fall Time (Note 5) Total Gate Charge (Note 5) Gate-Source Charge (Note 5) Gate-Drain Charge (Note 5) Short-Circuit Input Capacitance, Common Source Short-Circuit Output Capacitance, Common Source for Upper FET Short Circuit Output Capacitance Common Source for Lower FET Short-Circuit Reverse Transfer Capacitance, Common Source Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient TC = 25oC, Unless Otherwise Specified (Continued) SYMBOL td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS(U) COSS(L) CRSS RJC RJA VDS = 25V, VGS = 0V, f = 1MHz VDS = 50V, VGS = 10V, ID = 10A See Figures 16 and 17 TEST CONDITIONS VDD = 30V, RL = 3 ID = 10A, VGS = 10V, RG = 50 See Figure 14 MIN TYP 4 5 12 6 10.5 1.4 4.9 230 MAX 12.0 2.0 5.5 UNITS ns ns ns ns nC nC nC pF - 150 - pF - 225 - pF - 40 - pF oC/W oC/W - - 2.7 60 Source-Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SOURCE-TO-DRAIN DIODE SPECIFICATIONS (Across Z1 and Z2) Forward Voltage (Note 4) Reverse Recovery Time (Across Z1) Reverse Recovery Time (Across Z2) VSD trr(S1-D1) trr(S2-D2) ISD = 10A, VGS = 0V ISD = 10A, dISD/dt = 100A/s ISD = 10A, dISD/dt = 100A/s 1.05 50 75 1.25 V ns ns SOURCE2-TO-DRAIN1 DIODE SPECIFICATIONS D (Across D1) Forward Voltage (Note 4) Reverse Recovery Time DEVICE MATCHING Drain-Source On Resistance Match NOTES: 4. Pulse test: Pulse Width 300s, Duty Cycle 2%. 5. Independent of operating temperature. rDS(ON)M VGS = 10V, ID = 10A, TC = 25oC 90 % VSD trr ISD = 10A, VGS = 0V ISD = 10A, dISD/dt = 100A/s 8.5 200 9.5 V ns 3 HIP2060 Typical Performance Curves 50 50 TC = 25oC 10s 10 5 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 5 10 50 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 10ms DC 100 1 0.001 0.01 0.1 tAV, TIME IN AVALANCHE (ms) 1 100s IAS, AVALANCHE CURRENT (A) STARTING TC = 25oC ID, DRAIN CURRENT (A) 10 STARTING TC = 125oC 5 1 0.5 FIGURE 1. SAFE-OPERATING AREA CURVE FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING 20 VGS = 15V VGS = 12V ID, DRAIN CURRENT (A) VGS = 8V ID, DRAIN CURRENT (A) 15 VGS = 10V 20 -40oC 25oC VDS = 15V 15 150oC 10 10 5 5 0 0 PULSE DURATION = 300s, TC = 25oC 2 4 6 8 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 0 0 2 4 6 8 10 VGS, GATE-TO-SOURCE VOLTAGE (V) FIGURE 3. SATURATION CHARACTERISTICS FIGURE 4. TRANSFER CHARACTERISTICS 2.5 PULSE DURATION = 300s, VGS = 10V, ID = 10A 2.0 NORMALIZED rDS(ON) NORMALIZED BVDSS 1.2 ID = 100A 1.1 1.5 1.0 1.0 0.9 0.5 0 -75 -25 25 75 125 175 0.8 -75 -25 25 75 125 175 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 5. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE FIGURE 6. NORMALIZED BVDSS vs JUNCTION TEMPERATURE 4 HIP2060 Typical Performance Curves 2.0 VGS, GATE-SOURCE VOLTAGE (V) VGS = VDS, ID = 250A NORMALIZED VGS(TH) 1.5 (Continued) 16 VDS = 50V VDS = 30V VDS = 20V 12 ID = 10A, TC = 25oC 8 1.0 0.5 4 0 -75 0 -25 25 75 125 175 0 5 TJ, JUNCTION TEMPERATURE (oC) 10 Q, GATE CHARGE (nC) 15 20 FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION TEMPERATURE 1000 FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE VGS = 0V, f = 1MHz, TC = 25oC 12 10 ID, DRAIN CURRENT (A) 8 6 VGS = 15V VGS = 10V 800 C, CAPACITANCE (pF) CRSS 600 COSS(U) COSS(L) 400 CISS 4 200 2 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 0 0 5 10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 9. CAPACITANCE vs VOLTAGE FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZJC, NORMALIZED THERMAL RESPONSE 10 TC = 25oC 1 D = 1.0 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE NOTES: 1. DUTY FACTOR, D = t1/t2 2. PEAK TJ = PDM x (ZJC) +TC 101 0.01 10-5 10-3 10-1 10-4 10-2 10o t1, RECTANGULAR PULSE DURATION (s) FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 5 HIP2060 Test Circuits and Waveforms VDS L RG VGS + VDD ID tP ID 0.01 0 BVDSS VGS tP tAV 10V 0 IAS DUT 0V VDS 0 FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS tON VDD td(ON) tr RL VDS VGS DUT 0V RGS VGS 10% 50% PULSE WIDTH 10% VDS 90% tOFF td(OFF) tf 90% 10% 90% 50% FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR +VDS QG SAME TYPE AS DUT 10V + 15V BATTERY 0.2F - 25k 0.1F QGS QGD DUT 0 IGS VG CHARGE FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. BASIC GATE CHARGE WAVEFORM 6 HIP2060 +36V 30H 1F RL = 8 0.47F 3.9 0.22F BHB +12V HEN DIS VSS OUT IN+ INHDEL LDEL AHB BHO BHS BLO BLS VDD VCC ALS ALO AHS AHO 10 HIP4080A ILIM 100k 100k 0.22F UF 4002 0.22F 0.001F 100 0.1 10 +12V 10 HIP2060 HIP2060 1F 10 30H UF 4002 0.22F 0.22F + FEEDBACK AUDIO INPUT + 250kHz FIGURE 18. 70W SWITCHING AUDIO AMPLIFIER APPLICATION CIRCUIT Device Model Netlist for HIP2060 Half Bridge Power MOSFET Array .SUBCKT HIP2060 1 2 3 4 5 X1 6 1 7 3 HIP2060_1 LS1 5 6 7.5n X2 7 2 8 3 HIP2060_1 LS2 7 4 7.5n LS3 8 3 7.5n .ENDS .SUBCKT HIP2060_1 3 2 11 9 MOS1 4 2 1 1 NMOS1 JFET 10 1 4 J1 D1 5 6 D1 DBODY 1 10 D2 DBREAK 10 7 D3 DSUB 9 3 D4 VBREAK 7 1 DC 90 C21 21 850P C23 2 10 50P C24 24 1350P RDRAIN 3 10 1.5e-03 RSOURCE 1 11 17.5e-03 FDSCHRG 4 2 VMEAS 1.0 E41 5 11 4 1 1.0 VPINCH 6 8 DC 10.0 VMEAS 8 11 DC 0.0 .MODEL NMOS1 NMOS LEVEL=3 (VTO=2.75 TOX=5e-08 KP=3.150e-03 PHI=0.65 GAMMA=2.55 + VMAX=6.42e+07 NSUB=4.33e+16 THETA=0.60973 ETA=0.0015 KAPPA=1.275 L=1u W=5950u) .MODEL J1 NJF (VTO=-15.0 BETA=10.736 LAMBDA=1.15e-02 P1.MODEL D1 D (IS=1.0e-15 N=0.03 RS=1.0) .MODEL D2 D (IS=3.0e-13 RS=2.5e-03 TT=20N CJO=350e-12) .MODEL D3 D (IS=1.0e-13 N=1.0 RS=2.0) .MODEL D4 D (IS=1.0e-13 RS=2.0e-03 CJO=197e-12) .ENDS NOTE: For further discussion of the PSPICE PowerFET Macromodel consult "Spicing-up SPICE II Software for Power MOSFET Modeling", Intersil Application Note AN8610. 7 HIP2060 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 8 |
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