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TMS320VC5409A
Fixed-PointDigital Signal Processor
Data Manual
Literature Number: SPRS140F November 2000 - Revised January 2005
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
Revision History
This data sheet revision history highlights the technical changes made to the SPRS140E device-specific data sheet to make it an SPRS140F revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following corrections.
SECTION Table 2-2 Section 5.2 Section 5.3 Table 5-1 Figure 5-29 Section 6.1 Global Added Note 6. Changed IOH from -2 to -8 mA and IOL from 2 to 8 mA. Changed Note 2 to read "These output current limits are used for the test conditions on VOL and VOH, except where noted otherwise." Changed test conditions for VOH from "DVDD = 2.7 V to 3.0 V, IOH = MAX" to "DVDD = 2.7 V to 3.0 V, IOH = - 2 mA". In Note 1, changed symbol for Infinity from "" to "". Updated figure to reduce confusion caused by unnecessary information. Moved the Package Thermal Resistance Characteristics to this section. A font substitution caused some symbols to display incorrectly in the E revisions of this document. This error has been corrected and validated in the F revision including the Electrical Specifications. ADDITIONS/CHANGES/DELETIONS
2
Revision History
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
Contents
Revision History ........................................................................................................................... 2 1 TMS320VC5409A Features .................................................................................................... 9 2 Introduction ....................................................................................................................... 10
2.1 2.2 Description .................................................................................................................. Pin Assignments............................................................................................................ 2.2.1 Terminal Assignments for the GGU Package ............................................................... 2.2.2 Pin Assignments for the PGE Package ...................................................................... Signal Descriptions......................................................................................................... Memory ...................................................................................................................... 3.1.1 Data Memory .................................................................................................... 3.1.2 Program Memory ............................................................................................... 3.1.3 Extended Program Memory ................................................................................... On-Chip ROM With Bootloader........................................................................................... On-Chip RAM ............................................................................................................... On-Chip Memory Security................................................................................................. Memory Map ................................................................................................................ 3.5.1 Relocatable Interrupt Vector Table ........................................................................... On-Chip Peripherals ....................................................................................................... 3.6.1 Software-Programmable Wait-State Generator ............................................................. 3.6.2 Programmable Bank-Switching ............................................................................... 3.6.3 Bus Holders ..................................................................................................... Parallel I/O Ports ........................................................................................................... 3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) ......................................................... 3.7.2 HPI Nonmultiplexed Mode ..................................................................................... Multichannel Buffered Serial Ports (McBSPs) .......................................................................... Hardware Timer ............................................................................................................ Clock Generator ............................................................................................................ Enhanced External Parallel Interface (XIO2) ........................................................................... DMA Controller ............................................................................................................. 3.12.1 Features .......................................................................................................... 3.12.2 DMA External Access .......................................................................................... 3.12.3 DMPREC Issue ................................................................................................. 3.12.4 DMA Memory Map .............................................................................................. 3.12.5 DMA Priority Level .............................................................................................. 3.12.6 DMA Source/Destination Address Modification ............................................................. 3.12.7 DMA in Autoinitialization Mode ............................................................................... 3.12.8 DMA Transfer Counting ........................................................................................ 3.12.9 DMA Transfer in Doubleword Mode .......................................................................... 3.12.10 DMA Channel Index Registers .............................................................................. 3.12.11 DMA Interrupts ................................................................................................ 3.12.12 DMA Controller Synchronization Events ................................................................... General-Purpose I/O Pins................................................................................................. 3.13.1 McBSP Pins as General-Purpose I/O ........................................................................ 3.13.2 HPI Data Pins as General-Purpose I/O ...................................................................... Device ID Register ......................................................................................................... Memory-Mapped Registers ............................................................................................... McBSP Control Registers and Subaddresses.......................................................................... DMA Subbank Addressed Registers ....................................................................................
Contents
2.3
10 10 10 12 13 17 17 18 18 18 19 19 20 20 22 22 23 25 25 25 26 27 30 30 32 35 35 35 36 38 39 39 40 40 41 41 41 42 43 43 43 44 45 47 48
3
3
Functional Overview ........................................................................................................... 17
3.1
3.2 3.3 3.4 3.5 3.6
3.7
3.8 3.9 3.10 3.11 3.12
3.13
3.14 3.15 3.16 3.17
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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3.18
Interrupts
....................................................................................................................
50
4
Support ............................................................................................................................. 51
4.1 4.2 Documentation Support ................................................................................................... 51 Device and Development-Support Tool Nomenclature................................................................ 52 Absolute Maximum Ratings ............................................................................................... Recommended Operating Conditions ................................................................................... Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) ........................................................................................ Test Load Circuit ........................................................................................................... Timing Parameter Symbology ............................................................................................ Internal Oscillator With External Crystal................................................................................. Clock Options ............................................................................................................... 5.7.1 Divide-By-Two and Divide-By-Four Clock Options.......................................................... 5.7.2 Multiply-By-N Clock Option (PLL Enabled)................................................................... Memory and Parallel I/O Interface Timing .............................................................................. 5.8.1 Memory Read ................................................................................................... 5.8.2 Memory Write ................................................................................................... 5.8.3 I/O Read ......................................................................................................... 5.8.4 I/O Write ......................................................................................................... Ready Timing for Externally Generated Wait States .................................................................. HOLD and HOLDA Timings............................................................................................... Reset, BIO, Interrupt, and MP/MC Timings............................................................................. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings .......................................... External Flag (XF) and TOUT Timings .................................................................................. Multichannel Buffered Serial Port (McBSP) Timing.................................................................... 5.14.1 McBSP Transmit and Receive Timings ...................................................................... 5.14.2 McBSP General-Purpose I/O Timing ......................................................................... 5.14.3 McBSP as SPI Master or Slave Timing ...................................................................... Host-Port Interface Timing ................................................................................................ 5.15.1 HPI8 Mode ....................................................................................................... 5.15.2 HPI16 Mode ..................................................................................................... 53 53 54 55 55 55 57 57 59 60 60 63 65 67 68 71 73 75 76 77 77 80 81 85 85 89
5
Electrical Specifications ...................................................................................................... 53
5.1 5.2 5.3 5.4 5.5 5.6 5.7
5.8
5.9 5.10 5.11 5.12 5.13 5.14
5.15
6
Mechanical Data ................................................................................................................. 93
6.1 Package Thermal Resistance Characteristics.......................................................................... 93
4
Contents
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
List of Figures
2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11
.............................................................................. 144-Pin PGE Low-Profile Quad Flatpack (Top View) ........................................................................ TMS320VC5409A Functional Block Diagram ................................................................................. Program and Data Memory Map ................................................................................................ Extended Program Memory Map ............................................................................................... Processor Mode Status Register (PMST) ..................................................................................... Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] ......................... Software Wait-State Control Register (SWCR) [MMR Address 002Bh] ...................................................
144-Ball GGU MicroStar BGATM (Bottom View)
10 12 17 20 20 21 22 23
Bank-Switching Control Register (BSCR) [MMR Address 0029h].......................................................... 24
................................................................................. HPI Memory Map ................................................................................................................. Pin Control Register (PCR) ...................................................................................................... Multichannel Control Register 2x (MCR2x) .................................................................................... Multichannel Control Register 1x (MCR1x) .................................................................................... Receive Channel Enable Registers Bit Layout for Partitions A to H .......................................................
Host-Port Interface -- Nonmultiplexed Mode
26 27 28 29 29 29
Transmit Channel Enable Registers Bit Layout for Partitions A to H....................................................... 30 Nonconsecutive Memory Read and I/O Read Bus Sequence .............................................................. 32 Consecutive Memory Read Bus Sequence (n = 3 reads) ................................................................... 33 Memory Write and I/O Write Bus Sequence................................................................................... 34 DMA Transfer Mode Control Register (DMMCRn)
...........................................................................
35
DMA Channel Enable Control Register (DMCECTL)......................................................................... 37 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) .......................................... 38 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)...................................... 39 DMPREC Register ................................................................................................................ 40 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] ................................................ 43 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] ................................................. 43 Device ID Register (CSIDR) [MMR Address 003Eh] ......................................................................... 44 IFR and IMR ....................................................................................................................... 50 Tester Pin Electronics ............................................................................................................ 55 Internal Divide-By-Two Clock Option With External Crystal ................................................................. 56 External Divide-By-Two Clock Timing .......................................................................................... 58 Multiply-By-One Clock Timing ................................................................................................... 60 Nonconsecutive Mode Memory Reads......................................................................................... 61 Consecutive Mode Memory Reads ............................................................................................. 62 Memory Write (MSTRB = 0) ..................................................................................................... 64 Parallel I/O Port Read (IOSTRB = 0) ........................................................................................... 66 Parallel I/O Port Write (IOSTRB = 0) ........................................................................................... 67 Memory Read With Externally Generated Wait States....................................................................... 69 Memory Write With Externally Generated Wait States....................................................................... 69
List of Figures
5
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34
I/O Read With Externally Generated Wait States............................................................................. 70 I/O Write With Externally Generated Wait States ............................................................................. 70 HOLD and HOLDA Timings (HM = 1) .......................................................................................... 72 Reset and BIO Timings........................................................................................................... 73 Interrupt Timing.................................................................................................................... 74 MP/MC Timing..................................................................................................................... 74 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings ................................................. 75 External Flag (XF) Timing........................................................................................................ 76 TOUT Timing ...................................................................................................................... 76 McBSP Receive Timings......................................................................................................... 78 McBSP Transmit Timings ........................................................................................................ 79 McBSP General-Purpose I/O Timings.......................................................................................... 80 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ..................................................... 81 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ..................................................... 82 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ..................................................... 83 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ..................................................... 84 HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low) ................................................ 87
....................................................................... HPI-8 Mode, HINT Timing ....................................................................................................... GPIOx(A) Timings .................................................................................................................. HPI-16 Mode, Nonmultiplexed Read Timings ................................................................................. HPI-16 Mode, Nonmultiplexed Write Timings ................................................................................. HPI-16 Mode, HRDY Relative to CLKOUT ....................................................................................
HPI-8 Mode Timing, Using HCS to Control Accesses
88 88 88 91 91 92
6
List of Figures
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
List of Tables
2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16
........................................................................................................... Signal Descriptions ............................................................................................................... Standard On-Chip ROM Layout ................................................................................................ Processor Mode Status Register (PMST) Field Descriptions ............................................................... Software Wait-State Register (SWWSR) Field Descriptions ................................................................ Software Wait-State Control Register (SWCR) Field Descriptions ......................................................... Bank-Switching Control Register (BSCR) Field Descriptions ............................................................... Bus Holder Control Bits .......................................................................................................... Sample Rate Generator Clock Source Selection ............................................................................. Receive Channel Enable Registers for Partitions A to H Field Descriptions .............................................. Transmit Channel Enable Registers for Partitions A to H Field Descriptions ............................................. Clock Mode Settings at Reset ...................................................................................................
Terminal Assignments
11 13 19 21 22 23 24 25 28 30 30 31
DMD Section of the DMMCRn Register........................................................................................ 36 DMA Channel Enable Control Register (DMCECTL) Field Description.................................................... 37
................................................................................................ DMA Interrupts ....................................................................................................................
DMA Reload Register Selection
40 41
DMA Synchronization Events.................................................................................................... 42 DMA Channel Interrupt Selection ............................................................................................... 42 CPU Memory-Mapped Registers................................................................................................ 45 Peripheral Memory-Mapped Registers for Each DSP Subsystem
.........................................................
45
McBSP Control Registers and Subaddresses................................................................................. 47 DMA Subbank Addressed Registers ........................................................................................... 48 Interrupt Locations and Priorities................................................................................................ 50 Input Clock Frequency Characteristics ......................................................................................... 56 Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options ........................................ 57
........................................................ Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics ....................................................
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
57 57
Multiply-By-N Clock Option Timing Requirements............................................................................ 59 Multiply-By-N Clock Option Switching Characteristics ....................................................................... 59 Memory Read Timing Requirements ........................................................................................... 60 Memory Read Switching Characteristics....................................................................................... 60 Memory Write Switching Characteristics....................................................................................... 63 I/O Read Timing Requirements ................................................................................................. 65 I/O Read Switching Characteristics............................................................................................. 65 I/O Write Switching Characteristics ............................................................................................. 67
....................................................... Ready Switching Characteristics for Externally Generated Wait States ................................................... HOLD and HOLDA Timing Requirements .....................................................................................
Ready Timing Requirements for Externally Generated Wait States
68 68 71
HOLD and HOLDA Switching Characteristics................................................................................. 71
List of Tables
7
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 6-1
................................................................... Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics ............................ External Flag (XF) and TOUT Switching Characteristics .................................................................... McBSP Transmit and Receive Timing Requirements ........................................................................ McBSP Transmit and Receive Switching Characteristics ................................................................... McBSP General-Purpose I/O Timing Requirements ......................................................................... McBSP General-Purpose I/O Switching Characteristics .....................................................................
Reset, BIO, Interrupt, and MP/MC Timing Requirements
73 75 76 77 78 80 80
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)................................... 81 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) .............................. 81 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)................................... 82 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) .............................. 82 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)................................... 83 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) .............................. 83 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)................................... 84 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) .............................. 84 HPI8 Mode Timing Requirements............................................................................................... 85 HPI8 Mode Switching Characteristics .......................................................................................... 86 HPI16 Mode Timing Requirements ............................................................................................. 89 HPI16 Mode Switching Characteristics......................................................................................... 90 Thermal Resistance Characteristics ............................................................................................ 93
8
List of Tables
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
1
* *
TMS320VC5409A Features
Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- x 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Extended Addressing Mode for 8M x 16-Bit Maximum Addressable External Program Space 32K x 16-Bit On-Chip RAM Composed of: - Four Blocks of 8K x 16-Bit On-Chip Dual-Access Program/Data RAM 16K x 16-Bit On-Chip ROM Configured for Program Memory Enhanced External Parallel Interface (XIO2) Single-Instruction-Repeat and Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better Program and Data Management Instructions With a 32-Bit Long Word Operand Instructions With Two- or Three-Operand Reads Arithmetic Instructions With Parallel Store and Parallel Load Conditional Store Instructions
* *
*
* *
*
*
* *
* * * * * * * * *
*
* * * * * * * *
Fast Return From Interrupt On-Chip Peripherals - Software-Programmable Wait-State Generator and Programmable Bank-Switching - On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source (1) - One 16-Bit Timer - Six-Channel Direct Memory Access (DMA) Controller - Three Multichannel Buffered Serial Ports (McBSPs) - 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16) Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic (2) 144-Pin Ball Grid Array (BGA) (GGU Suffix) 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS) 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS) 3.3-V I/O Supply Voltage (160 and 120 MIPS) 1.6-V Core Supply Voltage (160 MIPS) 1.5-V Core Supply Voltage (120 MIPS)
(1) (2)
The on-chip oscillator is not available on all 5409A devices. For applicable devices, see the TMS320VC5409A Digital Signal Processor Silicon Errata (literature number SPRZ186). IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C54x, MicroStar BGA, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000-2005, Texas Instruments Incorporated
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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2
Introduction
This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
NOTE This data manual is designed to be used in conjunction with the TMS320C54xTM DSP Functional Overview (literature number SPRU307).
2.1
Description
The TMS320VC5409A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5409A also includes the control mechanisms to manage interrupts, repeated operations, and function calls.
2.2
Pin Assignments
Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package.
2.2.1
Terminal Assignments for the GGU Package
13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N
Figure 2-1. 144-Ball GGU MicroStar BGATM (Bottom View)
10
Introduction
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
Table 2-1 lists each signal name and BGA ball number for the 144-pin TMS320VC5409AGGU package. Table 2-2 lists each terminal name, terminal function, and operating modes for the TMS320VC5409A.
Table 2-1. Terminal Assignments
SIGNAL QUADRANT 1 CVSS A22 CVSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS DVSS CVSS CVDD HCS HR/W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP/MC DVDD CVSS BDR1 BFSR1 BGA BALL # A1 B1 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 F4 F3 F2 F1 G2 G1 G3 G4 H1 H2 H3 H4 J1 J2 J3 J4 K1 K2 K3 L1 L2 L3 M1 M2 SIGNAL QUADRANT 2 BFSX1 BDX1 DVDD DVSS CLKMD1 CLKMD2 CLKMD3 HPI16 HD2 TOUT EMU0 EMU1/OFF TDO TDI TRST TCK TMS CVSS CVDD HPIENA DVSS CLKOUT HD3 X1 X2/CLKIN RS D0 D1 D2 D3 D4 D5 A16 DVSS A17 A18 BGA BALL # N13 M13 L12 L13 K10 K11 K12 K13 J10 J11 J12 J13 H10 H11 H12 H13 G12 G13 G11 G10 F13 F12 F11 F10 E13 E12 E11 E10 D13 D12 D11 C13 C12 C11 B13 B12 SIGNAL QUADRANT 3 CVSS BCLKR1 HCNTL0 DVSS BCLKR0 BCLKR2 BFSR0 BFSR2 BDR0 HCNTL1 BDR2 BCLKX0 BCLKX2 CVSS HINT CVDD BFSX0 BFSX2 HRDY DVDD DVSS HD0 BDX0 BDX2 IACK HBIL NMI INT0 INT1 INT2 INT3 CVDD HD1 CVSS BCLKX1 DVSS BGA BALL # N1 N2 M3 N3 K4 L4 M4 N4 K5 L5 M5 N5 K6 L6 M6 N6 M7 N7 L7 K7 N8 M8 L8 K8 N9 M9 L9 K9 N10 M10 L10 N11 M11 L11 N12 M12 SIGNAL QUADRANT 4 A19 A20 CVSS DVDD D6 D7 D8 D9 D10 D11 D12 HD4 D13 D14 D15 HD5 CVDD CVSS HDS1 DVSS HDS2 DVDD A0 A1 A2 A3 HD6 A4 A5 A6 A7 A8 A9 CVDD A21 DVSS BGA BALL # A13 A12 B11 A11 D10 C10 B10 A10 D9 C9 B9 A9 D8 C8 B8 A8 B7 A7 C7 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 A3 B3 C3 A2 B2
Introduction
11
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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2.2.2
Pin Assignments for the PGE Package
The TMS320VC5409APGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-2.
DVSS A21 CV DD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DV DD HDS2 DV SS HDS1 CVSS CVDD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DV DD CV SS A20 A19 CVSS A22 CVSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS DVSS CVSS CVDD HCS HR/W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP/MC DVDD CVSS BDR1 BFSR1
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
A.
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. DVSS is the ground for the I/O pins while CVSS is the ground for the core CPU. The DVSS and CVSS pins can be connected to a common ground plane in a system.
12
Introduction
CV SS BCLKR1 HCNTL0 DVSS BCLKR0 BCLKR2 BFSR0 BFSR2 BDR0 HCNTL1 BDR2 BCLKX0 BCLKX2 CVSS HINT CVDD BFSX0 BFSX2 HRDY DVDD DVSS HD0 BDX0 BDX2 IACK HBIL NMI INT0 INT1 INT2 INT3 CV DD HD1 CVSS BCLKX1 DVSS
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
A18 A17 DVSS A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT DVSS HPIENA CVDD CVSS TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT HD2 HPI16 CLKMD3 CLKMD2 CLKMD1 DVSS DVDD BDX1 BFSX1
Figure 2-2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
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TMS320VC5409A Fixed-PointDigital Signal Processor
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2.3
Signal Descriptions
Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section Section 2.2 for exact pin locations based on package type.
Table 2-2. Signal Descriptions
TERMINAL NAME A22 (MSB) A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) I/O (1) DATA SIGNALS DESCRIPTION
I/O/Z (2) (3)
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16 to A22, address external program space memory. A22-A0 is placed in the high-impedance state in the hold mode. A22-A0 also goes into the high-impedance state when OFF is low. A15-A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port interface (HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs. The address bus has a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into a high-impedance state.
I/O/Z (2) (3)
Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 is multiplexed to transfer data between the core CPU and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs. The data bus has a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
INITIALIZATION, INTERRUPT AND RESET OPERATIONS IACK INT0 INT1 INT2 INT3 NMI RS
(2) (2) (2) (2) (2)
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state when OFF is low. External user interrupt inputs. INT0-INT3 are maskable and are prioritized by the interrupt mask register (IMR) and the interrupt mode bit. INT0 -INT3 can be polled and reset by way of the interrupt flag register (IFR). Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits.
I
I I
(2)
(1) (2) (3)
I = Input, O = Output, Z = High-impedance, S = Supply These pins have Schmitt trigger inputs. This pin has an internal bus holder controlled by way of the BSCR register. Introduction 13
TMS320VC5409A Fixed-PointDigital Signal Processor
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Table 2-2. Signal Descriptions (continued)
TERMINAL NAME I/O (1) DESCRIPTION Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode that is selected at reset. MULTIPROCESSING SIGNALS BIO
(2)
MP/MC
I
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC instruction, and all other instructions sample BIO during the read phase of the pipeline. External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset. MEMORY CONTROL SIGNALS Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating to a particular external space. Active period corresponds to valid address information. DS, PS, and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance state when OFF is low. Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states. Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low. I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the 5409A, these lines go into the high-impedance state. Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing them to be available to the external circuitry. HOLDA also goes into the high-impedance state when OFF is low. Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low. Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus and goes into the high-impedance state when OFF is low. OSCILLATOR/TIMER SIGNALS Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the machine-cycle rate divided by 4. Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is revision depended, see Section Section 3.10 for additional information.) Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision depended, see Section Section 3.10 for additional information.) Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
XF
O/Z
DS PS IS MSTRB
O/Z
O/Z
READY
I
R/W
O/Z
IOSTRB HOLD HOLDA
O/Z I O/Z
MSC
O/Z
IAQ
O/Z
CLKOUT CLKMD1 (2) CLKMD2 (2) CLKMD3 (2) X2/CLKIN (2) X1 TOUT
O/Z
I
I O O/Z
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TMS320VC5409A Fixed-PointDigital Signal Processor
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Table 2-2. Signal Descriptions (continued)
TERMINAL NAME I/O (1) DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1), AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS BCLKR0 (2) BCLKR1 (2) BCLKR2 (2) BDR0 BDR1 BDR2 BFSR0 BFSR1 BFSR2 BCLKX0 (2) BCLKX1 (2) BCLKX2 (2) BDX0 BDX1 BDX2 BFSX0 BFSX1 BFSX2 I/O/Z Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver. Serial data receive input Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured as an input following reset. The BFSR pulse initiates the receive data process over BDR. Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes low. Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when OFF is low. Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes into the high-impedance state when OFF is low. HOST-PORT INTERFACE SIGNALS Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the 5409A, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs. Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1. Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1. Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input has an internal pullup resistor that is only enabled when HPIENA = 0. Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0. Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0. Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only enabled when HPIENA = 0. Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host when the HPI is ready for the next transfer. Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1. HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled when RS goes high and is ignored until RS goes low again. HPI16 mode selection. This pin must be tied to DVDD to enable HPI16 mode. The pin has an internal pulldown resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled. SUPPLY PINS CVSS CVDD DVSS (4) (5) S S S Ground. Dedicated ground for the core CPU +VDD. Dedicated power supply for the core CPU Ground. Dedicated ground for I/O pins
I
I/O/Z
I/O/Z
O/Z
I/O/Z
HD0-HD7 (2) (3)
I/O/Z
HCNTL0 (4) HCNTL1 (4) HBIL (4) HCS
(2) (4) (2) (4) (2) (4)
I I I I I I O/Z O/Z
HDS1 HDS2 HAS
(2) (4)
HR/W (4) HRDY HINT
HPIENA (5)
I
HPI16 (5)
I
This pin has an internal pullup resistor. This pin has an internal pulldown resistor. Introduction 15
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Table 2-2. Signal Descriptions (continued)
TERMINAL NAME DVDD I/O (1) S +VDD. Dedicated power supply for I/O pins TEST PINS TCK (2) (4) I IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: * TRST= low, * EMU0 = high * EMU1/OFF = low DESCRIPTION
TDI (4) TDO TMS (4) TRST
(5)
I O/Z I I
EMU0 (6)
I/O/Z
EMU1/OFF (6)
I/O/Z
(6)
This pin must be pulled up with a 4.7-k resistor to ensure the device is operable in functional mode or emulation mode.
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3
Functional Overview
The following functional overview is based on the block diagram in Figure 3-1.
P, C, D, E Buses and Control Signals Cbus Dbus Cbus Ebus Dbus Pbus Pbus Ebus Pbus 16K Program ROM GPIO TI BUS RHEA Bridge RHEA Bus McBSP1 McBSP2 McBSP3 TIMER APLL Clocks JTAG
54X cLEAD
32K RAM Dual Access Program/Data
MBus
XIO
Enhanced XIO RHEA bus
HPI
HPI
xDMA logic
RHEAbus
Figure 3-1. TMS320VC5409A Functional Block Diagram
3.1
Memory
The 5409A device provides both on-chip ROM and RAM memories to aid in system performance and integration.
3.1.1
Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: * Higher performance because no wait states are required * Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU) * Lower cost than external memory * Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space.
MBus
Functional Overview
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3.1.2
Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: * Higher performance because no wait states are required * Lower cost than external memory * Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space.
3.1.3
Extended Program Memory
The 5409A uses a paged extended memory scheme in program space to allow access of up to 8192K of program memory. In order to implement this scheme, the 5409A includes several features which are also present on C548/549/5410: * Twenty-three address lines, instead of sixteen * An extra memory-mapped register, the XPC * Six extra instructions for addressing extended program space Program memory in the 5409A is organized into 128 pages that are each 64K in length. The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.2
On-Chip ROM With Bootloader
The 5409A features a 16K-word x 16-bit on-chip maskable ROM that can only be mapped into program memory space. Customers can arrange to have the ROM of the 5409A programmed with contents unique to any particular application. A bootloader is available in the standard 5409A on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard 5409A devices provide different ways to download the code to accommodate various system requirements: * Parallel from 8-bit or 16-bit-wide EPROM * Parallel from I/O space, 8-bit or 16-bit mode * Serial boot from serial ports, 8-bit or 16-bit mode * Host-port interface boot * Serial EEPROM mode * Warm boot
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The standard on-chip ROM layout is shown in Table 3-1. Table 3-1. Standard On-Chip ROM Layout
ADDRESS RANGE C000h-D4FFh D500h-F7FFh F800h-FBFFh FC00h-FCFFh FD00h-FDFFh FE00h-FEFFh FF00h-FF7Fh FF80h-FFFFh Reserved Bootloader -Law expansion table A-Law expansion table Sine look-up table Reserved (1) Interrupt vector table DESCRIPTION ROM tables for the GSM EFR speech codec
(1)
In the 5409A ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h-FF7Fh in program space.
3.3
On-Chip RAM
The 5409A device contains 32K-word x 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one.
3.4
On-Chip Memory Security
The 5409A device has a maskable option to protect the contents of on-chip memories. When the ROM protect bit is set, no externally originating instruction can access the on-chip memory spaces; HPI writes have no restriction, but HPI reads are restricted to 4000h - 5FFFh.
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3.5
Memory Map
Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F On-Chip 0080 DARAM0-3 (OVLY = 1) External 7FFF (OVLY = 0) 8000 External FF7F FF80 FFFF MP/MC= 1 (Microprocessor Mode) Interrupts (External) Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F 0080 On-Chip DARAM0-3 (OVLY = 1) External 7FFF (OVLY = 0) 8000 External BFFF C000 On-Chip ROM FEFF (4K x 16-bit) FF00 Reserved FF7F Interrupts FF80 FFFF (On-Chip) MP/MC= 0 (Microcomputer Mode) Hex 0000 005F 0060 007F 0080 Data Memory-Mapped Registers Scratch-Pad RAM On-Chip DARAM0-3 (32K x 16-bit)
7FFF 8000
External
FFFF
Figure 3-2. Program and Data Memory Map Address ranges for on-chip DARAM in data memory are: DARAM0: 0080h-1FFFh; DARAM1: 2000h-3FFFh DARAM2: 4000h-5FFFh; DARAM3: 6000h-7FFFh
Hex 010000 Program On-Chip DARAM0-3 (OVLY=1) External (OVLY=0) Hex 7F0000 Program
017FFF 018000
On-Chip DARAM0-3 (OVLY=1) External (OVLY=0) 7F7FFF
......
External
7F8000 External
01FFFF Page 1 XPC=1
7FFFFF Page 127 XPC=7Fh
Figure 3-3. Extended Program Memory Map
3.5.1
Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft -- meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
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15 IPTR R/W-1FF 7 IPTR R/W-1FF 6 MP/MC R/W - MP/MC pin 5 OVLY R/W-0 4 AVIS R/W-0 3 Reserved R/W-0 2 CLK OFF R/W-0 1 SMUL R/W-0
8
0 SST R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-4. Processor Mode Status Register (PMST)
Table 3-2. Processor Mode Status Register (PMST) Field Descriptions
BIT 15-7 FIELD IPTR VALUE 1FFh DESCRIPTION Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The RESET instruction does not affect this field.
MP/MC Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in pin program memory space. 0 6 MP/MC 1 The on-chip ROM is enabled and addressable. The on-chip ROM is not available. MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software. RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are: 5 OVLY 0 1 The on-chip RAM is addressable in data space but not in program space. The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh), however, is not mapped into program space. Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins. 4 AVIS 0 1 3 2 1 0 CLKOFF SMUL SST 0 N/A N/A The external address lines do not change with the internal program address. Control and data lines are not affected and the address bus is driven with the last address on the bus. This mode allows the internal program address to appear at the pins of the 5409A so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside on on-chip memory. Reserved CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level. Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1 and FRCT = 1. Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation.
Functional Overview
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3.6
On-Chip Peripherals
The 5409A device has the following peripherals: * Software-programmable wait-state generator * Programmable bank-switching * A host-port interface (HPI8/16) * Three multichannel buffered serial ports (McBSPs) * A hardware timer * A clock generator with a multiple phase-locked loop (PLL) * Enhanced external parallel interface (XIO2) * A DMA controller (DMA)
3.6.1
Software-Programmable Wait-State Generator
The software wait-state generator of the 5409A can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the 5409A. The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3.
15 XPA R/W-0 7 Data R/W-111
14 I/O R/W-111 6 5
12
11 Data R/W-111 3 2
9
8 Data R/W-111 0
Program R/W-111
Program R/W-111
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions
BIT 15 14-12 FIELD XPA I/O VALUE 0 111 DESCRIPTION Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states. I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Upper data space. The field value (0-7) corresponds to the base number of wait states for external data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
11-9
Data
111
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Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions (continued)
BIT 8-6 FIELD Data VALUE 111 DESCRIPTION Lower data space. The field value (0-7) corresponds to the base number of wait states for external data space accesses within addresses 0000-7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Upper program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses:XPA = 0: xx8000 - xxFFFFhXPA = 1: 400000h - 7FFFFFhThe SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses:XPA = 0: xx0000 - xx7FFFhXPA = 1: 000000 3FFFFFhThe SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
5-3
Program
111
2-0
Program
111
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3-6 and described in Table 3-4.
15 14 13 12 Reserved 7 6 5 4 Reserved 3 2 1 0 SWSM R/W-0 LEGEND: R = Read, W = Write, n = value at reset 11 10 9 8
Figure 3-6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3-4. Software Wait-State Control Register (SWCR) Field Descriptions
BIT 15-1 FIELD Reserved VALUE DESCRIPTION These bits are reserved and are unaffected by writes. Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2. 0 SWSM 0 1 Wait-state base values are unchanged (multiplied by 1). Wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.6.2
Programmable Bank-Switching
Programmable bank-switching logic allows the 5409A to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space. Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at address 0029h. The bit fields of the BSCR are shown in Figure 3-7 and are described in Table 3-5.
15 CONSEC R/W-1 7
14 DIVFCT R/W-11
13
12 IACK OFF R/W-1
11 Reserved R 3 2 1
8
0
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Reserved R LEGEND: R = Read, W = Write, n = value at reset
HBH R/W-0
BH R/W-0
Reserved R
Figure 3-7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 3-5. Bank-Switching Control Register (BSCR) Field Descriptions
BIT FIELD VALUE DESCRIPTION Consecutive bank-switching.Specifies the bank-switching mode. 15 CONSEC
(1)
0 1
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for continuous memory reads (i.e., no starting and trailing cycles between read cycles). Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles: starting cycle, read cycle, and trailing cycle. CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency equal to 1/(DIVFCT+1) of the DSP clock.
00 13-14 DIVFCT 01 10 11 12 11-3 IACKOFF Reserved 0 1 0 1
CLKOUT is not divided. CLKOUT is divided by 2 from the DSP clock. CLKOUT is divided by 3 from the DSP clock. CLKOUT is divided by 4 from the DSP clock (default value following reset). IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset. The IACK signal output off function is disabled. The IACK signal output off function is enabled. Reserved HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset. The bus holder is disabled except when HPI16=1. The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous logic level. Bus holder. Controls the bus holder. BH is cleared to 0 at reset. The bus holder is disabled. The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic level. Reserved
2
HBH
1 0 (1)
BH Reserved
0 1
For additional information, see Section Section 3.11 of this document.
The 5409A has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address used for the current read does not match that contained in this internal register, the MSTRB (memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs. In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see Section Section 3.11 of this document. The bank-switching mechanism automatically inserts one extra cycle in the following cases: * A memory read followed by another memory read from a different memory bank. * A program-memory read followed by a data-memory read. * A data-memory read followed by a program-memory read. * A program-memory read followed by another program-memory read from a different page.
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3.6.3
Bus Holders
The 5409A has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[15-0]), data bus (D[15-0]), and the HPI data bus (HD[7-0]). Bus keeper enabling/disabling is described in Table 3-5.
Table 3-6. Bus Holder Control Bits
HPI16 PIN 0 0 0 0 1 1 1 1 BH 0 0 1 1 0 0 1 1 HBH 0 1 0 1 0 1 0 1 D[15-0] OFF OFF ON ON OFF OFF ON ON A[15-0] OFF OFF OFF OFF OFF ON OFF ON HD[7-0] OFF ON OFF ON ON ON ON ON
3.7
Parallel I/O Ports
The 5409A has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5409A can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
3.7.1
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
The 5409A host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier TMS320C54xTM DSPs (542, 545, 548, and 549). The 5409A HPI can be used to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external devices in program/data/IO spaces), the 5409A HPI can be configured as an HPI16 to interface to a 16-bit host. This configuration can be accomplished by connecting the HPI16 pin to logic "1". When the HPI16 pin is connected to a logic "0", the 5409A HPI is configured as an HPI8. The HPI8 is an 8-bit parallel port for interprocessor communication. The features of the HPI8 include: Standard features: * Sequential transfers (with autoincrement) or random-access transfers * Host interrupt and C54xTM interrupt capability * Multiple data strobes and control pins for interface flexibility The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers -- the HPI address register (HPIA), the HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the 5409A. Enhanced features: * Access to entire on-chip RAM through DMA bus * Capability to continue transferring during emulation stop
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The HPI16 is an enhanced 16-bit version of the TMS320C54xTM DSP 8-bit host-port interface (HPI8). The HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Some of the features of the HPI16 include: * 16-bit bidirectional data bus * Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts * Only nonmultiplexed address/data modes are supported * 16-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal extended address pages) * HRDY signal to hold off host accesses due to DMA latency * The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP.
NOTE Only the nonmultiplexed mode is supported when the 5409A HPI is configured as a HPI16 (see Figure 3-8).
The 5409A HPI functions as a slave and enables the host processor to access the on-chip memory. A major enhancement to the 5409A HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are always synchronized to the 5409A clock, an active input clock (CLKIN) is required for HPI accesses during IDLE states, and host accesses are not allowed while the 5409A reset pin is asserted.
3.7.2
HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. Figure 3-8 shows a block diagram of the HPI16 in nonmultiplexed mode.
HOST DATA[15:0] PPD[15:0] HPI16
HINT Address[15:0] VCC HCNTL0 HCNTL1 HBIL HAS R/W Data Strobes READY HRDY HR/W HDS1, HDS2, HCS
HPID[15:0] DMA
54xx CPU
Figure 3-8. Host-Port Interface -- Nonmultiplexed Mode
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Address (Hex) 000 0000 Reserved 000 005F 000 0060 Scratch-Pad RAM DARAM0 DARAM3 000 7FFF 000 8000
000 007F 000 0080
Reserved
07F FFFF
Figure 3-9. HPI Memory Map
3.8
Multichannel Buffered Serial Ports (McBSPs)
The 5409A device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. There are three multichannel buffered serial ports (McBSPs) on-chip. The McBSP provides: * Full-duplex communication * Double-buffer data registers, which allow a continuous data stream * Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: * Direct interface to: - T1/E1 framers - MVIP switching-compatible and ST-BUS compliant devices - IOM-2 compliant device - AC97-compliant device - Serial peripheral interface (SPI) * Multichannel transmit and receive of up to 128 channels * A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits * -law and A-law companding * Programmable polarity for both frame synchronization and data clocks * Programmable internal clock and frame generation
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The 5409A McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator input clock source. On previous TMS320C5000TM DSP platform devices, the McBSP sample rate input clock can be driven from one of two possible choices: the internal CPU clock, or the external CLKS pin. However, most C5000TM DSP devices have only the internal CPU clock as a possible source because the CLKS pin is not implemented on most device packages. To accommodate applications that require an external reference clock for the sample rate generator, the 5409A McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control register (PCR) bit 7 - enhanced sample clock mode (SCLKME), and sample rate generator register 2 (SRGR2) bit 13 - McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR contained in the McBSPs on previous C5000 devices. The new bit layout of the PCR is shown in Figure 3-10. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302).
15 Reserved R,+0 7 SCLKME RW,+0 6 CLKS_STAT R,+0 14 13 XIOEN RW,+0 5 DX_STAT R,+0 12 RIOEN RW,+0 4 DR_STAT R,+0 11 FSXM RW,+0 3 FSXP RW,+0 10 FSRM RW,+0 2 FSRP RW,+0 9 CLKXM RW,+0 1 CLKXP RW,+0 8 CLKRM RW,+0 0 CLKRP RW,+0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-10. Pin Control Register (PCR) The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM and SCLKME bit values as shown in Table 3-7. Table 3-7. Sample Rate Generator Clock Source Selection
SCLKME 0 0 1 1 CLKSM 0 1 0 1 CPU clock BCLKR pin BCLKX pin SRG CLOCK SOURCE CLKS (not available as a pin on 5409A)
When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKX pin because the BCLKR output is automatically disabled. The McBSP supports independent selection of multiple channels for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled. The 5409A McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3-11 and Figure 3-12. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302).
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*
In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each containing 16 channels as shown in Figure 3-11 and Figure 3-12. This is compatible with the McBSPs used in some earlier TMS320C54x devices, where only 32-channel selection is enabled (default).
14 13 Reserved R,+0 12 11 10 9 XMCME RW,+0 4 XCBLK R,+0 2 1 XMCM RW,+0 8 XPBBLK RW,+0 0
15
7 XPBBLK RW,+0
6 XPABLK RW,+0
5
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-11. Multichannel Control Register 2x (MCR2x)
15
14
13 Reserved R,+0
12
11
10
9 RMCME RW,+0
8 RPBBLK RW,+0 0 RMCM RW,+0
7 RPBBLK RW,+0
6 RPABLK RW,+0
5
4 RCBLK R,+0
2
1
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-12. Multichannel Control Register 1x (MCR1x) * In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection capability. Twelve new registers (RCERCx-RCERHx and XCERCx-XCERHx) are used to enable the 128 channel selection. The subaddresses of the new registers are shown in Table 3-19. These new registers, functionally equivalent to the RCERA0-RCERB1 and XCERA0-XCERB1 registers in the 5420, are used to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the128 channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112 to 127) of MCBSP1 for each DSP subsystem. See Figure 3-13, Table 3-8, Figure 3-14, and Table 3-9 for bit layout and function of the receive and transmit registers .
14 RCERyz14 RW,+0 6 RCERyz6 RW,+0 13 RCERyz13 RW,+0 5 RCERyz5 RW,+0 12 RCERyz12 RW,+0 4 RCERy4 RW,+0 11 RCERyz11 RW,+0 3 RCERyz3 RW,+0 10 RCERyz10 RW,+0 2 RCERyz2 RW,+0 9 RCERyz9 RW,+0 1 RCERyz1 RW,+0 8 RCERyz8 RW,+0 0 RCERyz0 RW,+0
15 RCERyz15 RW,+0 7 RCERyz7 RW,+0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-13. Receive Channel Enable Registers Bit Layout for Partitions A to H
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Table 3-8. Receive Channel Enable Registers for Partitions A to H Field Descriptions
BIT 15-0 FIELD RCERyz(15:0) VALUE Receive Channel Enable Register 0 1 Disables reception of nth channel in partition y. Enables reception of nth channel in partition y. DESCRIPTION
15 XCERyz15 RW,+0 7 XCERyz7 RW,+0
14 XCERyz14 RW,+0 6 XCERyz6 RW,+0
13 XCERyz13 RW,+0 5 XCERyz5 RW,+0
12 XCERyz12 RW,+0 4 XCERy4 RW,+0
11 XCERyz11 RW,+0 3 XCERyz3 RW,+0
10 XCERyz10 RW,+0 2 XCERyz2 RW,+0
9 XCERyz9 RW,+0 1 XCERyz1 RW,+0
8 XCERyz8 RW,+0 0 XCERyz0 RW,+0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-14. Transmit Channel Enable Registers Bit Layout for Partitions A to H
Table 3-9. Transmit Channel Enable Registers for Partitions A to H Field Descriptions
Bit 15-0 FIELD XCERyz(15:0) VALUE Transmit Channel Enable Register 0 1 Disables transmit of nth channel in partition y. Enables transmit of nth channel in partition y. DESCRIPTION
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI) protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave. The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum McBSP multichannel operating frequency on the 5409A is 9 MBps. Nonmultichannel operation is limited to 38 MBps.
3.9
Hardware Timer
The 5409A device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.
3.10
Clock Generator
The clock generator provides clocks to the 5409A device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5409A device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
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When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5409A device. This clock generator allows system designers to select the clock source. The sources that drive the clock generator are: * A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the 5409A to enable the internal oscillator. * An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected.
NOTE The crystal oscillator function is not supported by all die revisions of the 5409A device. See the TMS320VC5409A Silicon Errata (literature number SPRZ186) to verify which die revisions support this functionality.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: * PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. * DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 - CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options are shown in Table 3-10.
Table 3-10. Clock Mode Settings at Reset
CLKMD1 0 0 0 1 1 1 1 0 (1) CLKMD2 0 0 1 0 1 1 0 1 CLKMD3 0 1 0 0 0 1 1 1 CLKMD RESET VALUE 0000h 9007h 4007h 1007h F007h 0000h F000h -- CLOCK MODE (1) 1/2 (PLL and Oscillator disabled) PLL x 10 (Oscillator enabled) PLL x 5 (Oscillator enabled) PLL x 2(Oscillator enabled) PLL x 1 (Oscillator enabled) 1/2 (PLL disabled, Oscillator enabled) 1/4 (PLL disabled, Oscillator enabled) Reserved (Bypass mode)
The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. However, the oscillator enable/disable selection is performed independently of the state of RS; therefore, if CLKMD1-CLKMD3 are changed following reset, the oscillator enable/disable selection may change, but other aspects of the clock generation mode will not.
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3.11
Enhanced External Parallel Interface (XIO2)
The 5409A external interface has been redesigned to include several improvements, including: simplification of the bus sequence, more immunity to bus contention when transitioning between read and write operations, the ability for external memory access to the DMA controller, and optimization of the power-down modes. The bus sequence on the 5409A still maintains all of the same interface signals as on previous 54x devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide additional immunity against bus contention when switching between read operations and write operations. To maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous 54x devices is available. Figure 3-15 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or single memory reads in consecutive mode. The accesses shown in Figure 3-15 always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
READ
R/W
MSTRB or IOSTRB
PS/DS/IS Leading Cycle Read Cycle Trailing Cycle
Figure 3-15. Nonconsecutive Memory Read and I/O Read Bus Sequence
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Figure 3-16 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in Figure 3-16 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads performed.
CLKOUT
A[22:0]
D[15:0]
READ
READ
READ
R/W
MSTRB
PS/DS Leading Cycle Read Cycle Read Cycle Read Cycle Trailing Cycle
Figure 3-16. Consecutive Memory Read Bus Sequence (n = 3 reads)
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Figure 3-17 shows the bus sequence for all memory writes and I/O writes. The accesses shown in Figure 3-17 always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
WRITE
R/W
MSTRB or IOSTRB
PS/DS/IS Leading Cycle Write Cycle Trailing Cycle
Figure 3-17. Memory Write and I/O Write Bus Sequence The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more information on DMA capability, see the DMA sections that follow. The enhanced interface improves the low-power performance already present on the TMS320C5000TM DSP platform by switching off the internal clocks to the interface when it is not being used. This power-saving feature is automatic, requires no software setup, and causes no latency in the operation of the interface. Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching cycles when crossing 32K memory boundaries (see Section Section 3.6.2), the ability to program up to 14 wait states through software (see Section Section 3.6.1), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3-5).
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3.12
DMA Controller
The 5409A direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA allows movements of data to and from internal program/data memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU operation. The DMA has six independent programmable channels, allowing six different contexts for DMA operation.
3.12.1
Features
The DMA has the following features: * The DMA operates independently of the CPU. * The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. * The DMA has higher priority than the CPU for both internal and external accesses. * Each channel has independently programmable priorities. * Each channel's source and destination address registers can have configurable indexes through memory on each read and write transfer, respectively. The address may remain constant, be post-incremented, be post-decremented, or be adjusted by a programmable value. * Each read or write internal transfer may be initialized by selected events. * On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU. * The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.12.2
DMA External Access
The 5409A DMA supports external accesses to extended program, extended data, and extended I/O memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles for external writes and a minimum of 9 cycles for external reads assuming the XIO02 is in consecutive mode (CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00). The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes precedence over XIO requests. * Only two channels are available for external accesses. (One for external reads and one for external writes.) * Single-word (16-bit) transfers are supported for external accesses. * The DMA does not support transfers from the peripherals to external memory. * The DMA does not support transfers from external memory to the peripherals. * The DMA does not support external-to-external transfers. * The DMA does not support synchronized external transfers. To allow the DMA access to extended data pages, the SLAXS and DLAXS bits are added to the DMMCRn register (see Figure 3-18).
15 AUTOINIT 14 DINM 13 IMOD 12 CT MOD 4 11 SLAXS 10 SIND 8
7 DMS
6
5 DLAXS
3 DIND
2
1 DMD
0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-18. DMA Transfer Mode Control Register (DMMCRn)
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These new bit fields were created to allow the user to define the space-select for the DMA (internal/external). The functions of the DLAXS and SLAXS bits are as follows: DLAXS(DMMCRn[5]) Destination SLAXS(DMMCRn[11]) Source 0 = No external access (default internal) 1 = External access 0 = No external access (default internal) 1 = External access Table 3-11 lists the DMD bit values and their corresponding destination space. Table 3-11. DMD Section of the DMMCRn Register
DMD 00 01 10 11 DESTINATION SPACE PS DS I/O Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the address generation logic generates an address outside its bounds, the device automatically generates an external access.
3.12.3
DMPREC Issue
When updating the DE bits of the DMPREC register while one or more DMA channel transfers are in progress, it is possible for the write to the DMPREC to cause an additional transfer on one of the active channels. The problem occurs when an active channel completes a transfer at the same time that the user updates the DMPREC register. When the transfer completes, the DMA logic attempts to clear the DE bit corresponding to the complete channel transfer, but the register is instead updated with the CPU write (usually an ORM instruction) which can set the bit and cause an additional transfer on the channel. See the TMS320VC5409A Digital Signal Processor Silicon Errata (literature number SPRZ186) for further clarification. A hardware workaround has been implemented in revision A of the 5409A device. This solution consists of an additional memory mapped register, DMCECTL (DMA Channel Enable Control), at address 0x003E, with the following characteristics:
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15 Set/Reset W-0 7 Reserved W-0
14
13
12
11 Reserved W-0
10
9
8
6
5 CH5 W-0
4 CH4 W-0
3 CH3 W-0
2 CH2 W-0
1 CH1 W-0
0 CH0 W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-19. DMA Channel Enable Control Register (DMCECTL)
Table 3-12. DMA Channel Enable Control Register (DMCECTL) Field Description
BIT 15 14-6 FIELD Set/Reset Reserved VALUE 0 1 DESCRIPTION Sets or clears individual DE bits of the DMPREC register according to the values of CH0-CH5. Clears the DE bits of the DMPREC register as specified by CH0-CH5. Sets the DE bits of the DMPREC register as specified by CH0-CH5. Reserved These bits are used in conjunction with the set/reset bit to write to the individual DE bits of the DMPREC register. 5-0 CH0-CH5 0 1 Corresponding DE bit in the DMPREC register is unaffected by the Set/Reset bit. Corresponding bit in the DMPREC register is set or cleared depending on the state of Set/Reset.
Use this register to enable or disable DMA channels instead of writing to the DMPREC register. For example, to enable channels zero and five, write a value of 0x8021 to address 0x03E. In this case only DE0 and DE5 of the DMPREC are set to 1. Or for another example, to disable channel one, write a value of 0x02 to address 0x03E. In this case only DE1 is cleared. Note that this is a write-only register
Functional Overview
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3.12.4
DMA Memory Map
The DMA memory map, shown in Figure 3-20, allows the DMA transfer to be unaffected by the status of the MP/MC, DROM, and OVLY bits.
Hex 0000 005F 0060 DLAXS = 0 SLAXS = 0 Program Reserved On-Chip DARAM0 8K Words On-Chip DARAM1 8K Words On-Chip DARAM2 8K Words On-Chip DARAM3 8K Words Reserved Hex xx0000 Program
1FFF 2000
3FFF 4000
5FFF 6000
7FFF 8000
Reserved
FFFF Page 0
xxFFFF Page 1 - 127
Figure 3-20. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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Data Space (0000 - 005F) Hex 0000 Reserved 001F 0020 DRR20 0021 DRR10 DXR20 0022 0023 DXR10 0024 Reserved 002F DRR22 0030 DRR12 0031 DXR22 0032 0033 DXR12 0034 Reserved 0035 RCERA2 0036 0037 XCERA2 0038 Reserved 0039 003A RECRA0 003B XECRA0 003C Reserved 003F DRR21 0040 0041 DRR11 0042 DXR21 0043 DXR11 0044 Reserved 0049 004A RCERA1 004B XCERA1 004C Reserved 005F
Data Space 0000 Data Space (See Breakout) 005F 0060 007F 0080 1FFF 2000 3FFF 4000 Scratch-Pad RAM On-Chip DARAM0 8K Words On-Chip DARAM1 8K Words On-Chip DARAM2 8K Words On-Chip DARAM3 8K Words Hex 0000
I/O Space
5FFF 6000
Reserved
7FFF 8000
Reserved
FFFF
FFFF
Figure 3-21. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.5
DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.6
DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and can be post-incremented, post-decremented, or post-incremented with a specified index offset.
Functional Overview
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3.12.7
DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR, and DMGFR). Autoinitialization allows: * Continuous operation:Normally, the CPU would have to reinitialize the DMA immediately after the completion of the current block transfers, but with the reload registers, it can reinitialize these values for the next block transfer any time after the current block transfer begins. * Repetitive operation:The CPU does not preload the reload register with new values for each block transfer but only loads them on the first block transfer. The 5409A DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has its own DMA reload register set. For example, the DMA reload register set for channel 0 has DMGSA0, DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and DMGFR1, etc. To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown in Figure 3-22.
15 FREE 7 INTOSEL LEGEND: R = Read, W = Write, n = value at reset 14 AUTOIX 6 13 DPRC[5:0] 5 DE[5:0] 0 8
Figure 3-22. DMPREC Register
Table 3-13. DMA Reload Register Selection
AUTOIX 0 (default) 1 DMA RELOAD REGISTER USAGE IN AUTO INIT MODE All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0 Each DMA channel uses its own set of reload registers
3.12.8
DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields that represent the number of frames and the number of elements per frame to be transferred. * Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default value) means the block transfer contains a single frame. * Element count. This 16-bit value defines the number of elements per frame. This counter is decremented after the read transfer of each element. The maximum number of elements per frame is 65536(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded with the DMA global count reload register (DMGCR).
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3.12.9
DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated following each transfer. In this mode, each 32-bit word is considered to be one element.
3.12.10
DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA transfer mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is the last in the current frame. The normal adjustment value (element index) is contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1. The element index and the frame index affect address adjustment as follows: * Element index: For all except the last transfer in the frame, the element index determines the amount to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by the SIND/DIND bits. * Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.
3.12.11
DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available modes are shown in Table 3-14.
Table 3-14. DMA Interrupts
MODE ABU (non-decrement) ABU (non-decrement) Multiframe Multiframe Either Either DINM 1 1 1 1 0 0 IMOD 0 1 0 1 X X At full buffer only At half buffer and full buffer At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0) At end of frame and end of block (DMCTRn = 0) No interrupt generated No interrupt generated INTERRUPT
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3.12.12
DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in Table 3-15. Table 3-15. DMA Synchronization Events
DSYN VALUE 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b DMA SYNCHRONIZATION EVENT No synchronization used McBSP0 receive event McBSP0 transmit event McBSP2 receive event McBSP2 transmit event McBSP1 receive event McBSP1 transmit event McBSP0 receive event - ABIS mode McBSP0 transmit event - ABIS mode McBSP2 receive event - ABIS mode McBSP2 transmit event - ABIS mode McBSP1 receive event - ABIS mode McBSP1 transmit event - ABIS mode Timer interrupt event External interrupt 3 Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When the 5409A is reset, the interrupts from these three DMA channels are deselected. The INTOSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3-16.
Table 3-16. DMA Channel Interrupt Selection
INTOSEL Value 00b (reset) 01b 10b 11b IMR/IFR[6] BRINT2 BRINT2 DMAC0 IMR/IFR[7] BXINT2 BXINT2 DMAC1 Reserved IMR/IFR[10] BRINT1 DMAC2 DMAC2 IMR/IFR[11] BXINT1 DMAC3 DMAC3
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3.13
General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the 5409A has pins that can be configured for general-purpose I/O. These pins are: * 18 McBSP pins -- BCLKX0/1/2, BCLKR0/1/2, BDR0/1/2, BFSX0/1/2, BFSR0/1/2, BDX0/1/2 * 8 HPI data pins--HD0-HD7 The general-purpose I/O function of these pins is only available when the primary pin function is not required.
3.13.1
McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose inputs or outputs. For more details on this feature, see Section Section 3.8.
3.13.2
HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two memory-mapped registers are used to control the GPIO function of the HPI data pins--the general-purpose I/O control register (GPIOCR) and the general-purpose I/O status register (GPIOSR). The GPIOCR is shown in Figure 3-24.
15 Reserved 7 DIR7 R/W-0 6 DIR6 R/W-0 5 DIR5 R/W-0 4 DIR4 R/W-0 3 DIR3 R/W-0 2 DIR2 R/W-0 1 DIR1 R/W-0 0 DIR0 R/W-0 8
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-23. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] The direction bits (DIRx) are used to configure HD0-HD7 as inputs or outputs. The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in Figure 3-23.
15 Reserved 7 IO7 R/W-0 6 IO6 R/W-0 5 IO5 R/W-0 4 IO4 R/W-0 3 IO3 R/W-0 2 IO2 R/W-0 1 IO1 R/W-0 0 IO0 R/W-0 8
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-24. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
Functional Overview
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3.14
Device ID Register
A read-only memory-mapped register has been added to the 5409A to allow user application software to identify on which device the program is being executed.
15 Chip ID R 7 Chip Revision R 4 3 SUBSYSID R 0 8
LEGEND: R = Read, W = Write, n = value at reset #IMPLIED. NOTE: Bits 15-8 Chip_ID (hex code of 09) Bits 7:4 Chip_Revision ID Bits 3:0 Sybsystem_ID (0000b for single core device)
Figure 3-25. Device ID Register (CSIDR) [MMR Address 003Eh]
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3.15
Memory-Mapped Registers
The 5409A has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to 1Fh. Each 5409A device also has a set of memory-mapped registers associated with peripherals. Table 3-17 gives a list of CPU memory-mapped registers (MMRs) available on 5409A. Table 3-18 shows additional peripheral MMRs associated with the 5409A.
Table 3-17. CPU Memory-Mapped Registers
NAME IMR IFR -- ST0 ST1 AL AH AG BL BH BG TREG TRN AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK BRC RSA REA PMST XPC -- ADDRESS DEC 0 1 2-5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 HEX 0 1 2-5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Interrupt mask register Interrupt flag register Reserved for testing Status register 0 Status register 1 Accumulator A low word (15-0) Accumulator A high word (31-16) Accumulator A guard bits (39-32) Accumulator B low word (15-0) Accumulator B high word (31-16) Accumulator B guard bits (39-32) Temporary register Transition register Auxiliary register 0 Auxiliary register 1 Auxiliary register 2 Auxiliary register 3 Auxiliary register 4 Auxiliary register 5 Auxiliary register 6 Auxiliary register 7 Stack pointer register Circular buffer size register Block repeat counter Block repeat start address Block repeat end address Processor mode status (PMST) register Extended program page register Reserved DESCRIPTION
Table 3-18. Peripheral Memory-Mapped Registers for Each DSP Subsystem
NAME DRR20 DRR10 DXR20 ADDRESS DEC 32 33 34 HEX 20 21 22 McBSP 0 Data Receive Register 2 McBSP 0 Data Receive Register 1 McBSP 0 Data Transmit Register 2 DESCRIPTION
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Table 3-18. Peripheral Memory-Mapped Registers for Each DSP Subsystem (continued)
NAME DXR10 TIM PRD TCR -- SWWSR BSCR -- SWCR HPIC -- DRR22 DRR12 DXR22 DXR12 SPSA2 SPSD2 -- SPSA0 SPSD0 -- GPIOCR GPIOSR CSIDR -- DRR21 DRR11 DXR21 DXR11 -- SPSA1 SPSD1 -- DMPREC DMSA DMSDI DMSDN CLKMD -- (1) (2) ADDRESS DEC 35 36 37 38 39 40 41 42 43 44 45-47 48 49 50 51 52 53 54-55 56 57 58-59 60 61 62 63 64 65 66 67 68-71 72 73 74-83 84 85 86 87 88 89-95 HEX 23 24 25 26 27 28 29 2A 2B 2C 2D-2F 30 31 32 33 34 35 36-37 38 39 3A-3B 3C 3D 3E 3F 40 41 42 43 44-47 48 49 4A-53 54 55 56 57 58 59-5F McBSP 0 Data Transmit Register 1 Timer Register Timer Period Register Timer Control Register Reserved Software Wait-State Register Bank-Switching Control Register Reserved Software Wait-State Control Register HPI Control Register (HMODE = 0 only) Reserved McBSP 2 Data Receive Register 2 McBSP 2 Data Receive Register 1 McBSP 2 Data Transmit Register 2 McBSP 2 Data Transmit Register 1 McBSP 2 Subbank Address Register (1) McBSP 2 Subbank Data Register (1) Reserved McBSP 0 Subbank Address Register (1) McBSP 0 Subbank Data Register (1) Reserved General-Purpose I/O Control Register General-Purpose I/O Status Register Device ID Register Reserved McBSP 1 Data Receive Register 2 McBSP 1 Data Receive Register 1 McBSP 1 Data Transmit Register 2 McBSP 1 Data Transmit Register 1 Reserved McBSP 1 Subbank Address Register (1) McBSP 1 Subbank Data Register (1) Reserved DMA Priority and Enable Control Register DMA Subbank Address Register (2) DMA Subbank Data Register with Autoincrement (2) DMA Subbank Data Register (2) Clock Mode Register (CLKMD) Reserved DESCRIPTION
See Table 3-19 for a detailed description of the McBSP control registers and their subaddresses. See Table 3-20 for a detailed description of the DMA subbank addressed registers.
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3.16
McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register. Table 3-19 shows the McBSP control registers and their corresponding subaddresses.
Table 3-19. McBSP Control Registers and Subaddresses
McBSP0 NAME SPCR10 SPCR20 RCR10 RCR20 XCR10 XCR20 SRGR10 SRGR20 MCR10 MCR20 RCERA0 RCERB0 XCERA0 XCERB0 PCR0 RCERC0 RCERD0 XCERC0 XCERD0 RCERE0 RCERF0 XCERE0 XCERF0 RCERG0 RCERH0 XCERG0 XCERH0 ADDRESS 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h 39h McBSP1 NAME SPCR11 SPCR21 RCR11 RCR21 XCR11 XCR21 SRGR11 SRGR21 MCR11 MCR21 RCERA1 RCERB1 XCERA1 XCERB1 PCR1 RCERC1 RCERD1 XCERC1 XCERD1 RCERE1 RCERF1 XCERE1 XCERF1 RCERG1 RCERH1 XCERG1 XCERH1 ADDRESS 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h 49h McBSP2 NAME SPCR12 SPCR22 RCR12 RCR22 XCR12 XCR22 SRGR12 SRGR22 MCR12 MCR22 RCERA2 RCERA2 XCERA2 XCERA2 PCR2 RCERC2 RCERD2 XCERC2 XCERD2 RCERE2 RCERF2 XCERE2 XCERF2 RCERG2 RCERH2 XCERG2 XCERH2 ADDRESS 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h 35h SUBADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh DESCRIPTION Serial port control register 1 Serial port control register 2 Receive control register 1 Receive control register 2 Transmit control register 1 Transmit control register 2 Sample rate generator register 1 Sample rate generator register 2 Multichannel register 1 Multichannel register 2 Receive channel enable register partition A Receive channel enable register partition B Transmit channel enable register partition A Transmit channel enable register partition B Pin control register Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection Additional channel enable register for 128-channel selection
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3.17
DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register. When the DMSDI register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. This autoincrement feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature is not required, the DMSDN register should be used to access the subbank. Table 3-20 shows the DMA controller subbank addressed registers and their corresponding subaddresses.
Table 3-20. DMA Subbank Addressed Registers
NAME DMSRC0 DMDST0 DMCTR0 DMSFC0 DMMCR0 DMSRC1 DMDST1 DMCTR1 DMSFC1 DMMCR1 DMSRC2 DMDST2 DMCTR2 DMSFC2 DMMCR2 DMSRC3 DMDST3 DMCTR3 DMSFC3 DMMCR3 DMSRC4 DMDST4 DMCTR4 DMSFC4 DMMCR4 DMSRC5 DMDST5 DMCTR5 DMSFC5 DMMCR5 DMSRCP ADDRESS 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h SUBADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh DESCRIPTION DMA channel 0 source address register DMA channel 0 destination address register DMA channel 0 element count register DMA channel 0 sync select and frame count register DMA channel 0 transfer mode control register DMA channel 1 source address register DMA channel 1 destination address register DMA channel 1 element count register DMA channel 1 sync select and frame count register DMA channel 1 transfer mode control register DMA channel 2 source address register DMA channel 2 destination address register DMA channel 2 element count register DMA channel 2 sync select and frame count register DMA channel 2 transfer mode control register DMA channel 3 source address register DMA channel 3 destination address register DMA channel 3 element count register DMA channel 3 sync select and frame count register DMA channel 3 transfer mode control register DMA channel 4 source address register DMA channel 4 destination address register DMA channel 4 element count register DMA channel 4 sync select and frame count register DMA channel 4 transfer mode control register DMA channel 5 source address register DMA channel 5 destination address register DMA channel 5 element count register DMA channel 5 sync select and frame count register DMA channel 5 transfer mode control register DMA source program page address (common channel)
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Table 3-20. DMA Subbank Addressed Registers (continued)
NAME DMDSTP DMIDX0 DMIDX1 DMFRI0 DMFRI1 DMGSA0 DMGDA0 DMGCR0 DMGFR0 DMGSA1 DMGDA1 DMGCR1 DMGFR1 DMGSA2 DMGDA2 DMGCR2 DMGFR2 DMGSA3 DMGDA3 DMGCR3 DMGFR3 DMGSA4 DMGDA4 DMGCR4 DMGFR4 DMGSA5 DMGDA5 DMGCR5 DMGFR5 DMCECTL ADDRESS 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h 56h/57h SUBADDRESS 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh DESCRIPTION DMA destination program page address (common channel) DMA element index address register 0 DMA element index address register 1 DMA frame index register 0 DMA frame index register 1 DMA global source address reload register, channel 0 DMA global destination address reload register, channel 0 DMA global count reload register, channel 0 DMA global frame count reload register, channel 0 Reserved Reserved DMA global source address reload register, channel 1 DMA global destination address reload register, channel 1 DMA global count reload register, channel 1 DMA global frame count reload register, channel 1 DMA global source address reload register, channel 2 DMA global destination address reload register, channel 2 DMA global count reload register, channel 2 DMA global frame count reload register, channel 2 DMA global source address reload register, channel 3 DMA global destination address reload register, channel 3 DMA global count reload register, channel 3 DMA global frame count reload register, channel 3 DMA global source address reload register, channel 4 DMA global destination address reload register, channel 4 DMA global count reload register, channel 4 DMA global frame count reload register, channel 4 DMA global source address reload register, channel 5 DMA global destination address reload register, channel 5 DMA global count reload register, channel 5 DMA global frame count reload register, channel 5 DMA channel enable control register
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3.18
Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-21.
Table 3-21. Interrupt Locations and Priorities
NAME RS, SINTR NMI, SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 INT0, SINT0 INT1, SINT1 INT2, SINT2 TINT, SINT3 RINT0, SINT4 XINT0, SINT5 RINT2, SINT6 XINT2, SINT7 INT3, SINT8 HINT, SINT9 RINT1, SINT10 XINT1, SINT11 DMAC4,SINT12 DMAC5,SINT13 Reserved 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120-127 LOCATION DECIMAL HEX 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78-7F PRIORITY 1 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- FUNCTION Reset (hardware and software reset) Nonmaskable interrupt Software interrupt #17 Software interrupt #18 Software interrupt #19 Software interrupt #20 Software interrupt #21 Software interrupt #22 Software interrupt #23 Software interrupt #24 Software interrupt #25 Software interrupt #26 Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30 External user interrupt #0 External user interrupt #1 External user interrupt #2 Timer interrupt McBSP #0 receive interrupt (default) McBSP #0 transmit interrupt (default) McBSP #2 receive interrupt (default) McBSP #2 transmit interrupt (default) External user interrupt #3 HPI interrupt McBSP #1 receive interrupt (default) McBSP #1 transmit interrupt (default) DMA channel 4 (default) DMA channel 5 (default) Reserved
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3-26.
15 Reserved 7 XINT2 6 RINT2 14 13 DMAC5 5 XINT0 12 DMAC4 4 RINT0 11 XINT1 3 TINT 10 RINT1 2 INT2 9 HINT 1 INT1 8 INT3 0 INT0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-26. IFR and IMR
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4
4.1
Support
Documentation Support
Extensive documentation supports all TMS320TM DSP family of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the C5000TM platform of DSPs: SPRU307: TMS320C54x DSP Family Functional Overview Provides a functional overview of the devices included in the TMS320C54xE DSP generation of digital signal processors. Included are descriptions of the CPU architecture, bus structure, memory structure, on-chip peripherals, and instruction set. Calculation of TMS320LC54x Power Dissipation Describes the power-saving features of the TMS320LC54x and presents techniques for analyzing systems and device conditions to determine operating current levels and power dissipaton. From this information, informed decisions can be made regarding power supply requirements and thermal management considerations.
SPRA164:
The five-volume TMS320C54x DSP Reference Set consists of: SPRU131: TMS320C54x DSP Reference Set, Volume 1: CPU Describes the TMS320C54x 16-bit fixed-point general-purpose digital signal processors. Covered are its architecture, internal register structure, data and program addressing, and the instruction pipeline. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator. TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set Describes the TMS320C54x digital signal processor mnemonic instructions individually. Also includes a summary of instruction set classes and cycles. TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set Describes the TMS320C54x digital signal processor algebraic instructions individually. Also includes a summary of instruction set classes and cycles. TMS320C54x DSP Reference Set, Volume 4: Applications Guide Describes software and hardware applications for the TMS320C54x digital signal processor. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator. TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals Describes the enhanced peripherals available on the TMS320C54x digital signal processors. Includes the multichannel buffered serial ports (McBSPs), direct memory access (DMA) controller, interprocessor communications, and the HPI-8 and HPI-16 host port interfaces.
SPRU172:
SPRU179:
SPRU173:
SPRU302:
The reference set describes in detail the TMS320C54xTM DSP products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320TM DSP family of devices. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding TI DSP porducts is also available on the web at www.ti.com.
Support
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4.2
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX TMP TMS Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
Support tool development evolutionary flow: TMDX TMDS Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
52
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5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320VC5409A DSP.
5.1
Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to DVSS. Figure 5-1 provides the test load circuit values.
DVDD CVDD VI VO TC Tstg
Supply voltage I/O range Supply voltage core range Input voltage range Output voltage range Operating case temperature range Storage temperature range
- 0.3 V to 4.0 V - 0.3 V to 2.0 V - 0.3 V to 4.5 V - 0.3 V to 4.5 V - 40C to 100C - 55C to 150C
5.2
DVDD CVDD CVDD DVSS, CVSS
Recommended Operating Conditions
MIN Device supply voltage, I/O Device supply voltage, core (VC5409A-160) Device supply voltage, core (VC5409A-120) Supply voltage, GND RS, INTn, NMI, X2/CLKIN, CLKMDn, BCLKRn, BCLKXn, HCS, HDS1, HDS2, HAS, TRST, TCK, BIO, Dn, An, HDn (DVDD = 2.7 V to 3.6 V) All other inputs 2.7 1.55 1.42 NOM 3.3 1.6 1.5 0 MAX 3.6 1.65 1.65 UNIT V V V V
VIH
High-level input voltage, I/O
2.4
DVDD + 0.3
V
2 - 0.3
DVDD + 0.3 0.8 -8 8 V mA mA C
VIL IOH IOL TC (1) (2)
Low-level input voltage High-level output current (1) (2) Low-level output current (1) (2) Operating case temperature
- 40
100
These output current limits are used for the test conditions on VOL and VOH, except where noted otherwise. The maximum output currents are DC values only. Transient currents may exceed these values.
Electrical Specifications
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5.3
Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS (DVDD = 2.7 V to 3.0 V), IOH = - 2 mA (DVDD = 3.0 V to 3.6 V), IOH = MAX IOL = MAX DVDD = MAX, VO = DVSS to DVDD - 275 - 40 With internal pulldown With internal pulldown, RS = 0 HPI (3) With internal pullups Bus holders enabled, DVDD = MAX (4) CVDD = 1.6 V, fx = 160 MHz, (5)TC = 25C DVDD = 3.0 V, fx = 160 IDLE2 IDLE3 divide-by-two mode, CLKIN stopped TC = 25C TC = 100C MHz, (5)TC = 25C PLL x 1 mode, 20 MHz input - 10 - 10 - 400 - 275 -5 60 (6) 40 (7) 2 1 (8) 30 5 5 MIN TYP (1) 2.2 2.4 0.4 275 40 800 400 10 275 5 mA mA mA mA pF pF A MAX UNIT V V A A
VOH VOL IIZ
High-level output voltage (2) Low-level output voltage (2) Input current in high impedance A[15:0] X2/CLKIN TRST, HPI16 HPIENA TMS, TCK, TDI, D[15:0], HD[7:0] All other input-only pins
II
Input current (VI = DVSS to DVDD)
IDDC IDDP IDD Ci Co (1) (2) (3) (4) (5) (6) (7) (8)
Supply current, core CPU Supply current, pins Supply current, standby Input capacitance Output capacitance
All values are typical unless otherwise specified. All input and output voltage levels except RS, INT0-INT3, NMI, X2/CLKIN, CLKMD1-CLKMD3, BCLKR0 - BCLKR2, BCLKX0 - BCLKX2, HCS, HAS, HDS1, HDS2, BIO, TCK, TRST, D0 - D15, HD0 - HD7, A0 - A16 are LVTTL-compatible. HPI input signals except for HPIENA and HPI16, when HPIENA = 0. VIL(MIN)VI VIL(MAX)or VIH(MIN) VI VIH(MAX) Clock mode: PLL x 1 with external source This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed. This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed, refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164). Material with high IDD has been observed with a typical IDD value of 5 to 10 mA during high temperature testing.
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TMS320VC5409A Fixed-PointDigital Signal Processor
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5.4
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this data manual.
Tester Pin Electronics
Data Sheet Timing Reference Point
42 W
3.5 nH Transmission Line Z0 = 50 W (see note)
Output Under Test
Device Pin (see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. Tester Pin Electronics
5.5
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings: a c d dis en f h r su t v w X access time cycle time (period) delay time disable time enable time fall time hold time rise time setup time transition time valid time pulse duration (width) Unknown, changing, or don't care level
Letters and symbols and their meanings: H L V Z High Low Valid High impedance
5.6
Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent; see Section Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register.
Electrical Specifications
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The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance of 30 maximum and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5-2. The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL (recommended value of 10 pF) in the equation is the load specified for the crystal.
CL + C 1C 2 (C1 ) C2)
Table 5-1. Input Clock Frequency Characteristics
MIN fx (1) (2) Input clock frequency 10 (1) MAX 20 (2) UNIT MHz
This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
X1 Crystal
X2/CLKIN
C1
C2
Figure 5-2. Internal Divide-By-Two Clock Option With External Crystal
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5.7
Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or multiplied by one of several values to generate the internal machine cycle.
5.7.1
Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to generate the internal machine cycle. The selection of the clock mode is described in Section Section 3.10. When an external clock source is used, the frequency injected must conform to specifications listed in Table 5-3. An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected. Table 5-2 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or divide-by-4 clock option.
Table 5-2. Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
CLKMD1 0 1 1 CLKMD2 0 0 1 CLKMD3 0 1 1 CLOCK MODE 1/2, PLL disabled 1/4, PLL disabled 1/2, PLL disabled
Table 5-3 and Table 5-4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-3).
Table 5-3. Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
VC5409A120VC5409A160 MIN tc(CI) tf(CI) tr(CI) tw(CIL) tw(CIH) Cycle time, X2/CLKIN Fall time, X2/CLKIN Rise time, X2/CLKIN Pulse duration, X2/CLKIN low Pulse duration, X2/CLKIN high 4 4 20 4 4 MAX ns ns ns ns ns
Unit
Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
PARAMETER tc(CO) td(CIH-CO) tf(CO) tr(CO) tw(COL) (1) (2) Cycle time, CLKOUT Delay time, X2/CLKIN high to CLKOUT high/low Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low H-3 5409A-120 MIN 8.33 (1) 4 7 1 1 H H+3 H-3 TYP MAX
(2)
5409A-160 MIN 6.25 (1) 4 7 1 1 H H+3 TYP MAX
(2)
UNIT ns ns ns ns ns
11
11
It is recommended that the PLL clocking option be used for maximum frequency operation. This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz. Electrical Specifications 57
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Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics (continued)
PARAMETER tw(COH) Pulse duration, CLKOUT high
tw(CIH) tc(CI) X2/CLKIN tw(CIL)
5409A-120 MIN H-3 TYP H MAX H+3
tr(CI)
5409A-160 MIN H-3 TYP H MAX H+3
UNIT ns
tf(CI)
tc(CO) td(CIH-CO) CLKOUT(A)
tf(CO) tr(CO)
tw(COH) tw(COL)
A.
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-3. External Divide-By-Two Clock Timing
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5.7.2
Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in Section Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for detailed information on programming the PLL. When an external clock source is used, the external frequency injected must conform to specifications listed in Table 5-5. Table 5-5 and Table 5-6 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-4).
Table 5-5. Multiply-By-N Clock Option Timing Requirements
5409A-120 5409A-160 MIN Integer PLL multiplier N (N = 1-15) (1) tc(CI) Cycle time, X2/CLKIN PLL multiplier N = x.5 (1) PLL multiplier N = x.25, x.75 (1) tf(CI) tr(CI) tw(CIL) tw(CIH) (1) Fall time, X2/CLKIN Rise time, X2/CLKIN Pulse duration, X2/CLKIN low Pulse duration, X2/CLKIN high 4 4 20 20 20 MAX 200 100 50 4 4 ns ns ns ns ns
UNIT
N is the multiplication factor.
Table 5-6. Multiply-By-N Clock Option Switching Characteristics
PARAMETER tc(CO) td(CI-CO) tf(CO) tr(CO) tw(COL) tw(COH) tp Cycle time, CLKOUT Delay time, X2/CLKIN high/low to CLKOUT high/low Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low Pulse duration, CLKOUT high Transitory phase, PLL lock-up time 5409A-120 MIN 8.33 4 7 2 2 H H 30 11 TYP MAX 5409A-160 MIN 6.25 4 7 2 2 H H 30 11 TYP MAX UNIT ns ns ns ns ns ns ms
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tw(CIH) tc(CI) X2/CLKIN td(CI-CO) tc(CO) tp CLKOUT(A) Unstable
tw(CIL)
tr(CI)
tf(CI)
tw(COH)
tf(CO) tw(COL) tr(CO)
A.
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-4. Multiply-By-One Clock Timing
5.8
Memory and Parallel I/O Interface Timing
Address delay times are longer for cycles immediatly following a HOLD operation. All timings related to the address bus have been seperated in to two cases; one showing normal operation and the other showing the delays related to the HOLD operation.
5.8.1
Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the CONSEC bit in the BSCR. Table 5-7 and Table 5-8 assume testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see Figure 5-5 and Figure 5-6). Table 5-7. Memory Read Timing Requirements
5409A-120 5409A-160 MIN Access time, read data access from address valid, first read access (1) For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation 7 0 MAX 4H-9 4H-11 2H-9 ns ns ns ns ns
UNIT
ta(A)M1
ta(A)M2 tsu(D)R th(D)R (1)
Access time, read data access from address valid, consecutive read accesses (1) Setup time, read data valid before CLKOUT low Hold time, read data valid after CLKOUT low
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5-8. Memory Read Switching Characteristics
5409A-120 5409A-160 MIN For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation -1 -1 -1 -1 MAX 4 6 4 4 ns ns ns ns
PARAMETER
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address
valid (1)
td(CLKL-MSL) td(CLKL-MSH) (1)
Delay time, CLKOUT low to MSTRB low Delay time, CLKOUT low to MSTRB high
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
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CLKOUT td(CLKL-A) A[22:0](A) td(CLKL-MSL) td(CLKL-MSH) ta(A)M1 D[15:0] tsu(D)R th(D)R MSTRB
R/W(A)
PS/DS(A)
A.
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-5. Nonconsecutive Mode Memory Reads
Electrical Specifications
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CLKOUT td(CLKL-A) td(CLKL-MSL) td(CLKL-MSH) A[22:0](A) ta(A)M1 ta(A)M2 D[15:0] tsu(D)R th(D)R MSTRB tsu(D)R th(D)R
R/W(A)
PS/DS(A)
A.
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-6. Consecutive Mode Memory Reads
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5.8.2
Memory Write
Table 5-9 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see Figure 5-7). Table 5-9. Memory Write Switching Characteristics
5409A-120 5409A-160 MIN For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation -1 -1 2H - 3 2H - 5 -1 2H - 5 2H - 5 -1 2H - 2 -1 4 4 2H + 6 2H + 6 4 MAX 4 6 ns ns ns ns ns ns ns ns ns ns
PARAMETER
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address valid (1)
tsu(A)MSL
Setup time, address valid before MSTRB low (1) Delay time, CLKOUT low to data valid Setup time, data valid before MSTRB high Hold time, data valid after MSTRB high Delay time, CLKOUT low to MSTRB low Pulse duration, MSTRB low Delay time, CLKOUT low to MSTRB high
td(CLKL-D)W tsu(D)MSH th(D)MSH td(CLKL-MSL) tw(SL)MS td(CLKL-MSH) (1)
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Electrical Specifications
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CLKOUT td(CLKL-A) td(CLKL-D)W tsu(A)MSL A[22:0](A) tsu(D)MSH th(D)MSH D[15:0] td(CLKL-MSL) td(CLKL-MSH) tw(SL)MS MSTRB
R/W(A)
PS/DS(A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-7. Memory Write (MSTRB = 0)
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5.8.3
I/O Read
Table 5-10 and Table 5-11 assume testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see Figure 5-8). Table 5-10. I/O Read Timing Requirements
5409A-120 5409A-160 MIN For accesses not immediately following a Access time, read data access from address HOLD operation valid, first read access (1) For a read accesses immediately following a HOLD operation Setup time, read data valid before CLKOUT low Hold time, read data valid after CLKOUT low 7 0 MAX 4H - 9 4H - 11 ns ns ns ns
UNIT
ta(A)M1
tsu(D)R th(D)R (1)
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Table 5-11. I/O Read Switching Characteristics
5409A-120 5409A-160 MIN For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation -1 -1 -1 -1 MAX 4 6 4 4 ns ns ns ns
PARAMETER
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address
valid (1)
td(CLKL-IOSL) td(CLKL-IOSH) (1)
Delay time, CLKOUT low to IOSTRB low Delay time, CLKOUT low to IOSTRB high
Address R/W,PS, DS, and IS timings are included in timings referenced as address.
Electrical Specifications
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CLKOUT td(CLKL-A) td(CLKL-IOSL) td(CLKL-IOSH) A[22:0](A) ta(A)M1 tsu(D)R th(D)R D[15:0]
IOSTRB
R/W(A)
IS(A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-8. Parallel I/O Port Read (IOSTRB = 0)
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5.8.4
I/O Write
Table 5-12 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO)(see Figure 5-9). Table 5-12. I/O Write Switching Characteristics
5409A-120 5409A-160 MIN For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation For accesses not immediately following a HOLD operation For a read accesses immediately following a HOLD operation -1 -1 2H - 3 2H - 5 -1 2H - 5 2H - 5 -1 2H - 2 -1 4 4 2H + 6 2H + 6 4 MAX 4 6 ns ns ns ns ns ns ns ns ns ns
PARAMETER
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address valid (1)
tsu(A)IOSL
Setup time, address valid before IOSTRB low (1) Delay time, CLKOUT low to write data valid Setup time, data valid before IOSTRB high Hold time, data valid after IOSTRB high Delay time, CLKOUT low to IOSTRB low Pulse duration, IOSTRB low Delay time, CLKOUT low to IOSTRB high
td(CLKL-D)W tsu(D)IOSH th(D)IOSH td(CLKL-IOSL) tw(SL)IOS td(CLKL-IOSH) (1)
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT td(CLKL-A) A[22:0](A) td(CLKL-D)W tsu(A)IOSL D[15:0] tsu(D)IOSH td(CLKL-IOSH) td(CLKL-IOSL) IOSTRB th(D)IOSH td(CLKL-D)W
R/W(A)
tw(SL)IOS
IS(A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-9. Parallel I/O Port Write (IOSTRB = 0)
Electrical Specifications
67
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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5.9
Ready Timing for Externally Generated Wait States
Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13). Table 5-13. Ready Timing Requirements for Externally Generated Wait States (1)
5409A-120 5409A-160 MIN MAX ns ns 4H - 4 4H 4H - 4 4H ns ns ns ns
UNIT
tsu(RDY) th(RDY) tv(RDY)MSTRB th(RDY)MSTRB tv(RDY)IOSTRB th(RDY)IOSTRB (1) (2)
Setup time, READY before CLKOUT low Hold time, READY after CLKOUT low Valid time, READY after MSTRB low (2) Hold time, READY after MSTRB low (2) Valid time, READY after IOSTRB low (2) Hold time, READY after IOSTRB low (2)
7 0
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states. These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States (1)
5409A-120 5409A-160 MIN td(MSCL) td(MSCH) (1) Delay time, CLKOUT low to MSC low Delay time, CLKOUT low to MSC high -1 -1 MAX 4 4 ns ns
PARAMETER
UNIT
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
CLKOUT
A[22:0] tsu(RDY) th(RDY) READY tv(RDY)MSTRB th(RDY)MSTRB MSTRB td(MCSL) td(MCSH) MSC Leading Cycle Wait States Generated Internally
Wait States Generated by READY
Trailing Cycle
Figure 5-10. Memory Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0] tsu(RDY) th(RDY) READY tv(RDY)MSTRB th(RDY)MSTRB MSTRB td(MSCL) td(MSCH) MSC Leading Cycle Wait States Generated Internally Wait States Generated by READY
Trailing Cycle
Figure 5-11. Memory Write With Externally Generated Wait States
Electrical Specifications
69
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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CLKOUT
A[22:0] tsu(RDY) th(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB td(MSCL) td(MSCH) MSC Leading Cycle Wait States Generated Internally
Wait States Generated by READY
Trailing Cycle
Figure 5-12. I/O Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0] tsu(RDY) th(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB td(MSCL) td(MSCH) MSC Leading Cycle Wait States Generated Internally
Wait States Generated by READY
Trailing Cycle
Figure 5-13. I/O Write With Externally Generated Wait States
70
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.10
HOLD and HOLDA Timings
Table 5-15 and Table 5-16 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-14).
Table 5-15. HOLD and HOLDA Timing Requirements
5409A-120 5409A-160 MIN tw(HOLD) tsu(HOLD) Pulse duration, HOLD low duration Setup time, HOLD before CLKOUT low 4H+8 7 MAX ns ns
UNIT
Table 5-16. HOLD and HOLDA Switching Characteristics
5409A-120 5409A-160 MIN tdis(CLKL-A) tdis(CLKL-RW) tdis(CLKL-S) ten(CLKL-A) ten(CLKL-RW) ten(CLKL-S) tv(HOLDA) tw(HOLDA) Disable time, Address, PS, DS, IS high impedance from CLKOUT low Disable time, R/W high impedance from CLKOUT low Disable time, MSTRB, IOSTRB high impedance from CLKOUT low Enable time, Address, PS, DS, IS valid from CLKOUT low Enable time, R/W enabled from CLKOUT low Enable time, MSTRB, IOSTRB enabled from CLKOUT low Valid time, HOLDA low after CLKOUT low Valid time, HOLDA high after CLKOUT low Pulse duration, HOLDA low duration 2 -1 -1 2H-3 MAX 3 3 3 2H+6 2H+3 2H+3 4 4 ns ns ns ns ns ns ns ns ns
PARAMETER
UNIT
Electrical Specifications
71
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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CLKOUT tsu(HOLD) HOLD tv(HOLDA) HOLDA tdis(CLKL-A) A[22:0] PS, DS, IS tv(HOLDA) tw(HOLDA) ten(CLKL-A) tw(HOLD) tsu(HOLD)
D[15:0] tdis(CLKL-RW) R/W tdis(CLKL-S) MSTRB tdis(CLKL-S) IOSTRB ten(CLKL-S) ten(CLKL-S) ten(CLKL-RW)
Figure 5-14. HOLD and HOLDA Timings (HM = 1)
72
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.11
Reset, BIO, Interrupt, and MP/MC Timings
Table 5-17 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-15, Figure 5-16, and Figure 5-17).
Table 5-17. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5409A-120 5409A-160 MIN th(RS) th(BIO) th(INT) th(MPMC) tw(RSL) tw(BIO)S tw(BIO)A tw(INTH)S tw(INTH)A tw(INTL)S tw(INTL)A tw(INTL)WKP tsu(RS) tsu(BIO) tsu(INT) tsu(MPMC) (1) (2) (3) (4) Hold time, RS after CLKOUT low Hold time, BIO after CLKOUT low Hold time, INTn, NMI, after CLKOUT low (1) Hold time, MP/MC after CLKOUT low Pulse duration, RS low (2) (3) Pulse duration, BIO low, synchronous Pulse duration, BIO low, asynchronous Pulse duration, INTn, NMI high (synchronous) Pulse duration, INTn, NMI high (asynchronous) Pulse duration, INTn, NMI low (synchronous) Pulse duration, INTn, NMI low (asynchronous) Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup Setup time, RS before X2/CLKIN low (4) Setup time, BIO before CLKOUT low Setup time, INTn, NMI, RS before CLKOUT low Setup time, MP/MC before CLKOUT low 2 4 1 4 4H+3 2H+3 4H 2H+2 4H 2H+2 4H 7 3 7 7 5 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UNIT
The external interrupts (INT0-INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding to three CLKOUTs sampling sequence. If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 s to ensure synchronization and lock-in of the PLL. Note that RS may cause a change in clock frequency, therefore changing the value of H. The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
X2/CLKIN tsu(RS) tw(RSL) RS, INTn, NMI tsu(INT) th(RS) CLKOUT tsu(BIO) th(BIO) BIO tw(BIO)S
Figure 5-15. Reset and BIO Timings
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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CLKOUT
tsu(INT) INTn, NMI tw(INTH)A
tsu(INT)
th(INT)
tw(INTL)A
Figure 5-16. Interrupt Timing
CLKOUT
RS
th(MPMC) tsu(MPMC)
MP/MC
Figure 5-17. MP/MC Timing
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.12
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5-18 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-18).
Table 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
5409A-120 5409A-160 MIN td(CLKL-IAQL) td(CLKL-IAQH) td(A)IAQ td(CLKL-IACKL) td(CLKL-IACKH) td(A)IACK th(A)IAQ th(A)IACK tw(IAQL) tw(IACKL) Delay time, CLKOUT low to IAQ low Delay time, CLKOUT low to IAQ high Delay time, IAQ low to address valid Delay time, CLKOUT low to IACK low Delay time, CLKOUT low to IACK high Delay time, IACK low to address valid Hold time, address valid after IAQ high Hold time, address valid after IACK high Pulse duration, IAQ low Pulse duration, IACK low -2 -2 2H - 2 2H - 2 -1 -1 -1 -1 MAX 4 4 2 4 4 2 ns ns ns ns ns ns ns ns ns ns
PARAMETER
UNIT
CLKOUT
A[22:0] td(CLKL - IAQL) td(A)IAQ IAQ tw(IAQL) td(CLKL - IAQH) th(A)IAQ
td(CLKL - IACKL) td(A)IACK tw(IACKL) IACK
td(CLKL - IACKH) th(A)IACK
Figure 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Electrical Specifications
75
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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5.13
External Flag (XF) and TOUT Timings
Table 5-19 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-19 and Figure 5-20). Table 5-19. External Flag (XF) and TOUT Switching Characteristics
5409A-120 5409A-160 MIN MAX 4 4 4 4 ns ns ns ns -1 -1 -1 -1 2H - 4
PARAMETER Delay time, CLKOUT low to XF high Delay time, CLKOUT low to XF low Delay time, CLKOUT low to TOUT high Delay time, CLKOUT low to TOUT low Pulse duration, TOUT
CLKOUT
UNIT
td(XF) td(TOUTH) td(TOUTL) tw(TOUT)
td(XF) XF
Figure 5-19. External Flag (XF) Timing
CLKOUT
td(TOUTH) TOUT tw(TOUT)
td(TOUTL)
Figure 5-20. TOUT Timing
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.14 5.14.1
Multichannel Buffered Serial Port (McBSP) Timing McBSP Transmit and Receive Timings
Table 5-20 and Table 5-21 assume testing over recommended operating conditions (see Figure 5-21 and Figure 5-22). Table 5-20. McBSP Transmit and Receive Timing Requirements (1)
5409A-120 5409A-160 MIN tc(BCKRX) tw(BCKRX) tsu(BFRH-BCKRL) th(BCKRL-BFRH) tsu(BDRV-BCKRL) th(BCKRL-BDRV) tsu(BFXH-BCKXL) th(BCKXL-BFXH) tr(BCKRX) tf(BCKRX) (1) (2) Cycle time, BCLKR/X Pulse duration, BCLKR/X high or BCLKR/X low Setup time, external BFSR high before BCLKR low Hold time, external BFSR high after BCLKR low Setup time, BDR valid before BCLKR low Hold time, BDR valid after BCLKR low Setup time, external BFSX high before BCLKX low Hold time, external BFSX high after BCLKX low Rise time, BCKR/X Fall time, BCKR/X BCLKR/X ext BCLKR/X ext BCLKR int BCLKR ext BCLKR int BCLKR ext BCLKR int BCLKR ext BCLKR int BCLKR ext BCLKX int BCLKX ext BCLKX int BCLKX ext BCLKR/X ext BCLKR/X ext 4P (2) 2P-1 (2) 8 1 1 2 7 1 2 3 8 1 0 2 6 6 MAX ns ns ns ns ns ns ns ns ns ns
UNIT
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 0.5 * processor clock
Electrical Specifications
77
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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Table 5-21. McBSP Transmit and Receive Switching Characteristics (1)
5409A-120 5409A-160 MIN tc(BCKRX) tw(BCKRXH) tw(BCKRXL) td(BCKRH-BFRV) td(BCKXH-BFXV) tdis(BCKXH-BDXHZ) td(BCKXH-BDXV) td(BFXH-BDXV) (1) (2) (3) (4) (5) Cycle time, BCLKR/X Pulse duration, BCLKR/X high Pulse duration, BCLKR/X low Delay time, BCLKR high to internal BFSR valid Delay time, BCLKX high to internal BFSX valid Disable time, BCLKX high to BDX high impedance following last data bit of transfer Delay time, BCLKX high to BDX valid DXENA = 0 (4) BCLKR/X int BCLKR/X int BCLKR/X int BCLKR int BCLKR ext BCLKX int BCLKX ext BCLKX int BCLKX ext BCLKX int BCLKX ext BFSX int BFSX ext - 1 (5) 2 - 1 (5) 2 4P (2) D- 1 (3) D+ 1 (3) C - 1 (3) C + 1 (3) -3 0 -1 2 3 11 5 10 6 10 10 20 7 11 MAX ns ns ns ns ns ns ns ns ns
PARAMETER
UNIT
Delay time, BFSX high to BDX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 0.5 * processor clock T = BCLKRX period = (1 + CLKGDV) * 2P C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5409A. Minimum delay times also represent minimum output hold times.
tc(BCKRX) tw(BCKRXH) tw(BCKRXL) BCLKR td(BCKRH-BFRV) BFSR (int) tsu(BFRH-BCKRL) BFSR (ext) th(BCKRL-BDRV) tsu(BDRV-BCKRL) th(BCKRL-BFRH) td(BCKRH-BFRV) tr(BCKRX) tr(BCKRX)
BDR (RDATDLY=00b) BDR (RDATDLY=01b) BDR (RDATDLY=10b)
Bit (n-1) tsu(BDRV-BCKRL)
(n-2)
(n-3) th(BCKRL-BDRV)
(n-4)
Bit (n-1) tsu(BDRV-BCKRL)
(n-2)
(n-3) th(BCKRL-BDRV)
Bit (n-1)
(n-2)
Figure 5-21. McBSP Receive Timings
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
tc(BCKRX) tw(BCKRXH) tw(BCKRXL) BCLKX td(BCKXH-BFXV) BFSX (int) tsu(BFXH-BCKXL) BFSX (ext) td(BDFXH-BDXV) BDX (XDATDLY=00b) Bit 0 Bit (n-1) (n-2) th(BCKXL-BFXH) td(BCKXH-BFXV)
tr(BCKRX)
tf(BCKRX)
td(BCKXH-BDXV) (n-3) td(BCKXH-BDXV) (n-4)
BDX (XDATDLY=01b)
Bit 0 tdis(BCKXH-BDXHZ)
Bit (n-1)
(n-2) td(BCKXH-BDXV) Bit (n-1)
(n-3)
BDX (XDATDLY=10b)
Bit 0
(n-2)
Figure 5-22. McBSP Transmit Timings
Electrical Specifications
79
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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5.14.2
McBSP General-Purpose I/O Timing
Table 5-22 and Table 5-23 assume testing over recommended operating conditions (see Figure 5-23).
Table 5-22. McBSP General-Purpose I/O Timing Requirements
5409A-120 5409A-160 MIN tsu(BGPIO-COH) th(COH-BGPIO) (1) Setup time, BGPIOx input mode before CLKOUT high (1) Hold time, BGPIOx input mode after CLKOUT high (1) 7 0 MAX ns ns
UNIT
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 5-23. McBSP General-Purpose I/O Switching Characteristics
5409A-120 5409A-160 MIN td(COH-BGPIO) (1) Delay time, CLKOUT high to BGPIOx output mode (1) -2 MAX 4 ns
PARAMETER
UNIT
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
tsu(BGPIO-COH) CLKOUT th(COH-BGPIO) BGPIOx Input Mode(A) td(COH-BGPIO)
BGPIOx Output Mode(B)
A. B.
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5-23. McBSP General-Purpose I/O Timings
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Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.14.3
McBSP as SPI Master or Slave Timing
Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24, Figure 5-25, Figure 5-26, and Figure 5-27). Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
5409A-120 5409A-160 MASTER MIN MAX tsu(BDRV-BCKXL) th(BCKXL-BDRV) (1) (2) Setup time, BDR valid before BCLKX low Hold time, BDR valid after BCLKX low 12 4 SLAVE MIN 2 - 6P (2) 5 + 12P (2) MAX ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = 0.5 * processor clock
Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) (1)
5409A-120 5409A-160 PARAMETER MASTER (2) MIN th(BCKXL-BFXL) td(BFXL-BCKXH) td(BCKXH-BDXV) tdis(BCKXL-BDXHZ) tdis(BFXH-BDXHZ) td(BFXL-BDXV) (1) (2) (3) (4) (5) Hold time, BFSX low after BCLKX low (3) Delay time, BFSX low to BCLKX high (4) Delay time, BCLKX high to BDX valid Disable time, BDX high impedance following last data bit from BCLKX low Disable time, BDX high impedance following last data bit from BFSX high Delay time, BFSX low to BDX valid T-3 C-4 -4 C-2 MAX T+4 C+3 5 C+3 2P- 4 (5) 4P+ 2 (5) 6P + 17 (5) 8P + 17 (5) 6P + 2 (5) 10P + 17 (5) MIN SLAVE MAX ns ns ns ns ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. T = BCLKX period = (1 + CLKGDV) * 2P C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). P = 0.5 * processor clock
LSB MSB
BCLKX th(BCKXL-BFXL) BFSX tdis(BFXH-BDXHZ) tdis(BCKXL-BDXHZ) BDX Bit 0 tsu(BDRV-BCLXL) BDR Bit 0 Bit(n-1) Bit(n-1) td(BFXL-BDXV) td(BCKXH-BDXV) (n-2) th(BCKXL-BDRV) (n-2) (n-3) (n-4) (n-3) (n-4) td(BFXL-BCKXH)
Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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Table 5-26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
5409A-120 5409A-160 MASTER MIN MAX tsu(BDRV-BCKXL) th(BCKXH-BDRV) (1) (2) Setup time, BDR valid before BCLKX low Hold time, BDR valid after BCLKX high 12 4 SLAVE MIN 2- 6P (2) 5 + 12P (2) MAX ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = 0.5 * processor clock
Table 5-27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) (1)
5409A-120 5409A-160 PARAMETER MASTER (2) MIN th(BCKXL-BFXL) td(BFXL-BCKXH) td(BCKXL-BDXV) tdis(BCKXL-BDXHZ) td(BFXL-BDXV) (1) (2) (3) (4) (5) Hold time, BFSX low after BCLKX low (3) Delay time, BFSX low to BCLKX high (4) Delay time, BCLKX low to BDX valid Disable time, BDX high impedance following last data bit from BCLKX low Delay time, BFSX low to BDX valid C-3 T-4 -4 -2 D-2 MAX C+4 T+3 5 4 D+4 6P + 2 (5) 6P - 4 (5) 4P + 2 (5) 10P + 17 (5) 10P + 17 (5) 8P + 17 (5) MIN SLAVE MAX ns ns ns ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. T = BCLKX period = (1 + CLKGDV) * 2P C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). P = 0.5 * processor clock
LSB BCLKX th(BCKXL-BFXL) BFSX tdis(BCKXL-BDXHZ) BDX Bit 0 tsu(BDRV-BCKXL) BDR Bit 0 Bit(n-1) td(BFXL-BDXV) Bit(n-1) td(BCKXL-BDXV) (n-2) th(BCKXH-BDRV) (n-2) (n-3) (n-4) (n-3) (n-4) td(BFXL-BCKXH) MSB
Figure 5-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
Table 5-28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
5409A-120 5409A-160 MASTER MIN tsu(BDRV-BCKXH) th(BCKXH-BDRV) (1) (2) Setup time, BDR valid before BCLKX high Hold time, BDR valid after BCLKX high 12 4 MAX SLAVE MIN 2- 6P (2) 5 + 12P (2) MAX ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = 0.5 * processor clock
Table 5-29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) (1)
5409A-120 5409A-160 PARAMETER MASTER (2) MIN th(BCKXH-BFXL) td(BFXL-BCKXL) td(BCKXL-BDXV) tdis(BCKXH-BDXHZ) tdis(BFXH-BDXHZ) td(BFXL-BDXV) (1) (2) (3) (4) (5) Hold time, BFSX low after BCLKX high (3) Delay time, BFSX low to BCLKX low (4) Delay time, BCLKX low to BDX valid Disable time, BDX high impedance following last data bit from BCLKX high Disable time, BDX high impedance following last data bit from BFSX high Delay time, BFSX low to BDX valid T-3 D-4 -4 D-2 MAX T+4 D+3 5 D+3 2P - 4 (5) 4P + 2 (5) 6P + 17 (5) 8P + 17 (5) 6P + 2 (5) 10P + 17 (5) MIN SLAVE MAX ns ns ns ns ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. T = BCLKX period = (1 + CLKGDV) * 2P D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). P = 0.5 * processor clock
LSB MSB
BCLKX th(BCKXH-BFXL) BFSX tdis(BFXH-BDXHZ) tdis(BCKXH-BDXHZ) BDX Bit 0 tsu(BDRV-BCKXH) BDR Bit 0 Bit(n-1) Bit(n-1) td(BFXL-BDXV) td(BCKXL-BDXV) (n-2) th(BCKXH-BDRV) (n-2) (n-3) (n-4) (n-3) (n-4) td(BFXL-BCKXL)
Figure 5-26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Electrical Specifications
83
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
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Table 5-30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
5409A-120 5409A-160 MASTER MIN MAX tsu(BDRV-BCKXL) th(BCKXL-BDRV) (1) (2) Setup time, BDR valid before BCLKX low Hold time, BDR valid after BCLKX low 12 4 2- SLAVE MIN 6P (2) 5 + 12P (2) MAX ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = 0.5 * processor clock
Table 5-31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
5409A-120 5409A-160 PARAMETER MASTER (2) MIN th(BCKXH-BFXL) td(BFXL-BCKXL) td(BCKXH-BDXV) tdis(BCKXH-BDXHZ) td(BFXL-BDXV) (1) (2) (3) (4) (5) Hold time, BFSX low after BCLKX high (3) Delay time, BFSX low to BCLKX low (4) Delay time, BCLKX high to BDX valid Disable time, BDX high impedance following last data bit from BCLKX high Delay time, BFSX low to BDX valid D-3 T-4 -4 -2 C-2 MAX D+4 T+3 5 4 C+4 6P + 2 (5) 6P - 4 (5) 4P + 2 (5) 10P + 17 (5) 10P + 17 (5) 8P + 17 (5) MIN SLAVE MAX ns ns ns ns ns UNIT
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. T = BCLKX period = (1 + CLKGDV) * 2P C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). P = 0.5 * processor clock
LSB BCLKX th(BCKXH-BFXL) BFSX tdis(BCKXH-BDXHZ) BDX Bit 0 tsu(BDRV-BCKXL) BDR Bit 0 Bit(n-1) td(BFXL-BDXV) Bit(n-1) td(BCKXH-BDXV) (n-2) th(BCKXL-BDRV) (n-2) (n-3) (n-4) (n-3) (n-4) td(BFXL-BCKXL) MSB
Figure 5-27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
84
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.15 5.15.1
Host-Port Interface Timing HPI8 Mode
Table 5-32 and Table 5-33 assume testing over recommended operating conditions and P = 0.5 * processor clock (see Figure 5-28 through Figure 5-31). In the following tables, DS refers to the logical OR of HCS, HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1, and HR/W.
Table 5-32. HPI8 Mode Timing Requirements
5409A-120 5409A-160 MIN tsu(HBV-DSL) th(DSL-HBV) tsu(HSL-DSL) tw(DSL) tw(DSH) tsu(HDV-DSH) th(DSH-HDV)W tsu(GPIO-COH) th(GPIO-COH) Setup time, HBIL valid before DS low (when HAS is not used), or HBIL valid before HAS low Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low Setup time, HAS low before DS low Pulse duration, DS low Pulse duration, DS high Setup time, HD valid before DS high, HPI write Hold time, HD valid after DS high, HPI write Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input 6 3 8 13 7 3 2 3 0 MAX ns ns ns ns ns ns ns ns ns
UNIT
Electrical Specifications
85
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
www.ti.com
Table 5-33. HPI8 Mode Switching Characteristics
5409A-120 5409A-160 MIN ten(DSL-HD) Enable time, HD driven from DS low Case 1a: Memory accesses when DMAC is active and tw(DSH) < I8H (1) Case 1b: Memory accesses when DMAC is active and tw(DSH) I8H (1) Case 2a: Memory accesses when DMAC is inactive and tw(DSH) < 10H (1) Case 2b: Memory accesses when DMAC is inactive and tw(DSH) 10H (1) Case 3: Register accesses td(DSL-HDV2) th(DSH-HDV)R tv(HYH-HDV) td(DSH-HYL) Delay time, DS low to HD valid for second byte of an HPI read Hold time, HD valid after DS high, for a HPI read Valid time, HD valid after HRDY high Delay time, DS high to HRDY low (2) Case 1: Memory accesses when DMAC is active (1) td(DSH-HYH) Delay time, DS high to HRDY high (2) Case 2: Memory accesses when DMAC is inactive (1) Case 3: Write accesses to HPIC td(HCS-HRDY) td(COH-HYH) td(COH-HTX) td(COH-GPIO) (1) (2) (3) Delay time, HCS low/high to HRDY low/high Delay time, CLKOUT high to HRDY high Delay time, CLKOUT high to HINT change Delay time, CLKOUT high to HDx output change. HDx is configured as a general-purpose output register (3) 0 2 8 18P+6 10P+6 6P+6 6 9 6 5 ns ns ns ns ns 0 MAX 10 18P+10-tw(DSH) 10 10P+10-tw(DSH) 10 10 10 ns ns ns ns ns ns
PARAMETER
UNIT
td(DSL-HDV1)
Delay time, DS low to HD valid for first byte of an HPI read
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are affected by DMAC activity. The HRDY output is always high when the HCS input is high, regardless of DS timings. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.
86
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
Second Byte HAS tsu(HBV-DSL)
First Byte
Second Byte
tsu(HSL-DSL) th(DSL-HBV) Valid Valid
HAD(A) tsu(HBV-DSL)(B)
th(DSL-HBV)(B) HBIL
HCS tw(DSH) tw(DSL) HDS td(DSH-HYH) td(DSH-HYL) HRDY ten(DSL-HD) td(DSL-HDV2) th(DSH-HDV)R HD READ Valid td(DSL-HDV1) Valid Valid
tsu(HDV-DSH) th(DSH-HDV)W HD WRITE Valid
tv(HYH-HDV)
Valid
Valid
td(COH-HYH) Processor CLK
A. B.
HAD refers to HCNTL0, HCNTL1, and HR/W. When HAS is not used (HAS always high)
Figure 5-28. HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low)
Electrical Specifications
87
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
www.ti.com
HCS
HDS td(HCS-HRDY) HRDY
Figure 5-29. HPI-8 Mode Timing, Using HCS to Control Accesses
CLKOUT
td(COH-HTX)
HINT
Figure 5-30. HPI-8 Mode, HINT Timing
CLKOUT tsu(GPIO-COH) th(GPIO-COH) GPIOx Input Mode(A) td(COH-GPIO) GPIOx Output Mode(A)
A.
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
Figure 5-31. GPIOx(A) Timings
88
Electrical Specifications
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TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
5.15.2
HPI16 Mode
Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P = 0.5 * processor clock (see Figure 5-32 through Figure 5-34). In the following tables, DS refers to the logical OR of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,Volume 5: Enhanced Peripherals (literature number SPRU302) for addition information.
Table 5-34. HPI16 Mode Timing Requirements
5409A-120 5409A-160 MIN tsu(HBV-DSL) th(DSL-HBV) tsu(HAV-DSH) tsu(HAV-DSL) th(DSH-HAV) tw(DSL) tw(DSH) Setup time, HR/W valid before DS falling edge Hold time, HR/W valid after DS falling edge Setup time, address valid before DS rising edge (write) Setup time, address valid before DS falling edge (read) Hold time, address valid after DS rising edge Pulse duration, DS low Pulse duration, DS high Memory accesses with no DMA activity. tc(DSH-DSH) Cycle time, DS rising edge to next DS rising edge Memory accesses with 16-bit DMA activity. Memory accesses with 32-bit DMA activity. tsu(HDV-DSH)W th(DSH-HDV)W Setup time, HD valid before DS rising edge Hold time, HD valid after DS rising edge, write Reads Writes Reads Writes Reads Writes 6 5 5 -(4P - 6) 1 30 10 10P + 30 10P + 10 16P + 30 16P + 10 24P + 30 24P + 10 8 2 ns ns ns MAX ns ns ns ns ns ns ns
UNIT
Electrical Specifications
89
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
www.ti.com
Table 5-35. HPI16 Mode Switching Characteristics
5409A-120 5409A-160 MIN td(DSL-HDD) Delay time, DS low to HD driven Case 1a: Memory accesses initiated immediately following a write when DMAC is active in 16-bit mode and tw(DSH) was < 18H Case 1b: Memory accesses not immediately following a write when DMAC is active in 16-bit mode Delay time, DS low to HD valid for first word of an HPI read Case 1c: Memory accesses initiated immediately following a write when DMAC is active in 32-bit mode and tw(DSH) was < 26H Case 1d: Memory access not immediately following a write when DMAC is active in 32-bit mode Case 2a: Memory accesses initiated immediately following a write when DMAC is inactive and tw(DSH) was < 10H Case 2b: Memory accesses not immediately following a write when DMAC is inactive td(DSH-HYH) tv(HYH-HDV) th(DSH-HDV)R td(COH-HYH) td(DSL-HYL) td(DSH-HYL) Memory writes when no DMA is active Delay time, DS high to Memory writes with one or more 16-bit DMA channels active HRDY high Memory writes with one or more 32-bit DMA channels active Valid time, HD valid after HRDY high Hold time, HD valid after DS rising edge, read Delay time, CLKOUT rising edge to HRDY high Delay time, DS low to HRDY low Delay time, DS high to HRDY low 1 0 MAX 10 32P + 20 - tw(DSH) 16P + 20 48P + 20 - tw(DSH) 24P + 20 20P + 20 - tw(DSH) 10P + 20 10P + 5 16P + 5 24P + 5 7 6 5 12 12 ns ns ns ns ns ns ns
PARAMETER
UNIT
td(DSL-HDV1)
ns
90
Electrical Specifications
www.ti.com
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
HCS tw(DSH) tc(DSH-DSH) HDS tsu(HBV-DSL) tw(DSL) th(DSL-HBV)
tsu(HBV-DSL)
th(DSL-HBV) HR/W tsu(HAV-DSL) th(DSH-HAV) HA[15:0] Valid Address th(DSH-HDV)R td(DSL-HDV1) HD[15:0] td(DSL-HDD) tv(HYH-HDV) HRDY td(DSL-HYL) Data td(DSL-HDD)
Valid Address
td(DSL-HDV1) Data tv(HYH-HDV)
th(DSH-HDV)R
td(DSL-HYL)
Figure 5-32. HPI-16 Mode, Nonmultiplexed Read Timings
HCS tw(DSH) tc(DSH-DSH) HDS tsu(HBV-DSL) th(DSL-HBV) HR/W tsu(HAV-DSH) th(DSH-HAV) HA[15:0] Valid Address tsu(HDV-DSH)W th(DSH-HDV)W HD[15:0] Data Valid td(DSH-HYH) HRDY td(DSH-HYL) Data Valid tsu(HDV-DSH)W th(DSH-HDV)W Valid Address tw(DSL) tsu(HBV-DSL) th(DSL-HBV)
Figure 5-33. HPI-16 Mode, Nonmultiplexed Write Timings
Electrical Specifications 91
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
www.ti.com
HRDY td(COH-HYH) CLKOUT
Figure 5-34. HPI-16 Mode, HRDY Relative to CLKOUT
92
Electrical Specifications
www.ti.com
TMS320VC5409A Fixed-PointDigital Signal Processor
SPRS140F - NOVEMBER 2000 - REVISED JANUARY 2005
6
Mechanical Data
The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s).
6.1
Package Thermal Resistance Characteristics
Table 6-1 provides the estimated thermal resistance characteristics for the recommended package types used on the device.
Table 6-1. Thermal Resistance Characteristics
PARAMETER RJA RJC GGU PACKAGE 38 5 PGE PACKAGE 56 5 UNIT C/W C/W
Mechanical Data
93
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2005
PACKAGING INFORMATION
Orderable Device TMS320VC5409AGGU12 TMS320VC5409AGGU16 TMS320VC5409APGE12 TMS320VC5409APGE16 TMS320VC5409AZGU12 TMS320VC5409AZGU16 TMSDVC5409APGE16G4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type BGA BGA LQFP LQFP BGA BGA LQFP
Package Drawing GGU GGU PGE PGE ZGU ZGU PGE
Pins Package Eco Plan (2) Qty 144 144 144 144 144 144 144 160 160 60 60 160 160 60 TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish SNPB SNPB CU NIPDAU CU NIPDAU SNAGCU SNAGCU CU NIPDAU
MSL Peak Temp (3) Level-3-220C-168HR Level-3-220C-168HR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-3-260C-168HR Level-3-260C-168HR Level-1-260C-UNLIM
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPBG021C - DECEMBER 1996 - REVISED MAY 2002
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
12,10 SQ 11,90 0,80
9,60 TYP
A1 Corner
N M L K J H G F E D C B A
1 2 3 4 5 6 7 8 9 10 11 12 13 Bottom View 0,95 0,85 1,40 MAX
Seating Plane 0,55 0,45 0,08 0,10
0,45 0,35
4073221-2/C 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGAt configuration
MicroStar BGA is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
0,80 1
MECHANICAL DATA
MTQF017A - OCTOBER 1994 - REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72 0,27 0,17 0,08 M
0,50
144
37
0,13 NOM
1 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80
36 Gage Plane
0,05 MIN
0,25 0- 7
1,45 1,35
0,75 0,45
Seating Plane 1,60 MAX 0,08
4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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