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INTEGRATED CIRCUITS
DATA SHEET
SAA8117HL Digital camera USB interface IC
Product specification File under Integrated Circuits, IC22 1999 Apr 02
Philips Semiconductors
Product specification
Digital camera USB interface IC
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 10 11 12 13 14 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Video synchronization CIF formatter Compression engine Transfer buffer SNERT interface Sensor pulse generator Pulse diagrams USB video FIFO PSIE-MMU, I2C-bus interface and USB RAM space ATX and external ATX interface Audio Power management CONTROL REGISTER DESCRIPTION SNERT (UART) I2C-bus interface Commands End-points Control top registers Video FIFO registers ADIF top registers LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING APPLICATION INFORMATION 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 PACKAGE OUTLINE SOLDERING
SAA8117HL
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1999 Apr 02
2
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
1
FEATURES
2
APPLICATIONS
* Medium resolution CCD sensors (PAL non-interlaced mode) or VGA CCD sensors (progressive mode) * D1 digital video input (8 bits YUV 4 : 2 : 2, time multiplexed) * Internal Pulse Pattern Generator (PPG) dedicated for medium resolution Sharp or compatible sensors and VGA sensors and for frame rate selection * Video formatter (programmable CIF formatter and compression engine) controlled via SNERT (UART) interface * Selectable output frame rate (1 fps in VGA, up to 15 fps in CIF format) * Video packetizer FIFO * I2C-bus interface for communication between the USB protocol hardware and the external microcontroller * Integrated analog bus driver (ATX) * Microphone/audio input to USB (FGA, ADC, PLL and decimator filter) * Integrated analog bus driver (ATX) * Integrated main oscillator * Miscellaneous functions e.g. power management, PLL backup oscillator. 4 ORDERING INFORMATION TYPE NUMBER SAA8117HL
* Low-cost desktop video applications with USB interface. 3 GENERAL DESCRIPTION
The SAA8117HL is a monolithic integrated circuit which can be used in PC video cameras to convert D1 video signals and analog audio signals to properly formatted USB packets. It is designed as a back-end for the SAA8110G or SAA8112HL (general camera digital processing ICs) and is optimized for use with the TDA8784/87 (camera pre-processing IC) and the 83C51RC (microcontroller).
PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm VERSION SOT407-1
1999 Apr 02
3
Philips Semiconductors
Product specification
Digital camera USB interface IC
5 QUICK REFERENCE DATA Measured over full voltage and operating temperature range. SYMBOL VDDD VDDA IDD(tot) Vi(bus) Vo(bus) Vi(n) Vo(n) fclk Ptot Tstg Tamb Tj PARAMETER digital supply voltage analog supply voltage total supply current input voltage on I2C-bus interface pins 3.0 V < VDD < 3.6 V 3.0 V < VDD < 3.6 V Tamb = 25 C output voltage on I2C-bus interface pin SDA input signal voltage on other pins output signal voltage on other pins clock frequency total power dissipation storage temperature operating ambient temperature junction temperature Tamb = 70 C VDD = 3.3 V CONDITIONS MIN. 3.0 3.0 - TYP. 3.3 3.3 91
SAA8117HL
MAX. 3.6 3.6 -
UNIT V V mA
5 V tolerant TTL compatible V 5 V tolerant TTL compatible V low voltage TTL compatible V low voltage TTL compatible V - - -55 0 -40 48 300 - 25 - - - +150 70 +125 MHz mW C C C
1999 Apr 02
4
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1999 Apr 02
SMP 58 56 55 57 SNERT INTERFACE AND HATCH RESET 51 GENPOR 76 SNCL SNDA SNRES
6
Philips Semiconductors
Digital camera USB interface IC
BLOCK DIAGRAM
SNAPSHOT UCINT CLOCKON SUSREADYNOT SCL SDA 94 95 CLOCK UCPOR 93 64 77 TRC 96 100 97 DCDCON 99 98
63 I2C-BUS INTERFACE POWER MANAGEMENT EXTERNAL ATX INTERFACE 65 66
SPEED SUSPEND VM VP RCV VMO VPO OEBAR ATXCTRL ATXDP ATXDM VDD1 to VDD3 VDDA1 to VDDA4 VDDD1 to VDDD4 GND1 to GND4 AGND1 to AGND5 DGND1 to DGND5
SAA8117HL
USB RAM SPACE
67 68 71 72 73
RESERVED2 RESERVED1
53 52 35, 36, 37, 38, 42, 43 44, 45
YUV0 to YUV7
CIF FORMATTER
COMPRESSION ENGINE
TRANSFER BUFFER
USB VIDEO FIFO
PSIE MMU
74 60
5
HREF VSYNC LLC 49 50 47 VIDEO SYNCHRONISATION AUDIO ADC 32, 25, 15 85, 84, 62, 7 70, 48, 41, 39 PATTERN PULSE GENERATOR (PPG) MAIN OSCILLATOR AUDIO PLL AUDIO AMP I2S-BUS INTERFACE 54, 34, 26, 14 88, 80, 78, 59, 4 92, 75, 69, 46, 40 19, 18 13, 12 17, 16 11, 10 B1 to B4 A1 to A4 C1 to C3 23, 22, 21 24 20 RG 28 29 27 33 8 9 31 30 HD VD 5 XIN1 XOUT1 6 86 XIN2 XOUT2 87 79 MIC 89 WS DA 90 91 3, 2, 1 81, 82, 83 ATX 61
FCE130
SHP
CLK1
CLPDM
BCK
REF1 to REF3 M0 to M2
SHUTTER SHD
CLK2
CLPOB
SAA8117HL
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital camera USB interface IC
7 PINNING SYMBOL M2 M1 M0 AGND1 XIN1 XOUT1 VDDA1 CLPDM CLPOB B4 B3 B2 B1 GND1 VDD1 A4 A3 A2 A1 SHUTTER C3 C2 C1 RG VDD2 GND2 CLK1 SHP SHD VD HD VDD3 CLK2 GND3 YUV0 YUV1 YUV2 YUV3 VDDD1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 TYPE I I I P I O P O O O O O O P P O O O O O O O O O P P O O O O O P O P I I I I P test mode control signal bit 2 test mode control signal bit 1 test mode control signal bit 0 analog ground 1 for main oscillator (48 MHz, 3rd overtone) oscillator input oscillator output DESCRIPTION
SAA8117HL
analog supply voltage 1 for main oscillator (48 MHz, 3rd overtone) dummy clamp pulse output to TDA8784/87 optical black clamp pulse output to TDA8784/87 vertical CCD load pulse output (VH1X) vertical CCD load pulse output (VH3X) vertical CCD load pulse output vertical CCD load pulse output ground 1 for output buffers supply voltage 1 for output buffers vertical CCD transfer pulse output (V4X) vertical CCD transfer pulse output (V3X) vertical CCD transfer pulse output (V2X) vertical CCD transfer pulse output (V1X) shutter control output for CCD charge reset horizontal CCD transfer pulse output horizontal CCD transfer pulse output (FH1) horizontal CCD transfer pulse output (FH2) reset output for CCD output amplifier gate supply voltage 2 for output buffers ground 2 for output buffers pixel clock output to TDA8784/87and SAA8110G preset sample-and-hold pulse output to TDA8784/87 (FCDS) data sample-and-hold pulse output to TDA8784/87 (FS) vertical definition pulse output to SAA8110G horizontal definition pulse output to SAA8110G supply voltage 3 for output buffers double pixel clock output to SAA8110G ground 3 for output buffers multiplexed input YUV-bit 0 (LSB) multiplexed input YUV-bit 1 input multiplexed input YUV-bit 2 input multiplexed input YUV-bit 3 input digital supply voltage 1 for input buffers and predrivers and one part of the digital core 6
1999 Apr 02
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL DGND1 VDDD2 YUV4 YUV5 YUV6 YUV7 DGND2 LLC VDDD3 HREF VSYNC RESET RESERVED1 RESERVED2 GND4 SNDA SNCL SNRES SMP AGND2 ATXDP ATXDM VDDA2 SPEED UCINT SUSPEND VM VP RCV DGND3 VDDD4 VMO VPO OEBAR ATXCTRL DGND4 GENPOR
PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
TYPE P P I I I I P I P I I I - - P I/O I O O P I/O I/O P O O O O O I P P I I O I P I
DESCRIPTION digital ground 1 for input buffers and predrivers and for the digital core digital supply voltage 2 for digital core multiplexed input YUV-bit 4 multiplexed input YUV-bit 5 multiplexed input YUV-bit 6 multiplexed input YUV-bit 7 digital ground 2 for input buffers and predrivers and for the digital core line-locked clock input (delayed CLK2) for YUV-port from SAA8110G digital supply voltage 3 for digital core horizontal reference input for YUV-port from SAA8110G vertical synchronization input for YUV-port from SAA8110G Power-on reset input (for video processing and PPG) test pin (should not be used) test pin (should not be used) ground 4 for output buffer data I/O for SNERT-interface (communication between SAA8117HL and SAA8110G) input clock for SNERT-interface (communication between SAA8117HL and SAA8110G) output reset for SNERT-interface (communication between SAA8117HL and SAA8110G) output switch mode pulse for DC-to-DC power supply analog ground 2 for ATX (transceiver) positive driver of the differential data pair input/output (ATX) negative driver of the differently data pair input/output (ATX) analog supply voltage 2 for ATX required output for ATX-backup solution interrupt output from USB protocol hardware to microcontroller control output from USB protocol hardware to microcontroller required output for ATX-backup solution (txdn) required output for ATX-backup solution (txdp) required output for ATX-backup solution digital ground 3 for input buffers and predrivers and for the digital core digital supply voltage 4 for one part of input buffers and predrivers and for the digital core required input or ATX-backup solution (rxdn) required input for ATX-backup solution (rxdp) required output for ATX-backup solution required input for ATX-backup solution digital ground 4 for input buffers and predrivers and for the digital core Power-on reset input (for USB protocol hardware)
1999 Apr 02
7
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL UCPOR AGND3 MIC AGND4 REF1 REF2 REF3 VDDA3 VDDA4 XIN2 XOUT2 AGND5 WS DA BCK DGND5 CLOCK SCL SDA CLOCKON SNAPSHOT DCDCON SUSREADYNOT TRC
PIN 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
TYPE O P I P I I I P P I O P I I I P O I I/O O I O I I analog ground 3 for FGA microphone input analog ground 4 for FGA/ADC
DESCRIPTION output control from USB protocol hardware to microcontroller
reference input voltage 1 for FGA/ADC (double-bonding) reference input voltage 2 for DACn (used in the ADC) reference input voltage 3 for DACp (used in the ADC) analog supply voltage 3 for FGA/ADC analog supply voltage 4 for PLL oscillator input required for PLL backup solution oscillator output required for PLL backup solution analog ground 5 for PLL I2S-bus word select (required for FGA/ADC backup solution) I2S-bus data (required for FGA/ADC backup solution) I2S-bus clock (required for FGA/ADC backup solution) digital ground 5 for input buffers and predrivers and for the digital core clock output from USB protocol hardware to microcontroller slave I2C-bus clock input slave I2C-bus data input/output control output for main oscillator switched on input for remote wake-up (snapshot) control output from USB protocol hardware to power supply module input from microcontroller for SUSPEND mode threshold control input for enabling the clock (switching for power management)
1999 Apr 02
8
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
handbook, full pagewidth
99 SUSREADYNOT
97 SNAPSHOT
96 CLOCKON
98 DCDCON
100 TRC
76 GENPOR 75 DGND4 74 ATXCTRL 73 OEBAR 72 VPO 71 VMO 70 VDDD4 69 DGND3 68 RCV 67 VP 66 VM 65 SUSPEND 64 UCINT 63 SPEED 62 VDDA2 61 ATXDM 60 ATXDP 59 AGND2 58 SMP 57 SNRES 56 SNCL 55 SNDA 54 GND4 53 RESERVED2 52 RESERVED1 51 RESET VSYNC 50
M2 M1 M0 AGND1 XIN1 XOUT1 VDDA1 CLPDM CLPOB
1 2 3 4 5 6 7 8 9
B4 10 B3 11 B2 12 B1 13 GND1 14 VDD1 15 A4 16 A3 17 A2 18 A1 19 SHUTTER 20 C3 21 C2 22 C1 23 RG 24 VDD2 25 GND2 26 CLK1 27 SHP 28 SHD 29 VD 30 HD 31 VDD3 32 CLK2 33 GND3 34 YUV0 35 YUV1 36 YUV2 37 YUV3 38 VDDD1 39 DGND1 40 VDDD2 41 YUV4 42 YUV5 43 YUV6 44 YUV7 45 DGND2 46 LLC 47 VDDD3 48 HREF 49
SAA8117HL
77 UCPOR
92 DGND5
93 CLOCK
88 AGND5
80 AGND4
78 AGND3
85 VDDD4
87 XOUT2
84 VDDA3 83 REF3
82 REF2
81 REF1
86 XIN2
95 SDA
91 BCK
94 SCL
79 MIC
89 WS
90 DA
FCE131
Fig.2 Pin configuration.
1999 Apr 02
9
Philips Semiconductors
Product specification
Digital camera USB interface IC
8 8.1 FUNCTIONAL DESCRIPTION Video synchronization
SAA8117HL
This prefilter must be chosen by selecting prefilter B and setting SN_Prefilter_B_Comb. Prefilter B-comb can be used independently from prefilter A. The incoming 4 : 2 : 2 data is vertically filtered to 4 : 2 : 0 by throwing away colour samples. In the even lines the V-samples are discarded, in the odd lines the U-samples. The vertical scaling in PAL mode is from CIF (352 x 288) to QCIF (176 x 144) only. This is done via a vertical prefilter A (3 taps). In VGA mode a VPD-4 vertical filter is applied to scale from 640 x 480 to CIF and QCIF. From the QCIF image a sub-QCIF cut (128 x 96) can be made. Due to the granularity of the cropping origin, a UV interchange can occur. This interchange can be corrected with SN_EIRRAH. In VGA mode the CIF formatter can be bypassed to create a full resolution snapshot. The snapshot can be in 4 : 2 : 0 and in 4 : 2 : 2 format, selectable with SN_4 : 2 : 2. 8.3 Compression engine
The video synchronization module (see Fig.1) is capable of locking onto the video signal thereby implementing a horizontal gate signal HREF (HREF = HIGH when data is valid) and a VS signal indicating the start of a new video frame. This module expects, in the PAL mode, 288 active lines from a total of 292 lines and in the VGA mode, 480 active lines from a total of 486 lines. The module generates control signals for the CIF formatter. 8.2 CIF formatter
The video data must be progressive (or non-interlaced) and in 4 : 2 : 2 (UYVY) format. The CIF formatter module (see Figs 1 and 3) is programmable to perform down scaling from 512 x 288 (PAL mode) or 640 x 480 (VGA mode) to 352 x 288 or 176 x 144 without affecting the aspect ratio. The horizontal scaling is achieved with a Variable Phase Delay filter (VPD-4). To avoid aliasing, this module also contains a prefilter which has three modes: * Prefilter A (3 taps) * Prefilter B (7 taps) * Prefilter B-comb (13 taps). Prefilter B-comb is similar to prefilter B, but inserts extra taps with amplification 0.
The compression engine module (see Figs 1 and 3) works on CIF format only. The CIF data is compressed to a fixed number of bytes per frame. This number can be selected leading a compression factor of either 3 or 4. As a result the data stream of CIF 4 : 2 : 0 equals the data stream of QCIF 4 : 2 : 2 (3 times compression) or QCIF 4 : 2 : 0 (4 times compression). The algorithm is Philips proprietary. Real-time decoding can be done in software on any Pentium platform.
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SN_4:2:2 SN_EIRRAH SN_PAL_VGA SN_Prefilter A_On/Off SN_Output_Format_Select to transfer buffer
YUV0 to YUV7
PREFILTER A
PREFILTER B
DOWN SCALER
COMPRESSION ENGINE
SN_Prefilter B_On/Off SN_Prefilter B_Comb
SN_Compress SN_Compression_Ratio SN_Clk_Compress_On
FCE132
Fig.3 The CIF formatter and compression engine.
1999 Apr 02
10
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.4 Transfer buffer
SAA8117HL
It should be noted that in case of medium resolution Sharp or compatible sensors an external inverter driver is required to convert the 3 V pulses into a voltage suitable for the used CCD sensor. For the medium resolution Sharp CCD sensor driver, the name of the pins to which the PPG pulses must be connected are indicated between brackets in the SAA8117HL pinning list (pins C3, B1 and B2 are not used). For both type of sensors the PPG generates 8 different frame rates (see Table 6). The active video size is 512 x 288 for PAL and 640 x 480 for VGA. The total H x V size is 685 x 292 for PAL and 823 x 486 for VGA. It should be noted that additional HD pulses are added during the vertical blanking interval to reach a total of 312 lines in PAL mode and 525 lines in VGA mode as required by the SAA8110G. The following registers are associated with the PPG: * CONTROL17_0 * CONTROL17_2 * PPG_SHUTTERSPEED_0 * PPG_SHUTTERSPEED_1 * PPG_CLPOB_START_LSB * PPG_CLPOB_STOP_LSB * PPG_CLPDM_START_LSB * PPG_CLPDM_STOP_LSB * CLPMSB. 8.7 Pulse diagrams
The transfer buffer module (see Fig.1) ensures a smooth transfer of the data to the FIFO of the USB. Moreover the transfer buffer can insert in band synchronization words in the video data stream. This function can be switched on and off with SN_In band_Control in register CONTROL17_0. The synchronization words can only be used with non-compressed data streams and are formatted like 0x00 0xFF 0x79. The subscript denotes the number of bits and the frame counter is circular incrementing. The non-compressed data is formatted like: 4 : 2 : 0: ...., 4 : 2 : 2: ...., where C denotes U-data in the even lines (0, 2, 4, etc.) and V-data in the odd lines (1, 3, 5, etc.). 8.5 SNERT interface
In a USB camera the SAA8110G will operate on a clock frequency which depends on the actual frame rate. For the slowest frame rates, this frequency can be so low that the SNERT communication is no longer functional over the specified entire frequency range of the microcontroller. The microcontroller must adapt its SNERT bus frequency to a frequency appropriate for the current mode in which the SAA8110G is operating. The SAA8117HL itself is also partly controlled via SNERT. The CIF formatter, compression engine and the PPG function are controlled via SNERT. This SNERT interface works independently from the frame rate and can always be operated in the full frequency range. 8.6 Sensor pulse generator
For medium resolution CCD sensors (PAL): * High-speed pulses, see Figs 4 and 5 * Horizontal pulses, see Fig.6 * Vertical pulses, see Figs 7 to 11. For VGA-sensors: * High-speed pulses, see Figs 12 to 14 * Horizontal pulses, see Fig.15 * Vertical pulses, see Figs 16 to 21.
The SAA8117HL incorporates a Pulse Pattern Generator (PPG) function. The PPG can be used for PAL medium resolution Sharp sensors (LZ2423) or compatible CCD sensors. The SAA8117HL can also handle VGA type CCD sensors, so a set of pulses is provided to simplify the use of such sensors. Depending on the type of sensor, it will be necessary to reformat these pulses externally according to the sensor specification.
1999 Apr 02
11
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CCD OUTPUT 0123456789 CLOCK ENABLE 01234567890 C1 (FH1) C2 (FH2)
Philips Semiconductors
handbook, full pagewidth
Digital camera USB interface IC
901234567890123456789
12
RG (FR) SHD (FS) SHP(FCDS) CLK1 CLK2
FCE133
SAA8117HL
Product specification
mode 0: 1/(4.8 MHz)
Fig.4 High-speed pulses for PAL medium resolution (1).
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CCD OUTPUT 0 CLOCK ENABLE 1 2 3 0 1 2 3 0 C1 (FH1) C2 (FH2) RG (FR)
Philips Semiconductors
handbook, full pagewidth
Digital camera USB interface IC
3
0
1
2
3
0
1
2
3
13
SHD (FS)
SHP (FCDS)
CLK1
CLK2
FCE134
mode 1: 1/(4 MHz) mode 2: 1/(3 MHz) mode 3: 1/(2.4 MHz) mode 4: 1/(2 MHz) mode 5: 1/(1.5 MHz) mode 6: 1/(1 MHz) mode 7: 1/(750 kHz)
SAA8117HL
Product specification
Fig.5 High-speed pulses for PAL medium resolution (2).
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683 685/0 4 12 16 22
Philips Semiconductors
100 BLK 101 BLK 102 A1 103 A2
612 A511 613 A512
614 BLK
619 BLK
636 BLK
641 BLK
642 643
1 HD
4
74
15 CLOCK ENABLE
91
(1)
(1)
CLPOB
(1) (1)
CLPDM 64 SHUTTER (OFDX) 29 A1 (V1X) 39 A2 (V2X) 24 A3 (V3X) 34 A4 (V4X) 64 54 59 49 72
FCE135
685/0
680
91
99
0
2
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Digital camera USB interface IC
14
SAA8117HL
Product specification
(1) CLPOB and CLPDM are programmable.
Fig.6 Horizontal pulses for PAL medium resolution.
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1999 Apr 02
A285 INE# 289 A286 290 A287 291 A288 292 Hd 1 HD VD CLPOB (DCP) CLPDM (BCP) B4 (VH1X)
Philips Semiconductors
Digital camera USB interface IC
Hd 2
AL1 3
AL2 4
A1 5
A2 6
15
B3 (VH3X)
SHUTTER (OFDX)
A1 (V1X)
A2 (V2X)
A3 (V3X)
A4 (V4X)
FCE136
SAA8117HL
Product specification
Fig.7 Vertical pulses for PAL medium resolution (1).
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INE# 292 1 4 HD 64 72 SHUTTER (OFDX) B4 (VH1X) 29 49 39 59 24 54 34 64
Philips Semiconductors
B3 (VH3X) 29 49
A1 (V1X) 39 59
A2 (V2X) 24 54
A3 (V3X) 34 64
A4 (V4X)
FCE137
1 4
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Digital camera USB interface IC
1
2
16
SAA8117HL
Product specification
Fig.8 Vertical pulses for PAL medium resolution (2).
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INE# 1 1 4 HD 545 553 64 72 SHUTTER (OFDX) RESET_DATA [9 to 0] B4 (VH1X) 599 614 29 49 39 59 24 54 34 64
Philips Semiconductors
2
647 651 655 659 663 667 671 675 679 683 1 4
RESET_DATA [9 to 0] + 8 584 599
B3 (VH3X) 664 684 29 49
A1 (V1X) 554 644 674 39 9 59
A2 (V2X) 559 24 54 4
A3 (V3X) 669 14 34 64
A4 (V4X)
FCE138
1 4
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Digital camera USB interface IC
3
17 Fig.9 Vertical pulses for PAL medium resolution (3).
SAA8117HL
Product specification
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INE# 2 1 4 HD 64 72 SHUTTER (OFDX) B4 (VH1X) 664 684 29 49 674 59 39 A2 (V2X) 24 54 24 54 4 A3 (V3X) 669 14 34 64 34 64 A4 (V4X)
FCE139
Philips Semiconductors
567 571 575 579 583 587 591 595 599 603 607 611 615 619 623 627 631 635 639 643 647 651 655 659 663 667 671 675 679 683 1 4
3
B3 (VH3X) 29 49
A1 (V1X) 39 9 59
1 4
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Digital camera USB interface IC
4
18
SAA8117HL
Product specification
Fig.10 Vertical pulses for PAL medium resolution (4).
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INE# 3 1 4 HD 64 72 64 72 SHUTTER (OFDX) B4 (VH1X) 29 49 39 59 24 54 34 64
Philips Semiconductors
4
B3 (VH3X) 29 49
A1 (V1X) 39 59
A2 (V2X) 24 54
A3 (V3X) 34 64
A4 (V4X)
FCE140
1 4
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Digital camera USB interface IC
5
19
SAA8117HL
Product specification
Fig.11 Vertical pulses for PAL medium resolution (5).
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CCD OUTPUT 0 CLOCK ENABLE 1 2 3 4 0 1 2 3 4 0 C1 C2 C3
Philips Semiconductors
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Digital camera USB interface IC
4
0
1
2
3
4
0
1
2
3
4
20
RG SHD SHP CLK1 CLK2
FCE141
SAA8117HL
Product specification
mode 0: 1/(9.6 MHz)
Fig.12 High-speed pulses for VGA sensors (1).
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1999 Apr 02
CCD OUTPUT 0123450123450123450 CLOCK ENABLE C1 C2 C3
Philips Semiconductors
Digital camera USB interface IC
5012345012345012345
21
RG
SHD
SHP
CLK1
CLK2 mode 1: 1/(8 MHz) mode 3: 1/(4 MHz)
FCE142
SAA8117HL
Product specification
Fig.13 High-speed pulses for VGA sensors (2).
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1999 Apr 02
CCD OUTPUT 01234567012345670 CLOCK ENABLE C1 C2 C3 RG
Philips Semiconductors
Digital camera USB interface IC
70123456701234567
22
SHD SHP CLK1 CLK2
FCE143
mode 2: 1/(6 MHz) mode 4: 1/(3 MHz) mode 5: 1/(2 MHz) mode 6: 1/(1.5 MHz) mode 7: 1/(1 MHz)
SAA8117HL
Product specification
Fig.14 High-speed pulses for VGA sensors (3).
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728 A656
732 BLK
731 A659
766 BLK 767
65 D
70 D
73 A1
79 A7
821 823/0
751 HD 15 CLOCK ENABLE
(1)
755
63
(1)
CLPOB
(1) (1)
CLPDM 2 SHUTTER
FCE144
22
2 A1 2 A2
22
22
A3
A4 25 28 B1 27 30 B2 24 B3 26 B4 (1) CLPOB and CLPDM are programmable. 31 29
823/0
4
771
818
60
12
36
64
2
1999 Apr 02 23
Philips Semiconductors
Digital camera USB interface IC
71 BLK 72 BLK
SAA8117HL
Product specification
Fig.15 Horizontal pulses for VGA sensors.
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1999 Apr 02
INE# HD VD CLPOB CLPDM SHUTTER A1
Philips Semiconductors
Digital camera USB interface IC
A476 482 483 485
A480 486
Hd 1
Hd 2
Hd 3
Hd 4
AL1 5
AL2 6
A1 7
24
A2 A3 A4 B1 B2 B3 B4
FCE145
SAA8117HL
Product specification
Fig.16 Vertical pulses for VGA sensors (1).
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HD
22
751 755
SHUTTER 22 2
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20 RESET_DATA [9 to 0] + 20 22 2 22 2
A1 22 2
RESET_DATA [9 to 0]
A2
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
A3
A4 25 28 25 28
B1 27 30 27 30
B2 24 29 24 29
B3 26 31 26 31
B4
22
2
2
1999 Apr 02
INE# 486
Philips Semiconductors
Digital camera USB interface IC
1
2
25
SAA8117HL
Product specification
FCE146
Fig.17 Vertical pulses for VGA sensors (2).
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HD 779 799
SHUTTER 22 2
22
2
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20 RESET_DATA [9 to 0] + 20 779 799
A1 22 2
RESET_DATA [9 to 0]
A2
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
A3
A4 25 28 780 800
B1 27 30 780 800
B2 24 29
B3 26 31
779 799
751 755
1999 Apr 02
INE# 1
Philips Semiconductors
Digital camera USB interface IC
2
687 691 695 699 703 707 711 715 719 723 727 731 735 739 743 747 751 755
3
26
SAA8117HL
Product specification
B4
FCE147
Fig.18 Vertical pulses for VGA sensors (3).
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INE#
2
631 635 639 643 647 651 655 659 663 667 671 675 679 683 687 691 695 699 703 707 711 715 719 723 727 731 735 739 743 747 751 755
HD 22 2
SHUTTER 22 2
A1 22 2
A2
A3
A4 25 28
B1 27 30
B2 24 29
B3 26 31
751 755
1999 Apr 02 27
B4
Philips Semiconductors
Digital camera USB interface IC
3
4
SAA8117HL
Product specification
FCE148
Fig.19 Vertical pulses for VGA sensors (4).
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INE#
3
623 627 631 635 639 643 647 651 655 659 663 667 671 675 679 683 687 691 695 699 703 707 711 715 719 723 727 731 735 739 743 747 751 755
HD 22 22 2 2
SHUTTER 22 22 2 2
A1 22 22 2 2
A2
A3
A4 25 28 25 28
B1 27 30 27 30
B2 24 29 24 29
B3 26 31 26 31
751 755
1999 Apr 02 28
B4
Philips Semiconductors
Digital camera USB interface IC
4
5
SAA8117HL
Product specification
FCE149
Fig.20 Vertical pulses for VGA sensors (5).
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1999 Apr 02
1/(6 MHz) = 0.167 s INE# 0 1 2 3 489 490 491 A1 A2 A3 A4
Philips Semiconductors
Digital camera USB interface IC
492
493
494
518
519
520
521
522
29
B1
B2
B3
B4
FCE150
SAA8117HL
Product specification
Fig.21 Vertical pulses for VGA sensors (6).
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.8 USB video FIFO I2C-bus
SAA8117HL
Moreover the FIFO is enabled and disabled with I2C_Active. The write process to the FIFO is controlled by the transfer buffer and is not programmable. The read process is executed in the PSIE-MMU and is driven by the USB frame interval (1 ms). Every frame interval the PSIE-MMU tries to read I2C_Packet_Size bytes from the FIFO. This read process will not be started when a new video frame is stored in the FIFO and there are less than I2C_FIFO_Offset bytes written. The read process stops if the next bytes are of another video frame, or if the read-pointer overtakes the write-pointer. I2C_Read_Spacing determines the read rate. Its value can easily be determined with the formula: 2 12000 I C_Read_Spacing < --------------------------------------------2 I C_Packet_Size
The USB video FIFO is programmed via the (see Fig.22). The FIFO is designed to achieve three different packets containing video on the isochronous USB channel. Video data is contained in a chain of equally sized USB packets, except for the last packet of a video frame which is always smaller. The video frames can be separated from each other by one or more 0-length packets. For low frame rates (below 10 frames/s) there are always 0-length packets in the stream. The host can synchronize on the smaller packets for the high frame rates and on the 0-length packets for the low frame rates. For every mode the FIFO must be adjusted. There are three parameters to program the video FIFO: * I2C_Packet_Size: this value indicates the length of all packets with video data except for the last packet of a video frame * I2C_FIFO_Offset: this value indicates the number of data in the FIFO before a new packet is transmitted over the USB * I2C_Read_Spacing: this value indicates the number of 12 MHz clock cycles between read actions from the FIFO.
handbook, full pagewidth
data to PSIE-MMU data from transfer buffer read
write
FIFO read enable WRITE SYNC
I2C_FIFO_Offset I2C_Packet_Size I2C_Read_Spacing I2C_Active
FCE151
Ptr_to_start_Vframe
Fig.22 USB video FIFO.
1999 Apr 02
30
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.9 PSIE-MMU, I2C-bus interface and USB RAM space 8.10
SAA8117HL
ATX and external ATX interface
The Programmable Serial Interface Engine (PSIE) and Memory Management Unit (MMU) is the heart of the USB protocol hardware (see Fig.23). It formats the actual packets that are transferred to the USB and passes the incoming packets to the right end-point buffers. These buffers are allocated as part of the USB RAM space. The microcontroller communicates via the I2C-bus with the PSIE-MMU. The I2C-bus protocol distinguishes three register spaces. These spaces are addressed via different commands. The command is sent to the command address. Depending on the command it is sent to the PSIE-MMU and/or to the command interpreter which configures the (de-)mux to open the path to the right register space. Subsequent write/read to/from the data address store or retrieve data from the register space is selected by the command.
The SAA8117HL contains an analog bus driver, called the ATX. It incorporates a differential and two single-ended receivers and a differential transmitter. The interface to the bus consists of a differential data pair (ATXDM and ATXDP). The SAA8117HL contains also an interface to an external ATX as backup solution.
handbook, full pagewidth
PSIE-MMU REGISTER SPACE PI_Address + 0X to/from microcontroller (DE)MUX SET MODE REGISTER SPACE
I2C-BUS INTERFACE
PI_Address + 10
COMMAND INTERPRETER
NON USB AND VIDEO FIFO REGISTERS
FCE152
to PSIE-MMU
Fig.23 I2C-bus interface and register map.
1999 Apr 02
31
Philips Semiconductors
Product specification
Digital camera USB interface IC
8.11 Audio 8.12 Power management
SAA8117HL
The PLL converts the 48 MHz to 256fs (fs = audio sample frequency). There are three modes for the PLL to achieve the sample frequencies of 48, 44.1 or 32 kHz (see Table 1). In the Fixed Gain Amplifier (FGA) the microphone input is amplified by 20 dB. The bit stream ADC samples the audio signal. It runs at an oversample rate of 256 times the base sample rate. In the application, the bit stream can be converted to parallel 16-bit samples. This conversion is programmable with respect to the effective sample frequency (dropping sample results in a lower effective sample frequency) and sample resolution. As a result the effective sample rate can be determined. Table 1 ADC clock frequencies and sample frequencies DIVIDING NUMBER 1 2 4 8 11.2996 1 2 4 8 12.2880 1 2 4 8 Note 1. Not supported. SAMPLE ADC CLOCK FREQUENCY (MHz) (kHz) 32 16 8 note 1 44.1 22.05 11.025 5.5125 48 24 12 6 4.096 2.048 1.042 note 1 5.6448 2.8224 1.4112 0.7056 6.144 3.072 1.536 0.768
The USB requires the device to switch power states. The SAA8117HL contains a power management module since the device may not consume more than 500 A during the power state called SUSPEND. This requires that even the crystal oscillator must be switched off. The SAA8117HL is also not functional except for some logic that enables the IC to wake-up the camera. After wake-up of the SAA8117HL first the clock to the microcontroller is generated and thereafter an interrupt is generated to wake-up the controller. Therefore the clock of the microcontroller is generated by the SAA8117HL. The power management module also sets a flag in register I2C_SET_MODE_AND_READ. After a reset the microcontroller should check this register via the I2C-bus and find the cause of the wake-up. Different causes may require different start-up routines. The internal video processing core uses another VDDD domain which can be switched during SUSPEND. The PPG is switched off by setting SN_Resume and resetting SN_PAL_VGA. In non CIF modes the power consumption is reduced by resetting SN_Compress and SN_CLK_Compress_On. The SAA8117HL has the feature to independently wake-up from SUSPEND, but requires a signal from the microcontroller before going into SUSPEND (via the signal on pin SUSREADYNOT). Since the main oscillator of the SAA8117HL is switched off during SUSPEND precautions are needed to avoid undefined states when the clock is switched on. This is ensured via the pins CLOCKON and TRC. Pin CLOCKON goes HIGH as soon as the main oscillator is switched on. The oscillator will need some time to make a stable 48 MHz signal. However, the clock is only passed through to other parts of the SAA8117HL when the level on pin TRC reaches a certain threshold. The time needed to reach the threshold can be trimmed with an RC-circuit.
CLOCK (MHz) 8.1920
1999 Apr 02
32
Philips Semiconductors
Product specification
Digital camera USB interface IC
9 CONTROL REGISTER DESCRIPTION
SAA8117HL
This Chapter gives an overview of all registers. 9.1 SNERT (UART)
The following registers are accessible via SNERT (see Table 2). Table 2 SNERT write registers of the SAA8117HL NAME - - CONTROL17_0 CONTROL17_1 VP_SQCIF_OFFSET CONTROL17_2 PPG_SHUTTERSPEED_0 PPG_SHUTTERSPEED_1 PPG_CLPOB_START_LSB PPG_CLPOB_STOP_LSB PPG_CLPDM_START_LSB PPG_CLPDM_STOP_LSB CLPMSB reserved reserved various control bits various control bits vertical (MSN) and horizontal (LSN) offset for sub-QCIF mode various control bits bits of shutter speed 0 bits of shutter speed 1 LSB start position control for CLPOB pulse LSB stop position control for CLPOB pulse LSB start position control for CLPDM pulse LSB stop position control for CLPDM pulse MSBs of CLPOB_Start, CLPOB_Stop, CLPDM_Start and CLPDM_Stop FUNCTION - - see Table 3 see Table 5 nibble see Table 6 see Table 8 see Table 9 byte byte byte byte see Table 10 FORMAT
ADDRESS C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC
1999 Apr 02
33
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 3 7 X 6 Detailed description of SNERT register CONTROL17_0 (address 0xC2) 5 4 3 2 1 0 EIRRAH PARAMETER
SAA8117HL
exchanges the chrominance irregularities when needed; toggle the bit to ensure timing of chrominance signal; the value must be determined experimentally (can be different for different modes) Snapshot 1 0 1 0 1 0 1 transported in 4 : 2 : 2 format transported in 4 : 2 : 0 format Inband_Control in band synchronization words are inserted in the video data stream only active video data is transmitted over USB Compression_Ratio ratio is 4 times ratio is 3 times Compress compression is active; only to be used in case (for this register) bit 2 = 1 and bit 1 = 0 since compression functions are for CIF only; CIF format must be compressed unless the frame rate is 3.75 Hz compression module is switched off and power consumption is minimized for this module Output_Format_Select X X 1 0 see Table 4 PAL_VGA PAL sensor VGA sensor
0
Table 4 2 0 0 1 1 Note 1 0 1 0 1
Detailed description of bit 2 and bit 1 of SNERT register CONTROL17_0 OUTPUT_FORMAT_SELECT PARAMETER sub-QCIF QCIF CIF VGA; note 1 24 24 - - FRAME RATE WITH RESPECT TO OUTPUT FORMAT 20 20 - - 15 15 15 - 12 12 12 - 10 10 10 - 7.5 7.5 7.5 - 5 5 5 - 3.75 3.75 3.75 - - - - 0.9375
1. Only valid when a VGA sensor is applied. The VGA output is not compressed.
1999 Apr 02
34
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 5 7 X 6 X Detailed description of SNERT register CONTROL17_1 (address 0xC3) 5 X 4 X 1 0 1 0 1 0 1 0 Table 6 7 X 6 X 3 2 1 0 reserved CLK_Compress_On compression clock active compression module is brought to low power state Prefilter B_Comb PARAMETER
SAA8117HL
horizontal scaling factor exceeds 3 (only functioning if bit 1 is also set to logic 1); this bit switches prefilter B to 13 taps prefilter B is as described for bit 1 Prefilter B_On/Off horizontal scaling factor exceeds 2; the prefilter with 7 taps is switched on prefilter B is bypassed Prefilter A_On/Off prefilter A with 3 taps is on; must be set to logic 1 when bit 2 is set to logic 1 to obtain the overall wanted frequency response prefilter A is bypassed
Detailed description of SNERT register CONTROL17_2 (address 0xC5) 5 X 1 0 1 4 3 2 1 0 PIX_nr0 to PIX_nr2 3 LSBs of 10 bits pixel number for autoexposure control (7 LSBs in register 0xC6) Shutter_Update_Buffer update of the shutter speed is buffered no buffering (immediately destroying of the current video frame) Resume video processing and PPG are switched of; if a VGA sensor is selected the vertical transport pulses are not switched off but this must be done by selecting a PAL sensor (register 0xC2 bit 0) PGG pulses generated PPG_Mode_Frame_Rate X X X see Table 7 PARAMETER
0
1999 Apr 02
35
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 7 BIT 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 VGA 24 20 15 10 7.5 5 3.75 0.9375 Detailed description of bit 2 to bit 0 of SNERT register CONTROL17_2 PARAMETER OF PPG_MODE_FRAME_RATE PAL 24 20 15 12 10 7.5 5 3.75
SAA8117HL
Table 8 7 X X Table 9 7 X 6 X 6
Detailed description of SNERT register PPG_SHUTTERSPEED_0 (address 0xC6) 5 X 4 X 3 X 2 X 1 X 0 X PARAMETER 1 LSB of 9-bit line number (8 MSBs in register 0xC7) 7 MSBs of 10-bit pixel number (3 LSBs in register 0xC5)
Detailed description of SNERT register PPG_SHUTTERSPEED_1 (address 0xC7) 5 X 4 X 3 X 2 X 1 X 0 X PARAMETER 8 MSBs of 9-bit line number (LSB in register 0xC6)
Table 10 Detailed description of SNERT register CLPMSB (address0xCC) 7 X 6 X X X X X X X 5 4 3 2 1 0 PARAMETER 2 MSBs of CLPOB_Start (LSBs in register 0xC8) 2 MSBs of CLPOB_Stop (LSBs in register 0xC9) 2 MSBs of CLPDM_Start (LSBs in register 0xCA) 2 MSBs of CLPDM_Stop (LSBs in register 0xCB)
1999 Apr 02
36
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2 I2C-bus interface
SAA8117HL
The I2C-bus interface uses two addresses: * Command address for writing commands to the Memory Manager (MM) * Data address for writing/reading data to/from the Memory Manager (MM). The 6 MSBs of the two addresses are equal and are defined by the PI_address = 010111 (see Table 11). The LSBs of the addresses differentiate between the command address and the data address. When bit 1 is logic 1 the address is the command address (0x5E) and when bit 1 is logic 0 the address is one of the data addresses (0x5C or 0x5D). Table 11 I2C-bus addresses BIT ADDRESS 7 0 0 0 0 9.2.1 6 1 1 1 1 5 0 0 0 0 4 1 1 1 1 3 1 1 1 1 2 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0x5C: for writing data to the memory manager 0x5D: for reading data from the memory manager 0x5E: for writing commands 0x5F: not in use
COMMANDS
The commands listed in Table 12 must be sent to the I2C-bus address 0x5E. Table 12 I2C-bus USB command codes BIT FUNCTION 7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 6 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 select end-point read/write status initialize/read status information read/write register bank X 0 0 1 0 0 0 1 0 1 1 not used set non-USB register read/write data acknowledge setup set buffer empty set buffer full read interrupt register read current frame number send resume set status change bits set mode end-point number end-point number end-point number 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 address X 0 0 0 0 0 1 1 1 1 0 X 0 0 0 1 1 0 0 1 1 1
1999 Apr 02
37
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 13 Set mode and write register overview BYTE 1 2 3 SET MODE AND WRITE N1 timer; programmable timer for power management; counts 12 MHz cycles; must be bigger than number of cycles needed for the microcontroller to go in power-down state after pin SUSREADYNOT is made LOW N2 timer; programmable timer for power management; counts 12 MHz cycles; determines the time between when the microcontroller clock is switched off and the main clock is switched off PSIE-MMU control byte (see Table 14)
Table 14 Detailed description of PSIE-MMU control byte (byte 3) 7 X 6 X 5 X 1 4 3 2 1 0 reserved interrupt after isochronous audio transfer for each isochronous audio transfer an interrupt to the microcontroller will be generated; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8117HL no interrupts are given to the microcontroller interrupt after isochronous video transfer 1 for each isochronous video transfer an interrupt to the microcontroller will be generated; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8117HL no interrupts are given to the microcontroller audio end-point 1 0 audio end-point enabled; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8117HL audio end-point disabled; the PSIE-MMU will not react on in-tokens on the audio end-point video end-point 1 0 video end-point enabled; default set to logic 1 upon general Power-on reset and/or bus reset by the SAA8117HL video end-point disabled; the PSIE-MMU will not react on in-tokens on the video end-point error debug mode 1 interrupts are generated only in the event that the transfer is not successfully completed; the microcontroller can read data from the interrupt and status registers to see the cause of this error all successful USB transactions are reported to the microcontroller via an interrupt; default set to logic 0 upon general Power-on reset by the SAA8117HL PARAMETER
0
0
0
1999 Apr 02
38
Philips Semiconductors
Product specification
Digital camera USB interface IC
Table 15 Detailed description of PSI-MMU set mode and status byte 7 X 6 X 5 X 4 X 1 0 1 0 1 0 1 0 9.2.2 END-POINTS 3 2 1 0 reserved remote wake-up status flag remote wake-up when device is in SUSPEND mode no remote wake-up resume status flag bus resume by the host when device is in SUSPEND mode no bus resume bus reset status flag bus reset no bus reset power-up status flag general power up reset no power up reset PARAMETER
SAA8117HL
The SAA8117HL has 6 logical end-points which are listed in Table 16. Table 16 Mapping of logic to physical end-point numbers for used end-points END-POINT NAME Control end-point Control end-point Interrupt end-point Interrupt end-point Iso video end-point Iso video end-point LOGIC END-POINT 0 1 2 3 4 5 PHYSICAL END-POINT BUFFER SIZE OUT 8 8 8 8 96.0 35.1 0 2 - - - - IN 1 3 4 5 6 7
1999 Apr 02
39
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2.3 CONTROL TOP REGISTERS
SAA8117HL
The following registers can be written on I2C-bus address 1 after the command 0xE8 on I2C-bus address 0. Table 17 I2C-bus control top registers (base address 0x08) ADDRESS 0x08 0x09 0x0A 0x0B NAME CLKSHOP CONTROL RSTGEN AND_PLL CONTROL I/O MUX CONTROL POWER CONTROL ANALOG MODULES clock control reset control mux block control power-on analog modules control FUNCTION
Table 18 Detailed description of I2C-bus control top register CLKSHOP CONTROL (address 0x08) 7 1 0 0 0 1 1 0 1 0 1 X 1 0 1 0 1 0 X 6 5 4 3 2 1 0 select ADC clock source sel_ad: clock generated from ADC sel_pll: clock generated from PLL set clock dividers for ADC set_divide00: divided by 1 set_divide01: divided by 2 set_divide10: divided by 4 set_divide11: divided by 8 reserved disable 48 MHz clock dis_clk_48: disable 48 MHz clock enable clock disable receiver clock dis_clk_rec: disable receiver clock enable clock disable ADC clock dis_clk_ad: disable ADC clock enable clock reserved PARAMETER
1999 Apr 02
40
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 19 Detailed description of I2C-bus control top register RSTGEN AND PLL CONTROL (address 0x09) 7 0 0 1 1 6 0 1 0 1 X X 1 0 X 1 0 1 0 5 4 3 2 1 0 set PLL frequency fcode00: 256 x 44.1 kHz fcode01: 256 x 32 kHz fcode10: 256 x 48 kHz fcode11: 256 x 44.1 kHz reserved reset PSIE-MMU top module upc_rst_mmu: resetting the USB protocol block (called PSIE-MMU) during tests or in the event of errors no reset reserved reset ADIF top module upc_rst_adif: resetting the digital audio part during tests or in the event of errors no reset reset AGC module upc_rst_AGC: resetting the AGC control during tests or in the event of errors no reset PARAMETER
Table 20 Detailed description of I2C-bus control top register I/O MUX CONTROL (address 0x0A) 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X reserved PARAMETER
1999 Apr 02
41
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 21 Detailed description of I2C-bus control top register POWER CONTROL OF ANALOG MODULES (address 0x0B) 7 X 6 X 1 0 X 1 0 1 0 1 0 1 0 5 4 3 2 1 0 reserved power control PLL module upc_pll_off: PLL power off power on reserved power control ADC module left channel upc_adl_off: power off power on power control ADC module right channel upc_adr_off: power off power on power control AGC module left channel upc_AGCl_off: power off power on power control AGC module right channel upc_AGCr_off: power off power on PARAMETER
1999 Apr 02
42
Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2.4 VIDEO FIFO REGISTERS
SAA8117HL
Table 22 Overview of I2C-bus video FIFO registers (base address 0x04) ADDRESS 0x04 0x05 0x06 0x07 FIFO OFFSET FIFO ACTIVE AND FIFI OFFSET PACKET SIZE READ SPACING AND PACKET SIZE NAME FUNCTION 8 LSBs of the offset value FIFO active and 3 MSBs of the offset value 8 LSBs of packet size value read spacing and 2 MSBs of packet size value
Table 23 Detailed description of I2C-bus video FIFO register FIFO OFFSET (address0x04) 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 FIFO offset X mode_fifo_offset: sets the minimum contents of the FIFO that has to be reached, before a new video frame will be put on the USB bus. This value can be set between 0 and 2047. Total of 11 bits with 8 LSBs in this register and 3 MSBs in register 0x05. PARAMETER
Table 24 Detailed description of I2C-bus video FIFO register FIFO ACTIVE AND FIFI OFFSET (address 0x05) 7 1 0 X X X X X X X 6 5 4 3 2 1 0 FIFO active mode_active: FIFO is active and the contents of the other mode registers should not be updated by the microcontroller (maledictive) FIFO not active reserved FIFO offset 3 MSBs of the offset value; see also register 0x04 PARAMETER
Table 25 Detailed description of I2C-bus video FIFO register PACKET SIZE (address 0x06) 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 packet size X mode_packet_size: sets the packet size of the USB video channel. Packets can vary in size between 0 and 1023. Total of 10 bits with 8 LSBs in this register and 2 MSBs in register 0x07. PARAMETER
Table 26 Detailed description of I2C-bus video FIFO register READ SPACING AND PACKET SIZE (address 0x07) 7 X 6 X 5 X 4 X 3 X 2 X 1 0 read spacing mode_read_spacing: sets the periodicity of the read pulses; the periodicity can be set from 1 to 63 (from `000001' to `111111') packet size X X mode_packet_size: 2 MSBs of the value (8 LSBs in register 0x06) PARAMETER
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Philips Semiconductors
Product specification
Digital camera USB interface IC
9.2.5 ADIF TOP REGISTERS
SAA8117HL
Table 27 Overview of I2C-bus ADIF top registers (base address 0x0C) ADDRESS 0x0C 0x0D 0x0E 0x0F NAME AGC CONTROL GENERAL AGC CONTROL GAIN LEFT AGC CONTROL GAIN RIGHT ADIF CONTROL AGC control general AGC control gain left AGC control gain right I2S-bus input and ADIF2MMU FUNCTION
Table 28 Detailed description of I2C-bus ADIF top register ADIF CONTROL (address 0x0F) 7 X 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 6 5 4 3 2 1 0 reserved number of bytes per sample 0 (reserved) 1 (8 bits audio samples) 2 (16 bits audio samples) 3 (24 bits audio samples) selection mono/stereo operation mono stereo selection input for ADC path (ADIF mux) digital input (from I2S-bus) analog input (from Vin_left and Vin_right) selection high-pass filter (DC filter) for ADC down-sample filter high-pass filter off high-pass filter on selection UDAI serial input format I2S-bus LSB justified, 16 bits LSB justified, 18 bits LSB justified, 20 bits PARAMETER
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VDDD Vn PARAMETER analog supply voltage digital supply voltage voltage on pins AGND and DGND pins SCL and SDA all other pins Tstg Tamb Tj Note 1. 5 V tolerant buffers. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 51 UNIT K/W storage temperature operating ambient temperature junction temperature note 1 -0.5 -0.5 -0.5 - 55 0 -40 +4.0 +5.5 VDD + 0.5 +150 70 +125 V V V C C C CONDITIONS MIN. -0.5 -0.5 MAX. +4.0 +4.0 V V UNIT
thermal resistance from junction to ambient in free air
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Philips Semiconductors
Product specification
Digital camera USB interface IC
12 CHARACTERISTICS VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C. SYMBOL Supplies VDDD VDDA VDGND VAGND IDDD IDDA Tamb Inputs digital supply voltage analog supply voltage voltage on pins DGND voltage on pins AGND digital supply current analog supply current operating ambient temperature Tamb = 25 C Tamb = 25 C 3.0 3.0 0 0 - - 0 3.3 3.3 0 0 70 20 25 PARAMETER CONDITIONS MIN. TYP.
SAA8117HL
MAX.
UNIT
3.6 3.6 0 0 - - 70
V V V V mA mA C
DATA AND CONTROL INPUTS: PINS M0 TO M2, YUV0 TO YUV7, LLC, HREF, VSYNC, RESET, GENPOR, ATXCTRL, RCV, VM0 AND VP0 VIL VIH Outputs DATA AND CONTROL OUTPUTS: PINS CLK2, SMP, SPEED, SUSPEND, VM, VP AND OEBAR VOL VOH VOL VOH VOL VOH VOL VOH Interfaces I2S-BUS: PINS DA, BCK AND WS VIL VIH I2C-BUS AND VIL VIH VOL VOH LOW-level input voltage HIGH-level input voltage - 0.7VDDD - note 1 note 1 - VDDD - 0.7 - - - - - 0.3VDDD - 0.7 VDDD + 0.5 0.4 - V V LOW-level output voltage HIGH-level output voltage - 0.85VDDD - 2.0 - 2.6 - 2.2 - - - - - - - - 0.1VDDD - 0.8 - 0.8 - 0.6 - V V LOW-level input voltage HIGH-level input voltage - 2 - - 0.8 - V V
CONTROL OUTPUTS: PINS RG, SHUTTER, C1 TO C3, CLK1, SHP AND SHD LOW-level output voltage HIGH-level output voltage V V
CONTROL OUTPUTS: PINS A1 TO A4 AND B1 TO B4 LOW-level output voltage HIGH-level output voltage V V
CONTROL OUTPUTS: PINS CLPDM AND CLPOB LOW-level output voltage HIGH-level output voltage V V
SNERT BUS: PINS SDA, SCL, SNDA, SNCL AND SNRES LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage V V V V 0.2VDDD + 0.9 -
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
AND
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
MICROCONTROLLER INTERFACE: PINS
SUSREADYNOT, UCPOR, UCINT, CLOCK, CLOCKON, TRC, SNAPSHOT note 2 note 2 note 3 note 3 - - VDDD - 0.7 - note 4 - - - - - - 0.7 VDDD + 0.5 0.4 - - - - - V V V V
DCDCON LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage 0.2VDDD + 0.9 -
VIL VIH VOL VOH fi fo B
Audio Phase-Locked Loop (PLL) clock input frequency clock output frequency bandwidth damping 48 11.2996 2.3 0.98 MHz MHz kHz
convertor INPUTS fi Vi(rms) N Nbit Neqbit DRi fclk input signal frequency input voltage (RMS value) order of the number of output bits equivalent output resolution (bit) dynamic range at input clock frequency clock frequency duty factor note 5 1 - - - - - - - - 800 20 - - - - - 5.6448 - dB MHz % kHz mV
TRANSFER FUNCTION 3 1 16 96.6 - 50
Fixed Gain Amplifier (FGA) LOAD RL CL Vi(nom)(p-p) A1 Vo(nom)(rms) S/N THD Ri Ro fi load resistance load capacitance 5 - - - - note 6 at HIGH-level; note 7 - - 3.35 - 3 dB range 100 - - 226.3 20 800 60 -65 4.7 - - - 15 - - - - - 6.0 100 20000 k pF
TRANSFER FUNCTION nominal input voltage (peak-to-peak value) amplification nominal output voltage (RMS value) signal-to-noise ratio total harmonic distortion input impedance output impedance input frequency mV dB mV dB dB k Hz
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL BIASING Iref
PARAMETER
CONDITIONS -
MIN.
TYP. -
MAX.
UNIT A
reference current
25
FGA/ path TRANSFER FUNCTION A1 S/N THD amplification signal-to-noise ratio total harmonic distortion - 51 -70 20 60 -66 - 70 -61 dB dB dB
ATX transceiver DRIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM fo(sample) tt(rise) tt(fall) tt(match) Vo(cr) Zo audio sample output frequency rise transition time fall transition time transition time matching output signal crossover voltage driver output impedance steady state drive CL = 50 pF CL = 50 pF note 8 4 4 4 90 1.3 30 - - - - - - 48 20 20 110 2.0 42 MHz ns ns % V
RECEIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM fs fi(D) tframe Notes 1. This applies the outputs: pins SDA and SNDA. 2. This applies the inputs: pins SUSREADYNOT, TRC and SNAPSHOT. 3. This applies the outputs: pins CLOCK, UCINT, UCPOR, CLOCKON and DCDCON. 4. Frequencies depend on PLL settings (see Table 1). Vi 5. Defined here as: 20 x log ----------------- where Vi = input voltage and Vn(i)(eq) = equivalent input noise voltage. V n(i)(eq) 6. The noise is measured with A-weighting at the nominal input voltage. 7. The distortion is measured at a maximum output voltage of 2.4 V (p-p). t t(rise) 8. Transition time matching: t t(match) = -----------t t(fall) audio sample input frequency data input frequency rate frame interval 5 - - - 12.00 1.000 55 - - kHz Mbits/s ms
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
13 TIMING VDDD = VDDA = 3.3 V 10%; load capacitance = 10 pF; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Data input related to LCC (see Fig.24) Pins YUV0 toYUV7, HREF and VSYNC tsu(i)(D) th(i)(D) td1 td2 td3 td4 td5 td6 td7 td8 tWH(C1) tWL(C2) tWL(SHP) tWL(SHD) tWL(RG) tWL(CLK1) tWH(CLK2) tr data input set-up time data input hold time 1 1 -2 1 -3 -0.5 0.5 0 -0.5 -2 164 166 81 81 83 164 79 note 1 - - - - - note 1 - - - - - 4 4 4 4.5 4.5 - - - - - ns ns ns ns ns 4.5 4 4 4 4 - - - - - ns ns ns ns ns - - -1.5 1.5 -1.5 0 1 1 0 0 165 167 82 82 84 165 80 - - ns ns
PPG high-speed pulses for PAL medium resolution sensors; mode 0 (see Fig.25) delay between falling edge C2 and rising edge C1 delay between rising edge C2 and falling edge C1 delay between falling edge C1 and rising edge SHP delay between rising edge C1 and rising edge SHD delay between rising edge C1 and falling edge RG delay between falling edge CLK1 and rising edge C1 delay between rising edge CLK1 and falling edge C1 delay between rising edge CLK2 and rising edge C1 C1 pulse width HIGH C2 pulse width LOW SHP pulse width LOW SHD pulse width LOW RG pulse width LOW CLK1 pulse width LOW CLK2 pulse width HIGH rise time pulse C1 pulse C2 pulse RG pulse SHP pulse SHD tf fall time pulse C1 pulse C2 pulse RG pulse SHP pulse SHD 0 2 -1 +0.5 2 2 +0.5 +2 - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PPG high-speed pulses for VGA sensors (see Fig.26) td1 td2 td3 td4 td5 td6 td7 td8 tWH(C1) tWH(C2) tWH(C3) tWL(SHP) tWL(SHD) tWL(RG) tWH(CLK1) tWH(CLK2) Note 1. Load capacity = 11 pF; VDDD = VDDA = 3.3 V; Tamb = 25 C. delay between rising edge C2 and rising edge C1 delay between rising edge C3 and rising edge C2 delay between rising edge SHP and falling edge C3 delay between falling edge SHD and rising edge C2 delay between rising edge SHD and rising edge C3 delay between rising edge RG and rising edge C1 delay between rising edge C1 and falling edge CLK1 delay between rising edge C1 and rising edge CLK2 C1 pulse width HIGH C2 pulse width HIGH C3 pulse width HIGH SHP pulse width LOW SHD pulse width LOW RG pulse width LOW CLK1 pulse width HIGH CLK2 pulse width HIGH 61 61 -1.5 8 -12 -0.5 18 20 81 81 82 21 43 21 81 41 62 62 -1 9 -11 0 19 21 82 82 85 22 44 22 82 43 63 63 +0.5 10 -10 +0.5 21 22 - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
handbook, full pagewidth
LCC
tsu(i)D
th(i)D
data input
FCE153
Fig.24 Data input timing.
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
handbook, full pagewidth
tWH(C1) 50% td1 50% td2 50% tWL(C2) 50%
C1
C2
50%
SHP
50%
50% tWL(SHP) td3 50% tWL(SHD) 50% td4
SHD td5 RG 50% td6 CLK1 50%
tWL(RG)
50% td7 50% tWL(CLK1) td8
CLK2
50% tWH(CLK2)
50%
FCE154
Fig.25 PPG high-speed pulses for PAL medium resolution sensors (mode 0).
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Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
handbook, full pagewidth
tWH(C1) 50% td1 50% tWH(C2) 50% td2 50% 50%
C1
C2
C3
50% td3 tWL(SHP) tWH(C3)
SHP
50%
50%
td4 50% tWL(SHD) 50%
td5
SHD
td6 50% 50%
RG td7 CLK1 50% td8 CLK2 50% tWH(CLK2) 50% 50% tWH(CLK1) tWL(RG)
50%
FCE155
Fig.26 PPG high-speed pulses for VGA sensors (mode 2).
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Philips Semiconductors
Product specification
Digital camera USB interface IC
14 APPLICATION INFORMATION
SAA8117HL
handbook, full pagewidth
MIC SYNC SENSOR
TDA8784/87
SAA8110G OR SAA8112HL
USB YUV
SAA8117HL
CLOCKON
48 MHz
TRC PPG pulses SNERT I2C-BUS power management
FCE157
MICROCONTROLLER
Fig.27 Application diagram.
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Philips Semiconductors
Product specification
Digital camera USB interface IC
15 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA8117HL
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
ISSUE DATE 95-12-19 97-08-04
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Philips Semiconductors
Product specification
Digital camera USB interface IC
16 SOLDERING 16.1 Introduction to soldering surface mount packages
SAA8117HL
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Digital camera USB interface IC
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
SAA8117HL
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
Digital camera USB interface IC
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA8117HL
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
Digital camera USB interface IC
NOTES
SAA8117HL
1999 Apr 02
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Philips Semiconductors
Product specification
Digital camera USB interface IC
NOTES
SAA8117HL
1999 Apr 02
59
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545006/750/01/pp60
Date of release: 1999 Apr 02
Document order number:
9397 750 04381

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