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PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
FLASH MEMORY
MT28F322P3
Low Voltage, Extended Temperature
FEATURES
* Flexible dual-bank architecture Support for true concurrent operation with zero latency Read bank a during program bank b and vice versa Read bank a during erase bank b and vice versa * Basic configuration: Seventy-one erasable blocks Bank a (8Mb for data storage) Bank b (24Mb for program storage) * VCC, VCCQ, VPP voltages 2.7V (MIN), 3.3V (MAX) VCC 2.2V (MIN), 3.3V (MAX) VCCQ 3.0V (TYP) VPP (in-system PROGRAM/ERASE) 12V 5% (HV) VPP tolerant (factory programming compatibility) * Random access time: 70ns @ 2.7V VCC * Page Mode read access Eight-word page Interpage read access: 70ns @ 2.7V Intrapage read access: 30ns @ 2.7V * Low power consumption (VCC = 3.3V) Asynchronous/interpage READ < 15mA Intrapage READ < 7mA WRITE < 20mA (MAX) ERASE < 25mA (MAX) Standby < 15A (TYP), 50A (MAX) @ 3.3V Automatic power save (APS) feature * Enhanced write and erase suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank * Dual 64-bit chip protection registers for security purposes * Cross-compatible command support Extended command set Common flash interface * PROGRAM/ERASE cycle 100,000 WRITE/ERASE cycles per block * Fast programming algorithm VPP = 12V 5%
BALL ASSIGNMENT 48-Ball FBGA
1 A B C D E F
A13
2
A11
3
A8
4
VPP
5
WP#
6
A19
7
A7
8
A4
A14
A10
WE#
RST#
A18
A17
A5
A2
A15
A12
A9
NC
A20
A6
A3
A1
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
A0
VCCQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
VSS
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE#
Top View (Ball Down)
NOTE: See page 7 for Ball Description Table. See page 35 for mechanical drawing.
OPTIONS
* Timing 70ns access 80ns access * Boot Block Configuration Top Bottom * Package 48-ball FBGA (6 x 8 ball grid) * Operating Temperature Range Commercial (0C to +70C) Extended (-40C to +85C)
Part Number Example:
MARKING
-70 -80 T B FJ None ET
MT28F322P3FJ-70 BET
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(c)2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR
EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
GENERAL DESCRIPTION
The MT28F322P3 is a high-performance, highdensity, nonvolatile memory solution that can significantly improve system performance. This new architecture features a two-memory-bank configuration that supports background operation with no latency. A high-performance bus interface allows a fast page mode data transfer; a conventional asynchronous bus interface is provided as well. The MT28F322P3 allows soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). Two on-chip status registers, one for each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of the program/erase task. The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages. The device is manufactured using 0.18m process technology. Please refer to Micron's Web site (www.micron.com/ flash) for the latest data sheet.
ARCHITECTURE AND MEMORY ORGANIZATION
The MT28F322P3 Flash device contains two separate banks of memory (bank a and bank b) for simultaneous READ and WRITE operations. The MT28F322P3 Flash memory is available in the following bank segmentation configuration: * Bank a comprises one-fourth of the memory and contains 8 x 4K-word parameter blocks and 15 x 32K-word blocks. * Bank b represents three-fourths of the memory, is equally sectored, and contains 48 x 32K-word blocks. Figures 2 and 3 show the bottom and top memory organizations.
DEVICE MARKING
Due to the size of the package, Micron's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 1.
Table 1 Cross Reference for Abbreviated Device Marks
PART NUMBER MT28F322P3FJ-70 BET MT28F322P3FJ-70 TET MT28F322P3FJ-80 BET MT28F322P3FJ-80 TET PRODUCT MARKING FW816 FW817 FW814 FW815 SAMPLE MARKING FX816 FX817 FX814 FX815 MECHANICAL SAMPLE MARKING FY816 FY817 FY814 FY815
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
PART NUMBERING INFORMATION
Micron's low-power devices are available with several different combinations of features (see Figure 1). Valid combinations of features and their corresponding part numbers are listed in Table 2.
Figure 1 Part Number Chart
MT 28F 322 P 3 FJ -70 T ET
Micron Technology Flash Family
28F = Dual-Supply Flash
Operating Temperature Range
None = Commercial (0C to +70C) ET = Extended (-40C to +85C)
Boot Block Starting Address
B = Bottom boot T = Top boot
Density/Organization/Banks
322 = 32Mb (2,048K x 16) bank a = 1/4; bank b = 3/4
Access Time
-70 = 70ns -80 = 80ns
Read Mode Operation
P = Asynchronous/Page Read
Package Code Operating Voltage Range
3 = 2.7V-3.3V FJ = 48-ball FBGA (6 x 8 grid)
Table 2 Valid Part Number Combinations
ACCESS TIME (ns) 70 70 80 80 BOOT BLOCK STARTING ADDRESS Bottom Top Bottom Top OPERATING TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC
PART NUMBER MT28F322P3FJ-70 BET MT28F322P3FJ-70 TET MT28F322P3FJ-80 BET MT28F322P3FJ-80 TET
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
PR Lock PR Lock Query Query/OTP OTP DQ0-DQ15 X DEC Data Input Buffer Data Register RST# CE# WE# OE# Y/Z DEC Bank 1 Blocks Y/Z Gating/Sensing Manufacturer's ID Device ID Block Lock RCR ID Reg.
CSM
Status Reg.
WSM
Program/ Erase Pump Voltage Generators Output Multiplexer
DQ0-DQ15
I/O Logic
Output Buffer
A0-A20
Address Input Buffer Address CNT WSM Address Multiplexer
Y/Z DEC X DEC
Y/Z Gating/Sensing Bank 2 Blocks
Address Latch
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Figure 2 Bottom Boot Block Device
Block 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Bank b = 24Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-097FFFh 090000h-097FFFh 088000h-087FFFh 080000h-087FFFh Block 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank a = 8Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 Address Range (x16) 078000h-07FFFFh 070000h-077FFFh 068000h-067FFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Figure 3 Top Boot Block Device
Block 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Bank a = 8Mb Block Size (K-bytes/K-words) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh Block 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank b = 24Mb Block Size (K-bytes/K-words) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (x16) 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
BALL DESCRIPTIONS
48-BALL FBGA NUMBERS D8, C8, B8, C7, A8, B7, C6, A7, A3, C3, B2, A2, C2, A1, B1, C1, D1, B6, B5, A6, C5 D7 F8 B3 SYMBOL A0-A20 TYPE Input DESCRIPTION Address Inputs: Inputs for the address during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles.
CE# OE# WE#
Input Input Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Output Enable: Enables the output buffer when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array. Reset: When RST# is a logic LOW, the device is in reset mode, which drives the outputs to High-Z and resets the write state machine (WSM). When RST# is at logic HIGH, the device is in standard operation. When RST# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Write Protect: Controls the lock down function of the flexible locking feature. Program/Erase Enable: [1.8V-3.3V] Operates as input at logic levels to control complete device protection. Provides factory programming compatibility when driven to 11.4V-12.6V. Data Inputs/Outputs: Input array data on the second CE# and WE# cycle during PROGRAM command. Input commands to the command user interface when CE# and WE# are active. DQ0-DQ15 output data when CE# and OE# are active. Do not float any ground ball. Device Power Supply: [2.7V-3.3V] Supplies power for device operation. I/O Power Supply: [2.2V-3.3V] Supplies power for input/output buffers. Internally not connected.
B4
RST#
Input
A5 A4
WP# VPP
Input Input
E7, F7, D5, E5, DQ0-DQ15 F4, D3, E3, F2, D6, E6, F6, D4, E4, F3, D2, E2 E8, F1 F5 E1 C4 VSS VCC VCCQ NC
Input/ Output
Supply Supply Supply -
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
COMMAND STATE MACHINE (CSM)
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal WSM. The available commands are listed in Table 3, their definitions are given in Table 4, and their descriptions in Table 5. Program and erase algorithms are automated by an on-chip WSM. For more specific information about the CSM transition states, see Micron technical note TN-28-33, "Command State Machine Description and Command Definition." Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally and accomplish the requested operation. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 7) is set to a logic HIGH level (1), allowing the CSM to respond to the full command set again. trol signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH (VIH). Table 6 shows the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two memory partitions, an on-chip status register is available. These two registers allow the progress of the various operations that can take place on a memory bank to be monitored. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/Os DQ0-DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 7).
COMMAND DEFINITION
Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles.
OPERATIONS
Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE# and WE# must be at a logic LOW level (VIL), and OE# and RST# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, con-
STATUS REGISTER
The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# and reading the resulting status code on I/Os DQ0-DQ7. The high-order I/Os
Table 3 Command State Machine Codes For Device Mode Selection
COMMAND DQ0-DQ7 40h/10h 20h 30h 50h 60h 70h 90h 98h B0h C0h D0h FFh
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
CODE ON DEVICE MODE Program setup/alternate program setup Block erase setup Fast programming algorithm setup Clear status register Protection configuration setup Read status register Read protection configuration register Read query Program/erase suspend Protection register program/lock Program/erase resume - erase confirm Read array
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PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
(DQ8-DQ15) are set to 00h internally, so only the loworder I/Os (DQ0-DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated and latched on the falling edge of OE# or CE#, whichever occurs last. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 7 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0-DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM.
CSM OPERATIONS
The CSM decodes instructions for read array, read protection configuration register, read query, read status register, clear status register, program, erase, erase suspend, erase resume, program suspend, program resume, lock block, unlock block, and lock down block, chip protection program, and set read configuration register. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 3 for CSM codes and Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a
Table 4 Command Definitions
FIRST BUS CYCLE COMMAND OPERATION ADDRESS1 DATA SECOND BUS CYCLE OPERATION ADDRESS1 DATA1
READ ARRAY READ PROTECTION CONFIGURATION REGISTER READ STATUS REGISTER CLEAR STATUS REGISTER READ QUERY BLOCK ERASE SETUP PROGRAM SETUP/ALTERNATE PROGRAM SETUP FAST PROGRAMMING ALGORITHM SETUP PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME - ERASE CONFIRM LOCK BLOCK UNLOCK BLOCK LOCK DOWN BLOCK PROTECTION REGISTER PROGRAM PROTECTION REGISTER LOCK
NOTE: 1. BA: IA: ID: LPA: PA: PD: QA: Address within the block Identification code address Identification code data Lock protection register address Protection register address Data to be written at location PA Query code address
WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE
WA IA BA BA QA BA WA WA BA BA BA BA BA PA LPA
FFh 90h 70h 50h 98h 20h 40h/10h 30h B0h D0h 60h 60h 60h C0h C0h READ READ READ WRITE WRITE WRITE IA X QA BA WA WA ID SRD QD D0h WD D0h
WRITE WRITE WRITE WRITE WRITE
BA BA BA PA LPA
01h D0h 2Fh PD FFFDh
QD: Query code data SRD: Data read from the status register WA: Word address of memory location to be written, or read WD: Data to be written at the location WA X: "Don't Care"
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Table 5 Command Descriptions
CODE DEVICE MODE 10h 20h Alt. Program Setup Erase Setup BUS CYCLE First First DESCRIPTION Operates the same as a PROGRAM SETUP command. Prepares the CSM for an ERASE CONFIRM command. If the next command is not an ERASE CONFIRM command, the command will be ignored, and the bank will go to the read array mode and wait for another command. Prepares the CSM for an FPA CONFIRM command. A two-cycle command: The first cycle prepares for a PROGRAM operation, and the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash device outputs status register data on the falling edge of OE# or CE#, whichever occurs first. The WSM can set the block lock status (SR3), program status (SR4), and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Prepares the CSM for changes to the block locking status. If the next command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN, the command will be ignored, and the device will go to read status mode. Places the device into read status register mode. Reading the device will output the contents of the status register for the addressed bank. The device will automatically enter this mode for the addressed bank after a PROGRAM or ERASE operation has been initiated. Puts the device into the read protection configuration mode so that reading the device will output the manufacturer/device codes or block lock status. Puts the device into the read query mode so that reading the device will output common Flash interface information. Suspends the currently executing PROGRAM/ERASE operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6), and the WSM status bit (SR7) to a "1" (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control signals except RST#, which will immediately shut down the WSM and the remainder of the chip if RST# is driven to VIL. Writes a specific code into the device protection register. Locks the device protection register; data can no longer be changed.
30h 40h
FPA Setup Program Setup
First First
50h
Clear Status Register Protection Configuration Setup Read Status Register
First
60h
First
70h
First
90h
Read Protection Configuration Read Query Program/Erase Suspend
First
98h B0h
First First
C0h
Program Device Protection Register Lock Device Protection Register
First First
(continued on the next page)
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Table 5 Command Descriptions (continued)
CODE DEVICE MODE D0h Erase Confirm BUS CYCLE Second DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM will close the address and data latches, and it will begin erasing the block indicated on the address balls. During programming/erase, the device will respond only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND commands and will output status register data on the falling edge of OE# or CE#, whichever occurs last. If a PROGRAM or ERASE operation was previously suspended, this command will resume the operation. If the previous command was FPA SETUP, the CSM will latch the address indicated on the address bus and enter the FPA mode. During the array mode, array data will be output on the data bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock down the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and unlock the block indicated on the address bus. If the block had been previously set to lock down, this operation will have no effect. Unassigned command that should not be used.
Program/Erase Resume D0h FFh 01h FPA Confirm Read Array Lock Block
First Second First Second
2Fh
Lock Down
Second
D0h
Unlock Block
Second
00h
Invalid /Reserved
logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the device returns to the read array mode.
READ ARRAY The array is read by entering the command code FFh on DQ0-DQ7. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial powerup or device reset, the device defaults to the read array mode. READ PROTECTION CONFIGURATION DATA The chip identification mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0-DQ7 to the bank containing address 0h and the identification code address on the address lines. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at a logic HIGH level (VIH) to read data from the protection con-
READ OPERATIONS
The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
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figuration register. Data is available on DQ0-DQ15. After data is read from the protection configuration register, the read array command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 9 for further details. READ QUERY The read query mode outputs common flash interface (CFI) data when the device is read (see Table 11). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0-DQ7 to the bank containing address 0h. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at a logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0-DQ7. READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0-DQ7. Two bus cycles are required for this operation: one to enter the command code and the block address and a second to read the status register. In a READ cycle, the address is latched and register data is updated on the falling edge of OE# or CE#, whichever occurs last. set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume). Taking RST# to VIL during programming aborts the PROGRAM operation. During programming, VPP must remain in the appropriate VPP voltage range as shown in the recommended operating conditions table.
FAST PROGRAMMING ALGORITHM (FPA) MODE
The fast programming algorithm (FPA) is intended for in-factory use. It enables fast data stream programming. For in-factory programming, the FPA, along with an optimized set of programming parameters, minimizes chip programming time when 11.4V VPP 12.6V. Executing the FPA command (30h), followed by FPA CONFIRM (D0h), enables an entire block to be programmed. This eliminates the need to continuously update the address to be programmed. An initial delay is required after issuing the FPA command. (See the Erase and Program Cycle Timing Requirements Table.) The delay enables the device to detect 12V on VPP. If VPP < 11.4V, or if the block is locked, the status register returns an error. When the FPA command is executed successfully, a data stream can be programmed beginning at the first address. The address can be held constant, or it can be incremented within the address range. The program ends when the programmer enters an address outside the address range of the current block. When the FPA is activated, the data must be provided in sequential order to the WSM. Immediately after programming, verification is executed. The address sequence is again provided to the WSM, which automatically performs a data consistency check between the data stored in the memory array, and the programmed data. The result is stored in the status register. Issuing an address outside the memory block boundaries exits the verification cycle. Figure 8 shows the FPA flowchart.
PROGRAMMING OPERATIONS
There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 3). After the desired command code is entered (10h or 40h command code on DQ0-DQ7), the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM will only respond to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, PROGRAM SETUP, or PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously
ERASE OPERATIONS
An ERASE operation must be used to initialize all bits in an array block to "1s." After BLOCK ERASE confirm is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE setup
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(20h) followed by BLOCK ERASE CONFIRM (D0h) (see Figure 6). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. The ERASE operation may be monitored through the status register (see the Status Register section). During the execution of an ERASE operation the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME and LOCK SETUP (see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 7). It is also possible to suspend an ERASE in any bank and initiate a WRITE to another block in the same bank. After the completion of a WRITE, an ERASE can be resumed by writing an ERASE RESUME command.
Table 6 Bus Operations
MODE Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write RST# VIH CE# VIL OE# VIL WE# VIH ADDRESS DQ0-DQ15 X DOUT
VIH VIH VIL VIH
VIH VIH X VIL
X X X VIH
X X X VIL
X X X X
High-Z High-Z High-Z DIN
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Table 7 Status Register Bit Definition
WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 FPAS 0
STATUS BIT # STATUS REGISTER BIT SR7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful BLOCK ERASE PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP = OK
DESCRIPTION Check write state machine bit first to determine word program or block erase completion, before checking program or erase status bits. When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1," WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP < 1.8V. The VPP level is also checked before the PROGRAM/ERASE operation is verified by the WSM. When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted and the device is returned to read status mode. When this bit is set to "1," the FPA algorithm is active. When the FPA operation is complete, this bit is reset to "0."
SR6
SR5
SR4
SR3
SR2
PROGRAM SUSPEND STATUS (PSS) 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks FAST PROGRAMMING ALGORITHM STATUS (FPAS) 1 = FPA PROGRAM/ERASE Busy 0 = FPA Ready
SR1
SR0
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Figure 4 Automated Word Programming Flowchart
Start
BUS OPERATION COMMAND COMMENTS WRITE WRITE Data = 40h or 10h PROGRAM Addr = Address of word to SETUP be programmed WRITE DATA Data = Word to be programmed Addr = Address of word to be programmed Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
WRITE
Issue PROGRAM SETUP Command and Word Address
READ
Issue Word Address and Word Data
Standby
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop
Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode.
YES
Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION COMMAND COMMENTS Standby Standby Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP LOW Check SR43 1 = Word program error
SR1 = 0? YES
NO PROGRAM Attempted on a Locked Block
Standby
NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed
VPP Range Error
Word Program Failed
NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts.
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Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
Start
BUS OPERATION COMMAND COMMENTS WRITE READ PROGRAM Data = B0h SUSPEND Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR2 1 = Suspended READ ARRAY Data = FFh Read data from block other than that being programmed. PROGRAM Data = D0h RESUME
Issue PROGRAM SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE READ
NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command PROGRAM Complete
WRITE
Finished Reading ? YES Issue PROGRAM RESUME Command
NO
PROGRAM Resumed
NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked.
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Figure 6 BLOCK ERASE Flowchart
Start Issue ERASE SETUP Command and Block Address
BUS OPERATION COMMAND COMMENTS WRITE WRITE ERASE SETUP ERASE Data = 20h Block Addr = Address within block to be erased Data = D0h Block Addr = Address within block to be erased Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
WRITE
READ
Issue BLOCK ERASE CONFIRM Command and Block Address
Standby
Read Status Register Bits NO NO SR 7 = 1? YES Full Status Register Check (optional)1 ERASE SUSPEND? ERASE SUSPEND Loop
Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode.
YES
BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION COMMAND COMMENTS Standby Standby Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP block Check SR53 1 = BLOCK ERASE error
NO SR1 = 0? YES NO SR3 = 0? YES NO SR5 = 0? YES BLOCK ERASE Passed
ERASE Attempted on a Locked Block
Standby
VPP Range Error
BLOCK ERASE Failed
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked.
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Figure 7 ERASE SUSPEND/ERASE RESUME Flowchart
Start
BUS OPERATION COMMAND COMMENTS WRITE READ ERASE SUSPEND Data = B0h Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR6 1 = Suspended READ ARRAY Data = FFh Read data from block other than that being erased. ERASE RESUME Data = D0h
Issue ERASE SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE READ
NO SR7 = 1?
WRITE
YES NO SR6 = 1? YES ERASE Complete PROGRAM
READ or PROGRAM? READ Issue READ ARRAY Command
PROGRAM Loop
(Note 1)
NO
READ or PROGRAM Complete? YES Issue ERASE RESUME Command
ERASE Continued2
NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure.
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Figure 8 Fast Programming Algorithm Flowchart
FPA Setup FPA Program FPA Verify FPA Exit
Start
Read Status Register
Read Status Register
Read Status Register
VPP = 12V Unlock Block
SR0 = 1
Data Stream Ready? SR0 = 0 WRITE Data Address = WA
SR0 = 1
Verify Stream Ready? SR0 = 0 WRITE Data Address = WA
SR7 = 0
FPA Exited? SR7 = 1 Full Status Check Procedure
WRITE 30h Address = WA
WRITE D0h Address = WA
Read Status Register FPA Setup Time SR0 = 1 Read Status Register Program Done? SR0 = 0 FPA Setup Done? SR7 = 1 Check VPP and Lock Errors (SR3, SR1) No Last Data? SR7 = 0 Yes WRITE FFFFh Address BBA No SR0 = 1
Read Status Register
Operation Complete
Verify Done? SR0 = 0 Last Data? Yes WRITE FFFFh Address BBA
Exit
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READ-WHILE-WRITE/ERASE CONCURRENCY
It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank a changes to the read status mode and bank b defaults to the read array mode. The device will read from bank b if the latched address resides in bank b (see Figure 9). Similarly, if a PROGRAM/ERASE command is issued in bank b, then bank b changes to read status mode and bank a defaults to read array mode. When returning to bank a, the device will read PROGRAM/ERASE status if the latched address resides in bank a. A correct bank address must be specified to read status register after returning from concurrent read in the other bank. When reading the CFI or the chip protection register, concurrent operation is not allowed on the top boot device. Concurrent READ of the CFI or the chip protection register is only allowed when a PROGRAM or ERASE operation is performed on bank b on the bottom boot device. For a bottom boot device, reading of the CFI table or the chip protection register is only allowed if bank b is in read array mode. For a top boot device, reading of the CFI table or the chip protection register is only allowed if bank a is in read array mode.
Figure 9 READ-While-WRITE Concurrency
Bank a 1 - Erasing/writing to bank a 2 - Erasing in bank a can be suspended, and a WRITE to another block in bank a can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 1 - Reading bank a Bank b
1 - Reading from bank b
1 - Erasing/writing to bank b 2 - Erasing in bank b can be suspended, and a WRITE to another block in bank b can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command.
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BLOCK LOCKING
The MT28F322P3 Flash memory provides a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The device offers two-level protection for the blocks. The first level allows software-only control of block locking (for data which needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code which does not require frequent updates). Control signals WP#, DQ0, and DQ1 define the state of a block; for example, state [001] means WP# = 0, DQ0 = 0 and DQ1 = 1. Table 8 defines all of the possible locking states. NOTE: All blocks are software-locked upon powerup sequence completion. LOCKED STATE After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block. UNLOCKED STATE Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to ERASE operations, but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked state when the device is reset or powered down (see Table 4). LOCKED DOWN STATE Blocks that are locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked state when the device is reset or powered down. The LOCK DOWN function is dependent on the WP# input. When WP# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. When WP# = 1, the lock down function is disabled ([111]), and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired while WP# remains HIGH. When WP# goes LOW, blocks that were previously locked down return to the locked down state [011] regardless of any changes made while WP# was HIGH. Device reset or powerdown resets all locks, including those in lock down, to locked state (see Table 9). READING A BLOCK'S LOCK STATUS The lock status of every block can be read in the read device identification mode. To enter this mode, write 90h to the bank containing address 00h. Subsequent READs at block address +00002 will output the lock status of that block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/unlock status and is set by the LOCK com-
Table 8 Block Locking State Transition
WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 NAME Unlocked Locked (Default) Lock Down Unlocked Locked Lock Down Disabled Lock Down Disabled ERASE/PROGRAM ALLOWED Yes No No Yes No Yes No LOCK To [001] No Change No Change To [101] No Change To [111] No Change UNLOCK No Change To [000] No Change No Change To [100] No Change To [110] LOCK DOWN To [011] To [011] No Change To [111] To [111] To [111] No Change
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mand and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN command. It can only be cleared by reset or powerdown, not by software. Table 8 shows the locking state transition scheme. The read array command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h). If a block is locked or locked down during an ERASE SUSPEND on the same block, the locking status bits will be changed immediately. When the ERASE is resumed, the ERASE operation will complete. A locking operation cannot be performed during a PROGRAM SUSPEND.
CHIP PROTECTION REGISTER
A 128-bit chip protection register can be used to fulfill the security considerations in the system (preventing the device substitution). The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit unchangeable number. The other segment is left blank for customers to program as desired. (See Figure 10). READING THE CHIP PROTECTION REGISTER The chip protection register is read in the device identification mode. To enter this mode, load the 90h command to the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 9 retrieve the specified information. To return to the
Figure 10 Protection Register Memory Map
88h
85h 84h
4 Words User-Programmed 4 Words Factory-Programmed
81h 80h
PR Lock
0
Table 9 Chip Configuration Addressing1
ITEM Manufacturer Code (x16) Device Code Top boot configuration Bottom boot configuration ADDRESS 2 00000h 00001h 4494h 4495h XX002h Lock DQ0 = 0 DQ0 = 1 DQ1 = 1 PR Lock Factory Data User Data DATA 002Ch
* * Block Lock Configuration is unlocked * Block is locked Block * Block is locked down * Protection Register Lock Chip
Chip Protection Register 1 Chip Protection Register 2
80h 81h-84h 85h-88h
NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. "XX" specifies the block address of lock configuration.
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read array mode, write the READ ARRAY command (FFh). The read array command, FFh, must be issued to the bank containing address 00h prior to issuing other commands.
STANDBY MODE
Icc supply current is reduced by applying a logic HIGH level on CE# and RST# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on CE# and RST# reduces the current to ICC3 (MAX). If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete.
ASYNCHRONOUS READ CYCLE
When accessing addresses in a random order or when switching between pages, the access time is given by tAA. When CE# and OE# are LOW, the data is placed on the data bus and the processor can read the data.
AUTOMATIC POWER SAVE (APS) MODE
Substantial power savings are realized during periods when the array is not being read and the device is in the active mode. During this time the device switches to the automatic power save mode. When the device switches to this mode, ICC is reduced to a level comparable to ICC3. Further power savings can be realized by applying a logic HIGH level on CE# to place the device in standby mode. The low level of power is maintained until another operation is initiated. In this mode, the I/ Os retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control signals toggle.
PAGE READ MODE
The initial portion of the page mode cycle is the same as the asynchronous access cycle. Holding CE# LOW and toggling addresses A0-A2 allows random access of other words in the page. The page word size is eight words.
VPP / VCC PROGRAM AND ERASE VOLTAGES
The MT28F322P3 Flash memory provides insystem programming and erase with VPP in the 1.8V- 3.3V range. The 12V VPP mode programming is offered for compatibility with existing programming equipment, but does not enhance programming performance using the standard programming commands. The device can withstand 100,000 WRITE/ERASE operations when VPP = VCC or 100 WRITE/ERASE operations and 10 cumulative hours when VPP = 12V. In addition to the flexible block locking, the VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When VPP is below VPPLK, any PROGRAM or ERASE operation will result in an error, prompting the corresponding status register bit (SR3) to be set. During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the ranges specified in Table 10. When VCC is below VLKO, any WRITE/ERASE operation will be disabled.
DEVICE RESET
To correctly reset the MT28F322P3 Flash memory, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the device can be accessed for a READ operation with a delayed access time of tRWH from the rising edge of RST#. The circuitry used for generating the RST# signal needs to be common with the rest of the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
The following power-up sequence is recommended to initialize internal chip operations: * At power-up, RST# should be kept at VIL for 2s after VCC reaches VCC (MIN). * VCCQ should not come up before VCC. * VPP should be kept at VIL to maximize data integrity. When the power-up sequence is completed, RST# should be brought to VIH. To ensure a proper power-up, the rise time of RST# (10%-90%) should be <10s.
Table 10 VPP Range (V)
In-System In-Factory MIN 1.8 11.4 MAX 3.3 12.6
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ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Ball Except VCC and VPP with Respect to VSS ............................. -0.5V to +4V VPP Voltage (for BLOCK ERASE and PROGRAM with Respect to VSS) ................. -0.5V to +13.5V** VCC and VCCQ Supply Voltage with Respect to VSS ............................. -0.3V to +4V Output Short Circuit Current ............................... 100mA Operating Temperature Range ............ -40oC to +85oC Storage Temperature Range ............... -55oC to +125oC Soldering Cycle .......................................... 260oC for 10s *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on VPP may overshoot to +13.5V for periods <20ns.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Operating temperature VCC supply voltage I/O supply voltage VPP voltage VPP in-factory programming voltage Block erase cycling VPP = VPP1 VPP = VPP2
NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours.
SYMBOL
tA
MIN -40 2.7 2.2 1.8 11.4 - -
MAX +85 3.3 3.3 3.3 12.6 100,000 100
UNITS C V V V V Cycles Cycles
NOTE
VCC VCCQ VPP1 VPP2 VPP1 VPP2
1
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
DC CHARACTERISTICS1
PARAMETER Input Low Voltage Input High Voltage Output Low Voltage IOL = 100A Output High Voltage IOH = -100A VPP Lockout Voltage VPP During PROGRAM/ERASE Operations VCC Program/Erase Lock Voltage Input Leakage Current Output Leakage Current VCC Read Current Asynchronous Random Read, 70ns cycle Asynchronous Random Read, 200ns cycle VCC Page Mode Read Current at 70ns/30ns VCC Standby Current VCC Program Current VCC Erase Current VCC Erase Suspend Current VCC Program Suspend Current Read-While-Write Current VPP Current (Read, Standby, Erase Suspend, Program Suspend) VPP = VPP1 VPP = VPP2
NOTE: 1. 2. 3. 4. 5.
SYMBOL VIL VIH VOL VOH VPPLK VPP1 VPP2 VLKO IL IOZ ICC1
MIN 0 VCCQ - 0.4V -0.10 VCCQ - 0.1V - 1.8 11.4 1 - 0.2 - -
TYP - - - - - - - - - - - - - 15A 10mA 15mA 15A 15A -
MAX 0.4 VCCQ 0.10 - 1 3.3 12.6 - 1 1 15 6 7 50 20 25 50 50 40
UNITS NOTES V V V V V V V V A A mA mA mA A mA mA A A mA 5 5 3, 4 3, 4 2 2
ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 IPP1
- - - - - - -
- -
- -
1 200
A A
All currents are in RMS unless otherwise noted. VIL may decrease to -0.4V, and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. APS mode reduces ICC to approximately ICC3 levels. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. ICC6 and ICC7 values are valid when the device is deselected. Any READ operation performed while in suspend mode will have an additional current draw of suspend current (ICC6 or ICC7).
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
CAPACITANCE
(TA = +25C; f = 1 MHz) PARAMETER/CONDITION Input Capacitance Output Capacitance SYMBOL C COUT TYP 7 9 MAX 12 12 UNITS pF pF
READ CYCLE TIMING REQUIREMENTS
-70 PARAMETER Address to output delay CE# LOW to output delay Page address access OE# LOW to output delay RST# HIGH to output delay RST# LOW pulse width CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time SYMBOL tAA tACE tAPA tAOE tRWH tRP tOD tOH tRC MIN MAX 70 70 30 25 200 25 0 70 0 80 MIN -80 MAX 80 80 30 25 200 25 UNITS ns ns ns ns ns ns ns ns ns
100
100
Figure 11 Output Load Circuit
VCC 14.5K I/O 14.5K VSS 30pF
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
WRITE CYCLE TIMING REQUIREMENTS
-70/-80 PARAMETER tRST# HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH CE# hold from WE# HIGH Data hold from WE# HIGH Address hold from WE# HIGH Write pulse width HIGH WP# setup to WE# going HIGH VPP setup to WE# going HIGH Write recovery before READ WP# hold from valid SRD VPP hold from valid SRD WE# HIGH to data valid SYMBOL tRS tCS tWP tDS tAS tCH tDH tAH tWPH tRHS tVPS tWOS tRHH tVPH tWB MIN 150 0 30 30 30 0 0 0 30 0 200 50 0 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tAA + 50
ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS
-70/-80 PARAMETER 4KW parameter block program time 32KW parameter block program time Word program time 4KW parameter block erase time 32KW parameter block erase time Program suspend latency Erase suspend latency Chip programming time (FPA) FPA setup time TYP 40 320 8 0.3 0.5 5 5 5 MAX 800 6,400 10,000 6 6 10 20 20 UNITS ms ms s s s s s s s
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
SINGLE ASYNCHRONOUS READ OPERATION
A0-A20 VIH VALID ADDRESS VIL
tRC tAA tOD
VIH CE# VIL
tACE
VIH OE# VIL
tOH
VIH WE# VIL VOH DQ0-DQ15 VOL
tAOE
High-Z
tRWH
VALID OUTPUT
RP#
VIH VIL
UNDEFINED
READ TIMING PARAMETERS
-70 SYMBOL
tAA tACE tAOE tRWH
-80 MAX 70 70 25 200 MIN MAX 80 80 25 200 UNITS ns ns ns ns SYMBOL
tOD tOH tRC
-70 MIN 0 70 MAX 25 0 MIN
-80 MAX 25 80 UNITS ns ns ns
MIN
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
ASYNCHRONOUS PAGE MODE READ OPERATION
A3-A20 VIH VALID ADDRESS VIL VIH VALID ADDRESS VIL
tAA tOD
A0-A2
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VIH CE1# VIL
tACE
VIH OE# VIL VIH WE# VIL
tAOE tAPA tOH
VOH DQ0-DQ15 VOL
High-Z
tRWH
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VIH RP# VIL
UNDEFINED
READ TIMING PARAMETERS
-70 SYMBOL
tAA tACE tAPA tAOE
-80 MAX 70 70 30 25 MIN MAX 80 80 30 25 UNITS ns ns ns ns SYMBOL
tRWH tOD tOH
-70 MIN MAX 200 25 0 0 MIN
-80 MAX 200 25 UNITS ns ns ns
MIN
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
TWO-CYCLE PROGRAMMING/ERASE OPERATION
A0-A20 VIH VALID ADDRESS VIL VIH CE# VIL
tCS tCH tWOS
VALID ADDRESS
tAS tAH
VALID ADDRESS
VIH OE# VIL VIH WE# VIL VOH DQ0-DQ15 VOL High-Z
tRS tDH tRHS tWP tWB tWPH
CMD
CMD/ DATA
tDS
STATUS
VIH RST# VIL VIH WP# VIL
tRHH
tVPS
tVPPH
VIPPH VIPPLK VPP VIL
UNDEFINED
WRITE TIMING PARAMETERS
-70/-80 MIN MAX 150 0 30 30 30 0 0 -70/-80 MIN MAX 0 0 200 50 0 0
tAA + 50
SYMBOL
tRS tCS tWP tDS tAS tCH tDH
UNITS ns ns ns ns ns ns ns
SYMBOL
tAH tRHS tVPS tWOS tRHH tVPPH tWB
UNITS ns ns ns ns ns ns ns
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
RESET OPERATION
VIH VIL RST# VIH VIL
tRP
CE#
OE#
VIH VIL
DQ0-DQ15
VOH VOL
tRWH
READ AND WRITE TIMING PARAMETERS
-70/-80 MIN MAX 200 100
SYMBOL tRWH tRP
UNITS ns ns
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Table 11 CFI
OFFSET 00 01 02-0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 DATA 2Ch 94h 95h reserved 0051, 0052 0059 0003, 0000 0039, 0000 0000, 0000 0000, 0000 0027 0033 00B4 00C6 0003 0000 0009 0000 000C 0000 0003 0000 0016 0001 0000 0000, 0000 0003 002F, 0000 0007, 0000 0000, 0001 0020, 0000 000E, 0000 000E, 0000 0000, 0001 Manufacturer code Top boot block device code Bottom boot block device code Reserved "QR" "Y" Primary OEM command set Address for primary extended table Alternate OEM command set Address for OEM extended table VCC MIN for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VCC MAX for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP MIN for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD VPP MAX for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD Typical timeout for single byte/word program, 2n s, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Typical timeout for individual block erase, 2n ms, 0000 = not supported Typical timeout for full chip erase, 2n ms, 0000 = not supported Maximum timeout for single byte/word program, 2n s, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Maximum timeout for individual block erase, 2n ms, 0000 = not supported Maximum timeout for full chip erase, 2n ms, 0000 = not supported Device size, 2n bytes Bus interface x16 = 1 Flash device interface description 0000 = async Maximum number of bytes in multi-byte program or page, 2n Number of erase block regions within device (4K words and 32K words) Top boot block device erase block region information 1, 8 blocks ... Bottom boot block device erase block region information 1, 8 blocks ... Top boot block device.....of 8KB Bottom boot block device.....of 8KB Top boot block 15 blocks of .... Bottom boot block 15 blocks of .... ......64KB (continued on the next page) DESCRIPTION
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Table 11 CFI (continued)
OFFSET 35, 36 37, 38 39, 3A 3B 3C 3D 3E 3F 40 41 DATA 0007, 0000 002F, 0000 0020, 0000 0000, 0001 0050, 0052 0049 0030 0031 00E6 0002 0000 0000 DESCRIPTION Top boot block device.....48 blocks of Bottom boot block device.....48 blocks of Top boot block device......64KB Bottom boot block device......64KB "PR" "I" Major version number, ASCII Minor version number, ASCII Optional Feature and Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = no = 0 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 block lock status active = yes; Bit 1 block lock down active = yes VCC supply optimum, 00 = not supported, Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP supply optimum, 00 = not supported, Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 0004 = 50% block split Burst Mode Type 0000 = No burst mode 00x1 = 4 words MAX 00x2 = 8 words MAX 00x3 = 16 words MAX 001x = Linear burst, and/or 002x = Interleaved burst, and/or 004x = Continuous burst (continued on the next page)
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
42 43, 44 45 46 47 48, 49 4A, 4B 4C
0001 0003, 0000 0030 00C0 0001 0080, 0000 0003, 0003 0003
4D
0000
33
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
Table 11 CFI (continued)
OFFSET 4E DATA 0002 Page 0000 0001 0002 0003 0004 Mode Type = No page mode = 4-word page = 8-word page = 16-word page = 32-word page DESCRIPTION
4F
0000
Not used
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
48-BALL FBGA
.850 .075
0.10 C
C
7.00 .10 5.25 BALL A8 .75 TYP BALL A1 ID
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 37% Pb, 2%Ag SOLDER BALL PAD: O .27mm SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC
48X O 0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.33 C L
BALL A1 BALL A1 ID
3.75 10.00 .10
1.876 .05 5.00 .05
.75 TYP
C L 2.625 .05 3.50 .05 1.20 MAX
NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.
DATA SHEET DESIGNATION
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks, and the Micron logo is a trademark of Micron Technology, Inc.
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
35
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16 ASYNC/PAGE FLASH MEMORY
REVISION HISTORY
Rev. 3, PRELIMINARY ....................................................................................................................................................... 7/02 * Updated Status Register section * Updated command descriptions * Updated flowcharts * Updated Read-While-Write/EraseConcurrency section * Updated timing diagrams Rev. 2, PRELIMINARY ....................................................................................................................................................... 4/02 * Changed tAH from 9ns to 0ns * Updated READ CHIP PROTECTION IDENTIFICATION DATA text Rev. 2, PRELIMINARY ....................................................................................................................................................... 3/02 * Updated DC Characteristics table * Updated Table 10 * Updated Asynchronous READ Cycle Timing Requirements table * Updated WRITE Cycle Timing Requirements table * Updated timing diagrams and parameters Original document, PRELIMINARY ............................................................................................................................... 1/02
2 Meg x 16 Async/Page Flash Memory MT28F322P3FJ_3.p65 - Rev. 3, Pub. 7/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.

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