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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
ICM105B Color VGA CMOS Image Sensor Data Sheet V1.6 August 2002
IC Media Corporation 545 East Brokaw Road San Jose, CA 95112, U.S.A. Phone: (408) 451-8838 Fax: (408) 451-8839 Email: Sales@IC-Media.Com Web Site: www.ic-media.com IC Media Technology Corporation 6F, No. 61, ChowTze Street., NeiHu District Taipei, Taiwan, R.O.C. Phone: 886-2-2657-7898 Fax: 886-2-2657-8751 Email: Ap.Sales@IC-Media.Com.tw Web Site: www.ic-media.com.tw
Important notice: This document contains information of a new product. IC Media Corp reserves the right to make any changes without further notice to any product herein to improve design, function or quality and reliability. No responsibility is assumed by IC Media Corp for its use, nor for any infringements of patents of third parties, which may result from its use.
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
Features
* * * * * * * * * * * * * * 307,200 (640x480) pixels, VGA format, used with 1/4" optical system Progressive readout Output data format: 8-bit raw data Control interface: SIF Electronic exposure control On-chip 9-bit ADC Correlated double sampling Separate RGB gain Dead column removal Power down mode Automatic optical black compensation Support both master and slave mode Horizontal and vertical images Single 3.3 V power supply
General Description
ICM-105B is a single-chip digital color imaging device. It incorporates a 640x480 sensor array (650x490 in physical layout) operating at 1 ~ 30 frames per second in progressive manner. Each pixel is covered by a color filter, which formed a so-called Bayer pattern. Correlated double sampling is performed by the internal ADC and timing circuitry. The raw data can be adjusted by the digital gain. The output format is 8-bit raw data which can be fed to other DSP, color processing, or compression chips.
Application
* * * * * * * * * * * Digital camcorder Digital still camera Video phone Video conferencing Video mail Video cellular phone PC camera Security system Visual toy Industrial image capture/analysis Environment monitor system
Key Parameters
* * * * * Number of Active Pixels: 640x480 Number of Physical Pixels: 650x490 Frame Rate: 30/20/15/12/10/6/5/4/3/2/1 fps Pixel Size: 6.0 m x 6.0 m Sensor Area: 3.84 mm x 2.88 mm
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
* * * * * * * * * * * * Main Clock Frequency: 24 MHz Exposure Time: 64 s (@ 30 fps, 1 line, 24 MHz) ~ 126 s (@ 1 fps, 65535 lines, 24 MHz) Sensitivity: 1.0 V/lux-sec (555 nm) Quantum Efficiency: 38 % (555 nm) Dynamic Range: 55 dB (analog), 48 dB (digital) Digital Gain: 1 ~ 64 x Fill Factor: 36% S/N Ratio: 45 dB @ 75% full signal level Sensitive to infrared illumination source Power Supply: 3.3 V Power Requirement: 25 mA (@ 30fps, 24 MHz), 14 mA (@ 15 fps, 12 MHz) Package: Shrunk Plastic LCC48
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
1. Pin Assignment
Pin # 14 11 12 13 34 36 32 33 2 1 10 16 8 48 47 46 44 41 39 38 37 3 5 35 15 7, 31 9, 30 19 17 4, 43 6, 45 40 42 18 Name CLKSEL CLKIN XIN XOUT PCLK OEN SIFCID SIFCMS SCL SDA POWERDN RSET RSTN DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[3] DOUT[2] DOUT[1] DOUT[0] HSYNC VSYNC FLASH RAMP VDDA GNDA VDDD GNDD VDDK GNDK VDDO GNDO GNDS Class* D, I, N D, I, N A, I A, O D, O D, I, N D, I, N D, I, U D, I/O D, I/O D, I, U A, I D, I, U D, O D, I/O D, I/O D, I/O D, I/O D, I/O D, I/O D, I/O D, I/O D, I/O D, O A, O P P P P P P P P P Function Clock source selection. 0: internal oscillator, 1: CLKIN External clock source Oscillator in Oscillator out Pixel clock output Output enable. 0: enable, 1: disable Lsb of SIF slave address SIF master/slave selection. 0: slave, 1: master (auto load from EEPROM after reset) SIF clock SIF data Power down control, 0: power down, 1: active Resistor to ground = 47 K @ 24 MHz main clock, 51 K @ 24 MHz Chip reset, active low Data output bit 7 Data output bit 6; if pulled up/down, the initial value of TIMING_CONTROL_LOW[2] (VSYNC polarity) is 1/0 Data output bit 5; if pulled up/down, the initial value of TIMING_CONTROL_LOW[1] (HSYNC polarity) is 1/0 Data output bit 4; if pulled up/down, the initial value of AD_IDL[3] (Sub ID) is 1/0 Data output bit 3; if pulled up/down, the initial value of AD_IDL[2] (Sub ID) is 1/0 Data output bit 2; if pulled up/down, the initial value of AD_IDL[1] (Sub ID) is 1/0 Data output bit 1; if pulled up/down, the initial value of AD_IDL[0] (Sub ID) is 1/0 Data output bit 0; if pulled up/down, the synchronization mode is in master/slave mode which requires HSYNC and VSYNC operating in output/input mode Horizontal sync signal Vertical sync signal Flash light control Analog ramp output Sensor analog power Sensor analog ground Sensor digital power Sensor digital ground Digital power Digital ground Pad power Pad ground Substrate ground
Class Code: A - Analog signal, D - Digital signal, I - Input, O - Output, P - Power or ground, U - Internal pull-up, N - Internal pull-down
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
2. Functional Description
ICM-105B is a single-chip digital color imaging device. It includes a 640x480 sensor array, 640 columnlevel ADC, and correlated double sampling circuitry. All the programmable parameters are set by writing into the SIF interface which can address the register file consisting of 8-bit registers. The output format is 8-bit raw data, together with horizontal and vertical sync signals.
SIF Interface
Sensor Array 640x480
Column-Level ADC
Timing Control
Correlated Double Sampling
Digital Gain
Output Control
Figure 1. Block diagram
2.1 Image Array
The image array consists of 640x480 pixels. Each pixel has a light sensitive photo diode and a set of control and transfer transistors. At the beginning of the cycle, a row of pixels are pre-charged to its maximum value. Then they are exposed to light for several lines worth of time and sampled by the ADC. Correlated double sampling (CDS) is performed by subtracting the reset value (sampled right before sampling the signal) from the signal value. The purpose of CDS is to eliminate the point-wise fixed pattern noise (FPN). The output of CDS is approximately proportional to the amount of received light, ranging from 0 to 255.
2.2 Color Filter
Each pixel is covered by a color filter. They form the Bayer Pattern as shown in Figure 2. (Row 0, Column 0) is covered by a Red filter, (Row 0, Column 1) and (Row 1, Column 0) by Green filters, and (Row 1, Column 1) by a Blue filter. Since each pixel only gets part of the frequency band, the data need further processing (i.e., color interpolation and color correction) in order to approximate the full visible spectrum.
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
Figure 2. Color filter Bayer pattern
2.3 Exposure and Gain Control
The brightness of the scene may change by a great amount that renders the captured image either overexposed or under-exposed. To accommodate for different brightness, the user may change the exposure time by adjusting the AD_EXPOSE_TIMEH and AD_EXPOSE_TIMEL. The exposure time is measured in terms of the time to read out one line of data, which is equal to 64.17 s (assuming the line length is 770 @ 24 MHz). If the number of lines per frame is set at 520 (the default), the exposure time can vary from 1 to 519 lines. In addition, the user can adjust bit 7 to 5 of register AD_COL_BEGINH to digitally boost the output value by 1 to 64 times.
2.4 Timing Control
Timing control is performed by programming a 32-entry wave table. Its content is filled by external circuitry after power up. Bits 19 to 10 are the control signals. Bits 9 to 0 are the change position. Whenever the change position equals the column counter, a new set of signal values are applied. Please see the Wave Table Programming section for details.
2.5 Output Format
During normal operation, the output format is 8-bit raw data that ranges from 0 to 255. It may be used for off-chip color processing or compression. A typical configuration is to connect ICM-105B to a USB/Compression combo chip. When operated at 30 fps, the PCLK is 12 MHz when the input main clock is 24 MHz. In addition to the data pins, the chip also output VSYNC, HSYNC, and PCLK. The length and polarity of VSYNC and HSYNC can be adjusted through registers. The line and frame timing can be adjusted through registers AD_WIDTH and AD_HEIGHT.
2.6 SIF Interface
Register programming is through SIF interface (SCL and SDA pins). The 7-bit SIF device address is 0x20 by default, but the last bit can be configured by the SIFID pin. ICM-105B can operate in either SIF master mode or slave mode right after power up, depending on the pull-up or pull-down of the SIFMS pin. When SIFMS is pulled low during power-up, ICM-105B's SIF interface is operated as an SIF slave device, waiting to be controlled by an external SIF master such as a microprocessor. When SIFMS is pulled high during power-up, the SIF interface is first acting as an SIF master device trying to read from an external SIF EEPROM. After that, it will fall back to behave like an SIF slave.
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
3. SIF Registers
Address 0x00 Name PART_CONTROL Default 0 Description Processing control [0] 0: normal mode, 1: single frame mode [1] Slope adjustment enable [2] Exposure time control, writing a 1 will activate the new value set in AD_EXPOSE_TIME, when read back from it, 0 means either the exposure time change is finished (in video mode) or the entire frame is transmitted (in single frame mode), 1 means either the exposure time change is still in progress (in video mode) or the frame is yet to finish (in single frame mode) [6:3] Frame rate, 0: 30 fps 1: 20 fps 2: 15 fps 3: 12 fps 4: 10 fps 5: 6 fps 6: 5 fps 7: 4 fps 8: 3 fps 9: 2 fps 10: 1 fps [7] Latent change, writing a 1 means the changed latent registers now starts taking effect, when the entire operation is done, the read back value of this bit will change from 1 to 0. Timing control [0] Column count enable, set to 0 when filling wave table, set to 1 when normal operation [1] HSYNC polarity, 0: active low, 1: active high, the initial value is determined by DOUT[5] [2] VSYNC polarity, 0: active low, 1: active high, the initial value is determined by DOUT[6] [3] Auto dark correction enable [4] Timing select, 0: wave table timing, 1: default timing [6] Flash polarity, 0: active low, 1: active high [7] Blank polarity, 0: active low, 1: active high [8] IRST select, 0: from wave table, 1: from IRST_NUMBER register [10] Capture: when in single frame mode, writing a 1 here will start a frame capture [11] Dead column removal mode, 0: color, 1: black-and-white [12] Out-of-array exposure pointer control, 0: point to row 487, 1: point to row 490 (a nonexistent row)
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0x01 0x02
TIMING_CONTROL_LOW TIMING_CONTROL_HIGH
0x0019
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
[13] Column stop, 0: sensor column counter stop at 649 when exceeding real array, 1: sensor column counter keeps counting [9:0] Frame width [15:0] Frame height, should not be less than AD_ROW_BEGIN + 490 [9:0] Beginning of active line in terms of column position [10] Left-right mirror image enable [15:13] Digital gain 0: 1 1: 2 2: 4 3: 8 4: 16 5: 32 6: 64 [15:0] Beginning of active frame in terms of row position [9:0] End of horizontal sync in terms of column position [15:0] End of vertical sync in terms of row position [15:0] Exposure time in terms of number of rows [10:0] Gain coefficient (Gr), in unsigned 3.8 (default) format [10:0] Gain coefficient (R), in unsigned 3.8 (default) format [10:0] Gain coefficient (B), in unsigned 3.8 (default) format [10:0] Gain coefficient (Gb), in unsigned 3.8 (default) format [4:0] Output format 0: unsigned 3.8 format 1: unsigned 4.7 format 2: unsigned 5.6 format 3: unsigned 6.5 format 8: control signals 9: row address 10: column address 11: sensor raw data 4-7, 12-31: 8-bit raw data [7] External reference voltage enable [8:0] Reset (DA1) overflow value [8:0] Data (DA2) overflow value [8:0] Ramp low threshold [8:0] Ramp high threshold
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0x0C 0x0D 0x0E 0x0F 0x10 0x11
AD_WIDTHL AD_WIDTHH AD_HEIGHTL AD_HEIGHTH AD_COL_BEGINL AD_COL_BEGINH
0x0302 (770) 0x0208 (520) 0x0064 (100)
0x14 0x15 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x52
AD_ROW_BEGINL AD_ROW_BEGINH AD_HSYNC_ENDL AD_HSYNC_ENDH AD_VSYNC_ENDL AD_VSYNC_ENDH AD_EXPOSE_TIMEL AD_EXPOSE_TIMEH AD_M1_L AD_M1_H AD_M2_L AD_M2_H AD_M3_L AD_M3_H AD_M4_L AD_M4_H AD_INOUTSEL
0x000A (10) 0x0040 (64) 0x0003 (3) 0x0207 (519) 0x0100 (256) 0x0100 (256) 0x0100 (256) 0x0100 (256) 0
0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B
AD_RAMPSEL AD_DSRSTL AD_DSRSTH AD_DSDATAL AD_DSDATAH AD_DSLOWL AD_DSLOWH AD_DSHIGHL AD_DSHIGHH
0x04 0 0x01F9 (505) 0x00FF (255) 0x011D (285)
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 AD_DEAD0L AD_DEAD0H AD_DEAD1L AD_DEAD1H AD_DEAD2L AD_DEAD2H AD_DEAD3L AD_DEAD3H AD_DEAD4L AD_DEAD4H AD_DEAD5L AD_DEAD5H AD_DEAD6L AD_DEAD6H AD_DEAD7L AD_DEAD7H AD_DEAD8L AD_DEAD8H AD_DEAD9L AD_DEAD9H AD_IDL AD_IDH AD_FLASH_BEGINL AD_FLASH_BEGINH AD_FLASH_ENDL AD_FLASH_ENDH AD_BWIDTH_BEGINL AD_BWIDTH_BEGINH AD_BWIDTH_ENDL AD_BWIDTH_ENDH AD_BHEIGHT_BEGINL AD_BHEIGHT_BEGINH AD_BHEIGHT_ENDL AD_BHEIGHT_ENDH AD_DARK_DATA AD_SLOPEREG 0x03FF 0x03FF 0x03FF 0x03FF 0x03FF 0x03FF 0x03FF 0x03FF 0x03FF 0x03FF 0x9050 [9:0] Dead column #0 in terms of real sensor array [9:0] Dead column #1 in terms of real sensor array [9:0] Dead column #2 in terms of real sensor array [9:0] Dead column #3 in terms of real sensor array [9:0] Dead column #4 in terms of real sensor array [9:0] Dead column #5 in terms of real sensor array [9:0] Dead column #6 in terms of real sensor array [9:0] Dead column #7 in terms of real sensor array [9:0] Dead column #8 in terms of real sensor array [9:0] Dead column #9 in terms of real sensor array [3:0] Sub ID, automatically sampled from pins DOUT[4:1] during reset [15:4] Device ID, default 0x905, can be configured using SIF [15:0] Flash light begin position in terms of rows [15:0] Flash light end position in terms of rows [9:0] Blank begin in terms of columns [9:0] Blank end in terms of columns [15:0] Blank begin in terms of rows [15:0] Blank end in terms of rows [7:0] When auto dark correction is disabled, serve as the subtrahend for dark correction [3:0] Slope rate select, larger value means steeper ramp slope, resulting in larger ADC conversion value [6:4] Slope begin voltage select 0: 1.4 V 1: 1.5 V 2: 1.6 V 3: 1.7 V 4: 1.8 V (default) 5: 1.9 V 6: 2.0 V 7: 2.1 V [0] External ramp enable [1] Internal ramp reference 0: reference to GND
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0x01EA (490) 0x01F4 (500) 0x008B (139) 0x030A (778) 0x000E (14) 0x01ED (493) 0 0x4A
0x94
AD_BITCONTROL
0
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
1: reference to Vdd [2] Bit line read out power down 0: active 1: power down [3] Bit line read select 0: bit line 3 is read out 1: bit line 646 is read out [4] Bit line 3 external input enable [5] Bit line 646 external input enable [9:0] When auto slope adjustment is turned on, if the slope counter exceeds this value, the ramp will become steeper [9:0] Wave table beginning point [9:0] Wave table end point, when it is reached, the waveform will remain fixed until the start of next row [9:0] Column position where the CDS subtraction pulse is applied [15:0] Current exposure time, read only [9:0] Current frame width, read only [15:0] Current frame height, read only [9:0] Current column beginning position, read only [9:0] Current row beginning position, read only [9:0] Current HSync end position, read only [15:0] Current VSync end position, read only [7:0] Current part control setting, read only [9:0] Current wave table beginning point, read only [9:0] Current wave table end point, read only [15:0] Threshold above which the row address mapping mechanism will be activated [15:0] Second threshold above which another address mapping is kicking in [15:0] The substitute row address when the original address is above AD_F_OVER in the vertically flipped mode and when TIMING_CONTROL[12] is 0 [15:0] The substitute row address when the original address is above AD_F_OVER in the vertically flipped mode and when TIMING_CONTROL[12] is 1 [15:0] The substitute row address when the original address is between AD_F_MAX_ADDR and AD_F_OVER in vertically flipped mode
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0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF
AD_SLOPE_END_TIMEL AD_SLOPE_END_TIMEH AD_WT_BEGINL AD_WT_BEGINH AD_WT_ENDL AD_WT_ENDH AD_SUB_EN_TIMEL AD_SUB_EN_TIMEH AD_EXPOSE_TIMEL_C AD_EXPOSE_TIMEH_C AD_WIDTHL_C AD_WIDTHH_C AD_HEIGHTL_C AD_HEIGHTH_C AD_COL_BEGINL_C AD_COL_BEGINH_C AD_ROW_BEGINL_C AD_ROW_BEGINH_C AD_HSYNC_ENDL_C AD_HSYNC_ENDH_C AD_VSYNC_ENDL_C AD_VSYNC_ENDH_C AD_PART_CONTROL_C AD_WT_BEGINL_C AD_WT_BEGINH_C AD_WT_ENDL_C AD_WT_ENDH_C AD_F_MAX_ADDRL AD_F_MAX_ADDRH AD_F_OVERL AD_F_OVERH AD_F_LIMITAL AD_F_LIMITAH AD_F_LIMITBL AD_F_LIMITBH AD_F_LIMITCL AD_F_LIMITCH
0x02A9 (681) 0 0x03FC (1020) 0x02F8 (760) 0x0207 (519) 0x0302 (770) 0x0208 (520) 0x0064 (100) 0x000A (10) 0x0040 (64) 0x0003 (3) 0 0 0x03FC (1020) 0x01E9 (489) 0x01EA (490) 0x01EB (491) 0x0002 (2) 0x01EA (490)
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
4. Electrical Characteristics 4.1 DC Characteristics Symbol VCCA VINA VOUTA TSTG VCC VIN TOPR IDD Parameter Absolute Power Supply Absolute Input Voltage Absolute Output Voltage Storage Temperature Operating Power Supply Operating Input Voltage Operating Temperature Operating Current @ VCC=3.3 V, 25 C Input Low Current Input High Current Tri-state Leakage Current Input Capacitance Output Capacitance Bidirectional Buffer Minimum -0.3 -0.3 -0.3 0 3.14 0 0 25 30 25 3.3 Rating Typical Maximum 3.8 VCC + 0.3 VCC + 0.3 65 3.47 VCC 55 Unit V V V C V V C mA
IIL IIH IOZ CIN COUT CBID
-1 -1 -10 3 3 3
1 1 10
A A A pF pF pF
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
VIL VILS VIH VIHS VOL VOH RL Capacitance Input Low Voltage Schmitt Input Low Voltage Input High Voltage Schmitt Input High Voltage Output Low Voltage Output High Voltage Input Pullup/down Resistance 0.3 * VCC 1.1 0.7 * VCC 1.8 0.4 2.4 50 V V V V V V K
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
4.2 Timing
Reset Timing RSTN VDD CLKIN
Unstable clock >2 CLKIN >2 CLKIN
0.9 * Vcc
Pixel Timing PCLK DOUT[7:0] HSYNC VSYNC
Use PCLK rising edge to latch data
Default Line Timing
770 PCLK 100 5 640 5 20
HSYNC DOUT[7:0]
64
Column 105 ~ 744 is valid
Default Frame Timing
520 Rows 10 490 20
VSYNC HSYNC DOUT[7:0]
Row 15 ~ 494 is valid 0 1 2 9 10 11 499 500 524 0
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
4.3 Pixel Clock Duty Cycle
In different frame rate mode (controlled by PART_CONTROL[6:3]), the duty cycle (high time / clock period) of the PCLK signal is described in the following table: Frame Rate 30 20 15 12 10 6 5 4 3 2 1 Duty Cycle 50.0% 66.6% 50.0% 60.0% 50.0% 50.0% 50.0% 53.3% 50.0% 50.0% 50.0%
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
5. Mechanical Information
9 x 9 mm "T" LCC48 Plastic Packaging
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
11.43 x 11.43 mm "S" LCC48 Shrunk Plastic Packaging
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ICM105B VGA CMOS sensor Data Sheet V1.6, August 2002
6. Ordering Information
Description VGA resolution sensor (3.3 V), "S" Plastic LCC48 Packaged VGA resolution sensor (3.3V), "T" Plastic LCC48 Packaged
Package Size 11.43 x 11.43 mm 9 x 9 mm
Part Number ICM-105Bsa ICM-105Bta
IC Media Corporation 545 East Brokaw Road San Jose, CA 95112, U.S.A. Phone: (408) 451-8838 Fax: (408) 451-8839 Email: Sales@IC-Media.Com Web Site: www.ic-media.com
IC Media Technology Corporation 6F, No. 61, ChowTze Street., NeiHu District Taipei, Taiwan, R.O.C. Phone: 886-2-2657-7898 Fax: 886-2-2657-8751 Email: Sales@IC-Media.Com.tw Web Site: www.ic-media.com.tw
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