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PI6C185-01
Precision 1-5 Clock Buffer
Features
* High-speed, low-noise non-inverting 1-5 buffer * Switching speed up to 140 MHz * Supports up to two SODIMMs * Low skew (<250ps) between any two output clocks * I2C Serial Configuration interface * Multiple VDD, VSS pins for noise reduction * 3.3V power supply voltage * Packaging (Pb-free & Green available): -16-pin TSSOP (L) - 16-pin QSOP (Q)
Description
The PI6C185-01 is a high-speed low-noise 1-5 non-inverting buffer designed for SDRAM clock buffer applications. This buffer is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems. At power-up, all SDRAM outputs are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 5 output drivers. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips(R).
Block Diagram
SDRAM0
Pin Configuration
SDRAM1 BUF_IN SDRAM2
VDD SDRAM0 SDRAM1 VSS BUF_IN VDD SDATA SCLK
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD SDRAM4 VSS VDD SDRAM3 SDRAM2 VSS VSS
SDRAM3
SDRAM4
SDATA SCLOCK
I2C I/O
1
PS8318E
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PI6C185-01 Precision 1-5 Clock Buffer
Pin Description
Pin
2,3,11,12,15 5 7 8 1,6,13,16 4,9,10,14
Signal
SDRAM [0.4] BUF_IN SDATA SCLK VDD VSS
Type
I I I/O I Power Ground
Qty
5 1 1 1 4 4
De s cription
Buffered Clock Outputs Clock Buffer Input Serial Data for I2C interface, internal pull- up Serial Clock for I2C interface, internal pull- up 3.3V Power Supply Ground
I2C Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W 0
Serial Configuration Map
Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 12 11 3 2
De s cription SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 15
De s cription NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) SDRAM4 (Active/Inactive)
Note: Inactive means outputs are held LOW and are disabled from switching
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PS8318E
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PI6C185-01 Precision 1-5 Clock Buffer
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C185-01 is a slave receiver device. It can not be read back. Sub-addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH-to-LOW transition on SDATA while SCLK is HIGH indicates a "start" condition. A LOW-to-HIGH transition on SDATA while SCLK is HIGH is a "stop" condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device's own address is detected, PI6C185-01 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (0D2H), two more bytes must be sent: 1. "Command Code" byte, and 2. "Byte Count" byte. Although the data bits on these two bytes are "don't care," they must be sent and acknowledged.
1 2 3 4 5 6
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................... -65C to +150C Ambient Temperature with Power Applied ....... -40C to +85C 3.3V Supply Voltage to Ground Potential ........... -0.5V to +4.6V DC Input Voltage .............................................. -0.5V to +4.6V
7 8 9 10 11 12 13 14 15
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol IDD IDD IDD IDD Parame te r Supply Current Supply Current Supply Current Supply Current Te s t Condition BUF_IN = 0 MHz BUF_IN = 66.66 MHz BUF_IN = 100.0 MHz BUF_IN = 133.3 MHz 70 120 200 M in. Typ. M ax. 3 mA Units
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PS8318E
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PI6C185-01 Precision 1-5 Clock Buffer
DC Operating Specifications (VDD = +3.3V 5%, TA = 0C - 70C)
Symbol Input Voltage VIH VIL IIL Input High Voltage Input Low Voltage Input Leakage Current 0 < VIN < VDD VDD 2.0 VSS -0.3 -5 VDD +0.3 0.8 +5 A V Parame te r Condition M in. M a x. Units
VDD = 3.3V 5% VOH VOL Output High Voltage Output Low Voltage IOH = - 1mA IOL = 1mA 2.4 0.4 V
CIN COUT LPIN TA
Input Pin Capacitance Output pins Capacitance Pin Inductance Ambient Temperature No Airflow 0
5 6 7 70
pF nH C
SDRAM Clock Buffer Operating Specification
Symbol IOHMIN IOHMAX IOLMIN IOLMAX Parame te r Pull- up current Pull- up current Pull- down current Pull- down current Condition VOUT = 2.0V VOUT = 3.135V VOUT = 1.0V VOUT = 0.4V 3.3V 5% @0.4V- 2.4V 3.3V 5% @2.4V- 0.4V 1.5 1.5 54 53 4 V/ns tFHSDRAM Output fall edge rate SDRAM only 4 M in. Typ. M ax. Units -54 -46 mA
tRHSDRAM Output rise edge rate SDRAM only
AC Timing
66 MHz Min. Max. TDSKP SDRAM CLK period 15.0 15.5 TSDKH SDRAM CLK high time 5.6 TSDKL SDRAM CLK low time 5.3 TSDRISE SDRAM CLK rise time 1.5 4.0 TSDFALL SDRAM CLK fall time 1.5 4.0 t PLH SDRAM Buffer LH prop delay 1.0 5.5 t PHL SDRAM Buffer HL prop delay 1.0 5.5 DutyCycle Measured at 1.5V 45 55 tSDSKW SDRAM Output to Output Skew 250 Symbol Parameter 100 MHz Min. Max. 10.0 10.5 3.3 3.1 1.5 4.0 1.5 4.0 1.0 5.0 1.0 5.0 45 55 250 133 MHz Min. Max. 7.5 8.0 2.2 2.0 1.4 4.0 1.4 4.0 1.0 5.0 1.0 5.0 45 55 250 Units ns ns ns V/ns V/ns ns ns % ps
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Output Buffer Test Point
PI6C185-01 Precision 1-5 Clock Buffer
1 2
Test Load
tSDKP tSDKH
3 4
tSDKL
3.3V Clocking Interface (TTL)
2.4 1.5 0.4
5 6
tSDRISE
tSDFALL
Input Waveform tplh Output Waveform
1.5V
1.5V tphl 1.5V 1.5V
7 8 9 10 11 12 13 14 15
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock SDRAM M in Load M ax Load 20 30 Units pF Note s SDRAM DIMM Specification
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
Design Guidelines to Reduce EMI
1. Place R series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10 pF. R Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of "vias" of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
S S
5
PS8318E
10/14/04
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PI6C185-01 Precision 1-5 Clock Buffer
100/66 MHz Clock from Chipset
SDRAM
5
Rs CL
SDRAM DIMM Spec.
Figure 2. Design Guidelines Packaging Mechanical: 16-Pin TSSOP (L)
16
.169 .177
4.3 4.5
1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 SEATING PLANE 0.45 .018 0.75 .030 .252 BSC 6.4
0.09 0.20
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
6
PS8318E
10/14/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C185-01 Precision 1-5 Clock Buffer
Packaging Mechanical: 16-Pin QSOP (Q)
1 2
.008 0.20 MIN.
.008 .013 0.20 0.33 Guage Plane
16
.150 .157
3.81 3.99
3 4
.010 0.254
1
.189 .197 4.80 5.00 .008 0.203 REF .053 1.35 .069 1.75
Detail A
.016 .035 0.41 0.89
.041 1.04 REF
0-6
.015 x 45 0.38
Detail A
.007 .010
0.178 0.254
5 6 7 8
SEATING PLANE .004 0.101 .010 0.254
0.41 .016 1.27 .050 .228 .244 5.79 6.19
.025 BSC 0.635
.008 .012 0.203 0.305
X.XX DENOTES DIMENSIONS IN MILLIMETERS X.XX
Ordering Information
Ordering Code PI6C185-01L PI6C185-01LE PI6C185-01Q PI6C185-01QE PI6C185-01QI PI6C185-01QIE Packaging Code L L Q Q Q Q Package Description 16-Pin TSSOP Pb-free & Green, 16-Pin TSSOP 16-Pin QSOP Pb-free & Green, 16-Pin QSOP 16-Pin QSOP Pb-free & Green, 16-Pin QSOP Operating Temperature Commercial Commercial Commercial Commercial Industrial Industrial
9 10 11 12 13 14 15
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8318E 10/14/04

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