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| aqlN/|--1/2q Weltrend Semiconductor, Inc. WT6804 Monitor On-Screen Display Data Sheet REV. 1.02 August 17, 2001 The information in this document is subject to change without notice. (c)Weltrend Semiconductor, Inc. All Rights Reserved. *s|Ei3/4Cu*~eIu*~FEo 24 21/4O th 2F, No. 24, Industry E. 9 RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw WT6804 Data Sheet Rev. 1.02 GENERAL DESCRIPTION The WT6804 is an on-screen display (OSD) IC which display color symbols or characters onto monitor. 2 With the control of microcontroller through I C interface, it can display characters with special effect like blinking or shadowing automatically. FEATURES * * * * * * * * * * * * * * * * * * Programmable horizontal resolutions up to 1530 dots per line Horizontal frequency up to 120KHz On-chip PLL up to 100MHz Fully programmable character array of 15 rows by 30 columns 12x18 dot matrix per character 256 characters and graphic symbols ROM including 16 multi-color fonts 8 colors per display character 7 colors per display character background 4 programmable windows Double character height and width control Programmable character height (18 to 71 lines) Programmable row-to-row spacing Programmable vertical and horizontal positioning for display screen center Bordering, shadowing and blinking effect Fade-in/fade-out effects 2 I C interface with slave address $7AH Power supply : 5V Package type : 16-pin plastic DIP/SOP PIN CONFIGURATION Weltrend Semiconductor, Inc. Page 2 WT6804 Data Sheet Rev. 1.02 PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC LF VDDA HFLB CLKIN SDA SCL VDD VFLB POUT FBKG BOUT GOUT ROUT VSS I I I I Pin Name VSSA I/O Analog ground. No connection. I/O Loop filter of PLL. Analog power supply Horizontal sync input. External clock input. 2 Description I/O Serial data of I C interface. Serial clock of I C interface. Digital power supply Vertical sync input. O Programmable general purpose output pad Fast Blanking output. This pin controls the mixer of vedio O amplifier to cutoff the video signal while displaying character or window. O Blue color output O Green color output O Red color output Digital ground 2 Weltrend Semiconductor, Inc. Page 3 WT6804 Data Sheet Rev. 1.02 FUNCTIONAL DESCRIPTION I2C Interface This is a slave mode I C interface which address is $7AH. There are three data transmission formats for writing: Format (a), (b) and (c). Format (a): S 01111010 A ROW A COL A Data A ROW A COL A Data A ***** 2 P Format (b): S 01111010 A ROW A COL A Data A COL A Data A COL A ***** P Format (c): S 01111010 A ROW A COL A Data A Data A Data A Data A ***** P Where S = START condition R/W = Read/Write control bit. "1" means READ operation and "0" means WRITE operation. A = Acknowledge bit. "0" means acknowledge. P = STOP condition ROW = Row address byte COL = Column address byte Data = Data byte Format (a) is used when write data in different row and column address. Format (b) is used when write data in the same row. Format (c) is suitable for writing data sequentially. The column address will increase automatically. Format (a)/ (b), Format (a)/ (c), Format (b)/ (a) or Format (b)/ (c) is allowed. But Format (c)/ (a) and Format (c)/ (b) is not allowed. Transmission Format Address Row Address Bytes Control Bytes Columna,b Columnc Row Attribute Bytes Columna,b Columnc Bit7 1 0 0 1 0 0 Bit6 0 0 1 0 0 1 Bit5 0 x x 1 x x Bit4 D D D D D D Bit3 D D D D D D Bit2 D D D D D D Bit1 D D D D D D Bit0 D D D D D D Format a,b,c a,b c a,b,c a,b c "x" : Don't care. Weltrend Semiconductor, Inc. Page 4 WT6804 Data Sheet Rev. 1.02 Display RAM and Row Control Register DISPLAY RAM The display RAM stores the data to be displayed. Address byte determines display character and attribute bytes determines character background, character color and blinking effect. The memory location is shown as below. 0 0 COLUMN 29 30 31 0 R O W 14 CHARACTER Address ROW Control Reserved Register 14 0 0 COLUMN 29 30 31 0 R O W 14 CHARACTER Attribute Reserved Reserved 14 Weltrend Semiconductor, Inc. Page 5 WT6804 Data Sheet Rev. 1.02 Address Byte (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 ( 0, 0) : (14,29) W CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 CA7~CA0 - Address of Character ROM Attribute Byte (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 ( 0, 0) : (14,29) W -- BG_R BG_G BG_B BLINK CH_R CH_G CH_B BG_R, BG_G, BG_B - Background color of its corresponding character. BLINK - Enable blinking effect of its corresponding character. The blinking speed is controlled by BNK1 and BNK0 bits. CH_R, CH_G, CH_B - Color of its corresponding character. CH_R 0 0 0 0 1 1 1 1 CH_G 0 0 1 1 0 0 1 1 CH_B 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White BG_R 0 0 0 0 1 1 1 1 BG_G 0 0 1 1 0 0 1 1 BG_B 0 1 0 1 0 1 0 1 Color Background Blue Green Cyan Red Magenta Yellow White ROW Control Register (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 ( 0,30) : (14,30) W -- -- -- -- -- -- DCH DCW DCH - Double Character height DCW - Double Character width. The character width of even column (column 0, 2, 4, 6, ....) is doubled and the odd column will not display. Note: 1) Writing data into RAM must enable PLL or using external clock. 2 2) The I C interface clock frequency must less than 1/24 PLL clock frequency when writing RAM. Weltrend Semiconductor, Inc. Page 6 WT6804 Data Sheet Rev. 1.02 Window Control Window 1 has the highest priority and window 4 is the least. If window overlapping occurs, the higher priority covers the lower and the higher priority color will take over on the overlap window area. Window 1 Control Registers (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,0) (15,1) (15,2) W W W W1RS3 W1CS4 W1CE4 W1RS2 W1CS3 W1CE3 W1RS1 W1CS2 W1CE2 W1RS0 W1CS1 W1CE1 W1RE3 W1CS0 W1CE0 W1RE2 W1EN W1_R W1RE1 -W1_G W1RE0 W1SHD W1_B W1RS3~0 - Window 1 Row start address W1RE3~0 - Window 1 Row end address W1CS4~0 - Window 1 Column start address W1CE4~0 - Window 1 Column end address W1EN - Enable Window 1. Default value = 0 W1SHD - Enable the shadow effect of the window 1. Default value = 0 W1_R, W1_G, W1_B - Define the color of window 1 Window 2 Control Registers (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,3) (15,4) (15,5) W W W W2RS3 W2CS4 W2CE4 W2RS2 W2CS3 W2CE3 W2RS1 W2CS2 W2CE2 W2RS0 W2CS1 W2CE1 W2RE3 W2CS0 W2CE0 W2RE2 W2EN W2_R W2RE1 -W2_G W2RE0 W2SHD W2_B Window 3 Control Registers (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,6) (15,7) (15,8) W W W W3RS3 W3CS4 W3CE4 W3RS2 W3CS3 W3CE3 W3RS1 W3CS2 W3CE2 W3RS0 W3CS1 W3CE1 W3RE3 W3CS0 W3CE0 W3RE2 W3EN W3_R W3RE1 -W3_G W3RE0 W3SHD W3_B Window 4 Control Registers (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,9) (15,10) (15,11) W W W W4RS3 W4CS4 W4CE4 W4RS2 W4CS3 W4CE3 W4RS1 W4CS2 W4CE2 W4RS0 W4CS1 W4CE1 W4RE3 W4CS0 W4CE0 W4RE2 W4EN W4_R W4RE1 -W4_G W4RE0 W4SHD W4_B Weltrend Semiconductor, Inc. Page 7 WT6804 Data Sheet Rev. 1.02 Frame Control Register OSD Vertical Starting Position Register This register controls the vertical displacement from top. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,12) W VS7 VS6 VS5 VS4 VS3 VS2 VS1 VS0 Default Value = $04h Minimum value = $01h VS7~VS0 - Vertical starting position. Each step is 4 Horizontal lines. Vertical starting position = (VS x 4) +2 VFL B R,G,B Output VS OSD Horizontal Starting Position Register This register controls the vertical displacement from top. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,13) W HS7 HS6 HS5 HS4 HS3 HS2 HS1 HS0 Default Value = $0Fh Minimum value = $01h HS7~HS0 - Horizontal starting position. Each step is 6 dots. Horizontal starting position = (HS x 6) + 45 dot + PLL phase error HFL B R,G,B Output HS Weltrend Semiconductor, Inc. Page 8 WT6804 Data Sheet Rev. 1.02 Character Height Enlargement Register This register enlarges the character height. The enlargement is done by repeating lines of every row. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,14) W -- CH6 CH5 CH4 CH3 CH2 CH1 CH0 Default Value = $00h CH6~CH0 - Define the enlargement of character height. CH6 CH5 CH4 CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 1 1 1 1 1 X X X X X X X X 0 0 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 Total Lines 18 19 20 22 26 33 34 35 36 53 54 70 71 Repeat Line 0 1 2 3 4 5 6 7 8 v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v 9 10 11 12 13 14 15 16 17 v v v v v v For example, if CH[6:0] = $02h, insert line#4 and line#12. Weltrend Semiconductor, Inc. Page 9 WT6804 Data Sheet Rev. 1.02 Horizontal Resolution Register This register controls the pixel clock frequency which is multiplied by HFLB input. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,15) W -- HR6 HR5 HR4 HR3 HR2 HR1 HR0 Default Value = $40h HR6~HR0 - Define the Horizontal resolution (i.e. pixels per horizontal line). VCO frequency is ( HR[6:0] x12 +6) x fHFLB . HFLB Phase Detector Loop Filter VCO Pixel Clock / HRR / 12 Row-to-Row Spacing Register This register controls the row-to-row spacing. It adds line(s) below each row. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,16) W -- -- -- RSP4 RSP3 RSP2 RSP1 RSP0 Default Value = $00h RSP4~RSP0 - Define the line(s) below each row. Display Control Register (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,17) W ENOSD BSEN SHADW FADE BLANK WINCLR RAMCLR FBKGC Default Value = $00h ENOSD - Enable OSD Display. BSEN - Enable bordering and shadowing effect SHADW - "1" : Shadowing. "0" : Bordering FADE - Fade in /Fade out Enable BLANK - Force FBKG pin output high level when this bit is set. WINCLR - Clear all window enable bits. (W1EN ~ W4EN) RAMCLR - Clear all ADDRESS bytes, BG_R, BG_G, BG_B and BLINK bits of display RAM. FBKGC - FBKG pin control. "0" : FBKG pin active during display character or window "1" : FBKG pin active during display character only. The polarity of FBKG pin is controlled by FBKGP bit. Weltrend Semiconductor, Inc. Page 10 WT6804 Data Sheet Rev. 1.02 Normal Output Control Register (Row,Col) R/W Bit 7 Shadow Effect Border Effect Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,18) W TRIC FBKGP -- SELVCL HPOL VPOL VCO1 VCO0 Default Value = $FCh TRIC - Tri-state control of ROUT, GOUT, BOUT and FBKG pin. "1" - When OSD is disabled, these pins will drive low. "0" - When OSD is disabled, these pins will be in high impedance state FBKGP - Controls the polarity of FBKG pin. "0" - Negative polarity. "1" - Positive polarity. SELVCL - Auto synchronize Hsync with Vsync. "0" - Disable. "1" - Enable. HPOL - "1": Accept positive polarity of Hsync input. "0" : Accept negative polarity of Hsync input. VPOL - "1": Accept positive polarity of Vsync input. "0" : Accept negative polarity of Vsync input. VCO1,VCO0 - VCO control VCO1 0 0 1 1 VCO0 0 1 0 1 Frequency Range >104MHz 13MHz ~ 26MHz 26MHz ~ 52MHz 52MHz ~ 104MHz Weltrend Semiconductor, Inc. Page 11 WT6804 Data Sheet Rev. 1.02 Shadow and Border Effect (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,19) W -- WS_R WS_G WS_B -- CS_R CS_G CS_B WS_R, WS_G, WS_B - Define the color of window shadow CS_R, CS_G, CS_B - Define the color of character shadow or border WS_R 0 0 0 0 1 1 1 1 WS_G 0 0 1 1 0 0 1 1 WS_B 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White Weltrend Semiconductor, Inc. Page 12 WT6804 Data Sheet Rev. 1.02 Multi-color Font The character ROM has 256 fonts and16 multi-color fonts. Each character font has 12 dots width and 18 lines height. Multi-color font character address is located from $F0h to $FFh when CFONT bit is set. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,20) W -- -- -- -- -- -- -- CFONT Defualt = $00h CFONT - Enable multi-color font character when this bit is set. Multi-color font color table R G B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Color Background color Blue Green Cyan Red Magenta Yellow White + + Yellow Blue R Font G Font B Font Color Font Weltrend Semiconductor, Inc. Page 13 WT6804 Data Sheet Rev. 1.02 Window Shadow Width Register This register controls the width of window shadow. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,21) W WSW41 WSW40 WSW31 WSW30 WSW21 WSW20 WSW11 WSW10 WSW41,WSW40 - Shadow width of Window 4. WSW31,WSW30 - Shadow width of Window 3. WSW21,WSW20 - Shadow width of Window 2. WSW11,WSW10 - Shadow width of Window 1. Width = (bit value x 2) + 2 dots Window Shadow Height Register This register controls the height of window shadow. (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,22) W WSH41 WSH40 WSH31 WSH30 WSH21 WSH20 WSH11 WSH10 WSH41,WSH40 - Shadow height of Window 4. WSH31,WSH30 - Shadow height of Window 3. WSH21,WSH20 - Shadow height of Window 2. WSH11,WSH10 - Shadow height of Window 1. Height = (bit value x 2) + 2 lines Widow Shadow Height Widow Shadow Width Weltrend Semiconductor, Inc. Page 14 WT6804 Data Sheet Rev. 1.02 Fade in/Fade out Effect The fade-in/fade-out effect can be controlled either in horizontal direction only, vertical direction only or both direction. Fade in/out Control Register (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,23) W DISH DISV FVC1 FVC0 BKS1 BKS0 -- HORR Default Value = $00h DISH : Disable fade in/out horizontal direction. Increment/decrement one column per frame. DISV : Disable fade in/out vertical direction FVC1,FVC0 : Fade in/out vertical speed control 00 - increment/decrement 1 row per frame 01 - increment/decrement 2 row per frame 10 - increment/decrement 3 row per frame 11 - increment/decrement 4 row per frame BKS1,BKS0 : Blinking speed select 00 - 32 frames on, 32 frames off 01 - 40 frames on, 40 frames off 10 - 48 frames on, 48 frames off 11 - 56 frames on, 56 frames off HORR : Extension bit of horizontal resolution. VCO frequency is ( HR[6:0] x12 + HORRx6 +6) x fHFLB Enable horizontal direction only. Enable vertical direction only. Enable both direction. Weltrend Semiconductor, Inc. Page 15 WT6804 Data Sheet Rev. 1.02 RGB Output Control (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,24) W POC ROC GOC BOC PO RO GO BO Default = $00h POC: POUT pin output control "0" : POUT pin is tri-state "1" : POUT pin is output ROC: ROUT pin output control "0" : OSD red color output "1" : General output pin. The output level is controlled by RO bit GOC: GOUT pin output control "0" : OSD green color output "1" : General output pin. The output level is controlled by GO bit BOC: BOUT pin output control "0" : OSD blue color output "1" : General output pin. The output level is controlled by BO bit PO: POUT pin output level when POC bit is 1 "0" : POUT pin outputs low "1" : POUT pin outputs high RO: ROUT pin output level when ROC bit is 1 "0" : ROUT pin outputs low "1" : ROUT pin outputs high GO: GOUT pin output level when GOC bit is 1 "0" : GOUT pin outputs low "1" : GOUT pin outputs high BO: BOUT pin output level when BOC bit is 1 "0" : BOUT pin outputs low "1" : BOUT pin outputs high Weltrend Semiconductor, Inc. Page 16 WT6804 Data Sheet Rev. 1.02 Clock Source Selection Register (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,25) W ENPLL CLKS -- -- CKP CKD2 CKD1 CKD0 Default = $80h ENPLL - "1" : Enable PLL. "0" : Disable PLL. CLKS - Clock source select. "0" : From PLL. "1" : External clock from CLKIN pin. (For LCD monitor use) When CLKS=1, CKP control the polarity of CLKIN pin. If CKP =0, no change of CLKIN polarity. If CKP =1, reverse the polarity of CLKIN. CKD2~ CKD0 select the pixel clock delay time from CLKIN pin. CKD [2:0] 000 001 010 011 100 101 110 111 Delay Time No delay. Delay 2ns. Delay 4ns. Delay 6ns. Delay 8ns. Delay 10ns. Delay 12ns. Delay 14ns. Weltrend Semiconductor, Inc. Page 17 WT6804 Data Sheet Rev. 1.02 Reset Write (16,31) register will reset all registers same as power on reset. All registers are set to default value. TEST Mode (Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 (15,31) W -- -- TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 Default $00h For CRT monitor use, this register must keep $00h. For LCD monitor, this register must be $08h. ( Set TEST3 bit) Weltrend Semiconductor, Inc. Page 18 WT6804 Data Sheet Rev. 1.02 REGISTER MAP (Row,Col) R/W Initial Value Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Address Byte ( 0, 0) : (14,29) ( 0, 0) : (14,29) ( 0,30) : (14,30) (15,0) (15,1) (15,2) (15,3) (15,4) (15,5) (15,6) (15,7) (15,8) (15,9) (15,10) (15,11) (15,12) (15,13) (15,14) (15,15) (15,16) (15,17) (15,18) (15,19) (15,20) (15,21) (15,22) (15,23) (15,24) (15,25) (15,31) W b'00000000 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Attribute Byte W b'xxxx0000 -BG_R BG_G BG_B BLINK CH_R CH_G CH_B Address Byte W W W W W W W W W W W W W W W W W W W W W W W W W W W W b'xxxxxx00 --W1RS2 W1CS3 W2RS2 W2CS3 W3RS2 W3CS3 W4RS2 W4CS3 VS6 HS6 CH6 HR6 -BSEN FBKGP WS_R --W1RS1 W1CS2 W2RS1 W2CS2 W3RS1 W3CS2 W4RS1 W4CS2 VS5 HS5 CH5 HR5 -SHADW -WS_G --W1RS0 W1CS1 W2RS0 W2CS1 W3RS0 W3CS1 W4RS0 W4CS1 VS4 HS4 CH4 HR4 RSP4 FADE SELVCL WS_B ---DCH W1RE1 -W1_G W2RE1 -W2_G W3RE1 -W3_G W4RE1 -W4_G VS1 HS1 CH1 HR1 RSP1 VCO1 CS_G -WSH11 -GOUT CKD1 TEST1 DCW W1RE0 W1SHD W1_B W2RE0 W2SHD W2_B W3RE0 W3SHD W3_B W4RE0 W4SHD W4_B VS0 HS0 CH0 HR0 RSP0 VCO0 CS_B CFONT WSH10 HORR BOUT CKD0 TEST0 b'xxxxxxxx W1RS3 b'xxxxx0x0 W1CS4 b'xxxxxxxx W2RS3 b'xxxxx0x0 W2CS4 b'xxxxxxxx W3RS3 b'xxxxx0x0 W3CS4 b'xxxxxxxx W4RS3 b'xxxxx0x0 W4CS4 b'00000100 b'00001111 b'x0000000 b'x0000100 b'xxx00000 b'11x11100 b'xxxxxxxx b'xxxxxxx0 VS7 HS7 ---TRIC --- W1RE3 W1RE2 W1CS0 W1EN W1_R W2EN W2_R W3EN W3_R W4EN W4_R VS2 HS2 CH2 HR2 RSP2 VPOL CS_R -- b'xxxxxxxx W1CE4 W1CE3 W1CE2 W1CE1 W1CE0 W2CS0 W2RE3 W2RE2 b'xxxxxxxx W2CE4 W2CE3 W2CE2 W2CE1 W2CE0 W3CS0 W3RE3 W3RE2 b'xxxxxxxx W3CE4 W3CE3 W3CE2 W3CE1 W3CE0 W4CS0 VS3 HS3 CH3 HR3 RSP3 HPOL --- W4RE3 W4RE2 b'xxxxxxxx W4CE4 W4CE3 W4CE2 W4CE1 W4CE0 b'00000000 ENOSD BLANK WINCLR RAMCLR FBKGC b'xxxxxxxx WSW41 WSW40 WSW31 WSW30 WSW21 WSW20 WSW11 WSW10 b'xxxxxxxx WSH41 WSH40 WSH31 WSH30 WSH21 WSH20 b'00000000 b'00000000 b'00000000 DISH POC -DISV ROC CLKS -FVC1 GOC -TEST5 FVC0 BOC -TEST4 BKS1 POUT CKP TEST3 BKS0 ROUT CKD2 TEST2 b'10xx0000 ENPLL Weltrend Semiconductor, Inc. Page 19 WT6804 Data Sheet Rev. 1.02 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter DC Supply Voltage (VDD) Input and output voltage with respect to Ground Storage temperature Ambient temperature with power applied Min. -0.3 -0.3 -25 0 Max. 7.0 VDD+0.3 125 85 Units V V o o C C *Note: Stresses above those listed may cause permanent damage to the devices D.C Characteristics (VDD=5.0V5%, Ta=0-70C) Symbol VDD VIH,I2C VIL,I2C VIL,SYNC VOH VOL IIL IDD VRESET Parameter Supply Voltage SDA and SCL Input High Voltage SDA and SCL Input Low Voltage Sync Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Operating Current Low VDD Reset Voltage IOH = -6mA IOL = 6mA 0V A.C Characteristics (VDD=5.0V, Ta=0-70C) Symbol tRISE Parameter Rise time (ROUT,GOUT,BOUT and FBKG pins) Fall time (ROUT,GOUT,BOUT and FBKG pins) HFLB Input Frequency VFLB Input Frequency PLL Frequency Condition Cload=20pF Min. Typ. 2.5 Max. 4 Units ns tFALL fHFLB fVFLB FPLL Cload=20pF 10 4 13 2.5 - 4 120K 2047 104 ns Hz H lines MHz Weltrend Semiconductor, Inc. Page 20 WT6804 Data Sheet Rev. 1.02 I2C Timing Symbol fSCL tBF tHD,START tSU,START tHIGH,SCL tLOW,SCL tHD,DATA tSU,DATA tRISE,I2C tFALL,I2C tSU,STOP Bus free time Hold time for START condition Set-up time for START condition SCL clock high time SCL clock low time Hold time for DATA input Hold time for DATA output Set-up time for DATA input Set-up time for DATA output SCL and SDA rise time SCL and SDA fall time Set-up time for STOP condition Parameter SCL input clock frequency Min. 0 2 1 1 1 1 0 80 20 100 1 Typ. Max. 100 1 300 Units kHz us us us us us ns ns ns ns us ns us tBF SDA1 tHD,START SCL1 tSU,STOP tLOW,SCL tHD,DATA tHIGH,SCL tSU,DATA tSU,START tRISE tFALL Weltrend Semiconductor, Inc. Page 21 WT6804 Data Sheet Rev. 1.02 TYPICAL APPLICATION CIRCUIT This circuit is for reference only. WT6804 100u 0.1u VSSA VSS ROUT VCO GOUT BOUT FBKG POUT VFLB VDD 0.22u 1K ROUT GOUT BOUT FBKG 4700P HSYNC 100 SDA SCL 100 4.7K +5V 100uH VDDA HFLB CLKIN SDA SCL To Video Amplifier VSYNC +5V 0.1u 100u Weltrend Semiconductor, Inc. Page 22 WT6804 Data Sheet Rev. 1.02 PACKAGE OUTLINE PDIP 16-pin package Package typeG16 Pin DIP 300mil SYMBOLS A A1 A2 B C D E E1 F L MIN 0.015 0.125 NOR UNITGINCH MAX 0.210 0.135 0.735 0.245 0.115 0.335 0 0.130 0.018 0.060 0.755 0.300 BSC 0.250 0.100 0.130 0.355 7 0.775 0.255 0.150 0.375 15 eB cX Weltrend Semiconductor, Inc. Page 23 |
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