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Datasheet File OCR Text:

PCI6050
Serial PCI to PCI Bridge
Data Manual
June 2000
MSDS Bus Solutions
SLLS434A
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Contents
Section
1
Title
Page
1-1 1-1 1-1 1-2 1-2 2-1 3-1 3-1 3-2 3-2 3-2 3-3 3-3 3-4 3-4 3-6 3-7 3-7 3-7 3-7 3-7 3-7 3-8 3-8 3-8 3-8 3-8 3-8 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-14 3-15
2 3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction to the PCI6050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 PCI6050 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Protocol Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Start Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Packet Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Secondary PCI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Special Cycle Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 Primary Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Decode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 System Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Posted Write Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Posted Write Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 Target Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 Master Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 Master Delayed Write Timeout . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 Master Delayed Read Timeout . . . . . . . . . . . . . . . . . . . . . . . 3.9.7 Secondary SERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Parity Handling and Parity Error Reporting . . . . . . . . . . . . . . . . . . . . . . 3.11 Master and Target Abort Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Discard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 CompactPCI Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
4
5
3.17.1 Behavior in Low Power States . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Serial ROM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Vendor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Primary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Primary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Secondary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Secondary Bus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . 4.15 I/O Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 I/O Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Prefetchable Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 Prefetchable Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Prefetchable Base Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4.23 Prefetchable Limit Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4.24 I/O Base Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 I/O Limit Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Chip Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Primary SERR Event Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Primary GPIO Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Primary GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Primary GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Primary CLKOUT Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Primary SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Secondary CLKOUT Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Secondary SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-15 3-15 4-1 4-2 4-2 4-3 4-4 4-5 4-5 4-5 4-6 4-6 4-6 4-7 4-7 4-7 4-8 4-8 4-8 4-9 4-10 4-10 4-10 4-11 4-11 4-12 4-12 4-12 4-13 4-13 4-13 4-14 5-1 5-1 5-2 5-3 5-4 5-5 5-5 5-6 5-7 5-8 5-9 5-10
iv
5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 5.32
General Purpose Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Diagnostic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary GPIO Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . Secondary GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . Secondary GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Error Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transceiver Test Control and Status Register . . . . . . . . . . . . . . . . . . . PM Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PM Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . PMCSR Bridge Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary CPCI Hot Swap Control and Status Register . . . . . . . . . . . . . Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11 5-12 5-13 5-13 5-14 5-14 5-14 5-15 5-15 5-16 5-16 5-17 5-18 5-18 5-19 5-19 5-19 5-20 5-20 5-21 5-21
List of Illustrations
Figure Title Page 2-1 PCI6050 Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3-1 The PCI-to-PCI Bridge Implementation With PCI6050 Device . . . . . . . . . . . 3-1 3-2 PCI6050 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-3 Packet Format and Bit Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-4 AD[31-0] During Address Phase of a Type 0 Configuration Cycle . . . . . . . 3-4 3-5 AD[31-0] During Address Phase of a Type 1 Configuration Cycle . . . . . . . 3-5 3-6 Bus Hierarchy and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-7 Secondary PCI Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-8 Serial ROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
v
List of Tables
Table Title 2-1 Terminal Signal Names Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . 2-2 Terminal Signal Names Sorted Alphabetically to Terminal Number . . . . . . . 2-3 PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 PCI Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Secondary PCI Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 PCI6060 Clock and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 PCI6060 Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 PCI6060 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 JTAG Interface Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 PCI Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 AD[31-16] During Address Phase of a Type 0 Configuration Cycle . . . . . . 3-3 JTAG Instructions and Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Boundary Scan Pin Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 PCI Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 PCI Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Chip Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Diagnostic Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Arbiter Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Primary SERR Event Disable Register Description . . . . . . . . . . . . . . . . . . . . 5-5 Primary GPIO Output Data Register Description . . . . . . . . . . . . . . . . . . . . . . 5-6 Primary GPIO Output Enable Register Description . . . . . . . . . . . . . . . . . . . . 5-7 Primary GPIO Input Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Primary CLKOUT Control Register Description . . . . . . . . . . . . . . . . . . . . . . . 5-9 Primary SERR Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Secondary CLKOUT Control Register Description . . . . . . . . . . . . . . . . . . . . 5-11 Secondary SERR Status Register Description . . . . . . . . . . . . . . . . . . . . . . . 5-12 General Purpose Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Extended Diagnostic Status Register Description . . . . . . . . . . . . . . . . . . . . 5-14 Secondary GPIO Output Data Register Description . . . . . . . . . . . . . . . . . . 5-15 Secondary GPIO Output Enable Register Description . . . . . . . . . . . . . . . . 5-16 Secondary GPIO Input Data Register Description . . . . . . . . . . . . . . . . . . . . Page 2-2 2-3 2-4 2-4 2-5 2-6 2-6 2-7 2-7 2-8 2-8 2-9 2-9 3-4 3-5 3-10 3-11 4-3 4-4 4-9 4-14 5-1 5-2 5-3 5-4 5-5 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-13 5-14
vi
5-17 5-18 5-19 5-20 5-21 5-22
Transceiver Test Control and Status Register Description . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . . Power Management Control/Status Register Description . . . . . . . . . . . . . . PMCSR Bridge Support Register Description . . . . . . . . . . . . . . . . . . . . . . . . Primary CPCI Hot Swap Control and Status Register Description . . . . . . FIFO BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15 5-17 5-18 5-18 5-20 5-21
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1 Introduction
The Texas Instruments PCI6050 symmetric serialized PCI-to-PCI bridge provides a high-performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI6050 device allows bridged transactions to occur concurrently on both buses. The PCI6050 pipeline architecture supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently. A PCI6050-based PCI-to-PCI bridge is compliant with the PCI Local Bus Specification and can be used to overcome trace length limitations by allowing PCI-to-PCI implementations to span across separate system boards, and extend the electrical loading limits of 10 devices per PCI bus and 1 PCI device per expansion slot by creating hierarchical buses. The PCI6050 device provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external secondary PCI bus arbiter. The compact-PCI hot-swap extended PCI capability is provided, which makes the PCI6050 device an ideal solution for multifunction compact PCI cards, remote chassis-to-chassis interconnects, and the adaptation of single function cards for hot-swap compliance.
1.1 Features
The PCI6050 device supports the following features: * * * * * * * * * * * * * * * Configurable for PCI Bus Power Management Interface Specification Provides CompactPCI hot-swap functionality 3.3-V PCI core logic with universal PCI interface compatible with 3.3-V and 5-V PCI signaling environments 2.5-V serial link core logic compatible with the PCI6060 transceiver Supports 32-bit, 33-MHz PCI buses Provides internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus arbiter Performs burst data transfers with pipeline architecture to maximize data throughput in both directions Independent read and write buffers for each direction Allows up to three delayed transactions in both directions Provides 10 secondary PCI clock outputs Predictable latency per PCI Local Bus Specification Propagates bus locking Secondary bus is driven low during reset Provides VGA/palette memory and I/O, and subtractive decoding options Advanced submicron, low-power CMOS technology
1.2 Related Documents
* * * *
Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0) PCI Local Bus Specification (Revision 2.2) PCI-to-PCI Bridge Architecture Specification (Revision 1.1) PCI Bus Power Management Interface Specification (Revision 1.1)
1-1
ADVANCE INFORMATION
* *
PICMG Compact-PCI Hot Swap Specification (Revision 1.0) Texas Instruments PCI6060 Product Data Manual
1.3 Trademarks 1.4 Ordering Information
DEVICE PCI6050
NAME Serial PCI-to-PCI Bridge
VOLTAGE
PACKAGE 208-Terminal QFP
ADVANCE INFORMATION
1-2
2 Terminal Descriptions
Figure 2-1 illustrates the terminals in the PCI6050 device.
RSVD GND RSVD RSVD PRBS_EN VCC2_5 RX_ER/PRBS_PASS RX_DV RXD15 GND RXD14 RXD13 VCC2_5 RXD12 RXD11 GND RXD10 RXD9 VCC2_5 RXD8 RX_CLK GND RXD7 RXD6 VCC2_5 RXD5 RXD4 GND RXD3 RXD2 VCC2_5 RXD1 RXD0 GND CLKOUT0 CLKOUT1 CLKOUT2 VCC3_3 CLKOUT3 CLKOUT4 CLKOUT5 GND CLKOUT6 CLKOUT7 CLKOUT8 CLKOUT9 VCC3_3 HS_LED HS_SWITCH HS_ENUM VCC3_3 RSVD 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
RSVD TX_ER LOOP_EN TX_EN TXD15 VCC2_5 TXD14 TXD13 GND TXD12 TXD11 VCC2_5 TXD10 TXD9 TXD8 GND TLK_CLK GND SYS_CLK VCC2_5 TXD7 TXD6 GND TXD5 TXD4 VCC2_5 TDX3 TXD2 GND TXD1 TXD0 VCC2_5 RSVD TDI TDO TMS TCK GND TRST VCC3_3 SCL SDA GPE REG33 REG18 REG2_EN GPIO0 GPIO1 GPIO2 GPIO3 EXTARB PRI/SEC
PCI6050
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
EXT_CLK_SEL GND REG18 REG23 REG1_EN ENT_CLK VCC3_3 AD0 AD1 AD2 GND AD3 AD4 AD5 VCC3_3 AD6 AD7 C/BE0 AD8 VCC3_3 AD9 AD10 AD11 GND AD12 VCCP AD13 VCC3_3 AD14 AD15 C/BE1 GND SERR PERR PAR VCC3_3 STOP DEVSEL TRDY VCC3_3 IRDY FRAME C/BE2 GND AD16 AD17 AD18 VCC3_3 AD19 AD20 AD21 GND
Table 2-1 lists the PCI6050 device terminals in numeric order; Table 2-2 presents them in alphabetic order with their corresponding terminal number.
CRC_EN GND INTD INTC INTB INTA VCC3_3 RSVD GNT8 GNT7 GNT6 GNT5 VCC3_3 GNT4 GNT3 GNT2 GNT1 GNT0 GND RSVD REQ8 REQ7 REQ6 REQ5 VCC3_3 REQ4 REQ3 REQ2 REQ1 REQ0 GND PCI_RST PCI_CLK VCCP GLOBAL_RST VCC3_3 AD31 AD30 AD29 VCC3_3 AD28 C/BE3 IDSEL GND AD27 AD26 AD25 VCC3_3 AD24 AD23 AD22 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Figure 2-1. PCI6050 Terminal Diagram
2-1
ADVANCE INFORMATION
Table 2-1. Terminal Signal Names Sorted by Terminal Number
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TERMINAL NAME CRC_EN GND INTD INTC INTB INTA VCC3_3 RSVD GNT8 GNT7 GNT6 GNT5 VCC3_3 GNT4 GNT3 GNT2 GNT1 GNT0 GND RSVD REQ8 REQ7 REQ6 REQ5 VCC3_3 REQ4 REQ3 REQ2 REQ1 REQ0 GND PCI_RST PCI_CLK VCCP GLOBAL_RST VCC3_3 AD31 AD30 AD29 VCC3_3 AD28 C/BE3 IDSEL GND AD27 AD26 AD25 VCC3_3 AD24 AD23 AD22 GND NO. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 TERMINAL NAME GND AD21 AD20 AD19 VCC3_3 AD18 AD17 AD16 GND C/BE2 FRAME IRDY VCC3_3 TRDY DEVSEL STOP VCC3_3 PAR PERR SERR GND C/BE1 AD15 AD14 VCC3_3 AD13 VCCP AD12 GND AD11 AD10 AD9 VCC3_3 AD8 C/BE0 AD7 AD6 VCC3_3 AD5 AD4 AD3 GND AD2 AD1 AD0 VCC3_3 EXT_CLK REG1_EN REG33 REG18 GND EXT_CLK_SEL NO. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 TERMINAL NAME RSVD VCC3_3 HS_ENUM HS_SWITCH HS_LED VCC3_3 CLKOUT9 CLKOUT8 CLKOUT7 CLKOUT6 GND CLKOUT5 CLKOUT4 CLKOUT3 VCC3_3 CLKOUT2 CLKOUT1 CLKOUT0 GND RXD0 RXD1 VCC2_5 RXD2 RXD3 GND RXD4 RXD5 VCC2_5 RXD6 RXD7 GND RX_CLK RXD8 VCC2_5 RXD9 RXD10 GND RXD11 RXD12 VCC2_5 RXD13 RXD14 GND RXD15 RX_DV RX_ER/PRBS_PASS VCC2_5 PRBSEN RSVD RSVD GND RSVD NO. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 TERMINAL NAME RSVD TX_ER LOOP_EN TX_EN TXD15 VCC2_5 TXD14 TXD13 GND TXD12 TXD11 VCC2_5 TXD10 TXD9 TXD8 GND TLK_CLK GND SYS_CLK VCC2_5 TXD7 TXD6 GND TXD5 TXD4 VCC2_5 TXD3 TXD2 GND TXD1 TXD0 VCC2_5 RSVD TDI TDO TMS TCK GND TRST VCC3_3 SCL SDA GPE REG33 REG18 REG2_EN GPIO0 GPIO1 GPIO2 GPIO3 EXTARB PRI/SEC
ADVANCE INFORMATION
2-2
Table 2-2. Terminal Signal Names Sorted Alphabetically to Terminal Number
TERMINAL NAME AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0 C/BE1 C/BE2 C/BE3 CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6 CLKOUT7 CLKOUT8 CLKOUT9 CRC_EN DEVSEL EXTARB EXT_CLK EXT_CLK_SEL FRAME NO. 97 96 95 93 92 91 89 88 86 84 83 82 80 78 76 75 60 59 58 56 55 54 51 50 49 47 46 45 41 39 38 37 87 74 62 42 122 121 120 118 117 116 114 113 112 111 1 67 207 99 104 63 TERMINAL NAME GLOBAL_RST GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNT0 GNT1 GNT2 GNT3 GNT4 GNT5 GNT6 GNT7 GNT8 GPE GPIO0 GPIO1 GPIO2 GPIO3 HS_ENUM HS_LED HS_SWITCH IDSEL INTA INTB INTC INTD IRDY LOOP_EN PAR PCI_CLK PCI_RST NO. 35 2 19 31 44 52 53 61 73 81 94 103 115 123 129 135 141 147 155 165 172 174 179 185 194 18 17 16 15 14 12 11 10 9 199 203 204 205 206 107 109 108 43 6 5 4 3 64 159 70 33 32 TERMINAL NAME PERR PRBSEN PRI/SEC REG1_EN REG18 REG18 REG2_EN REG33 REG33 REQ0 REQ1 REQ2 REQ3 REQ4 REQ5 REQ6 REQ7 REQ8 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RX_CLK RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RX_DV RX_ER/PRBS_PASS SCL SDA SERR STOP SYS_CLK TCK TDI NO. 71 152 208 100 102 201 202 101 200 30 29 28 27 26 24 23 22 21 8 20 105 153 154 156 157 189 136 124 125 127 128 130 131 133 134 137 139 140 142 143 145 146 148 149 150 197 198 72 68 175 193 190 TERMINAL NAME TDO TLK_CLK TMS TRDY TRST TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TX_EN TX_ER VCCP VCCP VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 NO. 191 173 192 66 195 187 186 184 183 181 180 178 177 171 170 167 166 164 163 161 160 158 34 79 126 132 138 144 151 162 168 176 182 188 7 13 25 36 40 48 57 65 69 77 85 90 98 106 110 119 196 169
2-3
ADVANCE INFORMATION
Table 2-3 lists the PCI system terminals and describes their function. Table 2-3. PCI System
TERMINAL NAME GLOBAL_RST NO. 35 TYPE I FUNCTION Global reset. GLOBAL_RST is used to initialize the PCI6050 device to its default state after power is applied. This reset must be supplied to both the primary and secondary nodes in order for the serial link to be established. Note that GLOBAL_RST serves as the only reset input to a secondary PCI6050 node. PCI clock. PCI_CLK provides timing for all PCI transactions with a maximum frequency of 33 MHz. All PCI bus signals are sampled at rising edge of PCI_CLK. PCI reset. For a primary PCI6050 node, PCI_RST is an input that causes the bridge to put all output buffers in a high-impedance state and reset all internal registers. For a secondary PCI6050 node, PCI_RST is the output to the secondary PCI bus that initiates a bus reset.
PCI_CLK PCI_RST
33 32
I I/O
Table 2-4 lists the PCI address and data terminals and describes their function. Table 2-4. PCI Address and Data
TERMINAL
ADVANCE INFORMATION
NAME AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3 C/BE2 C/BE1 C/BE0
NO. 37 38 39 41 45 46 47 49 50 51 54 55 56 58 59 60 75 76 78 80 82 83 84 86 88 89 91 92 93 95 96 97 42 62 74 87
TYPE I/O
FUNCTION PCI address and data bus. The AD[31-0] signals make up the multiplexed PCI address and data bus on the PCI interface. During the address phase of a PCI bus cycle, AD[31-0] contain a 32-bit address or other destination information. During each data phase of the transaction, AD[31-0] contain data.
I/O
PCI command and byte enables. During the address phase of a PCI bus cycle, C/ BE3-C/BE0 defines the bus command for the transaction. During the data phase, this 4-bit bus determines which byte lanes of the full 32-bit data bus carries meaningful data. C/BE0 applies to byte 0 (AD[7-0]), C/BE1 applies to byte 1 (AD[15-8]), C/BE2 applies to byte 2 (AD[23-16]), and C/BE3 applies to byte 3 (AD[31-24]).
2-4
Table 2-5 describes the PCI interface control signals. Table 2-5. PCI Interface Control
TERMINAL NAME DEVSEL NO. 67 TYPE I/O FUNCTION PCI device select. DEVSEL is driven by the target of a PCI transaction to claim the cycle. As a PCI master, the PCI6050 device monitors DEVSEL until a target responds. If no target responds before the time-out condition occurs, then the bridge terminates the cycle with a master abort. PCI cycle frame. FRAME is driven by the master of a PCI bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the primary bus transaction is in the final data phase. PCI bus grant. For a primary PCI6050 node, GNT0 is the PCI bus grant input and is driven by the primary PCI bus arbiter to grant the bridge access to the primary PCI bus after the current data transaction has completed. For a secondary PCI6050 node, GNT0 is an output from the internal bus arbiter to another secondary bus master. If the internal arbiter is disabled (external arbiter), then this terminal is the secondary PCI6050 PCI bus grant input. PCI initialization and device select. IDSEL selects a primary PCI6050 node during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus. This terminal is not used in secondary PCI6050 node applications and should be tied to a valid logic level. Note: The configuration space of the PCI6050 device can only be accessed from the primary bus. INTD INTC INTB INTA IRDY 3 4 5 6 64 I/O PCI interrupts. The PCI6050 device provides PCI interrupt routing from the secondary PCI bus to the primary PCI bus. The INTx terminals are inputs to a secondary PCI6050 node, which are transmitted to the primary PCI6050 node by way of the serial link. The primary PCI6050 node provides the interrupt information to the host system by way of the INTx terminal outputs. PCI initiator ready. IRDY indicates ability of the PCI bus master to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCI_CLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PCI parity. In all primary bus read and write cycles, the bridge calculates even parity across the AD and C/BE buses. As a master during PCI write cycles, the bridge outputs this parity indicator with one PCI_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the parity indicator driven by the master; a miscompare can result in a parity error assertion (PERR). PCI parity error. PERR is driven by a primary PCI6050 node when enabled through the command register to indicate that the calculated parity does not match the sampled PAR or that PERR was detected by the secondary PCI6050 node. For a secondary PCI6050 node, PERR is an input asserted by a secondary bus PCI device to indicate that calculated parity does not match the sampled PAR. PCI bus request. For a primary PCI6050 node, REQ0 is the PCI bus request output and is driven by the PCI6050 device to request access to the primary PCI bus after the current data transaction has completed. For a secondary PCI6050 node, REQ0 is an input to the internal bus arbiter from another secondary bus master. If the internal arbiter is disabled (external arbiter), then this terminal is the secondary PCI6050 PCI bus request output. PCI system error. SERR is driven by a primary PCI6050 node to indicate that a critical system error has occurred or that SERR was detected on one of the subordinate buses downstream from the secondary PCI6050 node. The assertion need not be from the target of the primary PCI cycle. For a secondary PCI6050 node, SERR is an input asserted by a secondary bus PCI device to indicate that a critical system error has occurred. PCI cycle stop. STOP is driven by a PCI target to request that the initiator stop the current PCI bus transaction. This signal is used for target disconnects and is commonly asserted by target devices which do not support multiple data transfers. PCI target ready. TRDY indicates the ability of the PCI bus target to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both IRDY and TRDY are asserted. Until both IRDY and TRDY are both sampled asserted, wait states are inserted.
FRAME
63
I/O
GNT0
18
I/O
IDSEL
43
I
I/O
PAR
70
I/O
PERR
71
I/O
REQ0
30
I/O
SERR
72
I/O
STOP
68
I/O
TRDY
66
I/O
2-5
ADVANCE INFORMATION
Table 2-6 describes the PCI clock signals; Table 2-7 describes the secondary PCI arbitration and control signals. Table 2-6. PCI Clock Distribution
TERMINAL NAME CLKOUT9 CLKOUT8 CLKOUT7 CLKOUT6 CLKOUT5 CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1 CLKOUT0 EXT_CLK NO. 111 112 113 114 116 117 118 120 121 122 99 TYPE O FUNCTION PCI clocks outputs. CLKOUT[9-0] provide timing for all transactions on the secondary PCI bus. Each secondary bus device samples all secondary PCI signals at the rising edge of its corresponding CLKOUT input. If CLKOUT[9-0] are utilized as PCI clock sources, then CLKOUT9 is fed back to the PCI_CLK input. Note: The CLKOUT9 feedback trace should exceed the length of other CLKOUT traces by 2.5 inches.
I
External clock. EXT_CLK is an optional 33-MHz PCI clock input from an external oscillator or clock source. This input is multiplexed with the internal 31.25-MHz (125 MHz divided by 4) clock and may be used for driving the CLKOUT terminals. When unused, this terminal should be tied to a valid logic level. External clock select. EXT_CLK_SEL is used to select between an external 33-MHz clock source (EXT_CLK) and the internal 31.25-MHz (125 MHz divided by 4) clock as the CLKOUT terminal source. When EXT_CLK_SEL is high, the external clock is used. When EXT_CLK_SEL is low, the internal clock is used to drive CLKOUT terminals.
ADVANCE INFORMATION
EXT_CLK_SEL
104
I
Table 2-7. Secondary PCI Arbitration and Control
TERMINAL NAME GNT8 GNT7 GNT6 GNT5 GNT4 GNT3 GNT2 GNT1 REQ8 REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 EXTARB NO. 9 10 11 12 14 15 16 17 21 22 23 24 26 27 28 29 207 TYPE O FUNCTION Secondary PCI grants. When the internal arbiter is used, GNT8-GNT1 are outputs from the secondary PCI6050 node to other secondary bus masters to indicate when they are permitted to take ownership of the bus. These terminals are not used in a primary PCI6050 node.
I
Secondary PCI requests. When the internal arbiter is used, REQ8-REQ1 are inputs from other secondary bus masters to indicate when they wish to take ownership of the bus. These terminals are not used in a primary PCI6050 node.
I
Secondary external arbiter. EXTARB indicates whether or not an external arbiter is used in a secondary PCI6050 application and has no usage in primary PCI6050 applications. When EXTARB is sampled high, the internal secondary bus arbiter is disabled. When EXTARB is low, the PCI6050 internal secondary bus arbiter is enabled.
2-6
Table 2-8 describes the PCI6060 device clock and control interface signals; Table 2-9 describes the transmit data signals for the PCI6060 device. Table 2-8. PCI6060 Clock and Control Interface
TERMINAL NAME SYS_CLK NO. 175 TYPE I FUNCTION 125-MHz system clock. SYS_CLK is a 125-MHz clock input used to control the 16-bit transmit data path (TXD[15-0], TX_EN, and TX_ER) to the PCI6060 device. The PCI6050 device internally divides this clock by 4 to generate the 31.25-MHz clock which may be used for the CLKOUT[9-0] outputs. 125-MHz reference clock. This output clock is synchronous to the 16-bit transmit data path (TXD[15-0], TX_EN, and TX_ER) and should be used as the transmit clock source for the PCI6060 device. Loop enable. This output from the PCI6050 device can be connected to the PCI6060 LOOPEN terminal in order to allow the PCI6050 device to enable or disable its internal loop-back path. Pseudo-random bit stream enable. This output from the PCI6050 device can be connected to the PCI6060 PRBSEN terminal in order to allow the PCI6050 device to enable or disable its internal pseudo-random bit stream generator for loopback testing. Receive clock. This 125-MHz clock is synchronous to the receive data path (RXD[15-0], RX_DV, and RX_ER) and is provided by the PCI6060 device.
TLK_CLK LOOP_EN PRBSEN
173 159 152
O O O
RX_CLK
136
I
Table 2-9. PCI6060 Transmit Data Path
TERMINAL NAME TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 TX_EN NO. 161 163 164 166 167 169 170 171 177 178 180 181 183 184 186 187 160 TYPE O FUNCTION Transmit data. TXD[15-0] carries the 16-bit data stream from the PCI6050 device to the PCI6060 device.
O
Transmit data enable. TX_EN is driven by the PCI6050 device to indicate to the PCI6060 device when there is valid data on TXD[15-0]. This signal may also be used in conjunction with TX_ER to produce special control codes on the transceiver interface. Transmit error. This signal is used in conjunction with TX_EN to produce special control codes on the transceiver interface.
TX_ER
158
O
Table 2-10 describes the PCI6060 device receive data signals. Table 2-11 describes miscellaneous terminals on the PCI6050 device.
2-7
ADVANCE INFORMATION
Table 2-10. PCI6060 Receive Data Path
TERMINAL NAME RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 NO. 148 146 145 143 142 140 139 137 134 133 131 130 128 127 125 124 149 TYPE I FUNCTION Receive data. RXD[15-0] carries the 16-bit data stream from the PCI6060 device to the PCI6050 device.
ADVANCE INFORMATION
RX_DV
I
Receive data valid. RX_DV is driven by the PCI6060 device to indicate to the PCI6050 device when there is valid data on RXD[15-0]. This signal may also be used in conjunction with RX_ER to determine when there are special control codes on the receiver interface or when a receiver error has occurred. Receive error/status of PRBS test. The RX_ER may be used along with RX_DV by the PCI6050 device to determine when a special control code or transmit error was received by the PCI6060 device. The PRBS_PASS input from the PCI6060 device indicates whether the internal loop-back of pseudo-random data passed or failed. A primary PCI6050 device provides a mechanism to enable and read the status of the PRBS loop-back test via the transceiver test control and status registers.
RX_ER/ PRBS_PASS
150
I
Table 2-11. Miscellaneous Terminals
TERMINAL NAME CRC_EN NO. 1 TYPE I FUNCTION CRC enable. When CRC_EN is sampled high by a primary PCI6050 node, a 16-bit CRC is attached to each of the serial packets prior to its transmission over the serial link. The receiver compares this CRC with a calculated CRC in order to validate the incoming packet. When CRC_EN is sampled low, CRC-based packet validation is disabled. Mode select. PRI/SEC determines whether the PCI6050 device behaves as a primary or secondary serial PCI node. When sampled high, the PCI6050 device assumes the role of a primary node. When sampled low, the PCI6050 device acts as a secondary node. General purpose event. The PCI6050 device can be programmed to assert this output under various conditions that may require special service from an ACPI handler. This output provides open-drain fail-safe signaling. General purpose inputs/output. GPIO[3-0] provide basic general-purpose input and output functionality programmable through the PCI6050 device, and are available on both a primary and secondary PCI6050 nodes. Hot-swap enumeration. HS_ENUM is an input to a secondary PCI6050 node and is communicated via the serial link to the primary PCI6050 node, which asserts this open-drain output accordingly. Hot-swap LED. This output is controlled via the the HS_CSR register and is provided to indicate that a hot-swappable primary PCI6050 implementation may be safely removed. When PCI_RST is asserted to the PCI6050 device, it drives this LED output high. Hot-swap handle switch. This input provides the status of the ejector handle state and may be read through the extended diagnostic status register. Serial ROM clock. This terminal provides the serial ROM clock output from the PCI6050 device, and is sampled at reset to determine the presence of a serial ROM. Applications that do not support a serial ROM must place a weak pull-down on this terminal. Serial ROM data. This terminal provides the serial ROM data signal, which is both an output to select the word address and an input for the data transfer to the PCI6050 device.
PRI/SEC
208
I
GPE
199
O
GPIO3 GPIO2 GPIO1 GPIO0 HS_ENUM HS_LED
206 205 204 203 107 109
I/O
I/O O
HS_SWITCH SCL
108 197
I I/O
SDA
198
I/O
2-8
Table 2-12 describes the JTAG interface terminals, and Table 2-13 lists the power supply terminals for the PCI6050 device. Table 2-12. JTAG Interface Terminals
TERMINAL NAME TDI TDO TMS TCK TRST NO. 190 191 192 193 195 TYPE I O I I I FUNCTION JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG interface. The new data on TDI is sampled on the rising edge of TCLK. JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic leave the PCI6050 device. JTAG test mode select. TMS causes state transitions in the test access port controller. JTAG boundary-scan clock. TCLK is the clock controlling the JTAG logic. JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a reset state and initialize the test logic.
Table 2-13. Power Supply
TERMINAL GND 2, 19, 31, 44, 52, 53, 61, 73, 81, 94, 103, 115, 123, 129, 135, 141, 147, 155, 165, 172, 174, 179, 185, 194 34, 79 I Device ground terminals
VCCP
I
Primary bus-signaling environment supply. VCCP is used in protection circuitry on PCI bus I/O signals. Power supply terminals for core logic (2.5 V) Power supply terminals for core logic (3.3 V)
VCC2_5 VCC3_3
126, 132, 138, 144, 151, 162, 168, 176, 182, 188 7, 13, 25, 36, 40, 48, 57, 65, 69, 77, 85, 90, 98, 106, 110, 119, 196 202 100 101, 200 102, 201
I I
REG2_EN REG1_EN REG33 REG18
I I I/O
Regulator enables. The REGx_EN terminals are used to enable internal voltage regulators and should be tied to a low logic level. Power supply terminals for internal voltage regulators (3.3 V) Regulated output terminals supplied by the PCI6050 device that require external bypass capacitors of at least 0.1 F.
2-9
ADVANCE INFORMATION
NAME
NO.
TYPE
FUNCTION
ADVANCE INFORMATION
2-10
3 Feature/Protocol Descriptions
The Texas Instruments PCI6050 device is a symmetric serialized PCI-to-PCI bridge that provides a high-performance solution for connecting two PCI buses via a high-speed serial cable medium. The PCI6050 device has two major interfaces: a PCI interface and a transceiver (PCI6060) interface. The PCI6050 device communicates with a PCI bus and through a generic parallel interface to the PCI6060 transceiver. Two separate PCI6050 nodes are required, each with its own PCI6060 serial link, for a complete system. This four-chip solution provides a single, transparent PCI-to-PCI bridge, as illustrated in Figure 3-1.
Primary PCI Bus Serial PCI-to-PCI Bridge Secondary PCI Bus
PCI6050
PCI6060
PCI6060
PCI6050
Figure 3-1. The PCI-to-PCI Bridge Implementation With PCI6050 Device As a symmetrical device, the PCI6050 device can be implemented as either a primary or secondary serial PCI-to-PCI bridge node. The mode is determined by the level of the PRI/SEC input terminal. At a high level, a primary PCI6050 node claims downstream transactions that appear on the primary PCI bus which target either the PCI6050-based bridge or any devices located on a target bus that is subordinate to the bridge. These transactions are forwarded to the secondary PCI6050 node via the serial link so that they may be initiated and completed on the secondary PCI bus. In addition, a primary node initiates upstream transactions that are forwarded from the secondary PCI bus by the secondary node in a similar manner. The PCI6050 device, a single-function PCI device, provides an internal PCI bus arbiter that supports up to nine secondary PCI bus masters when it is configured as a secondary node. The PCI6050 device also provides 10 CLKOUT outputs that may supplied to PCI devices by dividing the SYS_CLK input clock by 4 or through an external clock source up to a maximum of 33 MHz provided by the system. The PCI6050 device supports primary PCI clock frequencies up to a maximum of 33 MHz. The PCI6050 serialized PCI-to-PCI bridge implementation provides parallel PCI interrupt routing from secondary devices to the primary system. In addition, the PCI6050 device supports CompactPCI hot swap on the primary interface by passing the CompactPCI hot-swap HS_ENUM signal from the secondary bus to the primary interface, and it supports four general purpose inputs and outputs which operate and are controlled independently for each node. A two-wire serial interface is provided for register pre-loading and subsystem identification for both primary and secondary nodes.
3-1
ADVANCE INFORMATION
High-Speed Cable
3.1 PCI6050 System Diagram
Figure 3-2 illustrates a system diagram for a notebook/dock application using the PCI6050 device.
Notebook Memory & Cache Core Logic CPU
Primary PCI Bus
PCI6050
CB Controller
Graphic Controller
ADVANCE INFORMATION
PCI6060
High-Speed Serial Wire
Dock PCI6060 Bus Master Bus Master Bus Master
PCI6050
Secondary PCI Bus
Figure 3-2. PCI6050 System Diagram
3.2 Protocol Fundamentals
The high-speed serial protocol defined here addresses a full duplex communication path with a continuous signaling rate for a point-to-point connection between two nodes. The protocol itself is not limited to any specific signaling rate, but the rate is constant transceiver tolerances and no speed scaling is built into the protocol. In the point-to-point connection, both nodes must implement the identical signaling rate within the transceiver tolerance. The Texas Instruments PCI6060 transceiver provides the data rate and functionality that is ideal for the serial protocol, and the transceiver has an integrated 8B/10B encoder/decoder (2.5 GHz) to allow for clock recovery and provide some means of error detection across the cable.
3.2.1
Packet Format
The serial protocol uses 48-bit or 64-bit packets transmitted most significant bit (MSB) first. The 6 most significant bits of a packet make up the packet identifier, which includes 5 bits to indicate the packet type and a single bit to
3-2
indicate the source of the packet as being the primary or secondary node. The 16 least significant bits of a 64-bit packet contain a CRC value when CRC protection is enabled. The remaining bits contain data that specific to each valid packet type. Figure 3-3 illustrates the general packet format, and MSB as the leftmost bit is assumed for all diagrams in this specification unless otherwise noted.
MSB Pkt Type 5 Prim 1 Packet-Specific Bits 42 CRC (optional) 16 LSB
Figure 3-3. Packet Format and Bit Ordering
3.2.2
Start-Up Procedure
3.2.3
Packet Summary
This section provides a general overview of the various packets used in communication between the two PCI6050 nodes during normal operation. The following list comprises the basic set of functional packets that comprise the PCI6050 protocol. Because this represents a proprietary interface, it is beyond the scope of this data manual to fully describe the PCI6050 protocol here. * PCI address - A PCI address packet supplies the command and address information for a given PCI transaction as well as the parity for the address phase of the transaction. In addition, this packet provides a sequence field, which is used to optimize FIFO performance and maintain the pipeline. PCI data - A PCI data packet supplies the byte-enable flags and transaction data information for a given PCI transaction as well as the parity for the current data phase of the transaction. In addition, this packet provides a sequence field, which is used to optimize FIFO performance and maintain the pipeline. Configuration register update packet - A configuration register update packet is used to synchronize the PCI configuration registers on both PCI6050 nodes. Both PCI6050 nodes have knowledge of registers and bits that need to be communicated through the serial link when configuration transactions or changes in the system status occur. These update packets are sent continuously until the destination node returns a value matching the source contents to confirm receipt. Completion status - Completion status packets are used to communicate the status of pending delayed transactions, including an indication if the transaction was terminated with a master abort, target abort, transaction timeout, or other erroneous condition. FIFO confirmation - FIFO confirmation packets are used to communicate the state of the pipeline, confirm a correctly received packet, or to notify the source node of any error that occurred during the packet transfer. This packet is also used to communicate error conditions such as a receiver error, CRC error, or sequence error condition to indicate that the packet must be retransmitted. Ordering tag - The ordering tag packet is used to notify the FIFO structures within the receiving node that a transaction (such as a memory write) is pending, and that the completion of that transaction should precede any other pending transactions (such as memory reads). This allows a PCI6050-based bridge to maintain the ordering rules within the PCI-to-PCI bridge specification.
*
*
*
*
*
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ADVANCE INFORMATION
Before any PCI6050 node can transfer serialized PCI-to-PCI bridge packets, the devices on both ends of the serial link must be in a valid state and ready to transmit and receive the packets. A start-up handshaking mechanism is used to bring the serial link into a default state after power-up or when the link is established. During this startup process, a primary PCI6050 node acknowledges all type-0 configuration cycles by signaling a retry. All type-1 configuration cycles are terminated as indicated by the bridge control register (target abort or normal completion), and all memory and I/O cycles are terminated with a master abort. After successful completion of this startup phase, all PCI cycles are handled normally.
3.3 PCI Commands
The bridge responds to PCI bus cycles as a PCI target device based on the decoding of each address phase and internal register settings. Table 3-1 lists the valid PCI bus cycles and their encoding on the command/byte enables (C/BE) bus during the address phase of a bus cycle. Table 3-1. PCI Command Definition
C/BE[3-0] 0000 0001 0010 0011 0100 0101 0110 0111 COMMAND Interrupt acknowledge Special cycle I/O read I/O write Reserved Reserved Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write and invalidate
ADVANCE INFORMATION
1000 1001 1010 1011 1100 1101 1110 1111
The bridge never responds as a PCI target to the interrupt acknowledge, special cycle, or reserved commands. The bridge does, however, initiate special cycles on both interfaces when a type 1 configuration cycle issues the special cycle request. The remaining PCI commands address either memory, I/O, or configuration space. The bridge accepts PCI cycles by asserting DEVSEL as a medium-speed device; that is, DEVSEL is asserted two clock cycles after the address phase. The PCI6050 device converts memory write and invalid commands to memory write commands when forwarding transactions from either the primary or secondary side of the bridge if the bridge cannot guarantee that an entire cache line will be delivered.
3.4 Configuration Cycles
The PCI Local Bus Specification defines two types of PCI configuration read and write cycles: type 0 and type 1. The bridge decodes each type differently. Type 0 configuration cycles are intended for devices on the primary bus, whereas type 1 configuration cycles are intended for devices on some hierarchically subordinate bus. The difference between these two types of cycles is the encoding of the primary PCI (AD) bus during the address phase of the cycle. Figure 3-4 shows the AD bus encoding during the address phase of a type 0 configuration cycle. The 6-bit register number field represents an 8-bit address with the lower bits masked to 0, indicating a double-word boundary. This results in a 256-byte configuration address space per function, per device. Individual byte accesses may be selected within a double word by using the P_C/BE signals during the data phase of the cycle.
31 Reserved 11 10 Function Number 87 2 Register Number 1 0 0 0
Figure 3-4. AD[31-0] During Address Phase of a Type 0 Configuration Cycle
3-4
The bridge claims only type 0 configuration cycles when its IDSEL terminal is asserted during the address phase of the cycle and the PCI function number encoded in the cycle ID is 0. If the function number is 1 or greater, then the bridge does not recognize the configuration command. In this case, the bridge does not assert DEVSEL, and the configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles by accessing internal registers from the configuration header. Because type 1 configuration cycles are issued to devices on the subordinate buses, the bridge claims type 1 cycles based on the bus number of the destination bus. The AD bus encoding during the address phase of a type 1 cycle is shown in Figure 3-5. The device number and bus number fields define the destination bus and device for the cycle.
31 Reserved 24 23 Bus Number 16 15 Device Number 11 10 Function Number 87 2 Register Number 1 0 0 1
Figure 3-5. AD[31-0] During Address Phase of a Type 1 Configuration Cycle Several bridge configuration registers shown in the configuration register table are significant for decoding and claiming type 1 configuration cycles. The destination bus number encoded on the AD bus is compared to the values programmed in the bridge configuration registers 18h, 19h, and 1Ah, which are primary bus number, secondary bus number, and subordinate bus number registers, respectively. These registers default to 00h and are programmed by the host software to reflect the bus hierarchy in the system (see Figure 3-6 for an example of a system bus hierarchy and how the PCI6050 bus number registers are programmed in this case). When the primary PCI6050 node claims a type 1 configuration cycle that has a bus number equal to its secondary bus number, the PCI6050 device converts the type 1 configuration cycle to a type 0 configuration cycle so that the secondary node may assert the proper AD line as the target device IDSEL (Table 3-2). All other type 1 transactions that access a bus number greater than the bridge's secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration cycles. Table 3-2. AD[31-16] During Address Phase of a Type 0 Configuration Cycle
DEVICE NUMBER 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h 10h 11h 12h 13h 14h 15h 10h-1Eh SECONDARY IDSEL AD[31-16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 AD ASSERTED 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -
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ADVANCE INFORMATION
PCI Bus 0
PCI6050 (Primary / Secondary Pair) Primary Bus Secondary Bus Subordinate Bus 00h 01h 02h
PCI6050 (Primary / Secondary Pair) Primary Bus Secondary Bus Subordinate Bus 00h 03h 03h
PCI Bus 1
PCI Bus 3
PCI6050 (Primary / Secondary Pair)
ADVANCE INFORMATION
Primary Bus Secondary Bus Subordinate Bus
01h 02h 02h
PCI Bus 2
Figure 3-6. Bus Hierarchy and Numbering
3.5 Secondary PCI Clocking
The PCI6050 device provides 10 secondary clock outputs (CLKOUT[0-9]). Nine are provided for clocking secondary devices. The tenth clock (CLKOUT9) should be routed back into the secondary PCI6050 node PCI_CLK input to ensure the all secondary bus devices are synchronized to the bridge, as shown in Figure 3-7.
PCI6050
PCI_CLK
CLKOUT9
CLKOUT3
PCI Device PCI Device PCI Device PCI Device
CLKOUT2
CLKOUT1
CLKOUT0
Figure 3-7. Secondary PCI Clock Block Diagram
3-6
3.6 Special Cycle Generation
The bridge is designed to generate special cycles on both buses through a type 1 conversion. During a type 1 configuration cycle, if the bus number field matches the bridge's secondary bus number, then the device number field is 1Fh, and the function number field is 07h; consequently, the bridge generates a special cycle on the secondary bus with a message that matches the type 1 configuration cycle data. If the bus number is a subordinate bus and not the secondary bus, then the bridge passes the type 1 special cycle request through to the secondary interface along with the proper message. Special cycles are never passed through the bridge, but they can be generated by the bridge through type 1 configuration cycles with a special cycle request.
3.7 Bus Arbitration
The primary PCI6050 node implements a bus request (REQ0) and a bus grant (GNT0) terminal for primary bus arbitration. Nine secondary bus requests and nine secondary bus grants are provided on the secondary PCI6050 node. Ten potential initiators, including the bridge, can be located on the secondary bus. The secondary PCI6050 node provides a two-tier arbitration scheme on the secondary PCI bus for priority bus-master handling. The two-tier arbitration scheme improves performance in systems in which not all master devices require the same bandwidth. Any master that requires frequent use of the bus can be programmed to be in the higher priority tier.
3.7.1
Primary Bus Arbitration
The primary PCI6050 node, acting as an initiator on the primary bus, asserts REQ0 when attempting to forward transactions upstream on the primary bus. In the upstream direction, as long as a posted write or a delayed transaction request is in the queue, the primary PCI6050 node keeps REQ0 asserted. If a target disconnect, a target retry, or a target abort is received in response to a transaction initiated on the primary bus by the PCI6050 device, then REQ0 is deasserted for two PCI clock cycles in accordance with the PCI Local Bus Specification. When the primary bus arbiter asserts GNT0 in response to REQ0 from the primary PCI6050 node, the device initiates a transaction on the primary bus during the next PCI clock cycle after the primary bus is sampled idle. When REQ0 is not asserted and the primary bus arbiter asserts GNT0 to the PCI6050 device, it responds by parking the AD[31-0], C/BE[3-0], and primary parity (PAR) (driving them to valid logic levels). If the PCI6050 device is parking the primary bus and wants to initiate a transaction on the bus, then it can start the transaction on the next PCI clock by asserting the primary cycle frame (FRAME) while GNT0 is still asserted. If GNT0 is deasserted, then the bridge must re-arbitrate for the bus to initiate another transaction.
3.7.2
Secondary Bus Arbitration
EXTARB controls the state of the secondary internal arbiter. The internal arbiter can be enabled by pulling the EXTARB terminal low. The PCI6050 device provides nine secondary bus request terminals and nine secondary bus grant terminals. Including the bridge, there are a total of 10 potential secondary bus masters. These request and grant signals are connected to the internal arbiter. An external secondary bus arbiter can be used instead of the PCI6050 internal arbiter. When an external arbiter is used, the internal arbiter of the PCI6050 device should be disabled by pulling the EXTARB terminal high. When an external secondary bus arbiter is used, the PCI6050 device internally reconfigures the REQ0 and GNT0 signals to its own REQ and GNT, respectively. When an external arbiter is used, all unused secondary bus grant outputs (GNT[8-1]) are placed in a high-impedance mode. Any unused secondary request inputs (REQ[8-1]) should be pulled high to prevent these inputs from oscillating.
3.8 Decode Options
The PCI6050 device supports positive decoding using the standard bridge memory windows on the primary interface and negative decoding on the secondary interface.
3.9 System Error Handling
The PCI6050 device can be configured to signal a system error (SERR) under a variety of conditions. The primary SERR event disable register (offset 64h, see Section 5.4) and the primary SERR status register (offset 6Ah, see
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ADVANCE INFORMATION
Section 5.9) provide control and status bits for each condition which can cause the bridge to signal SERR. These individual bits enable SERR reporting for both downstream and upstream transactions. By default, the PCI6050 device does not signal SERR. If the PCI6050 device is configured to signal SERR by setting bit 8 of the PCI command register (offset 04h, see Section 4.3), then the bridge signals SERR if any of the error conditions in the primary SERR event disable register occur and that condition is enabled. By default all error conditions are enabled in the primary SERR event disable register. When the bridge signals SERR, bit 14 of the secondary status register (offset 1Eh, see Section 4.17) is set.
3.9.1
Posted Write Parity Error
If bit 1 in the primary SERR event disable register is 0, then parity errors on the target bus during a posted write are passed to the initiating bus by the assertion of SERR. When this occurs, bit 1 of the primary SERR status register is set. The status bit may be cleared by writing a 1.
3.9.2
Posted Write Timeout
ADVANCE INFORMATION
If bit 2 in the primary SERR event disable register is 0 and the retry timer expires before a posted write is completed, then the PCI6050 signals SERR on the initiating bus. When this occurs, bit 2 of the primary SERR status register is set. The status bit may be cleared by writing a 1.
3.9.3
Target Abort on Posted Writes
If bit 3 in the primary SERR event disable register is 0 and the bridge gets a target abort during a posted write transaction, then the PCI6050 device signals SERR on the initiating bus. When this occurs, bit 3 of the primary SERR status register is set. The status bit may be cleared by writing a 1.
3.9.4
Master Abort on Posted Writes
If bit 4 in the primary SERR event disable register is 0 and a posted write transaction results in a master abort, then the PCI6050 device signals SERR on the initiating bus. When this occurs, bit 4 of the primary SERR status register is set. The status bit may be cleared by writing a 1.
3.9.5
Master Delayed Write Timeout
If bit 5 in the primary SERR event disable register is 0 and the retry timer expires before a delayed write is completed, then the PCI6050 device signals SERR on the initiating bus. When this occurs, bit 5 of the primary SERR status register is set. The status bit may be cleared by writing a 1.
3.9.6
Master Delayed Read Timeout
If bit 6 in the primary SERR event disable register is 0 and the retry timer expires before a delayed read is completed, then the PCI6050 device signals SERR on the initiating bus. When this occurs, bit 6 of the primary SERR status register is set. The status bit may be cleared by writing a 1.
3.9.7
Secondary SERR
The PCI6050 device passes SERR from the secondary bus to the primary bus via the serial link if it is enabled for SERR response, bit 8 in the PCI command register (offset 04h, see Section 4.3) is set, and bit 1 in the bridge control register (offset 3Eh, see Section 4.29) is set.
3.10 Parity Handling and Parity Error Reporting
The PCI6050 device forwards parity errors from the initiating bus to the target bus. The following parity conditions result in the bridge signaling an error.
3-8
* *
Address parity error - If the parity error response enable bit (bit 6) in the PCI command register is set, then the PCI6050 device signals SERR on address parity errors and target abort transactions. Data parity error - If the parity error response enable bit (bit 6) in the PCI command register is set, then the PCI6050 device signals PERR when it receives bad data. When the bridge detects bad parity, bit 15 (primary parity error) in the PCI status register is set. If the bridge is configured to respond to parity errors, then the data parity error detected bit (bit 8 in the status register) is set when the bridge detects bad parity. The data parity error detected bit is also set when the bridge, as a bus master, asserts PERR or detects PERR.
3.11 Master and Target Abort Handling
If the PCI6050 device receives a target abort during a write burst, then it signals target abort back to the initiator bus. If it receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and disconnects. Target aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification. Master aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification. If a transaction is attempted on the primary bus after a secondary reset is asserted, then the PCI6050 device follows the master abort mode bit setting in the bridge control register (offset 3Eh, see Section 4.29) for reporting errors.
3.12 Discard Timer
The PCI6050 device is free to discard the data or status of a delayed transaction that was completed with a delayed transaction termination when a bus master has not repeated the request within 210 or 215 PCI clocks (approximately 30 s and 993 s, respectively). The PCI Local Bus Specification states that a bridge should wait 215 PCI clocks before discarding the transaction data or status. The PCI6050 device implements a discard timer for use in delayed transactions. After a delayed transaction is completed on the destination bus, the bridge may discard it under two conditions. The first condition occurs when a read transaction is made to a region of memory that the bridge knows is prefetchable, or when the command is a memory read line or a memory read multiple, implying that the memory region is prefetchable. The other condition occurs when the master originating the transaction (either a read or a write, prefetchable or nonprefetchable) has not retried the transaction within 210 or 215 clocks. A timer referred to as the discard timer tracks the number of clocks. When the discard timer expires, the bridge is required to discard the data. The PCI6050 device default value for the discard timer is 215 clocks; however, this value can be set to 210 clocks by setting bit 9 in the bridge control register. For more information on the discard timer, see error conditions in the PCI Local Bus Specification.
3.13 Delayed Transactions
The bridge supports delayed transactions as defined in the PCI Local Bus Specification. A target must be able to complete the initial data phase in 16 PCI clocks or less from the assertion of the cycle frame (FRAME), and subsequent data phases must be completed in 8 PCI clocks or less. A delayed transaction consists of three phases: * * * An initiator device issues a request. The target completes the request on the destination bus and signals the completion to the initiator. The initiator completes the request on the originating bus.
If the bridge is the target of a PCI transaction and it must access a slow device to write or read the requested data, and the transaction takes longer than 16 clocks, then the bridge must latch the address, the command, and the byte enables, and then issue a retry to the initiator. The initiator must end the transaction without any transfer of data and is required to retry the transaction later using the same address, command, and byte enables. This is the first phase of the delayed transaction. During the second phase, if the transaction is a read cycle, then the bridge fetches the requested data on the destination bus, stores it internally, and obtains the completion status, thus completing the transaction on the destination bus. If it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the transaction on the destination bus. The bridge stores the completion status until the master on the initiating bus retries the initial request.
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ADVANCE INFORMATION
During the third phase, the initiator re-arbitrates for the bus. When the bridge sees the initiator retry the transaction, it compares the second request to the first request. If the address, command, and byte enables match the values latched from the first request, then the completion status (and data if the request was a read) is transferred to the initiator. At this point, the delayed transaction is complete. If the second request from the initiator does not match the first request exactly, then the bridge issues another retry to the initiator. The PCI6050 device supports three delayed transactions in each direction at any given time.
3.14 CompactPCI Hot-Swap Support
The PCI6050 device is hot-swap friendly silicon that supports all of the hot-swap capable features, contains support for software control, and integrates circuitry required by the CompactPCI Hot-Swap Specification. To be hot-swap capable, the PCI6050 device supports the following: * * * * * * * * Compliance with PCI Local Bus Specification Tolerance of VCC from early power Asynchronous reset Tolerance of precharge voltage I/O buffers must meet modified V/I requirements Limited I/O pin voltage at precharge voltage Hot-swap control and status programming via extended PCI capabilities linked list Hot-swap terminals: HS_ENUM, HS_SWITCH, and HS_LED
ADVANCE INFORMATION
CPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running system. The PCI6050 device provides this functionality so that it can be implemented on a board that can be removed and inserted in a hot-swap system. A primary PCI6050 node provides three terminals to support hot-swap: HS_ENUM (output), HS_SWITCH (input), and HS_LED (output). The HS_ENUM output indicates to the system that an insertion event occurred or that a removal event is about to occur. The HS_SWITCH input indicates that state of a board ejector handle, and the HS_LED output lights a blue LED to signal insertion and removal ready status. The primary PCI6050 node hot-swap functionality is controlled via the primary CPCI hot-swap control and status register (offset E6h, see Section 5.29). The PCI6050 device allows for a 2-ms debounce period on HS_SWITCH input to ensure that the state of the input has been stable for about 2 ms following the insertion and removal of a board implementing the PCI6050 device, before the state change is reported to the hot-swap status bits. When the HS_ENUM signal is received at the secondary PCI6050 node HS_ENUM input pin, the hardware forwards the hot-swap event to the primary system by way of the serial link.
3.15 JTAG Support
As shown in Table 3-3, the PCI6050 device supports the following JTAG instructions: * * * EXTEST, BYPASS, and SAMPLE HIGHZ and CLAMP Private (various private instructions are used by TI for test purposes) Table 3-3. JTAG Instructions and Op Codes
INSTRUCTION EXTEST SAMPLE CLAMP HIGHZ BYPASS OP CODE 00000 00001 00100 00101 11111 Sample I/O pins Drives pins from the boundary scan register and selects the bypass register for shifts 3-state all outputs and I/O pins except for the TDO pin Selects the bypass register for shifts DESCRIPTION External test: Drives pins from the boundary scan register
Table 3-4 describes the boundary scan pin order.
3-10
Table 3-4. Boundary Scan Pin Order
BOUNDARY SCAN REGISTER NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PIN NUMBER 197 198 199 203 - 204 - 205 - 206 - 207 208 1 3 4 5 6 9 10 11 12 - 14 15 16 17 18 21 22 23 24 26 27 28 29 30 - 32 - 33 35 37 PIN NAME SCL SDA GPE GPIO0 - GPIO1 - GPIO2 - GPIO3 - EXTARB PRI/SEC CRC_EN INTD INTC INTB INTA GNT8 GNT7 GNT6 GNT5 - GNT4 GNT3 GNT2 GNT1 GNT0 REQ8 REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 - PCI_RST - PCI_CLK GLOBAL_RST AD31 GROUP DISABLE REGISTER - - - 5 - 7 - 9 - 11 - - - - - - - - 23 23 23 23 - 23 23 23 23 23 - - - - - - - - 38 - 40 - - - 46 BOUNDARY SCAN CELL TYPE Bidirectional Bidirectional Output Bidirectional Control Bidirectional Control Bidirectional Control Bidirectional Control Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Output Output Output Output Control Output Output Output Output Bidirectional Input Input Input Input Input Input Input Input Bidirectional Control Input Control Input Input Bidirectional
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ADVANCE INFORMATION
Table 3-4. Boundary Scan Pin Order (Continued)
BOUNDARY SCAN REGISTER NUMBER 44 45 46 47 48 49 50 51 52 53 54 55 PIN NUMBER 38 39 - 41 42 - 43 45 46 47 - 49 50 51 54 55 56 - 58 59 60 62 - 63 - 64 - 66 67 68 - 70 - 71 - 72 74 - 75 76 78 80 - PIN NAME AD30 AD29 - AD28 C/BE3 - IDSEL AD27 AD26 AD25 - AD24 AD23 AD22 AD21 AD20 AD19 - AD18 AD17 AD16 C/BE2 - FRAME - IRDY - TRDY DEVSEL STOP - PAR - PERR - SERR C/BE1 - AD15 AD14 AD13 AD12 - GROUP DISABLE REGISTER 46 46 - 46 49 - - 54 54 54 - 54 61 61 61 61 61 - 61 61 61 66 - 68 - 70 - 74 74 74 - 76 - 78 - - 81 - 86 86 86 86 - BOUNDARY SCAN CELL TYPE Bidirectional Bidirectional Control Bidirectional Bidirectional Control Input Bidirectional Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Control Bidirectional Control Bidirectional Control Bidirectional Bidirectional Bidirectional Control Bidirectional Control Bidirectional Control Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Control
ADVANCE INFORMATION
56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
3-12
Table 3-4. Boundary Scan Pin Order (Continued)
BOUNDARY SCAN REGISTER NUMBER 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PIN NUMBER 82 83 84 86 87 - 88 89 91 92 93 - 95 96 97 99 104 107 108 109 111 112 113 114 116 117 118 120 121 122 124 125 127 128 130 131 133 134 136 137 139 140 PIN NAME AD11 AD10 AD9 AD8 C/BE0 - AD7 AD6 AD5 AD4 AD3 - AD2 AD1 AD0 EXT_CLK EXT_CLK_SEL HS_ENUM HS_SWITCH HS_LED CLKOUT9 CLKOUT8 CLKOUT7 CLKOUT6 CLKOUT5 CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1 CLKOUT0 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RX_CLK RXD8 RXD9 RXD10 GROUP DISABLE REGISTER 86 86 86 86 92 - 98 98 98 98 98 - 98 98 98 - - - - - - - - - - - - - - - - - - - - - - - - - - - BOUNDARY SCAN CELL TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Bidirectional Bidirectional Bidirectional Input Input Bidirectional Input Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input
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ADVANCE INFORMATION
Control
Table 3-4. Boundary Scan Pin Order (Continued)
BOUNDARY SCAN REGISTER NUMBER 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 PIN NUMBER 142 143 145 146 148 149 150 152 158 159 160 161 163 164 166 167 169 170 171 173 175 177 178 180 181 183 184 186 187 PIN NAME RXD11 RXD12 RXD13 RXD14 RXD15 RXDV RXER_PRBSPASS PRBS_EN TXER LOOP_EN TXEN TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 TLK_CLK SYS_CLK TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 GROUP DISABLE REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BOUNDARY SCAN CELL TYPE Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Output Output Output Output Output Output Output
ADVANCE INFORMATION
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3.16 GPIO Interface
The PCI6050 device implements a four-pin general purpose I/O interface that is controlled through software for both the primary and secondary nodes. The GPIO terminals of each node are controlled independently through two separate locations with the PCI6050 configuration space. The primary GPIO control registers begin at PCI offset 65h. The secondary GPIO control registers begin at PCI offset A9h. Setting the GPIOTOIIC bit in the diagnostic control register (bit 3 of offset 41h, see Section 5.2) maps the control bits for GPIO1 and GPIO2 to SDA and SCL on the serial ROM interface, respectively. This allows for the system designer to implement in-circuit serial ROM programming through software. In addition, the PCI6050 device stops forwarding I/O and memory transactions if bit 5 of the chip control register (offset 40h, see Section 5.1) is set to 1 and GPIO3 is driven high. The bridge will complete all queued posted writes and delayed requests but delayed completions will not be returned until GPIO3 is driven low and transaction forwarding is resumed. The bridge continues to accept configuration cycles in this mode.
3.17 PCI Power Management
The PCI Power Management Interface Specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned to one of four software visible power management states, which result in varying levels of power savings. The four power management states of PCI functions are D0 fully on state, D1, D2 intermediate states, and D3 Off state. Similarly, bus power states are B0-B3. The bus power states B0-B3 are derived from the device power state of the originating device. The power state of the secondary bus is derived from the power state of the PCI6050 device. For the operating system to power manage the device power states on the PCI bus, PCI functions support four power management operations: * * * * Capabilities reporting Power status reporting Setting the power state System wake-up
The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of the new capabilities list is indicated by the PCI status register which provides access to the capabilities list.
3.17.1 Behavior in Low Power States
The PCI6050 device supports D0, D1, D2, and D3hot power states. The PCI6050 device is fully functional only in the D0 state. In the lower power states, the bridge does not accept any I/O or memory transactions. These transactions are master aborted. The bridge accepts type 0 configuration cycles in all power states except D3cold. The bridge also accepts type 1 configuration cycles but does not pass these cycles to the secondary bus in any of the low power states. Type 1 configuration writes are discarded and type 1 configuration reads return all 1s. All error reporting is done in low power states. In the D2 and D3hot states, the bridge turns off all secondary clocks for additional power savings. When the PCI6050 device goes from D3hot to D0, an internal reset is generated. This reset initializes all PCI configuration registers to their default values. NOTE:Neither the TI extension registers (40h-FFh) nor the power management registers (beginning at offset E0h) are reset.
3.18 Serial ROM Implementation
The optional serial ROM is used to pre-load primary and secondary PCI6050 configuration registers and may be used for other diagnostic purposes. The serial ROM is optional, and is not expected in most PCI6050 implementations. The PCI6050 device samples the SCL terminal following GLOBAL_RST assertion to determine the presence of a serial ROM. When a serial ROM is not implemented, the SCL PCI6050 terminal should be pulled down with a weak resistor. Typically, only write-accessible bits in these registers may be pre-loaded, and exceptions are noted in the bit descriptions. However, configuration writes to the registers always takes priority over the data loaded from the secondary serial ROM, regardless of whether or not the serial ROM load has occurred or whether or not any serial ROM load value was ever communicated to the primary side. Thus, the value written by a host configuration write to the secondary CLKOUT control register takes priority on the value loaded from the secondary serial ROM. Figure 3-8 illustrates the PCI6050 serial ROM data format.
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ADVANCE INFORMATION
Primary Serial ROM Data Format
Secondary Serial ROM Data Format
Pri Clkout Ctrl Byte 0 Pri Clkout Ctrl Byte 1
Word Address 0 Word Address 1
Subsystem ID Byte 0 Subsystem ID Byte 1 Subsystem VID Byte 0
Word Address 0 Word Address 1 Word Address 2 Word Address 3 Word Address 4 Word Address 5 Word Address 6 Word Address 7
RSVD
Subsystem VID Byte 1 Arbiter Ctrl Byte 0 Arbiter Ctrl Byte 1 Sec Clkout Ctrl Byte 0 Sec Clkout Ctrl Byte 1
RSVD
ADVANCE INFORMATION
Figure 3-8. Serial ROM Data Format If the serial ROM is implemented, then it is addressed at slave address A0h after the PCI6050 device enters the active state and is loaded in a data-burst mode. Only serial ROMs that support the address auto-increment data-burst mode can be used with the PCI6050 device.
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4 Bridge Configuration Header
The PCI6050 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI Bridge Architecture Specification. The following table shows the PCI configuration header, which includes the predefined portion of the bridge's configuration space. The PCI configuration offset is shown in the right column under the OFFSET heading.
REGISTER NAME Device ID Status Class code BIST Header type Reserved Reserved Secondary bus latency timer Subordinate bus number Secondary bus number I/O limit Memory base Prefetchable memory base Prefetchable base upper 32 bits Prefetchable limit upper 32 bits I/O limit upper 16 bits Reserved Reserved Bridge control register Arbiter control Reserved Primary GPIO input Reserved Reserved Reserved Extended diagnostic status Secondary GPIO input Receive error count Reserved Reserved Power management capabilities PM data Reserved PMCSR bridge support Hot-swap control and status Subsystem ID Reserved Reserved Reserved Reserved Reserved PM next item pointer HS next item pointer FIFO BIST PM capability ID HS capability ID Power management control/status Subsystem vendor ID Secondary GPIO direction Reserved CRC error count Sequence error count Reserved Transceiver test control and status Primary GPIO direction Primary SERR status Secondary SERR status Reserved General purpose event Reserved Secondary GPIO output Reserved Primary GPIO output SERR control Primary CLKOUT control Secondary CLKOUT control Interrupt pin Diagnostic control Interrupt line Chip control I/O base upper 16 bits Capability pointer Primary bus number I/O base Secondary status Memory limit Prefetchable memory limit Latency timer Vendor ID Command Revision ID Cache line size OFFSET 00h 04h 08h 0Ch 10h 14h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h-63h 64h 68h 6Ch 70h-9Fh A0h A4h A8h ACh-BBh BCh C0h C4h-DBh DCh E0h E4h E8h ECh F0h F4h F8h FCH 18h
4-1
ADVANCE INFORMATION
4.1 Vendor Register
This 16-bit value is allocated by the PCI Special Interest Group (SIG) and identifies TI as the manufacturer of this device. The vendor ID assigned to TI is 104Ch.
Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 0 4 R 0 3 R 1 2 R 1 1 R 0 0 R 0
Vendor ID
Register: Type: Offset: Default:
Vendor ID Read-only 00h 104Ch
4.2 Device ID Register
ADVANCE INFORMATION
This 16-bit value is allocated by the vendor and identifies the PCI device. The device ID for the PCI6050 device is AC70h.
Bit Name Type Default R 1 R 0 R 1 R 0 R 1 R 1 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 1 4 R 1 3 R 0 2 R 0 1 R 0 0 R 0
Device ID
Register: Type: Offset: Default:
Device ID Read-only 02h AC70h
4-2
4.3 PCI Command Register
The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4-1 describes the bit functions in the command register.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R 0 6 R/W 0 5 R/W 0 4 R 0 3 R 0 2 R/W 0 1 R/W 0 0 R/W 0
Command
Register: Type: Offset: Default:
BIT 15-10 9 8 ACCESS R R/W R/W
Command Read-only, Read/Write 04h 0000h Table 4-1. PCI Command Register Description
DESCRIPTION Reserved. Bits 15-10 return 0s when read. Fast back-to-back enable. The PCI6050 device does not generate fast back-to-back transactions on the primary PCI bus. Bit 9 is read/write, but does not affect the bridge when set. This bit defaults to 0. SERR enable. Bit 8 controls the enable for the SERR driver on the primary interface. 0 = Disable SERR driver on primary interface (default). 1 = Enable the SERR driver on primary interface. Address/data stepping control. Bit 7 controls address/data stepping by the bridge on both interfaces. The PCI6050 device does not support address/data stepping and this bit is hardwired to 0. Parity error response enable. Bit 6 controls the bridge response to parity errors. 0 = Parity error response disabled (default) 1 = Parity error response enabled VGA palette snoop enable. When set, a primary PCI6050 node will pass I/O writes on the primary PCI bus with addresses 3C6h, 3C8h, and 3C9h inclusive of ISA aliases (that is, only AD[9-0] are included in decode) to the secondary PCI bus. Memory write and invalidate enable. In a PCI-to-PCI bridge, bit 4 must be read-only and return 0 when read. Special cycle enable. A PCI-to-PCI bridge cannot respond as a target to special cycle transactions, so bit 3 is defined as read-only and must return 0 when read. Bus master enable. Bit 2 controls the ability of the primary PCI6050 node to initiate a cycle on the primary PCI bus. When bit 2 is 0, the secondary PCI6050 node does not respond to any memory or I/O transactions on the secondary interface because they cannot be forwarded to the primary PCI bus. 0 = Bus master capability disabled (default) 1 = Bus master capability enabled Memory response enable. Bit 1 controls the bridge response to memory accesses for both prefetchable and nonprefetchable memory spaces on the primary PCI bus. Only when bit 1 is set does the bridge forward memory accesses to the secondary bus from a primary bus initiator. 0 = Memory space disabled (default) 1 = Memory space enabled I/O space enable. Bit 0 controls the bridge response to I/O accesses on the primary interface. Only when bit 0 is set does the bridge forward I/O accesses to the secondary bus from a primary bus initiator. 0 = I/O space disabled (default) 1 = I/O space enabled
7 6
R R/W
5
R/W
4 3 2
R R R/W
1
R/W
0
R/W
4-3
ADVANCE INFORMATION
4.4 PCI Status Register
The status register provides device information regarding the primary PCI bus to the host system. Table 4-2 describes the bit functions in the PCI status register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 0 15 14 13 12 11 10 9 8 Status R/W R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0
Register: Type: Offset: Default:
BIT 15 ACCESS R/W
Status Read/Write, Read-only 06h 0210h Table 4-2. PCI Status Register Description
DESCRIPTION
ADVANCE INFORMATION
Primary parity error. Bit 15 is set when either an address or data parity error is detected. 0 = No PERR detected (default) 1 = PERR detected Primary system error. Bit 14 is set if SERR is enabled (bit 8) in the PCI command register (offset 04h, see Section 4.3) and the bridge signals a system error (SERR). 0 = No SERR signaled (default) 1 = SERR signaled Primary master abort received. Bit 13 is set when a cycle initiated by the bridge on the primary bus has been terminated by a master abort. 0 = No master abort received (default) 1 = Master abort received Primary target abort received. Bit 12 is set when a cycle initiated by the bridge on the primary bus has been terminated by a target abort. 0 = No target abort received (default) 1 = Target abort received Primary target abort signaled. Bit 11 is set by the bridge when it terminates a transaction on the primary bus with a target abort. 0 = No target abort signaled by the bridge (default) 1 = Target abort signaled by the bridge Primary DEVSEL timing. These read-only bits encode the timing of DEVSEL and are hardwired 01b, indicating that the bridge asserts this signal at a medium speed. Primary PCI data parity error detected. Bit 8 is encoded as: 0 = The conditions for setting this bit have not been met. No parity error detected.(default). 1 = A data parity error occurred and the following conditions were met: a. PERR was asserted by any PCI device including the bridge. b. The bridge was the bus master during the data parity error. c. The parity error response enable bit (bit 6) is set in the PCI command register (offset 04h, see Section 4.3). Fast back-to-back capable. The PCI6050 device does not support fast back-to-back transactions as a target; therefore, bit 7 is hardwired to 0. User-definable feature (UDF) support. The PCI6050 device does not support the user-definable features; therefore, bit 6 is hardwired to 0. 66-MHz capable. The PCI6050 device operates at a maximum PCI_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Capabilities list. Bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power management capabilities is implemented by this function. Reserved. Bits 3-0 return 0s when read.
14
R/W
13
R/W
12
R/W
11
R/W
10-9 8
R R/W
7 6 5 4 3-0
R R R R R
4-4
4.5 Revision ID Register
The revision ID register indicates the silicon revision of the PCI6050 device.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Revision ID R 0 R 0 R 0 R 0 3 2 1 0
Register: Type: Offset: Default:
Revision ID Read-only 08h 00h (reflects the current revision of the silicon)
4.6 Class Code Register
This register categorizes the PCI6050 device as a PCI-to-PCI bridge device (0604h) with a 00h programming interface.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 7 R 0 6 R 0 5 R 0 4 R 0 R 0 3 R 0 R 1 2 R 0 R 1 1 R 0 23 22 21 20 19 18 17 16 R 0 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 1 9 R 0 8 R 0 Class code
Class code
Register: Type: Offset: Default:
Class code Read-only 09h 060400h
4.7 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size needed by the bridge on memory read line and memory read multiple transactions.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Cache line size
Register: Type: Offset: Default:
Cache line size Read/Write 0Ch 00h
4-5
ADVANCE INFORMATION
4.8 Primary Latency Timer Register
The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is a primary PCI bus initiator and asserts FRAME, the latency timer begins counting from 0. If the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its GNT is de-asserted.
Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 Latency timer R/W R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0
Register: Type: Offset: Default:
Latency timer Read/Write 0Dh 00h
4.9 Header Type Register
ADVANCE INFORMATION
The header type register is read-only and returns 01h when read, indicating that the PCI6050 configuration space adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h-3Fh of configuration space is considered.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Header type R 0 R 0 R 0 R 1 3 2 1 0
Register: Type: Offset: Default:
Header type Read-only 0Eh 01h
4.10 BIST Register
The PCI6050 device does not support built-in self test (BIST). The BIST register is read-only and returns the value 00h when read.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 BIST R 0 R 0 R 0 R 0 3 2 1 0
Register: Type: Offset: Default:
BIST Read-only 0Fh 00h
4-6
4.11 Primary Bus Number Register
The primary bus number register indicates the primary bus number to which the bridge is connected. The bridge uses this register, in conjunction with the secondary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Primary bus number
Register: Type: Offset: Default:
Primary bus number Read/Write 18h 00h
4.12 Secondary Bus Number Register
The secondary bus number register indicates the secondary bus number to which the bridge is connected. The PCI6050 device uses this register, in conjunction with the primary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles directed to the secondary bus are converted to type 0 configuration cycles.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Secondary bus number
Register: Type: Offset: Default:
Secondary bus number Read/Write 19h 00h
4.13 Subordinate Bus Number Register
The subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus existing behind the bridge. The PCI6050 device uses this register, in conjunction with the primary bus number and secondary bus number registers, to determine when to forward PCI configuration cycles to the subordinate buses. Configuration cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses the bridge.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Subordinate bus number
Register: Type: Offset: Default:
Subordinate bus number Read/Write 1Ah 00h
4-7
ADVANCE INFORMATION
4.14 Secondary Bus Latency Timer Register
The secondary bus latency timer specifies the latency timer for the secondary PCI6050 node in units of PCI clock cycles. When the bridge is a secondary PCI bus initiator and asserts FRAME, the latency timer begins counting from 0. If the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its GNT is de-asserted. The PCI-to-PCI bridge GNT is an internal signal and is removed when another secondary bus master arbitrates for the bus.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Secondary bus latency timer
Register: Type: Offset: Default:
Secondary bus latency timer Read/Write 1Bh 00h
ADVANCE INFORMATION
4.15 I/O Base Register
The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3-0 are read-only and default to 0001b. The upper 4 bits are writable and correspond to address bits AD15-AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O base address corresponds to the contents of the I/O base upper 16 bits register (offset 30h, see Section 4.24). Primary PCI6050 nodes positively decode the window defined by the I/O base and limit registers. Secondary PCI6050 nodes negatively decode the window programmed in these registers.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 I/O base R 0 R 0 R 0 R 1 3 2 1 0
Register: Type: Offset: Default:
I/O base Read/Write, Read-only 1Ch 01h
4.16 I/O Limit Register
The I/O limit register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3-0 are read-only and default to 0001b. The upper 4 bits are writable and correspond to address bits AD15-AD12. The lower 12 address bits of the I/O limit address are considered FFFh. Thus, the top of the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O limit address corresponds to the contents of the I/O limit upper 16 bits register (offset 32h, see Section 4.25). Primary PCI6050 nodes positively decode the window defined by the I/O base and limit registers. Secondary PCI6050 nodes negatively decode the window programmed in these registers.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 I/O limit R 0 R 0 R 0 R 1 3 2 1 0
Register: Type: Offset: Default:
I/O limit Read/Write, Read-only 1Dh 01h
4-8
4.17 Secondary Status Register
The secondary status register is similar in function to the PCI status register (offset 06h, see Section 4.4); however, its bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective bit.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 15 14 13 12 11 10 9 8 R/W 0 7 R 1 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
Secondary status
Register: Type: Offset: Default:
BIT 15 ACCESS R/W
Secondary status Read/Write, Read-only 1Eh 0280h Table 4-3. Secondary Status Register Description
DESCRIPTION Secondary parity error detected. Bit 15 is set when a parity error is detected on the secondary PCI interface. 0 = No parity error detected on the secondary bus (default) 1 = Parity error detected on the secondary bus Secondary SERR detected. Bit 14 is set when the secondary interface detects SERR asserted. Note that the secondary PCI6050 node never asserts SERR. 0 = No SERR detected on the secondary bus (default) 1 = SERR detected on the secondary bus Secondary master abort received. Bit 13 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a master abort. 0 = No master abort received (default) 1 = Bridge master aborted the cycle Secondary target abort received. Bit 12 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a target abort. 0 = No target abort received (default) 1 = Bridge received a target abort Secondary target abort signaled. Bit 11 is set by the PCI6050 device when it terminates a transaction on the secondary bus with a target abort. 0 = No target abort signaled (default) 1 = Bridge signaled a target abort Secondary DEVSEL timing. These read-only bits encode the timing of DEVSEL and are hardwired to 01b, indicating that the bridge asserts this signal at a medium speed. Secondary data parity error detected. Bit 8 is encoded as: 0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met: a. PERR was asserted by any PCI device including the bridge. b. The bridge was the bus master during the data parity error. c. The secondary parity error response enable bit (bit 0) is set in the bridge control register (offset 3Eh, see Section 4.29). Fast back-to-back capable. Hardwired to 1 to indicate that the PCI6050 device is able to respond to fast back-to-back transactions on the secondary interface. User-definable feature (UDF) support. The PCI6050 device does not support the user-definable features; therefore, bit 6 is hardwired to 0. 66-MHz capable. The PCI6050 device operates at a maximum PCI_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Reserved. Bits 4-0 return 0s when read.
14
R/W
13
R/W
12
R/W
11
R/W
10-9 8
R R/W
7 6 5 4-0
R R R R
4-9
ADVANCE INFORMATION
4.18 Memory Base Register
The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 0s; thus, the address range is aligned to a 1M-byte boundary. The bottom 4 bits are read-only and return 0s when read.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0
Memory base
Register: Type: Offset: Default:
Memory base Read/Write, Read-only 20h 0000h
ADVANCE INFORMATION
4.19 Memory Limit Register
The memory limit register defines the upper-limit address of a memory-mapped I/O address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom 4 bits are read-only and return 0s when read.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0
Memory limit
Register: Type: Offset: Default:
Memory limit Read/Write, Read-only 22h 0000h
4.20 Prefetchable Memory Base Register
The prefetchable memory base register defines the base address of a prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 0s; thus, the address range is aligned to a 1M-byte boundary. The bottom 4 bits are read-only and return 0s when read. The prefetchable memory window may be mapped anywhere in the 64-bit address space as indicated by bit 0 returning a value of 1 when read.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0
Prefetchable memory base
Register: Type: Offset: Default:
Prefetchable memory base Read/Write, Read-only 24h 0000h
4-10
4.21 Prefetchable Memory Limit Register
The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom 4 bits are read-only and return 0s when read. The prefetchable memory window may be mapped anywhere in the 64-bit address space as indicated by bit 0 returning a value of 1 when read.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0
Prefetchable memory limit
4.22 Prefetchable Base Upper 32 Bits Register
The prefetchable base upper 32 bits register plus the prefetchable memory base register define the base address of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The prefetchable base upper 32 bits register should be programmed to all 0s when 32-bit addressing is being used.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R/W 0 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Prefetchable base upper 32 bits
Prefetchable base upper 32 bits
Register: Type: Offset: Default:
Prefetchable base upper 32 bits Read/Write 28h 0000 0000h
4-11
ADVANCE INFORMATION
Register: Type: Offset: Default:
Prefetchable memory limit Read/Write, Read-only 26h 0000h
4.23 Prefetchable Limit Upper 32 Bits Register
The prefetchable limit upper 32 bits register plus the prefetchable memory limit register define the base address of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The prefetchable limit upper 32 bits register should be programmed to all 0s when 32-bit addressing is being used.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R/W 0 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Prefetchable limit upper 32 bits
Prefetchable limit upper 32 bits
ADVANCE INFORMATION
Register: Type: Offset: Default:
Prefetchable limit upper 32 bits Read/Write 2Ch 0000 0000h
4.24 I/O Base Upper 16 Bits Register
The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31-AD16 of the 32-bit address that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 9 R/W 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
I/O base upper 16 bits
Register: Type: Offset: Default:
I/O base upper 16 bits Read/Write 30h 0000h
4.25 I/O Limit Upper 16 Bits Register
The I/O limit upper 16 bits register specifies the upper 16 bits corresponding to AD31-AD16 of the 32-bit address that specifies the upper limit of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 9 R/W 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
I/O limit upper 16 bits
Register: Type: Offset: Default:
I/O limit upper 16 bits Read/Write 32h 0000h
4-12
4.26 Capability Pointer Register
The capability pointer register provides the pointer to the PCI configuration header where the PCI power management register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The capability pointer register is read-only and returns DCh when read, indicating the power management registers are located at PCI header offset DCh.
Bit Name Type Default R 1 R 1 R 0 7 6 5 4 R 1 3 R 1 2 R 1 1 R 0 0 R 0
Capability pointer
Register: Type: Offset: Default:
Capability pointer Read-only 34h DCh
The interrupt line register is read/write and is used to communicate interrupt line routing information. Because the bridge does not implement an interrupt signal terminal, this register defaults to FFh.
Bit Name Type Default R/W 1 R/W 1 R/W 1 1 7 6 5 4 Interrupt line R/W R/W 1 R/W 1 R/W 1 R/W 1 3 2 1 0
Register: Type: Offset: Default:
Interrupt line Read/Write 3Ch FFh
4.28 Interrupt Pin Register
The bridge default state does not implement any interrupt terminals. Reads from bits 7-0 of this register return 0s.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Interrupt pin R 0 R 0 R 0 R 0 3 2 1 0
Register: Type: Offset: Default:
Interrupt pin Read-only 3Dh 00h
4-13
ADVANCE INFORMATION
4.27 Interrupt Line Register
4.29 Bridge Control Register
The bridge control register (see Table 4-4) provides many of the same controls for the secondary interface that are provided by the command register for the primary interface. Some bits affect the operation of both interfaces.
Bit Name Type Default R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bridge control
Register: Type: Offset: Default:
BIT 15-12 11 ACCESS R R/W
Bridge control Read/Write, Read-only 3Eh 0000h Table 4-4. Bridge Control Register Description
DESCRIPTION Reserved. Bits 15-12 return 0s when read. Completion discard SERR enable. 0 = SERR signaling disabled for primary discard timeouts (default) 1 = SERR signaling enabled for primary discard timeouts Completion discard timeout status. When set, this bit must be cleared by writing 1 to it. 0 = No discard timer error (default) 1 = Discard timer error. Either primary or secondary discard timer expired and a delayed transaction was discarded from the queue in the bridge. Secondary completion discard timer. Selects the number of PCI clocks that the secondary PCI6050 node will wait for a master on the secondary interface to repeat a delayed transaction request. 0 = The secondary discard timer counts 215 PCI clock cycles (default). 1 = The secondary discard timer counts 210 PCI clock cycles. Primary completion discard timer. Selects the number of PCI clocks that the primary PCI6050 node will wait for a master on the primary interface to repeat a delayed transaction request. 0 = The primary discard timer counts 215 PCI clock cycles (default). 1 = The primary discard timer counts 210 PCI clock cycles. Secondary FBB enable. Controls the ability of the PCI6050 device to generate fast back-to-back transactions on the secondary interface. 0 = PCI6050 device does not generate fast back-to-back transactions on the secondary PIC bus. 1 = PIC6050 device generates fast back-to-back transactions on the secondary PIC bus. Secondary bus reset. When bit 6 is set, the secondary reset signal (PCI_RST) is asserted. PCI_RST is de-asserted by resetting this bit. Bit 6 is encoded as: 0 = Do not force the assertion of PCI_RST (default). 1 = Force the assertion of PCI_RST. Master abort mode. Bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge is the master. If this bit is set, a posted write transaction has completed on the requesting interface, and SERR enable (bit 8) of the PCI command register (offset 04h, see Section 4.3) is 1, then SERR is asserted when a master abort occurs. If the transaction has not completed, then a target abort is signaled. If the bit is cleared, then all 1s are returned on reads and write data is accepted and discarded when a transaction that crosses the bridge is terminated with master abort. The default state of bit 5 after a reset is 0. 0 = Do not report master aborts (return FFFF FFFFh on reads and discard data on writes) (default). 1 = Report master aborts by signaling target abort if possible, or if SERR is enabled via bit 1 of this register, by asserting SERR. Reserved. Bit 4 returns 0 when read. VGA enable. When bit 3 is set, the bridge positively decodes and forwards VGA-compatible memory addresses in the video frame buffer range 000A 0000h-000B FFFFh, I/O addresses in the range 03B0h-03BBh, and 03C0-03DFh from the primary to the secondary interface, independent of the I/O and memory address ranges. When this bit is set, the bridge blocks forwarding of these addresses from the secondary to the primary. Reset clears this bit. Bit 3 is encoded as: 0 = Do not forward VGA-compatible memory and I/O addresses from the primary to the secondary interface (default). 1 = Forward VGA-compatible memory and I/O addresses from the primary to the secondary, independent of the I/O and memory address ranges and independent of the ISA enable bit.
ADVANCE INFORMATION
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
4 3
R R/W
4-14
Table 4-4. Bridge Control Register Description (Continued)
BIT 2 ACCESS R/W DESCRIPTION ISA enable. When bit 2 is set, the bridge blocks the forwarding of ISA I/O transactions from the primary to the secondary, addressing the last 768 bytes in each 1K-byte block. This applies only to the addresses (defined by the I/O window registers) that are located in the first 64K bytes of PCI I/O address space. From the secondary to the primary, I/O transactions are forwarded if they address the last 768 bytes in each 1K-byte block in the address range specified in the I/O window registers. Bit 2 is encoded as: 0 = Forward all I/O addresses in the address range defined by the I/O base and I/O limit registers (default). 1 = Block forwarding of ISA I/O addresses in the address range defined by the I/O base and I/O limit registers when these I/O addresses are in the first 64K bytes of PCI I/O address space and address the top 768 bytes of each 1K-byte block. SERR forwarding enable. Bit 1 controls the forwarding of secondary interface SERR assertions to the primary interface. Only when this bit is set does the bridge forward SERR to the primary bus signal SERR. For the primary interface to assert SERR, bit 8 of the PCI command register (offset 04h, see Section 4.3) must be set. 0 = SERR disabled (default) 1 = SERR enabled Secondary parity error response enable. Bit 0 controls the bridge response to parity errors on the secondary interface. When this bit is set, the secondary PCI6050 node asserts PERR to report parity errors on the secondary interface. 0 = Ignore address and parity errors on the secondary interface (default). 1 = Enable parity error reporting and detection on the secondary interface.
1
R/W
0
R/W
4-15
ADVANCE INFORMATION
ADVANCE INFORMATION
4-16
5 Extension Registers
The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (that is, registers 40h-FFh in PCI configuration space in the PCI6050 device). These registers can be accessed through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard PCI-to-PCI bridge. Table 5-1 describes the bit functions in the chip control register.
5.1 Chip Control Register
The chip control register contains read/write and read-only bits and has a default value of 00h. This register is used to control the functionality of certain PCI transactions.
Bit Name Type Default R 0 R 0 R/W 0 0 7 6 5 4 Chip control 0 0 0 0 R/W 3 R 2 R 1 R/W 0 R
Register: Type: Offset: Default:
BIT 7-6 5 ACCESS R R/W
Chip control Read/Write, Read only 40h 00h Table 5-1. Chip Control Register Description
DESCRIPTION Reserved. Bits 7-5 return 0s when read. Transaction forwarding control for I/O and memory cycles. 0 = Transaction forwarding is controlled by bits 0 and 1 of the PCI command register (offset 04h, see Section 4.3) (default). 1 = Transaction forwarding is disabled if GPIO3 is driven high. Memory read prefetch disable. When bit 4 is set, memory read prefetching is disabled. 0 = Upstream memory reads are enabled (default). 1 = Upstream memory reads are disabled. Reserved. Bits 3-2 return 0s when read. Memory write and memory write and invalidate disconnect control. 0 = Disconnects on queue full or 4-KB boundaries (default) 1 = Disconnects on queue full, 4-KB boundaries, and cache line boundaries Reserved. Bit 0 returns 0 when read.
4
R/W
3-2 1
R R/W
0
R
5-1
ADVANCE INFORMATION
5.2 Diagnostic Control Register
The diagnostic control register is used to control or check the functionality of the serial PCI link or the serial ROM implementation. Table 5-2 describes the bit functions in the diagnostic control register.
Bit Name Type Default R 0 R/W 0 R/W x 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Diagnostic control
Register: Type: Offset: Default:
BIT 7 ACCESS R R/W
Diagnostic control Read-only, Read/Write 41h 00h Table 5-2. Diagnostic Control Register Description
DESCRIPTION Reserved. Bit 7 returns 0 when read. Serial ROM test mode. 0 = Serial ROM clock is PCI clock divided by 256 (default). 1 = Serial ROM clock is PCI clock divided by 4. CRC enable. Bit 5 reflects the PCI6050 mode of operation (CRC or non-CRC). Hardware updates this bit with the value of CRC_EN pin (pin 1) latched during reset. After reset, this may be used to switch modes. 0 = The PCI6050 device does not use a 16-bit CRC to protect the serial link packets. 1 = The PCI6050 device uses a 16-bit CRC to protect the serial link packets. Link dead. A primary PCI6050 device sets this bit if the start-up timer expires without receiving a confirmation packet from the secondary node. This bit can be cleared by a write of 1, which means that the node repeats the handshaking mechanism to establish the link. 0 = The serial link is functional and the secondary node is available. 1 = The serial link is nonfunctional and/or the secondary node is unavailable. GPIOTOIIC. Allows software to route the GPIO control registers to the SDA and SCL terminals for in-circuit serial ROM programming. 0 = GPIO1 and GPIO2 registers control their respective terminals. 1 = GPIO1 and GPIO2 registers control SDA and SCL, respectively. Internal counter test. These bits are used for chip validation only and should not be modified during operation in an actual system. Chip and secondary bus reset control. Writing a 1 to this bit causes the PCI6050 device to set bit 6 of the bridge control register (offset 3Eh, see Section 4.29) and internally reset the configuration registers. Bit 6 of the bridge control register is not reset by the internal reset. Bit 0 is self-clearing.
ADVANCE INFORMATION
6
5
R/W
4
R/W
3
R/W
2-1 0
R/W R/W
5-2
5.3 Arbiter Control Register
The arbiter control register is used for the bridge's internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The secondary PCI6050 node is the only secondary bus initiator that defaults to the higher priority arbitration tier. This internal arbiter is used in a secondary PCI6050 node if EXTARB (pin 207) is low. If EXTARB is high, then the PCI6050 device communicates to the external secondary PCI bus arbiter via REQ0 and GNT0. When PCI6050 device internal arbiter is used, a master may be connected to REQ0 and GNT0. Table 5-3 describes the bit functions in the arbiter control register.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R/W 1 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Arbiter control
Table 5-3. Arbiter Control Register Description
BIT 15-10 9 ACCESS R R/W Reserved. Bits 15-10 return 0s when read. Bridge tier select. This bit determines the priority of the PCI6050 bridge in the two-tier arbitration scheme. 0 = Lowest priority tier 1 = Highest priority tier (default) GNT8 tier select. This bit determines the priority of the GNT8 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT7 tier select. This bit determines the priority of the GNT7 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT6 tier select. This bit determines the priority of the GNT6 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT5 tier select. This bit determines the priority of the GNT5 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT4 tier select. This bit determines the priority of the GNT4 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT3 tier select. This bit determines the priority of the GNT3 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT2 tier select. This bit determines the priority of the GNT2 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT1 tier select. This bit determines the priority of the GNT1 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier GNT0 tier select. This bit determines the priority of the GNT0 device in the two-tier arbitration scheme. 0 = Lowest priority tier (default) 1 = Highest priority tier DESCRIPTION
8
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
5-3
ADVANCE INFORMATION
Register: Type: Offset: Default:
Arbiter control Read/Write, Read-only 42h 0200h
5.4 Primary SERR Event Disable Register
The primary SERR event disable register is used to enable/disable SERR event on the primary interface. All events are enabled by default. Table 5-4 describes the bit functions in the primary SERR event disable register.
Bit Name Type Default R 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R 0
Primary SERR event disable
Register: Type: Offset: Default:
BIT 7 ACCESS R R/W
Primary SERR event disable Read/Write, Read-only 64h 00h Table 5-4. Primary SERR Event Disable Register Description
DESCRIPTION Reserved. Bit 7 returns 0 when read. Master delayed read timeout 0 = SERR is signaled on a master timeout after 224 retries on a delayed read (default). 1 = SERR is not signaled on a master timeout. Master delayed write timeout 0 = SERR is signaled on a master timeout after 224 retries on a delayed write (default). 1 = SERR is not signaled on a master timeout. Master abort on posted write transactions. When set, bit 4 enables SERR reporting on master aborts on posted write transactions. 0 = Master aborts on posted writes are enabled (default). 1 = Master aborts on posted writes are disabled. Target abort on posted writes. When set, bit 3 enables SERR reporting on target aborts on posted write transactions. 0 = Target aborts on posted writes are enabled (default). 1 = Target aborts on posted writes are disabled. Master posted write timeout 0 = SERR is signaled on a master timeout after 224 retries on a posted write (default). 1 = SERR is not signaled on a master timeout. Posted write parity error 0 = SERR is signaled on a posted write parity error (default). 1 = SERR is not signaled on a posted write parity error. Reserved. Bit 0 returns 0 when read.
ADVANCE INFORMATION
6
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R
5-4
5.5 Primary GPIO Output Data Register
The primary GPIO output data register controls the data driven on the GPIO terminals of the primary node when configured as outputs. Table 5-5 describes the bit functions in the primary GPIO output data register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Primary GPIO output data
Register: Type: Offset: Default:
BIT 7-4 3-0 ACCESS R/W R/W
Primary GPIO output data ReadWrite 65h 00h Table 5-5. Primary GPIO Output Data Register Description
DESCRIPTION GPIO3-GPIO0 output high. Writing a 1 to any of these bits causes the corresponding GPIO signal to be driven high. Writing a 0 has no effect. GPIO terminals programmed as inputs are not affected by these bits. GPIO3-GPIO0 output low. Writing a 1 to any of these bits causes the corresponding GPIO signal to be driven low. Writing a 0 has no effect. GPIO terminals programmed as inputs are not affected by these bits.
5.6 Primary GPIO Output Enable Register
The primary GPIO output enable register controls the direction of the primary node GPIO signals. By default all GPIO terminals are inputs. Table 5-6 describes the bit functions in the primary GPIO output enable register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Primary GPIO output enable
Register: Type: Offset: Default:
BIT 7-4 3-0 ACCESS R/W R/W
Primary GPIO output enable Read/Write 66h 00h Table 5-6. Primary GPIO Output Enable Register Description
DESCRIPTION GPIO3-GPIO0 output enable. Writing a 1 to any of these bits causes the corresponding GPIO signal to be configured as an output. Writing a 0 has no effect. GPIO3-GPIO0 input enable. Writing a 1 to any of these bits causes the corresponding GPIO signal to be configured as an input. Writing a 0 has no effect.
5-5
ADVANCE INFORMATION
5.7 Primary GPIO Input Data Register
The primary GPIO input data register returns the current state of the primary node GPIO terminals when read. Table 5-7 describes the bit functions in the GPIO input data register.
Bit Name Type Default R x R x R x 7 6 5 4 R x 3 R 0 2 R 0 1 R 0 0 R 0
Primary GPIO input data
Register: Type: Offset: Default:
BIT 7-4 ACCESS R R
Primary GPIO input data Read-only 67h 00h Table 5-7. Primary GPIO Input Data Register Description
DESCRIPTION GPIO3-GPIO0 input data. These four bits return the current state of the GPIO terminals. Reserved. Bits 3-0 return 0s when read.
ADVANCE INFORMATION
5-6
3-0
5.8 Primary CLKOUT Control Register
The primary CLKOUT control register is used to control the primary node clock outputs. Table 5-8 describes the bit functions in the primary clock control register.
Bit Name Type Default R 0 R 0 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1
Primary CLKOUT control
Register: Type: Offset: Default:
BIT 15-14 13 ACCESS R R/W
Primary CLKOUT control Read/Write, Read-only 68h 3FFFh Table 5-8. Primary CLKOUT Control Register Description
DESCRIPTION Reserved. Bits 15-14 return 0s when read. CLKOUT9 disable 0 = CLKOUT9 enabled 1 = CLKOUT9 disabled and driven high (default) CLKOUT8 disable 0 = CLKOUT8 enabled 1 = CLKOUT8 disabled and driven high (default) CLKOUT7 disable 0 = CLKOUT7 enabled 1 = CLKOUT7 disabled and driven high (default) CLKOUT6 disable 0 = CLKOUT6 enabled 1 = CLKOUT6 disabled and driven high (default) CLKOUT5 disable 0 = CLKOUT5 enabled 1 = CLKOUT5 disabled and driven high (default) CLKOUT4 disable 0 = CLKOUT4 enabled 1 = CLKOUT4 disabled and driven high (default) CLKOUT3 disable 00, 01, 10 = CLKOUT3 enabled 11 = CLKOUT3 disabled and driven high (11 = default) CLKOUT2 disable 00, 01, 10 = CLKOUT2 enabled 11 = CLKOUT2 disabled and driven high (11 = default) CLKOUT1 disable 00, 01, 10 = CLKOUT1 enabled 11 = CLKOUT1 disabled and driven high (11 = default) CLKOUT0 disable 00, 01, 10 = CLKOUT0 enabled 11 = CLKOUT0 disabled and driven high (11 = default)
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7-6
R/W
5-4
R/W
3-2
R/W
1-0
R/W
5-7
ADVANCE INFORMATION
5.9 Primary SERR Status Register
The primary SERR status register indicates the cause of an SERR event on the primary interface. Table 5-9 describes the bit functions in the primary SERR status register.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
Primary SERR status
Register: Type: Offset: Default:
BIT 7 ACCESS R/W R/W R/W R/W R/W R/W R/W
Primary SERR status Read-only 6Ah 00h Table 5-9. Primary SERR Status Register Description
DESCRIPTION Delayed transaction master timeout SERR status. SERR condition has occurred because the master did not repeat a read or write transaction before the master timeout counter expired on the initiator's PCI bus. Write 1 to clear this bit. Delay read no data from target SERR status. SERR condition has occurred because the PCI6050 device was unable to read any data from the target after 224 attempts. Write 1 to clear this bit. Delayed write non-delivery SERR status. SERR condition has occurred because the PCI6050 device was unable to deliver delayed write data after 224 attempts. Write 1 to clear this bit. Master abort on posted writes SERR status. This bit indicates that an SERR condition occurred because a posted write request bound for either the primary or secondary bus was master-aborted when initiated by the PCI6050 device. Target abort on posted writes SERR status. This bit indicates that an SERR condition occurred because a posted write request bound for either the primary or secondary bus was target-aborted when initiated by the PCI6050 device. Posted write nondelivery SERR status. This bit indicates that an SERR condition occurred because the PCI6050 device was unable to deliver the posted write data to the target after 224 attempts. Write 1 to clear this bit. Parity error on posted writes SERR Status. This bit indicates that an SERR condition occurred because a posted write request bound for either the primary or secondary bus resulted in a parity error when the PCI6050 device initiated the transaction on the remote bus. This bit can be cleared by a write of 1. Address parity error status. This bit indicates the occurrence of address parity SERR condition has occurred. This bit can be cleared by a write of 1.
ADVANCE INFORMATION
6 5 4 3 2 1
0
R/W
5-8
5.10 Secondary CLKOUT Control Register
The secondary CLKOUT control register is used to control the secondary node clock outputs. Table 5-10 describes the bit functions in the secondary clock control register.
Bit Name Type Default R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Secondary CLKOUT control
Register: Type: Offset: Default:
BIT 15-14 13 ACCESS R R/W
Secondary CLKOUT control Read/Write, Read-only 6Ch 0000h Table 5-10. Secondary CLKOUT Control Register Description
DESCRIPTION Reserved. Bits 15-14 return 0s when read. CLKOUT9 disable 0 = CLKOUT9 enabled (default) 1 = CLKOUT9 disabled and driven high CLKOUT8 disable 0 = CLKOUT8 enabled (default) 1 = CLKOUT8 disabled and driven high CLKOUT7 disable 0 = CLKOUT7 enabled (default) 1 = CLKOUT7 disabled and driven high CLKOUT6 disable 0 = CLKOUT6 enabled (default) 1 = CLKOUT6 disabled and driven high CLKOUT5 disable 0 = CLKOUT5 enabled (default) 1 = CLKOUT5 disabled and driven high CLKOUT4 disable 0 = CLKOUT4 enabled (default) 1 = CLKOUT4 disabled and driven high CLKOUT3 disable 00, 01, 10 = CLKOUT3 enabled (00 = default) 11 = CLKOUT3 disabled and driven high CLKOUT2 disable 00, 01, 10 = CLKOUT2 enabled (00 = default) 11 = CLKOUT2 disabled and driven high CLKOUT1 disable 00, 01, 10 = CLKOUT1 enabled (00 = default) 11 = CLKOUT1 disabled and driven high CLKOUT0 disable 00, 01, 10 = CLKOUT0 enabled (00 = default) 11 = CLKOUT0 disabled and driven high
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7-6
R/W
5-4
R/W
3-2
R/W
1-0
R/W
5-9
ADVANCE INFORMATION
5.11 Secondary SERR Status Register
The secondary SERR status register indicates the cause of an SERR event on the secondary interface. Table 5-11 describes the bit functions in the secondary SERR status register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Secondary SERR status
Register: Type: Offset: Default:
BIT 7 ACCESS R/W R/W R/W R/W R/W R/W R/W
Secondary SERR status Read/Write 6Eh 00h Table 5-11. Secondary SERR Status Register Description
DESCRIPTION Delayed transaction master timeout SERR status. SERR condition has occurred because master did not repeat a read or write transaction before the master timeout counter expired on the initiator's PCI bus. Write 1 to clear this bit. Delay read no data from target SERR status. SERR condition has occurred because the PCI6050 device was unable to read any data from the target after 224 attempts. Write 1 to clear this bit. Delayed write nondelivery SERR status. SERR condition has occurred because the PCI6050 device was unable to deliver delayed write data after 224 attempts. Write 1 to clear this bit. Master abort on posted writes SERR status. This bit indicates that an SERR condition occurred because a posted write request bound for either the primary or secondary bus was master aborted when initiated by the PCI6050 device. Target abort on posted writes SERR status. This bit indicates that an SERR condition occurred because a posted write request bound for either the primary or secondary bus was target aborted when initiated by the PCI6050 device. Posted write non-delivery SERR status. SERR condition has occurred because the PCI6050 device was unable to deliver the posted write data to the target after 224 attempts. Write 1 to clear this bit. Parity error on posted writes SERR status. This bit indicates that an SERR condition occurred because a posted write request bound for either the primary or secondary bus resulted in a parity error when the PCI6050 device initiated the transaction on the remote bus. This bit can be cleared by a write of 1. Address parity error status. This bit indicates the occurrence of address parity SERR condition has occurred. This bit can be cleared by a write of 1.
ADVANCE INFORMATION
6 5 4 3 2 1
0
R/W
5-10
5.12 General Purpose Event Register
This register is provided for control and status of the general purpose event signal, GPE. The GPE, among other things, is used to indicate that there is a change of accessibility for devices on the system (for example, those behind the PCI6050 device PCI-to-PCI bridge implementation), and the GPE software handler requests appropriate PCI re-enumeration from the operating system. Table 5-12 describes the bit functions in the general purpose event register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 0 15 14 13 12 11 10 9 R/W 8 R/W 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R/W 0 1 R/W 0 0 R/W 1
General purpose event
Register: Type: Offset: Default:
BIT 15 14 13 12 11 10 9 8 7-3 2 1 0 ACCESS R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
General purpose event Read-only, Read/Write A0h 1001h
DESCRIPTION Start-up complete status. This bit is set when the start-up complete bit (bit 4) in the extended diagnostic status register (offset A6h, see Section 5.13) is set. This bit reflects the status of the start-up complete bit. GPE on start-up complete status. This bit enables the start-up complete bit (bit 4) in the extended diagnostic status register (offset A6h, see Section 5.13) to generate a GPE event. Unexpected secondary start-up status. This bit is set when an unexpected secondary start-up packet has been received. GPE on unexpected secondary start-up status. This bit enables an unexpected secondary start-up packet to generate a GPE event. GPE on receiver error. This bit enables the receive error count register (offset BFh, see Section 5.19). GPE on active state status. This bit enables the PCI6050 device to generate a GPE event when the serial link goes active. Force GPE. When software writes a 1 to this bit, a GPE is generated, and this bit is automatically cleared, returning 0 when read. GPE service scratch bit. This bit is implemented as read/write, and provides no additional functionality. Reserved. Bits 7-3 return 0s when read. Active state status. This bit is set when the PCI6050 node is active to start the transaction and the link active bit (bit 3) in the extended diagnostic status register (offset A6h, see Section 5.13) has transitioned to 1. GPE status. This bit is set when any of the potential GPE events occur and the associated enable bit is set. When this bit is set, a GPE is signaled if the GPE enable bit (bit 0) is set. GPE enable. This bit is the output enable for the GPE output signal. When this bit and an enabled event occurs, a generalpurpose event is signaled through the GPE output.
5-11
ADVANCE INFORMATION
Table 5-12. General Purpose Event Register Description
5.13 Extended Diagnostic Status Register
This register is provided for diagnostic purposes. Table 5-13 describes the bit functions in the extended diagnostic status register.
Bit Name Type Default R/W 0 R/W 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W x
Extended diagnostic status
Register: Type: Offset: Default:
BIT 15 ACCESS R/W
Extended diagnostic status Read/Write, Read-only A6h 0000h Table 5-13. Extended Diagnostic Status Register Description
DESCRIPTION Hot-swap switch status. Returns the logical value of HS_SWITCH input (pin 108). 0 = Hot-swap handle closed 1 = Hot-swap handle open External arbiter status. This bit indicates the status of the EXTARB input (pin 207) on the secondary node. 0 = Internal arbitration in use 1 = External arbiter present and in use Reserved. Bits 13-5 return 0s when read. Start-up complete. This bit reflects the current state of the serial link start-up process and is set once the start-up sequence has completed. Link active. This bit is set when the serial link start-up procedure has been completed and the link is ready to transmit data. Serial ROM error status. This bit is set when an error occurs on the serial ROM interface. Serial ROM busy status. This bit is set when the serial ROM interface is active, or busy, and is cleared when the serial ROM interface is idle. Serial ROM detect status. This bit indicates the presence of a serial ROM as determined by the state of the SCL terminal (pin 197) during reset. 0 = No serial ROM was detected. 1 = A serial ROM is present.
ADVANCE INFORMATION
14
R/W
13-5 4 3 2 1 0
R R/W R/W R/W R/W R/W
5-12
5.14 Secondary GPIO Output Data Register
The secondary GPIO output data register controls the data driven on the secondary node GPIO terminals configured as outputs. Table 5-14 describes the bit functions in the secondary GPIO output data register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Secondary GPIO output data
Register: Type: Offset: Default:
BIT 7-4 3-0 ACCESS R/W R/W
Secondary GPIO output data Read/Write A9h 00h Table 5-14. Secondary GPIO Output Data Register Description
DESCRIPTION GPIO3-GPIO0 output high. Writing a 1 to any of these bits causes the corresponding GPIO signal to be driven high. Writing a 0 has no effect. GPIO terminals programmed as inputs are not affected by these bits. GPIO3-GPIO0 output low. Writing a 1 to any of these bits causes the corresponding GPIO signal to be driven low. Writing a 0 has no effect. GPIO terminals programmed as inputs are not affected by these bits.
5.15 Secondary GPIO Output Enable Register
The secondary GPIO output enable register controls the direction of the secondary node GPIO signal. By default all GPIO terminals are inputs. Table 5-15 describes the bit functions in the secondary GPIO output enable register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Secondary GPIO output data
Register: Type: Offset: Default:
BIT 7-4 3-0 ACCESS R/W R/W
Secondary GPIO output data Read/Write AAh 00h Table 5-15. Secondary GPIO Output Enable Register Description
DESCRIPTION GPIO3-GPIO0 output enable. Writing a 1 to any of these bits causes the corresponding GPIO signal to be configured as an output. Writing a 0 has no effect. GPIO3-GPIO0 input enable. Writing a 1 to any of these bits causes the corresponding GPIO signal to be configured as an input. Writing a 0 has no effect.
5-13
ADVANCE INFORMATION
5.16 Secondary GPIO Input Data Register
The secondary GPIO input data register returns the current state of the secondary node GPIO terminals when read. Table 5-16 describes the bit functions in the secondary GPIO input data register.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
Secondary GPIO input data
Register: Type: Offset: Default:
BIT 7-4 ACCESS R R
Secondary GPIO input data Read-only ABh 00h Table 5-16. Secondary GPIO Input Data Register Description
DESCRIPTION GPIO3-GPIO0 input data. These four bits return the current state of the GPIO terminals. Reserved. Bits 3-0 return 0s when read.
ADVANCE INFORMATION
3-0
5.17 Sequence Error Count Register
The sequence error count register provides the number of packet sequence errors that have occurred on the serial interface. The counter stops after 255 errors are encountered and can be cleared by writing FFh to this location.
Bit Name Type Default RC 0 RC 0 RC 0 7 6 5 4 RC 0 3 RC 0 2 RC 0 1 RC 0 0 RC 0
Sequence error count
Register: Type: Offset: Default:
Sequence error count Read-clear BDh 00h
5.18 CRC Error Count Register
The CRC error count register provides the number of CRC errors that have occurred on the serial interface. The counter stops after 255 errors are encountered and can be cleared by writing FFh to this location.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
CRC error count
Register: Type: Offset: Default:
CRC error count Read-only BEh 00h
5-14
5.19 Receive Error Count Register
The receive error count register provides the number of receive errors that were encountered by the PCI6060 on the serial interface. The counter stops after 255 errors are encountered and can be cleared by writing FFh to this location.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
Receive error count
Register: Type: Offset: Default:
Receive error count Read-only BFh 00h
5.20 Transceiver Test Control and Status Register
Bit Name Type Default
15 R/W 0
14 R/W 0
13 R 0
12 R 0
11 R 0
10 R 0
9 R 0
8 R 0
7 R 0
6 R 0
5 R 0
4 R 0
3 R 0
2 R/W 0
1 R/W 0
0 R 0
Transceiver test control and status
Register: Type: Offset: Default:
BIT 15 14 13-3 2 1 0 ACCESS R/W R/W R R/W R/W R
Transceiver test control and status Read/Write, Read-only C0h 0000h Table 5-17. Transceiver Test Control and Status Register Description
DESCRIPTION Primary PRBS_PASS status. This bit reflects the state of the PRBS_PASS terminal. A value of 1 indicates that the PRBS test passed. Primary PRBS_FAIL status. This bit reflects the state of the PRBS_PASS terminal. A value of 1 indicates that the PRBS test failed. Reserved. Bits 13-3 return 0s when read. Primary loop-back test enable. A primary PCI6050 node drives the LOOP_EN signal to a logic level consistent with the value of this bit. When this bit is set in a primary PCI6050 node, the loop-back test is enabled until this bit is cleared. Primary PRBS test enable. A primary PCI6050 node drives the PRBS_EN signals to a logic level consistent with the value of this bit. When this bit is set in a primary PCI6050 node, the PRBS test is enabled until this bit is cleared. Reserved. Bit 0 returns 0 when read.
5-15
ADVANCE INFORMATION
The transceiver test control and status register is provided for TI diagnostic purposes only and should never be used in an actual system. Table 5-17 describes the bit functions in the transceiver test control and status register.
5.21 PM Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The capability ID register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Capability ID R 0 R 0 R 0 R 1 3 2 1 0
Register: Type: Offset: Default:
Capability ID Read-only DCh 01h
5.22 PM Next Item Pointer Register
ADVANCE INFORMATION
The PM next item pointer register is used to indicate the next item in the linked list of PCI power management (PM) capabilities. The next item pointer returns E4h indicating that the PCI6050 device supports more than one extended capability.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 1
Next item pointer
Register: Type: Offset: Default:
Next item pointer Read-only DDh 00h
5-16
5.23 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PCI6050 functions related to power management. The PCI6050 function supports D0, D1, D2, and D3 power states. Table 5-18 describes the bit functions in the power management capabilities register.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 1 15 14 13 12 11 10 9 R 1 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 1 0 R 0
Power management capabilities
Register: Type: Offset: Default:
BIT 15-11 ACCESS R
Power management capabilities Read-only DEh 0602h Table 5-18. Power Management Capabilities Register Description
DESCRIPTION PME support. This five-bit field indicates the power states that the device supports asserting PME. A 0 for any of these bits indicates that the PCI6050 device cannot assert the PME signal from that power state. For the PCI6050 device, these five bits return 00000b when read indicating that PME is not supported. D2 support. Bit 10 returns 1 when read indicating that the bridge function supports the D2 device power state. D1 support. Bit 9 returns 1 when read indicating that the bridge function supports the D1 device power state. Auxiliary current. Returns 000b when read. PME generation from D3cold is not supported. Device-specific initialization. This bit returns 0 when read, indicating that the bridge function does not require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it. Auxiliary power source. Bit 4 returns 0 when read indicating that the PCI6050 device does not require an auxiliary power supply. PME clock. This bit is implemented as read-only 0, because the PME signaling is not supported. Version. By returning 010b when read, this field indicates that the PCI6050 device is compliant with Revision 1.1 of the PCI Bus Power Management Specification.
10 9 8-6 5 4 3 2-0
R R R R R R R
5-17
ADVANCE INFORMATION
5.24 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI6050 device. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. Table 5-19 describes the bit functions in the power management control/status register.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R/W 0 0 R/W 0 Power management control/status
Register: Type: Offset: Default:
BIT ACCESS R R R R R R/W
Power management control/status Read/Write, Read-only E0h 0000h Table 5-19. Power Management Control/Status Register Description
DESCRIPTION PME status. This bit returns a 0 when read because the PCI6050 device does not support PME. Data scale. This two-bit read-only field indicates the scaling factor to be used when interpreting the value of the data register. These bits return only 00b because the data register is not implemented. Data select. This 4-bit field is used to select which data is to be reported through the data register and data scale field. These bits return only 0000b because the data register is not implemented. PME enable. This bit returns 0 when read because the PCI6050 device does not support PME signaling. Reserved. Bits 7-2 return 0s when read. Power state. This two-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of this is given below: 00 = D0 01 = D1 10 = D2 11 = D3hot
ADVANCE INFORMATION
15 14-13 12-9 8 7-2 1-0
5.25 PMCSR Bridge Support Register
The PMCSR bridge support register is required for all PCI bridges and supports PCI bridge-specific functionality. Table 5-20 describes the bit functions in the PMCSR bridge support register.
Bit Name Type Default R 1 R 1 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
PMCSR bridge support
Register: Type: Offset: Default:
BIT 7 6 ACCESS R R
PMCSR bridge support Read/Write, Read-only E2h C0h Table 5-20. PMCSR Bridge Support Register Description
DESCRIPTION Bus power control enable. This bit is implemented as read-only 1, indicating the bus power state follows the PCI6050 device power state. B2/B3 support for D3hot. This bit is implemented as read-only 1, indicating that when the PCI6050 device is programmed to D3hot the secondary bus clock is stopped. The PCI6050 device stops the CLKOUT[8-0] outputs at a low state when programmed to D3. CLKOUT9 cannot be stopped through PCI power management. Reserved. Bits 5-0 return 0s when read.
5-0
R
5-18
5.26 PM Data Register
The data register is an optional, 8-bit read-only register that provides a mechanism for the function to report state-dependent operating data such as power consumed or heat dissipation. The PCI6050 device does not implement the data register.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 PM data R 0 R 0 R 0 R 0 3 2 1 0
Register: Type: Offset: Default:
PM data Read-only E3h 00h
5.27 HS Capability ID Register
The HS capability ID register identifies the linked list item as the register for CPCI hot-swap (HS) capabilities. The register returns 06h when read, which is the unique ID assigned by the PICMG for PCI location of the capabilities pointer and the value.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 1 1 R 1 0 R 0
HS capability ID
Register: Type: Offset: Default:
HS capability ID Read-only E4h 06h
5.28 HS Next Item Pointer Register
The HS next item pointer register is used to indicate the next item in the linked list of CPCI hot-swap capabilities. Because the PCI6050 functions include only two capabilities list items, this register returns 0s when read.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
HS next item pointer
Register: Type: Offset: Default:
HS next item pointer Read-only E5h 00h
5-19
ADVANCE INFORMATION
5.29 Primary CPCI Hot-Swap Control and Status Register
The hot-swap control status register contains control and status information for CPCI hot-swap resources. Table 5-21 describes the bit functions in the hot-swap control status register.
Bit Name Type Default R/W 0 R/W 0 R 0 7 6 5 4 R 0 3 R/W 0 2 R 0 1 R/W 0 0 R 0
Primary PCI hot-swap control status
Register: Type: Offset: Default:
BIT 7 ACCESS R/W
Primary PCI hot-swap control status Read/Write, Read-only E6h 00h
DESCRIPTION Primary HS_ENUM insertion status. When set, the HS_ENUM output is driven by the PCI6050 device. This bit defaults to 0, and is set after a PCI reset occurs, the pre-load of serial ROM is complete, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set following an insertion when the board implementing the PCI6050 device is ready for configuration. This bit cannot be set under software control. Primary HS_ENUM extraction status. When set, the HS_ENUM output is driven by the primary PCI6050 node. This bit defaults to 0, and is set when the ejector handle is opened and bit 7 is 0. Thus, this bit is set when the board implementing the primary PCI6050 node is about to be removed. This bit cannot be set under software control. Reserved. Bits 5-4 return 0s when read. Primary LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HS_LED) under normal conditions. However, for a duration following a PCI_RST, the HS_LED output is driven high by the PCI6050 device and this bit will be ignored. When this bit is interpreted, a 1 drives HS_LED high, and a 0 drives HS_LED low. Following a PCI_RST, the HS_LED output is driven high by the PCI6050 device until the ejector handle is closed. When these conditions are met, the HS_LED is under software control via this bit. Reserved. Bit 2 returns 0 when read. Primary HS_ENUM interrupt mask. This bit allows the HS_ENUM output to be masked by software. Bits 6 and 7 are set independently from this bit. 0 = Enable HS_ENUM output 1 = Mask HS_ENUM output Reserved. Bit 0 returns 0 when read.
Table 5-21. Primary CPCI Hot-Swap Control and Status Register Description
ADVANCE INFORMATION
6
R/W
5-4 3
R R/W
2 1
R R/W
0
R
5.30 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for certain operating systems.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 9 R/W 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Subsystem vendor ID
Register: Type: Offset: Default:
Subsystem vendor ID Read/Write E8h 0000h
5-20
5.31 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain operating systems.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Subsystem ID
Register: Type: Offset: Default:
Subsystem ID Read/Write EAh 0000h
5.32 FIFO BIST Register
Bit Name Type Default Bit Name Type Default
31 R/W 0 15 R 0
30 R 0 14 R 0
29 R 0 13 R 0
28 R 0 12 R 0
27 R 0 11 R 0
26 R 0 10 R 0
25 R 0 9 R 0
24 R 0 8 R 0
23 R 0 7 R 0
22 R 0 6 R 0
21 R 0 5 R 0
20 R 0 4 R 0
19 R 0 3 R 0
18 R 0 2 R 0
17 R 0 1 R 0
16 R 0 0 R 0
FIFO BIST
FIFO BIST
Register: Offset: Type: Default:
BIT 31 30-26 25-24 ACCESS R/W R R
FIFO BIST ECh Read/Write, Read-only 0000h Table 5-22. FIFO BIST Register Description
DESCRIPTION Built-in self-test enable. When this bit is set, the BIST function is enabled. This bit is self-clearing when the BIST completes. Reserved. Bits 30-26 return 0s when read. Pass fail code. This two-bit field is used to communicate the results of BIST. 00 = Pass 01 = Failed initialization pattern 10 = Failed test pattern write verification 11 = Failed inverted test pattern verification Reserved. Bits 23-11 return 0s when read. SRAM select. This three-bit field is used to communicate which of the four SRAMs have failed BIST. 000 = Transmit posted write FIFO 001 = Transmit completion 0 FIFO 010 = Transmit completion 1 FIFO 011 = Transmit completion 2 FIFO 100 = Receive posted write FIFO 101 = Receive completion 0 FIFO 110 = Receive completion 1 FIFO 111 = Receive completion 2 FIFO Offset address. This field contains the 2K-byte address that is currently being accessed by the BIST logic. After a failure, this field contains the address of the failing DWORD.
23-11 10-8
R R
7-0
R
5-21
ADVANCE INFORMATION
The FIFO BIST register is used for internal TI purposes only and should not be used in an actual system. Table 5-22 describes the bit functions in the FIFO BIST register.
ADVANCE INFORMATION
5-22
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Copyright (c) 2000, Texas Instruments Incorporated

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