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| TSB12LV23A OHCI LynxTM PCI Based IEEE 1394 Host Controller Data Manual 2000 1394 Host Controller Solutions SLLS411 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated Contents Section 1 Title Page 1-1 1-1 1-1 1-2 1-2 1-2 2-1 3-1 3-3 3-3 3-4 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-8 3-9 3-10 3-10 3-11 3-11 3-12 3-12 3-13 3-14 3-14 3-15 3-16 3-17 3-18 4-1 4-4 4-5 4-6 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSB12LV23A Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . 3.1 PCI/CardBus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 3.8 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 CIS Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 3.15 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Capability ID and Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . 3.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 3.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . 3.21 Power Management Extension Register . . . . . . . . . . . . . . . . . . . . . . . . 3.22 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.24 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.25 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . iii 5 6 7 4.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 4.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 4.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 4.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 4.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4.27 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 4.33 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 4.34 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.36 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 4.37 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 4.38 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . 4.39 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 4.40 Isochronous Transmit Context Command Pointer Register . . . . . . . . 4.41 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 4.42 Isochronous Receive Context Command Pointer Register . . . . . . . . 4.43 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . 4.44 IR Digital Video Enhancements Register . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-7 4-7 4-8 4-8 4-9 4-10 4-10 4-11 4-11 4-12 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-20 4-21 4-22 4-22 4-23 4-23 4-24 4-25 4-26 4-27 4-28 4-30 4-31 4-33 4-33 4-34 4-35 4-36 4-37 4-37 4-39 4-40 4-41 5-1 6-1 7-1 iv 8 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Switching Characteristics for PCI Interface . . . . . . . . . . . . . . . . . . . . . . 7.5 Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . . Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 7-1 7-2 7-3 7-3 7-3 8-1 List of Illustrations Figure Title Page 2-1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3-1 TSB12LV23A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 5-1 GPIO2 and GPIO3 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 List of Tables Table Title 2-1 Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Signals Sorted Alphabetically to Terminal Number . . . . . . . . . . . . . . . . . . . . . 2-3 Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 IEEE 1394 PHY/Link Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . 3-6 Latency Timer and Class Cache Line Size Register Description . . . . . . . . . 3-7 Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 CIS Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 CardBus CIS Pointer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . 3-12 Interrupt Line and Pin Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . . . . 3-14 OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Capability ID and Next Item Pointer Register Description . . . . . . . . . . . . . . Page 2-2 2-3 2-3 2-4 2-4 2-5 2-6 2-6 3-1 3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-9 3-10 3-11 3-11 3-12 3-12 v 3-16 Power Management Capabilities Register Description . . . . . . . . . . . . . . . . 3-17 Power Management Control and Status Register Description . . . . . . . . . . 3-18 Power Management Extension Register Description . . . . . . . . . . . . . . . . . . 3-19 Miscellaneous Configuration Register Description . . . . . . . . . . . . . . . . . . . . 3-20 Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . . 3-21 Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . . . 4-5 CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . . . 4-7 Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . . . 4-9 Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . . . 4-10 Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Isochronous Receive Channel Mask High Register Description . . . . . . . . 4-13 Isochronous Receive Channel Mask Low Register Description . . . . . . . . . 4-14 Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . . 4-17 Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . . . 4-18 Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . . 4-23 Asynchronous Request Filter High Register Description . . . . . . . . . . . . . . . 4-24 Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . . 4-25 Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . . 4-26 Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . . 4-27 Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . . 4-28 Asynchronous Context Command Pointer Register Description . . . . . . . . 4-29 Isochronous Transmit Context Control Register Description . . . . . . . . . . . 4-30 Isochronous Receive Context Control Register Description . . . . . . . . . . . . 4-31 Isochronous Receive Context Match Register Description . . . . . . . . . . . . . 4-32 IR Digital Video Enhancements Register Description . . . . . . . . . . . . . . . . . 6-1 Registers and Bits Loadable Through Serial ROM . . . . . . . . . . . . . . . . . . . . . 6-2 Serial ROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-14 3-14 3-15 3-16 3-17 3-18 4-1 4-4 4-5 4-6 4-7 4-8 4-9 4-11 4-12 4-13 4-15 4-16 4-17 4-18 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-30 4-31 4-33 4-34 4-35 4-36 4-37 4-40 4-41 6-1 6-2 vi 1 Introduction This chapter provides an overview of the Texas Instruments TSB12LV23A device and its features. 1.1 Description The Texas Instruments TSB12LV23A device, the OHCI-Lynxt PCI-based IEEE 1394 host controller, is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specifications. The chip provides the IEEE 1394 link function and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. As required by the 1394 Open Host Controller Interface Specification (OHCI) and the IEEE 1394a-2000 specification, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV23A device is compliant with the PCI Bus Power Management Interface Specification, according to the PC 99 Design Guide requirements. The TSB12LV23A device supports the D0, D2, and D3 power states. The TSB12LV23A design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132 Mbytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer 1394 data. The TSB12LV23A device provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance. The TSB12LV23A device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface. The TSB12LV23A device implements an enhancement for formatted DV and audio/music isochronous transmissions which implement the common isochronous packet (CIP) format defined by IEC61883. The enhancements to the isochronous DMA contexts are implemented as hardware support for the synchronization time stamp for both DV and audio/music CIP formats. The TSB12LV23A device supports modification of the synchronization time stamp field to ensure that the value inserted via software is not stale, that is, less than the current cycle timer, when the packet is transmitted. An advanced CMOS process is used to achieve low power consumption with operation at PCI clock rates up to 33 MHz. 1.2 Features The TSB12LV23A device supports the following features: * * * * * * * * 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Supports serial bus data rates of 100, 200, and 400 Mbits/s Provides bus-holding buffers on physical interface for low-cost single-capacitor isolation Supports physical write posting of up to three outstanding transactions Serial ROM interface supports 2-wire devices Supports external cycle timer control for customized synchronization Implements PCI burst transfers and deep FIFOs to tolerate large host latency Provides two general-purpose I/Os 1-1 * * * * * * Fabricated in advanced low-power CMOS process Packaged in 100-terminal PQFP (PZ) Supports PCI_CLKRUN protocol Drop-in replacement for the TSB12LV22 device Supports PCI and CardBus applications Digital video and audio performance enhancements 1.3 Related Documents * * * * * * * * 1394 Open Host Controller Interface Specification (Revision 1.0) Digital Interface for Consumer Electronic Audio/Video Equipment Draft Version 2.1 (IEC61883) P1394 Standard for a High-Performance Serial Bus (IEEE 1394-1995) IEEE Standard for a High-Performance Serial Bus--Amendment 1 (IEEE 1394a-2000) PC 99 Design Guide PCI Bus Power Management Interface Specification (Revision 1.1) PCI Local Bus Specification (Revision 2.2) Serial Bus Protocol 2 (SBP-2) 1.4 Trademarks OHCI-Lynx and TI are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. 1.5 Ordering Information ORDERING NUMBER TSB12LV23A NAME OHCI-Lynxt PCI-based IEEE 1394 host controller VOLTAGE 3.3 V, 5 V-tolerant I/Os PACKAGE 100-terminal PQFP 1-2 2 Terminal Descriptions This section provides the terminal descriptions for the TSB12LV23A device. Figure 2-1 shows the signal assigned to each terminal in the package. Table 2-1 is a listing of signal names arranged by terminal number. Table 2-2 is a listing of signal names arranged in alphanumeric order. PZ PACKAGE (TOP VIEW) GND GPIO2 GPIO3 SCL SDA VCCP PCI_CLKRUN PCI_INTA/CINT 3.3 VCC G_RST GND PCI_CLK 3.3 VCC PCI_GNT PCI_REQ VCCP PCI_PME/CSTSCHG PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27 GND PCI_AD26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND PHY_LPS PHY_LINKON PHY_LREQ 3.3 VCC PHY_SCLK GND PHY_CTL0 PHY_CTL1 3.3 VCC PHY_DATA0 PHY_DATA1 PHY_DATA2 VCCP PHY_DATA3 PHY_DATA4 PHY_DATA5 GND PHY_DATA6 PHY_DATA7 3.3 VCC ISOLATED CYCLEIN CARDBUS/CYCLEOUT PCI_RST GND PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 3.3 VCC PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_C/BE0 PCI_AD8 VCCP PCI_AD9 PCI_AD10 GND PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 3.3 VCC PCI_AD15 PCI_C/BE1 PCI_PAR PCI_SERR PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL GND PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 3.3 VCC PCI_AD19 PCI_AD18 PCI_AD17 VCCP PCI_AD16 PCI_C/BE2 GND PCI_FRAME PCI_IRDY PCI_TRDY 3.3 VCC PCI_DEVSEL PCI_STOP PCI_PERR GND Figure 2-1. Terminal Assignments 2-1 Table 2-1. Signals Sorted by Terminal Number NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TERMINAL NAME GND GPIO2 GPIO3 SCL SDA VCCP PCI_CLKRUN PCI_INTA/CINT 3.3 VCC G_RST GND PCI_CLK 3.3 VCC PCI_GNT PCI_REQ VCCP PCI_PME/CSTSCHG PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27 GND PCI_AD26 NO. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TERMINAL NAME PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL GND PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 3.3 VCC PCI_AD19 PCI_AD18 PCI_AD17 VCCP PCI_AD16 PCI_C/BE2 GND PCI_FRAME PCI_IRDY PCI_TRDY 3.3 VCC PCI_DEVSEL PCI_STOP PCI_PERR GND NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TERMINAL NAME PCI_SERR PCI_PAR PCI_C/BE1 PCI_AD15 3.3 VCC PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 GND PCI_AD10 PCI_AD9 VCCP PCI_AD8 PCI_C/BE0 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 3.3 VCC PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 GND NO. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TERMINAL NAME PCI_RST CARDBUS/CYCLEOUT CYCLEIN ISOLATED 3.3 VCC PHY_DATA7 PHY_DATA6 GND PHY_DATA5 PHY_DATA4 PHY_DATA3 VCCP PHY_DATA2 PHY_DATA1 PHY_DATA0 3.3 VCC PHY_CTL1 PHY_CTL0 GND PHY_SCLK 3.3 VCC PHY_LREQ PHY_LINKON PHY_LPS GND 2-2 Table 2-2. Signal Names Sorted Alphanumerically to Terminal Number TERMINAL NAME CARDBUS/CYCLEOUT CYCLEIN GND GND GND GND GND GND GND GND GND GND GND GPIO2 GPIO3 G_RST ISOLATED PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 NO. 77 78 1 11 24 30 42 50 60 75 83 94 100 2 3 10 79 74 73 72 71 69 68 67 66 TERMINAL NAME PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0 NO. 64 62 61 59 58 57 56 54 40 38 37 36 34 33 32 31 27 26 25 23 22 21 19 18 65 TERMINAL NAME PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_CLK PCI_CLKRUN PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_INTA/CINT PCI_IRDY PCI_PAR PCI_PERR PCI_PME/CSTSCHG PCI_REQ PCI_RST PCI_SERR PCI_STOP PCI_TRDY PHY_CTL0 PHY_CTL1 PHY_DATA0 PHY_DATA1 PHY_DATA2 PHY_DATA3 NO. 53 41 28 12 7 47 43 14 29 8 44 52 49 17 15 76 51 48 45 93 92 90 89 88 86 TERMINAL NAME PHY_DATA4 PHY_DATA5 PHY_DATA6 PHY_DATA7 PHY_LINKON PHY_LREQ PHY_LPS PHY_SCLK SCL SDA VCCP VCCP VCCP VCCP VCCP 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC NO. 85 84 82 81 98 97 99 95 4 5 6 16 39 63 87 9 13 20 35 46 55 70 80 91 96 The terminals are grouped by functionality, such as PCI system function and power supply function, in Table 2-3 through Table 2-8. The terminal numbers are also listed for convenient reference. Table 2-3. Power Supply Terminals TERMINAL NAME GND NO. 1, 11, 24, 30, 42, 50, 60, 75, 83, 94, 100 6, 16, 39, 63, 87 9, 13, 20, 35, 46, 55, 70, 80, 91, 96 I/O DESCRIPTION I Device ground terminals VCCP 3.3 VCC I PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification. I 3.3-V power supply terminals 2-3 Table 2-4. PCI System Terminals TERMINAL NAME NO. I/O DESCRIPTION Global power reset. This reset brings all of the TSB12LV23A internal registers to their default states, including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. When wake capabilities are implemented from the 1394 host controller, it is necessary to implement two resets to the TSB12LV23A device. G_RST should be a one-time power-on reset. PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCI_CLK. Interrupt signal. This output indicates interrupts from the TSB12LV23A device to the host. This terminal is implemented as open-drain. PCI reset. When this bus reset is asserted, the TSB12LV23A device places all output buffers in a high-impedance state and resets all internal registers except device power management context and vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional. This terminal should be connected to the PCI bus RST signal. G_RST 10 I PCI_CLK PCI_INTA/CINT 12 8 I O PCI_RST 76 I Table 2-5. PCI Address and Data Terminals TERMINAL NAME PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 NO. 18 19 21 22 23 25 26 27 31 32 33 34 36 37 38 40 54 56 57 58 59 61 62 64 66 67 68 69 71 72 73 74 I/O DESCRIPTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface. During the address phase of a PCI cycle, AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 contain data. 2-4 Table 2-6. PCI Interface Control Terminals TERMINAL NAME PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_CLKRUN NO. 65 53 41 28 7 I/O DESCRIPTION PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3-PCI_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. Clock run. This terminal provides clock control through the PCI_CLKRUN protocol. An internal pulldown resistor is implemented on this terminal. This terminal is implemented as open-drain. PCI device select. The TSB12LV23A device asserts this signal to claim a PCI cycle as the target device. As a PCI initiator, the TSB12LV23A device monitors this signal until a target responds. If no target responds before timeout occurs, then the TSB12LV23A device terminates the cycle with an initiator abort. PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME is de-asserted, the PCI bus transaction is in the final data phase. PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV23A device access to the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI bus request, depending upon the PCI bus parking algorithm. Initialization device select. PCI_IDSEL selects the TSB12LV23A device during configuration space accesses. PCI_IDSEL can be connected to 1 of the upper 24 PCI address lines on the PCI bus. PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. PCI parity. In all PCI bus read and write cycles, the TSB12LV23A device calculates even parity across the PCI_AD and PCI_C/BE buses. As an initiator during PCI cycles, the TSB12LV23A device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR). PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PCI_PAR when bit 6 (PERR_ENB) is set in the command register (offset 04h, see Section 3.4). Power management event or card status change. This terminal indicates wake events to the host. When in a CardBus configuration, per the CARDBUS sample, the CSTSCHG output is an active high. PCI bus request. Asserted by the TSB12LV23A device to request access to the bus as an initiator. The host arbiter asserts the PCI_GNT signal when the TSB12LV23A device has been granted access to the bus. PCI system error. When bit 8 (SERR_ENB) of the command register (offset 04h, see Section 3.4) is set, the output is pulsed, which indicates an address parity error has occurred. The TSB12LV23A device need not be the target of the PCI cycle to assert this signal. This terminal is implemented as open-drain. PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers. PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted; until which wait states are inserted. I/O I/O PCI_DEVSEL 47 I/O PCI_FRAME 43 I/O PCI_GNT 14 I PCI_IDSEL 29 I PCI_IRDY 44 I/O PCI_PAR 52 I/O PCI_PERR PCI_PME/ CSTSCHG PCI_REQ 49 17 15 I/O O O PCI_SERR 51 O PCI_STOP 48 I/O PCI_TRDY 45 I/O 2-5 Table 2-7. IEEE 1394 PHY/Link Terminals TERMINAL NAME PHY_CTL1 PHY_CTL0 PHY_DATA7 PHY_DATA6 PHY_DATA5 PHY_DATA4 PHY_DATA3 PHY_DATA2 PHY_DATA1 PHY_DATA0 PHY_LINKON NO. 92 93 81 82 84 85 86 88 89 90 98 I/O DESCRIPTION PHY-link interface control. These bidirectional signals control passage of information between the two devices. The TSB12LV23A device can only drive these terminals after the PHY device has granted permission following a link request (PHY_LREQ). I/O I/O PHY-link interface data. These bidirectional signals pass data between the TSB12LV23A and the PHY devices. These terminals are driven by the TSB12LV23A device on transmissions and are driven by the PHY device on reception. Only PHY_DATA1-PHY_DATA0 are valid for 100-Mbit speeds, PHY_DATA3-PHY_DATA0 are valid for 200-Mbit speeds, and PHY_DATA7-PHY_DATA0 are valid for 400-Mbit speeds. I/O LinkOn wake indication. The PHY_LINKON signal is pulsed by the PHY device to activate the link, and 3.3-V signaling is required. When this signal is connected to the TSB41LV0X C/LKON terminal, a 1-k series resistor is required between the link and the PHY device. Link power status. The PHY_LPS signal is asserted when the link is powered on, and 3.3-V signaling is required. Link request. This signal is driven by the TSB12LV23A device to initiate a request for the PHY device to perform some service. System clock. This input from the PHY device provides a 49.152-MHz clock signal for data synchronization. PHY_LPS PHY_LREQ PHY_SCLK 99 97 95 I/O O I Table 2-8. Miscellaneous Terminals TERMINAL NAME CARDBUS/ CYCLEOUT NO. 77 I/O DESCRIPTION This terminal is sampled when G_RST is asserted, and it selects between PCI buffers and CardBus buffers. After reset, this terminal may also function as CYCLEOUT, which provides an 8-kHz cycle timer synchronization signal. The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other system devices. If this terminal is not implemented, then it should be pulled high to the link VCC through a 4.7-k resistor. GPIO2 GPIO3 ISOLATED 2 3 79 I/O I/O I General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, then it is recommended that it be pulled low to ground with a 220- resistor. General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, then it is recommended that it be pulled low to ground with a 220- resistor. For isolated designs, the busholders are implemented by pulling this terminal low to ground with a 220- resistor. If this terminal is not implemented, it should be pulled high to the link VCC with a 4.7-k resistor. Serial clock. This terminal provides the serial clock signaling and is implemented as open-drain. For normal operation (a ROM is implemented in the design), this terminal should be pulled high to the ROM VCC with a 2.7-k resistor. Otherwise, it should be pulled low to ground with a 220- resistor. Serial data. At PCI_RST, the SDA signal is sampled to determine if a two-wire serial ROM is present. If the serial ROM is detected, then this terminal provides the serial data signaling. SDA 5 I/O This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design), this terminal should be pulled high to the ROM VCC with a 2.7-k resistor. Otherwise, it should be pulled low to ground with a 220- resistor. I/O CYCLEIN 78 I/O SCL 4 I/O 2-6 3 TSB12LV23A Controller Programming Model This section describes the PCI internal registers used to program the TSB12LV23A device. All registers are detailed in the same format: a brief description for each register, followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, field access tags which appear in the type column, and a detailed field description. Table 3-1 describes the field access tags. Table 3-1. Bit Field Access Tag Descriptions ACCESS TAG R W S C U NAME Read Write Set Clear Update MEANING Field may be read by software. Field may be written by software to any value. Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of 1. Writes of 0 have no effect. Field may be autonomously updated by the TSB12LV23A device. A simplified block diagram of the TSB12LV23A device is provided in Figure 3-1. 3-1 PCI Target SM Internal Registers Serial ROM OHCI PCI Power Mgmt and CLKRUN GPIOs Misc Interface ISO Transmit Contexts Async Transmit Contexts Transmit FIFO Physical DMA and Response Link Transmit Resp Time-out PCI Host Bus Interface Receive Acknowledge Central Arbiter and PCI Initiator SM PHY Register Access and Status Monitor Cycle Start Generator and Cycle Monitor CRC Request Filters Synthesized Bus Reset PHY/ Link Interface General Request Receive Link Receive Async Response Receive Receive FIFO ISO Receive Contexts Figure 3-1. TSB12LV23A Block Diagram 3-2 3.1 PCI/CardBus Configuration Registers The TSB12LV23A device is a single-function PCI device that can be configured as either a PCI or CardBus device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3-2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Most of the registers in this configuration have not changed from the TSB12LV22 design. Table 3-2. PCI Configuration Register Map REGISTER NAME Device ID Status Class code BIST Header type Latency timer OHCI base address TI extension base address CIS base address Reserved CardBus CIS pointer Subsystem device ID Reserved Reserved Reserved Maximum latency Minimum grant Interrupt pin Next item pointer Reserved Miscellaneous configuration Link enhancements control Subsystem device ID alias GPIO3 GPIO2 Subsystem vendor ID alias Reserved Interrupt line Capability ID OHCI control Power management capabilities PM data PMCSR_BSE Power management control and status Power management capabilities pointer Subsystem vendor ID Vendor ID Command Revision ID Cache line size OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch-24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch-ECh F0h F4h F8h FCh 3.2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 0 4 R 0 3 R 1 2 R 1 1 R 0 0 R 0 Vendor ID Register: Type: Offset: Default: Vendor ID Read-only 00h 104Ch 3-3 3.3 Device ID Register The device ID register contains a value assigned to the TSB12LV23A device by Texas Instruments. The device identification for the TSB12LV23A device is 8019h. Bit Name Type Default R 1 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 0 4 R 1 3 R 1 2 R 0 1 R 0 0 R 1 Device ID Register: Type: Offset: Default: Device ID Read-only 02h 8019h 3.4 Command Register The command register provides control over the TSB12LV23A interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the bit descriptions of Table 3-3. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R/W 0 7 R 0 6 R/W 0 5 R 0 4 R/W 0 3 R 0 2 R/W 0 1 R/W 0 0 R 0 Command Register: Type: Offset: Default: Command Read/Write, Read-only 04h 0000h Table 3-3. Command Register Description BIT 15-10 9 8 7 6 5 4 FIELD NAME RSVD FBB_ENB SERR_ENB STEP_ENB PERR_ENB VGA_ENB MWI_ENB TYPE R R R/W R R/W R R/W DESCRIPTION Reserved. Bits 15-10 return 0s when read. Fast back-to-back enable. The TSB12LV23A device does not generate fast back-to-back transactions; therefore, this bit returns 0 when read. PCI_SERR enable. When this bit is set, the TSB12LV23A PCI_SERR driver is enabled. PCI_SERR can be asserted after an address parity error on the PCI bus is detected. Address/data stepping control. The TSB12LV23A device does not support address/data stepping; therefore, this bit is hardwired to 0. Parity error enable. When this bit is set, the TSB12LV23A device is enabled to drive PCI_PERR response to parity errors through the PCI_PERR signal. VGA palette snoop enable. The TSB12LV23A device does not feature VGA palette snooping. This bit returns 0 when read. Memory write and invalidate enable. When this bit is set, the TSB12LV23A device is enabled to generate MWI PCI bus commands. If this bit is cleared, then the TSB12LV23A device generates memory write commands instead. Special cycle enable. The TSB12LV23A function does not respond to special cycle transactions. This bit returns 0 when read. Bus master enable. When this bit is set, the TSB12LV23A device is enabled to initiate cycles on the PCI bus. Memory response enable. Setting this bit enables the TSB12LV23A device to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. I/O space enable. The TSB12LV23A device does not implement any I/O mapped functionality; therefore, this bit returns 0 when read. 3 2 1 0 SPECIAL MASTER_ENB MEMORY_ENB IO_ENB R R/W R/W R 3-4 3.5 Status Register The status register provides status over the TSB12LV23A interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the bit descriptions of Table 3-4. Bit Name Type Default RCU 0 RCU 0 RCU 0 RCU 0 RCU 0 R 0 R 1 0 15 14 13 12 11 10 9 8 Status RCU R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Status Read/Clear/Update, Read-only 06h 0210h Table 3-4. Status Register Description BIT 15 14 13 12 11 10-9 8 FIELD NAME PAR_ERR SYS_ERR MABORT TABORT_REC TABORT_SIG PCI_SPEED DATAPAR TYPE RCU RCU RCU RCU RCU R RCU DESCRIPTION Detected parity error. This bit is set when either an address parity or data parity error is detected. Signaled system error. This bit is set when PCI_SERR is enabled and the TSB12LV23A device has signaled a system error to the host. Received master abort. This bit is set when a cycle initiated by the TSB12LV23A device on the PCI bus has been terminated by a master abort. Received target abort. This bit is set when a cycle initiated by the TSB12LV23A device on the PCI bus was terminated by a target abort. Signaled target abort. This bit is set by the TSB12LV23A device when it terminates a transaction on the PCI bus with a target abort. DEVSEL timing. Bits 10-9 encode the timing of PCI_DEVSEL and are hardwired to 01b indicating that the TSB12LV23A device asserts this signal at a medium speed on nonconfiguration cycle accesses. Data parity error detected. This bit is set when the following conditions have been met: a. PCI_PERR was asserted by any PCI device including the TSB12LV23A device. b. The TSB12LV23A device was the bus master during the data parity error. c. Bit 6 (PERR_EN) is set in the command register (offset 04h, see Section 3.4). Fast back-to-back capable. The TSB12LV23A device cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0. User-definable features (UDF) supported. The TSB12LV23A device does not support the UDF; therefore, this bit is hardwired to 0. 66-MHz capable. The TSB12LV23A device operates at a maximum PCI_CLK frequency of 33 MHz; therefore, this bit is hardwired to 0. Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power management capabilities is implemented in this function. Reserved. Bits 3-0 return 0s when read. 7 6 5 4 3-0 FBB_CAP UDF 66MHZ CAPLIST RSVD R R R R R 3-5 3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12LV23A device as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3-5 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 1 11 R 1 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Class code and revision ID Class code and revision ID Register: Type: Offset: Default: BIT 31-24 23-16 15-8 7-0 FIELD NAME BASECLASS SUBCLASS PGMIF CHIPREV Class code and revision ID Read-only 08h 0C00 1000h Table 3-5. Class Code and Revision ID Register Description TYPE R R R R DESCRIPTION Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus controller. Subclass. This field returns 00h when read, which specifically classifies the function as controlling an IEEE 1394 serial bus. Programming interface. This field returns 10h when read, indicating that the programming model is compliant with the 1394 Open Host Controller Interface Specification. Silicon revision. This field returns 00h when read, indicating the silicon revision of the TSB12LV23A device. 3.7 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the TSB12LV23A device. See Table 3-6 for a complete description of the register contents. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 R/W 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Latency timer and class cache line size Register: Type: Offset: Default: BIT 15-8 FIELD NAME Latency timer and class cache line size Read/Write 0Ch 0000h TYPE R/W DESCRIPTION PCI latency timer. The value in this register specifies the latency timer for the TSB12LV23A device, in units of PCI clock cycles. When the TSB12LV23A device is a PCI bus initiator and asserts PCI_FRAME, the latency timer begins counting from zero. If the latency timer expires before the TSB12LV23A transaction has terminated, then the TSB12LV23A device terminates the transaction when its PCI_GNT is deasserted. Cache line size. This value is used by the TSB12LV23A device during memory write and invalidate, memory read line, and memory read multiple transactions. Table 3-6. Latency Timer and Class Cache Line Size Register Description LATENCY_TIMER 7-0 CACHELINE_SZ R/W 3-6 3.8 Header Type and BIST Register The header type and BIST register indicates the TSB12LV23A PCI header type, and indicates no built-in self-test. See Table 3-7 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Header type and BIST Register: Type: Offset: Default: Header type and BIST Read-only 0Eh 0000h Table 3-7. Header Type and BIST Register Description BIT 15-8 7-0 FIELD NAME BIST HEADER_TYPE TYPE R R DESCRIPTION Built-in self-test. The TSB12LV23A device does not include a built-in self-test; thus, this field returns 00h when read. PCI header type. The TSB12LV23A device includes the standard PCI header, and this is communicated by returning 00h when this field is read. 3.9 OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 3-8 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 31 30 29 28 27 26 25 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 OHCI base address OHCI address Register: Type: Offset: Default: OHCI base address Read/Write, Read-only 10h 0000 0000h Table 3-8. OHCI Base Address Register Description BIT 31-11 10-4 3 2-1 0 FIELD NAME OHCIREG_PTR OHCI_SZ OHCI_PF OHCI_MEMTYPE OHCI_MEM TYPE R/W R R R R DESCRIPTION OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register. OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a 2-Kbyte region of memory. OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are nonprefetchable. OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. OHCI memory indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped into system memory space. 3-7 3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See the OHCI Base Address Register, Section 3.9, for bit field details. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 TI extension base address TI extension base address Register: Type: Offset: Default: TI extension base address Read/Write, Read-only 14h 0000 0000h 3.11 CIS Base Address Register If CARDBUS is sampled high on a G_RST, then this 32-bit register returns 0s when read. If CARDBUS is sampled low, then this register is to be programmed with a base address referencing the memory-mapped CIS. This register must be programmed with a nonzero value before the CIS may be accessed. See Table 3-9 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 31 30 29 28 27 26 25 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 CIS base address CIS base address Register: Type: Offset: Default: CIS base address Read/Write, Read-only 18h 0000 0000h Table 3-9. CIS Base Address Register Description BIT 31-11 10-4 3 FIELD NAME CIS_BASE CIS_SZ CIS_PF TYPE R/W R R DESCRIPTION CIS base address. Specifies the upper 21 bits of the 32-bit CIS base address. If the CARDBUS input is sampled high on a G_RST, then this field is read-only, returning 0s when read. CIS address space size. This field returns 0s when read, indicating that the CIS space requires a 2-Kbyte region of memory. CIS prefetch. This bit returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the CIS is a byte-accessible address space, and doubleword or 16-bit word access yields indeterminate results. CIS memory type. This field returns 0s when read, indicating that the CIS base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. CIS memory indicator. This bit returns 0 when read, indicating that the CIS is mapped into system memory space. 2-1 0 CIS_MEMTYPE CIS_MEM R R 3-8 3.12 CardBus CIS Pointer Register The CARDBUS input to the TSB12LV23A device is sampled at G_RST to determine the TSB12LV23A application. If CARDBUS is sampled high, then this register is read-only returning 0s when read. If CARDBUS is sampled low, then this register is the CardBus card information structure pointer. See Table 3-10 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R X 17 R 0 1 R X 16 R 0 0 R X CardBus CIS pointer CardBus CIS pointer Register: Type: Offset: Default: CardBus CIS pointer Read-only 28h 0000 000Xh Table 3-10. CardBus CIS Pointer Register Description BIT 31-28 27-3 FIELD NAME ROM_IMAGE CIS_OFFSET TYPE R R DESCRIPTION Since the CIS is not implemented as a ROM image, this field returns 0s when read. This field indicates the offset into the CIS address space where the CIS begins, and bits 7-3 are loaded from the serial ROM field CIS_Offset (7-3). This implementation allows the TSB12LV23A device to produce serial ROM addresses equal to the lower PCI address byte to acquire data from the serial ROM. This field indicates the address space where the CIS resides and returns 011b if CARDBUS is sampled low during a G_RST reset. If CARDBUS is sampled high during a G_RST, then this field returns 000b when read. 2-0 CIS_INDICATOR R 3-9 3.13 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial ROM or programmed via the subsystem ID and subsystem vendor ID alias registers (offset F8h, see Section 3.24). See Table 3-11 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RU 0 RU 0 RU 0 RU 0 RU 0 RU 0 RU 0 15 RU 0 14 RU 0 13 RU 0 12 RU 0 11 RU 0 10 31 30 29 28 27 26 25 RU 0 9 RU 0 24 RU 0 8 RU 0 23 RU 0 7 RU 0 22 RU 0 6 RU 0 21 RU 0 5 RU 0 20 RU 0 4 RU 0 19 RU 0 3 RU 0 18 RU 0 2 RU 0 17 RU 0 1 RU 0 16 RU 0 0 RU 0 Subsystem identification Subsystem identification Register: Type: Offset: Default: Subsystem identification Read/Update 2Ch 0000 0000h Table 3-11. Subsystem Identification Register Description BIT 31-16 15-0 FIELD NAME OHCI_SSID OHCI_SSVID TYPE RU RU DESCRIPTION Subsystem device ID. This field indicates the subsystem device ID. Subsystem vendor ID. This field indicates the subsystem vendor ID. 3.14 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. The TSB12LV23A configuration header doublewords at offsets 44h and 48h provide the power management registers. This register is read-only and returns 44h when read. Bit Name Type Default R 0 R 1 R 0 7 6 5 4 R 0 3 R 0 2 R 1 1 R 0 0 R 0 Power management capabilities pointer Register: Type: Offset: Default: Power management capabilities pointer Read-only 34h 44h 3-10 3.15 Interrupt Line and Pin Register The interrupt line and pin register is used to communicate interrupt line routing information. See Table 3-12 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 1 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Interrupt line and pin Register: Type: Offset: Default: Interrupt line and pin Read/Write, Read-only 3Ch 0100h Table 3-12. Interrupt Line and Pin Register Description BIT 15-8 7-0 FIELD NAME INTR_PIN INTR_LINE TYPE R R/W DESCRIPTION Interrupt pin. Returns 01h when read, indicating that the TSB12LV23A PCI function signals interrupts on the PCI_INTA terminal. Interrupt line. This field is programmed by the system and indicates to software which interrupt line the TSB12LV23A PCI_INTA is connected to. 3.16 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of bits 15-8 of the latency timer and class cache line size register (offset 0Ch, see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI_RST. If no serial ROM is detected, then this register returns a default value that corresponds to MAX_LAT = 4, MIN_GNT = 2. See Table 3-13 for a complete description of the register contents. Bit Name Type Default RU 0 RU 0 RU 0 RU 0 RU 0 RU 1 15 14 13 12 11 10 9 RU 0 8 RU 0 7 RU 0 6 RU 0 5 RU 0 4 RU 0 3 RU 0 2 RU 0 1 RU 1 0 RU 0 MIN_GNT and MAX_LAT Register: Type: Offset: Default: MIN_GNT and MAX_LAT Read/Update 3Eh 0402h Table 3-13. MIN_GNT and MAX_LAT Register Description BIT 15-8 FIELD NAME MAX_LAT TYPE RU DESCRIPTION Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration priority-level to the TSB12LV23A device. The default for this register indicates that the TSB12LV23A device may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial ROM. Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer and class cache line size register (offset 0Ch, see Section 3.7) value to the TSB12LV23A device. The default for this register indicates that the TSB12LV23A device may need to sustain burst transfers for nearly 64 s; thus, requesting a large value be programmed in bits 15-8 of the TSB12LV23A latency timer and class cache line size register. 7-0 MIN_GNT RU 3-11 3.17 OHCI Control Register The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3-14 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R/W 0 OHCI control OHCI control Register: Type: Offset: Default: OHCI control Read/Write, Read-only 40h 0000 0000h Table 3-14. OHCI Control Register Description BIT 31-1 0 FIELD NAME RSVD GLOBAL_SWAP TYPE R R/W Reserved. Bits 31-1 return 0s when read. DESCRIPTION When this bit is set, all quadlets read from and written to the PCI interface are byte swapped (big endian). This bit is loaded from ROM and should be cleared for normal operation. 3.18 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item. See Table 3-15 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 1 Capability ID and next item pointer Register: Type: Offset: Default: Capability ID and next item pointer Read-only 44h 0001h Table 3-15. Capability ID and Next Item Pointer Register Description BIT 15-8 FIELD NAME NEXT_ITEM TYPE R DESCRIPTION Next item pointer. The TSB12LV23A device supports only one additional capability that is communicated to the system through the extended capabilities list; thus, this field returns 00h when read. Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power management capability. 7-0 CAPABILITY_ID R 3-12 3.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB12LV23A device related to PCI power management. See Table 3-16 for a complete description of the register contents. Bit Name Type Default RU 0 RU 1 RU 1 RU 0 RU 0 RU 1 15 14 13 12 11 10 9 R 0 8 R X 7 R X 6 R X 5 R 0 4 R 0 3 R 0 2 R 0 1 R 1 0 R 0 Power management capabilities Register: Type: Offset: Default: Power management capabilities Read/Update, Read-only 46h 6XX2h Table 3-16. Power Management Capabilities Register Description BIT 15 FIELD NAME PME_D3COLD TYPE RU DESCRIPTION PCI_PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in the miscellaneous configuration register (offset F0h, see Section 3.22). The miscellaneous configuration register is loaded from ROM. When this bit is set to 1, it indicates that the TSB12LV23A device is capable of generating a PCI_PME wake event from D3cold. This bit state is dependent upon the TSB12LV23A VAUX implementation and may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see Section 3.22). PCI_PME support. This 4-bit field indicates the power states from which the TSB12LV23A device may assert PCI_PME. This field returns a value of 1100b by default, indicating that PCI_PME may be asserted from the D3hot and D2 power states. Bit 13 may be modified by host software using bit 13 (PME_SUPPORT_D2) in the miscellaneous configuration register (offset F0h, see Section 3.22). D2 support. This bit can be set or cleared via bit 10 (D2_SUPPORT) in the miscellaneous configuration register (offset F0h, see Section 3.20). The miscellaneous configuration register is loaded from ROM. When this bit is set, it indicates that D2 support is present. When this bit is cleared, it indicates that D2 support is not present for backward compatibility with the TSB12LV22. For normal operation, this bit is set to 1. D1 support. This bit returns a 0 when read, indicating that the TSB12LV23A device does not support the D1 power state. Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is set to 1, this field returns 001b; otherwise, it returns 000b. 000b = Self-powered 001b = 55 mA (3.3 VAUX maximum current required) Device specific initialization. This bit returns 0 when read, indicating that the TSB12LV23A device does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. Reserved. This bit returns 0 when read. PCI_PME clock. This bit returns 0 when read, indicating that no host bus clock is required for the TSB12LV23A device to generate PCI_PME. Power management version. This field returns 010b when read, indicating that the TSB12LV23A device is compatible with the registers described in the PCI Bus Power Management Interface Specification (Revision 1.1). 14-11 PME_SUPPORT RU 10 D2_SUPPORT RU 9 8-6 D1_SUPPORT AUX_CURRENT R R 5 DSI R 4 3 2-0 RSVD PME_CLK PM_VERSION R R R 3-13 3.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3-17 for a complete description of the register contents. Bit Name Type Default RC 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R/W 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R/W 0 0 R/W 0 Power management control and status Register: Type: Offset: Default: BIT 15 FIELD NAME PME_STS Power management control and status Read/Clear, Read/Write, Read-only 48h 0000h TYPE RC DESCRIPTION This bit is set when the TSB12LV23A device would normally be asserting the PCI_PME signal, independent of the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, and this also clears the PCI_PME signal driven by the TSB12LV23A device. Writing a 0 to this bit has no effect. This field returns 0s because the data register is not implemented. This field returns 0s because the data register is not implemented. When bit 8 = 1, PME assertion is enabled. When bit 8 = 0, PME assertion is disabled. This bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Functions that do not support PME generation from any D-state (that is, bits 15-11 in the power management capabilities register (offset 46h, see Section 3.19) equal 00000b), may hardwire this bit to be read-only always returning a 0 when read by system software. Reserved. Bits 7-2 return 0s when read. Power state. This 2-bit field is used to set the TSB12LV23A device power state and is encoded as follows: 00 = Current power state is D0 01 = Current power state is D1 10 = Current power state is D2 11 = Current power state is D3 Table 3-17. Power Management Control and Status Register Description 14-13 12-9 8 DATA_SCALE DATA_SELECT PME_ENB R R R/W 7-2 1-0 RSVD PWR_STATE R R/W 3.21 Power Management Extension Register The power management extension register provides extended power management features not applicable to the TSB12LV23A device, thus it is read-only and returns 0s when read. See Table 3-18 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Power management extension Register: Type: Offset: Default: BIT 15-0 FIELD NAME RSVD Power management extension Read-only 4Ah 0000h Table 3-18. Power Management Extension Register Description TYPE R Reserved. Bits 15-0 return 0s when read. DESCRIPTION 3-14 3.22 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3-19 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R 0 R/W 1 R 0 R 0 R/W 1 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Miscellaneous configuration Miscellaneous configuration Register: Type: Offset: Default: Miscellaneous configuration Read/Write, Read-only F0h 0000 2400h Table 3-19. Miscellaneous Configuration Register Description BIT 31-16 15 14 13 FIELD NAME RSVD PME_D3COLD RSVD PME_SUPPORT_D2 TYPE R R/W R R/W DESCRIPTION Reserved. Bits 31-16 return 0s when read. PCI_PME support from D3cold. This bit is used to program bit 15 (PME_D3COLD) in the power management capabilities register (offset 46h, see Section 3.19). Reserved. Bit 14 returns 0 when read. PCI_PME support. This bit is used to program bit 13 (PME_SUPPORT_D2) in the power management capabilities register (offset 46h, see Section 3.19). If wake from the D2 power state implemented in the TSB12LV23A device is not desired, then this bit may be cleared to indicate to power management software that wake-up from D2 is not supported. Reserved. Bits 12-11 return 0s when read. D2 support. This bit is used to program bit 10 (D2_SUPPORT) in the power management capabilities register (offset 46h, see Section 3.19). If the D2 power state in the TSB12LV23A device is not desired, then this bit may be cleared to indicate to power management software that D2 is not supported. Reserved. Bits 9-5 return 0s when read. This bit defaults to 0, which provides OHCI-Lynxt compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in which the TSB12LV23A device returns indeterminate data instead of signaling target abort. The link is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, a target abort is issued by the link. On some systems this can cause a problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types of requests by returning FFh. It is recommended that this bit be set to 1. When this bit is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA, respectively. The GPIO3 and GPIO2 terminals are also placed in a high impedance state. When this bit is set to 1, the internal SCLK runs identically with the chip input. This bit is a test feature only and should be cleared to 0 (all applications). When this bit is set, the internal PCI clock runs identically with the chip input. This bit is a test feature only and should be cleared to 0 (all applications). When this bit is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol. When this bit is cleared, the PCI clock may be stopped using PCI_CLKRUN. 12-11 10 RSVD D2_SUPPORT R R/W 9-5 4 RSVD DIS_TGT_ABT R R/W 3 2 1 0 GP2IIC DISABLE_SCLKGATE DISABLE_PCIGATE KEEP_PCLK R/W R/W R/W R/W 3-15 3.23 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial ROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. See Table 3-20 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R/W 0 R/W 1 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R/W 0 24 R 0 8 R/W 0 23 R 0 7 R/W 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R 0 Link enhancement control Link enhancement control Register: Type: Offset: Default: Link enhancement control Read/Write, Read-only F4h 0000 1000h Table 3-20. Link Enhancement Control Register Description BIT 31-14 13-12 FIELD NAME RSVD atx_thresh TYPE R R/W DESCRIPTION Reserved. Bits 31-14 return 0s when read. This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the TSB12LV23A device retries the packet, it uses a 2-Kbyte threshold resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.7K bytes (default) 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7-K threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency. Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds, or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition will occur, resulting in a packet error at the receiving node. As a result, the link will then commence store-and-forward operation, that is, wait until it has the complete packet in the FIFO before retransmitting it on the second attempt, to ensure delivery. An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. Note that this device will always use store-and-forward when the asynchronous transmit retries register (OHCI offset 08h, see Section 4.3) is cleared. 11-10 9 8 7 6 RSVD enab_audio_ts enab_dv_ts enab_unfair RSVD R R/W R/W R/W R Reserved. Bits 11-10 return 0s when read. Enable audio/music CIP time stamp enhancement. When this bit is set, the enhancement is enabled for audio/music CIP transmit streams (FMT = 10h). Enable DV CIP time stamp enhancement. When this bit is set, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). Enable asynchronous priority requests. OHCI-Lynxt compatible. Setting this bit to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1. This bit is not assigned in the TSB12LV23A follow-on products since this bit location loaded by the serial ROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register (OHCI offset 50h/54h, see Section 4.16). 3-16 Table 3-20. Link Enhancement Control Register Description (Continued) BIT 5-3 2 FIELD NAME RSVD enab_insert_idle TYPE R R/W Reserved. Bits 5-3 return 0s when read. Enable insert idle. OHCI-Lynxt compatible. When the PHY device has control of the PHY_CTL0-PHY_CTL1 control lines and PHY_DATA0-PHY_DATA7 data lines and the link requests control, the PHY device drives 11b on the PHY_CTL0-PHY_CTL1 lines. The link can then start driving these lines immediately. Setting this bit to 1 inserts an idle state, so the link waits one clock cycle before it starts driving the lines (turnaround time). It is recommended that this bit be set to 1. Enable acceleration enhancements. OHCI-Lynxt compatible. When set to 1, this bit notifies the PHY device that the link supports the IEEE 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. Reserved. Bit 0 returns 0 when read. DESCRIPTION 1 enab_accel R/W 0 RSVD R 3.24 Subsystem Access Register Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynxt. The system ID value written to this register may also be read back from this register. See Table 3-21 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 31 30 29 28 27 26 25 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Subsystem access Subsystem access Register: Type: Offset: Default: Subsystem access Read/Write F8h 0000 0000h Table 3-21. Subsystem Access Register Description BIT 31-16 15-0 FIELD NAME SUBDEV_ID SUBVEN_ID TYPE R/W R/W DESCRIPTION Subsystem device ID alias. This field indicates the subsystem device ID. Subsystem vendor ID alias. This field indicates the subsystem vendor ID. 3-17 3.25 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3-22 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 15 R 0 14 R/W 0 13 R/W 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 RWU 0 8 R 0 23 R/W 0 7 R 0 22 R 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 RWU 0 0 R 0 GPIO control GPIO control Register: Type: Offset: Default: GPIO control Read/Write/Update, Read/Write, Read-only FCh 0000 0000h Table 3-22. GPIO Control Register Description BIT 31 FIELD NAME INT_3EN TYPE R/W DESCRIPTION When this bit is set, a TSB12LV23A general-purpose interrupt event occurs on a level change of the GPIO3 input. This event may generate an interrupt, with mask and event status reported through the OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset 80h/84h, see Section 4.21) registers. Reserved. Bit 30 returns 0 when read. GPIO3 polarity invert. When this bit is set, the polarity of GPIO3 is inverted. GPIO3 enable control. When this bit is set, the output is enabled. Otherwise, the output is high impedance. Reserved. Bits 27-25 return 0s when read. GPIO3 data. Reads from this bit return the logical value of the input to GPIO3. Writes to this bit update the value to drive to GPIO3 when output is enabled. When this bit is set, a TSB12LV23A general-purpose interrupt event occurs on a level change of the GPIO3 input. This event may generate an interrupt, with mask and event status reported through the OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset 80h/84h, see Section 4.21) registers. Reserved. Bit 22 returns 0 when read. GPIO2 polarity invert. When this bit is set, the polarity of GPIO2 is inverted. GPIO2 enable control. When this bit is set, the output is enabled. Otherwise, the output is high impedance. Reserved. Bits 19-17 return 0s when read. GPIO2 data. Reads from this bit return the logical value of the input to GPIO2. Writes to this bit update the value to drive to GPIO2 when the output is enabled. Reserved. Bits 15-0 return 0s when read. 30 29 28 27-25 24 23 RSVD GPIO_INV3 GPIO_ENB3 RSVD GPIO_DATA3 INT_2EN R R/W R/W R RWU R/W 22 21 20 19-17 16 15-0 RSVD GPIO_INV2 GPIO_ENB2 RSVD GPIO_DATA2 RSVD R R/W R/W R RWU R 3-18 4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9). These registers are the primary interface for controlling the TSB12LV23A IEEE 1394 link function. This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 4-1 for an illustration. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected. Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior. Table 4-1. OHCI Register Map DMA CONTEXT -- REGISTER NAME OHCI version GUID ROM Asynchronous transmit retries CSR data CSR compare CSR control Configuration ROM header Bus identification Bus options GUID high GUID low Reserved Configuration ROM mapping Posted write address low Posted write address high Vendor ID Reserved Host controller control Reserved ABBREVIATION Version GUID_ROM ATRetries CSRData CSRCompareData CSRControl ConfigROMhdr BusID BusOptions GUIDHi GUIDLo -- ConfigROMmap PostedWriteAddressLo PostedWriteAddressHi VendorID -- HCControlSet HCControlClr -- OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch-30h 34h 38h 3Ch 40h 44h-4Ch 50h 54h 58h-5Ch 4-1 Table 4-1. OHCI Register Map (Continued) DMA CONTEXT Self-ID Reserved Self-ID buffer Self-ID count Reserved -- Isochronous receive channel mask high Isochronous receive channel mask low Interrupt event Interrupt mask Isochronous transmit interrupt event Isochronous transmit interrupt mask -- Isochronous receive interrupt event Isochronous receive interrupt mask Reserved Fairness control Link control Node identification PHY layer control Isochronous cycle timer Reserved AsyncRequestFilterHiSet Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low Physical upper bound Reserved AsyncRequestFilterHiClear AsyncRequestFilterLoSet AsyncRequestFilterLoClear PhysicalRequestFilterHiSet PhysicalRequestFilterHiClear PhysicalRequestFilterLoSet PhysicalRequestFilterLoClear PhysicalUpperBound -- FairnessControl LinkControlSet LinkControlClear NodeID PhyControl Isocyctimer REGISTER NAME -- SelfIDBuffer SelfIDCount -- IRChannelMaskHiSet IRChannelMaskHiClear IRChannelMaskLoSet IRChannelMaskLoClear IntEventSet IntEventClear IntMaskSet IntMaskClear IsoXmitIntEventSet IsoXmitIntEventClear IsoXmitIntMaskSet IsoXmitIntMaskClear IsoRecvIntEventSet IsoRecvIntEventClear IsoRecvIntMaskSet IsoRecvIntMaskClear ABBREVIATION OFFSET 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0-D8h DCh E0h E4h E8h ECh F0h F4h-FCh 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h-17Ch 4-2 Table 4-1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME Asynchronous context control Asynchronous Request Transmit [ ATRQ ] Reserved Asynchronous context command pointer Reserved Asynchronous context control Asynchronous Res onse Response Transmit [ ATRS ] Reserved Asynchronous context command pointer Reserved Asynchronous context control Asynchronous Request Receive [ ARRQ ] Reserved Command pointer Reserved Asynchronous context control Asynchronous Res onse Response Receive [ ARRS ] Reserved Command pointer Reserved Isochronous transmit context control Isochronous Transmit Context n n = 0, 1, 2, 3, ..., 7 Reserved Isochronous transmit context command pointer Reserved Isochronous receive context control Isochronous Receive Context n n = 0, 1, 2, 3 Reserved Isochronous receiver context command pointer Context match Isochronous Receive Digital Video Enhancement ABBREVIATION ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr ContextMatch Context control set Context control Context control clear A8Ch OFFSET 180h 184h 188h 18Ch 190h-19Ch 1A0h 1A4h 1A8h 1ACh 1B0h-1BCh 1C0h 1C4h 1C8h 1CCh 1D0h-1DCh 1E0h 1E4h 1E8h 1ECh 1F0h-1FCh 200h + 16*n 204h + 16*n 208h + 16*n 20Ch + 16*n 280h - 3FCh 400h + 32*n 404h + 32*n 408h + 32*n 40Ch + 32*n 410h + 32*n A88h 4-3 4.1 OHCI Version Register This register indicates the OHCI version support, and whether or not a serial ROM is present. See Table 4-2 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R X 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 1 0 R 0 OHCI version OHCI version Register: Type: Offset: Default: OHCI version Read-only 00h 0X01 0000h Table 4-2. OHCI Version Register Description BIT 31-25 24 23-16 15-8 7-0 FIELD NAME RSVD GUID_ROM version RSVD revision TYPE R R R R R DESCRIPTION Reserved. Bits 31-25 return 0s when read. The TSB12LV23A device sets this bit if the serial ROM is detected. If the serial ROM is present, then the Bus_Info_Block is automatically loaded on hardware reset. Major version of the OHCI. The TSB12LV23A device is compliant with the 1394 Open Host Controller Interface Specification; thus, this field reads 01h. Reserved. Bits 15-8 return 0s when read. Minor version of the OHCI. The TSB12LV23A device is compliant with the 1394 Open Host Controller Interface Specification; thus, this field reads 00h. 4-4 4.2 GUID ROM Register The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register (OHCI offset 00h, see Section 4.1) is set. See Table 4-3 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 RSU 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 RSU 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 RU X 7 R 0 22 RU X 6 R 0 21 RU X 5 R 0 20 RU X 4 R 0 19 RU X 3 R 0 18 RU X 2 R 0 17 RU X 1 R 0 16 RU X 0 R 0 GUID ROM GUID ROM Register: Type: Offset: Default: GUID ROM Read/Set/Update, Read/Update, Read-only 04h 00XX 0000h Table 4-3. GUID ROM Register Description BIT 31 FIELD NAME addrReset TYPE RSU DESCRIPTION Software sets this bit to reset the GUID ROM address to 0. When the TSB12LV23A device completes the reset, it clears this bit. The TSB12LV23A device does not automatically fill bits 23-16 (rdData field) with the 0th byte. Reserved. Bits 30-26 return 0s when read. A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared when the TSB12LV23A device completes the read of the currently addressed GUID ROM byte. Reserved. Bit 24 returns 0 when read. This field represents the data read from the GUID ROM. Reserved. Bits 15-0 return 0s when read. 30-26 25 24 23-16 15-0 RSVD rdStart RSVD rdData RSVD R RSU R RU R 4-5 4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12LV23A device attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4-4 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R/W 0 24 R 0 8 R/W 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Asynchronous transmit retries Asynchronous transmit retries Register: Type: Offset: Default: Asynchronous transmit retries Read/Write, Read-only 08h 0000 0000h Table 4-4. Asynchronous Transmit Retries Register Description BIT 31-29 28-16 15-12 11-8 FIELD NAME secondLimit cycleLimit RSVD maxPhysRespRetries TYPE R R R R/W DESCRIPTION The second limit field returns 0s when read because outbound dual-phase retry is not implemented. The cycle limit field returns 0s when read because outbound dual-phase retry is not implemented. Reserved. Bits 15-12 return 0s when read. This field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. This field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 7-4 maxATRespRetries R/W 3-0 maxATReqRetries R/W 4.4 CSR Data Register The CSR data register is used to access the bus management CSR registers from the host through compare-swap operations. This register contains the data to be stored in a CSR if the compare is successful. Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 R X 10 R X 9 31 30 29 28 27 26 25 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X CSR data CSR data Register: Type: Offset: Default: CSR data Read-only 0Ch XXXX XXXXh 4-6 4.5 CSR Compare Register The CSR compare register is used to access the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 R X 10 R X 9 31 30 29 28 27 26 25 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X CSR compare CSR compare Register: Type: Offset: Default: CSR compare Read-only 10h XXXX XXXXh 4.6 CSR Control Register The CSR control register is used to access the bus management CSR registers from the host through compare-swap operations. This register is used to control the compare-swap operation and to select the CSR resource. See Table 4-5 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 RU 1 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R/W X 16 R 0 0 R/W X CSR control CSR control Register: Type: Offset: Default: CSR control Read/Update, Read/Write, Read-only 14h 8000 000Xh Table 4-5. CSR Control Register Description BIT 31 30-2 1-0 FIELD NAME csrDone RSVD csrSel TYPE RU R R/W DESCRIPTION This bit is set by the TSB12LV23A device when a compare-swap operation is complete. It is cleared whenever this register is written. Reserved. Bits 30-2 return 0s when read. This field selects the CSR resource as follows: 00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO 4-7 4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 4-6 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W X R/W X R/W X R/W X R/W X R/W X R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R/W X 24 R/W 0 8 R/W X 23 R/W 0 7 R/W X 22 R/W 0 6 R/W X 21 R/W 0 5 R/W X 20 R/W 0 4 R/W X 19 R/W 0 3 R/W X 18 R/W 0 2 R/W X 17 R/W 0 1 R/W X 16 R/W 0 0 R/W X Configuration ROM header Configuration ROM header Register: Type: Offset: Default: Configuration ROM header Read/Write 18h 0000 XXXXh Table 4-6. Configuration ROM Header Register Description BIT 31-24 23-16 15-0 FIELD NAME info_length crc_length rom_crc_value TYPE R/W R/W R/W DESCRIPTION IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. IEEE 1394 bus management field. Must be valid at any time bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. The reset value is undefined if no serial ROM is present. If a serial ROM is present, then this field is loaded from the serial ROM. 4.8 Bus Identification Register The bus identification register externally maps to the first quadlet in the Bus_Info_Block, and contains the constant 3133 3934h, which is the ASCII value of 1394. Bit Name Type Default Bit Name Type Default R 0 R 0 R 1 R 1 R 1 R 0 R 0 R 0 15 R 0 14 R 1 13 R 1 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 1 8 R 1 23 R 0 7 R 0 22 R 0 6 R 0 21 R 1 5 R 1 20 R 1 4 R 1 19 R 0 3 R 0 18 R 0 2 R 1 17 R 1 1 R 0 16 R 1 0 R 0 Bus identification Bus identification Register: Type: Offset: Default: Bus identification Read-only 1Ch 3133 3934h 4-8 4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4-7 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 1 R/W 0 R/W 1 R/W 0 R 0 R 0 R 0 R/W X 15 R/W X 14 R/W X 13 R/W X 12 R/W 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R/W X 7 R/W X 22 R/W X 6 R/W X 21 R/W X 5 R 0 20 R/W X 4 R 0 19 R/W X 3 R 0 18 R/W X 2 R 0 17 R/W X 1 R 1 16 R/W X 0 R 0 Bus options Bus options Register: Type: Offset: Default: Bus options Read/Write, Read-only 20h X0XX A0X2h Table 4-7. Bus Options Register Description BIT 31 30 29 28 27 FIELD NAME irmc cmc isc bmc pmc TYPE R/W R/W R/W R/W R/W DESCRIPTION Isochronous resource manager capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. Cycle master capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. Isochronous support capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. Bus manager capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. Power management capable. When set, this indicates that the node is power management capable. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. Reserved. Bits 26-24 return 0s when read. Cycle master clock accuracy, in parts per million. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. Maximum request. IEEE 1394 bus management field. Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes, must be 512 or greater and is calculated by 2^(max_rec + 1). Software may change this field; however, this field must be valid at any time bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a soft reset, and defaults to a value indicating 2048 bytes on a hard reset. Reserved. Bits 11-8 return 0s when read. Generation counter. This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset. Reserved. Bits 5-3 return 0s when read. Link speed. This field returns 010, indicating that the link speeds of 100, 200, and 400 Mbits/s are supported. 26-24 23-16 RSVD cyc_clk_acc R R/W 15-12 max_rec R/W 11-8 7-6 5-3 2-0 RSVD g RSVD Lnk_spd R R/W R R 4-9 4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI_RST. At that point, the contents of this register cannot be changed. If no serial ROM is detected, then the contents of this register are loaded by the BIOS after a PCI_RST. At that point, the contents of this register cannot be changed. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 GUID high GUID high Register: Type: Offset: Default: GUID high Read-only 24h 0000 0000h 4.11 GUID Low Register The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a hardware reset and behaves identically to the GUID high register (OHCI offset 24h, see Section 4.10). Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 GUID low GUID low Register: Type: Offset: Default: GUID low Read-only 28h 0000 0000h 4-10 4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4-8 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 Configuration ROM mapping Configuration ROM mapping Register: Type: Offset: Default: Configuration ROM mapping Read/Write, Read-only 34h 0000 0000h Table 4-8. Configuration ROM Mapping Register Description BIT 31-10 FIELD NAME configROMaddr TYPE R/W DESCRIPTION If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is received, then the low order 10 bits of the offset are added to this register to determine the host memory address of the read request. Reserved. Bits 9-0 return 0s when read. 9-0 RSVD R 4.13 Posted Write Address Low Register The posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. This register contains the lower 32 bits of the 1394 destination offset of the write request that failed. Bit Name Type Default Bit Name Type Default RU X RU X RU X RU X RU X RU X RU X 15 RU X 14 RU X 13 RU X 12 RU X 11 RU X 10 31 30 29 28 27 26 25 RU X 9 RU X 24 RU X 8 RU X 23 RU X 7 RU X 22 RU X 6 RU X 21 RU X 5 RU X 20 RU X 4 RU X 19 RU X 3 RU X 18 RU X 2 RU X 17 RU X 1 RU X 16 RU X 0 RU X Posted write address low Posted write address low Register: Type: Offset: Default: Posted write address low Read/Update 38h XXXX XXXXh 4-11 4.14 Posted Write Address High Register The posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4-9 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RU X RU X RU X RU X RU X RU X RU X 15 RU X 14 RU X 13 RU X 12 RU X 11 RU X 10 31 30 29 28 27 26 25 RU X 9 RU X 24 RU X 8 RU X 23 RU X 7 RU X 22 RU X 6 RU X 21 RU X 5 RU X 20 RU X 4 RU X 19 RU X 3 RU X 18 RU X 2 RU X 17 RU X 1 RU X 16 RU X 0 RU X Posted write address high Posted write address high Register: Type: Offset: Default: Posted write address high Read/Update 3Ch XXXX XXXXh Table 4-9. Posted Write Address High Register Description BIT 31-16 15-0 FIELD NAME sourceID offsetHi TYPE RU RU DESCRIPTION This field is the 10-bit bus number (bits 31-22) and 6-bit node number (bits 21-16) of the node that issued the write request that failed. The upper 16 bits of the 1394 destination offset of the write request that failed. 4.15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The TSB12LV23A device does not implement Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only and returns 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Vendor ID Vendor ID Register: Type: Offset: Default: Vendor ID Read-only 40h 0000 0000h 4-12 4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB12LV23A device. See Table 4-10 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 RSC X 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 RC 0 7 R 0 22 RSC 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 RSC 0 3 R 0 18 RSC X 2 R 0 17 RSC 0 1 R 0 16 RSCU 0 0 R 0 Host controller control Host controller control Register: Type: Offset: Default: Host controller control Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only 50h set register 54h clear register X00X 0000h Table 4-10. Host Controller Control Register Description BIT 31 30 29-24 23 FIELD NAME RSVD noByteSwapData RSVD programPhyEnable TYPE R RSC R RC Reserved. Bit 31 returns 0 when read. DESCRIPTION This bit is used to control whether physical accesses to locations outside the TSB12LV23A device itself as well as any other DMA data accesses should be swapped. Reserved. Bits 29-24 return 0s when read. This bit informs upper level software that lower level software has consistently configured the IEEE 1394a-2000 enhancements in the link and PHY device. When this bit is 1, generic software such as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY device and bit 22 (aPhyEnhanceEnable) in the TSB12LV23A device. When this bit is 0, the generic software may not modify the IEEE 1394a-2000 enhancements in the TSB12LV23A or PHY device and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from serial ROM. When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set this bit to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is set to 0, the software does not change PHY enhancements or this bit. Reserved. Bits 21-20 return 0s when read. This bit is used to control the link power status. Software must set this bit to 1 to permit link-PHY communication. A 0 prevents link-PHY communication. The OHCI-link is divided into two clock domains (PCI_CLK and PHY_SCLK). If software tries to access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, then a target abort issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1 in the miscellaneous configuration register (offset F0h, see Section 3.22). This allows the link to respond to these types of request by returning all F's (hex). OHCI registers at offsets DCh-F0h and 100h-11Ch are in the SCLK domain. After setting LPS software should wait at least 10 ms before attempting to access any of the OHCI registers. This gives the PHY_SCLK time to stabilize. 22 aPhyEnhanceEnable RSC 21-20 19 RSVD LPS R RSC 18 17 postedWriteEnable linkEnable RSC RSC This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only when bit 17 (linkEnable) is 0. This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is cleared, the TSB12LV23A device is logically and immediately disconnected from the 1394 bus, no packets are received or processed nor are packets transmitted. 4-13 Table 4-10. Host Controller Control Register Description (Continued) BIT 16 FIELD NAME softReset TYPE RSCU DESCRIPTION When this bit is set, all TSB12LV23A states are reset, all FIFOs are flushed, and all OHCI registers are set to their hardware reset values unless otherwise specified. PCI registers are not affected by this bit. This bit remains set while the soft reset is in progress and reverts back to 0 when the reset has completed. Reserved. Bits 15-0 return 0s when read. 15-0 RSVD R 4.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2-Kbyte-aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31-11 are read/write accessible. Bits 10-0 are reserved and return 0s when read. Bit Name Type Default Bit Name Type Default R/W X R/W X R/W X R/W X R/W X R 0 R 0 R/W X 15 R/W X 14 R/W X 13 R/W X 12 R/W X 11 R/W X 10 X 9 31 30 29 28 27 26 25 R/W 24 R/W X 8 R 0 23 R/W X 7 R 0 22 R/W X 6 R 0 21 R/W X 5 R 0 20 R/W X 4 R 0 19 R/W X 3 R 0 18 R/W X 2 R 0 17 R/W X 1 R 0 16 R/W X 0 R 0 Self-ID buffer pointer Self-ID buffer pointer Register: Type: Offset: Default: Self-ID buffer pointer Read/Write, Read-only 64h XXXX XX00h 4-14 4.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4-11 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 RU 0 RU 0 RU X 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 RU 0 23 RU X 7 RU 0 22 RU X 6 RU 0 21 RU X 5 RU 0 20 RU X 4 RU 0 19 RU X 3 RU 0 18 RU X 2 RU 0 17 RU X 1 R 0 16 RU X 0 R 0 Self-ID count Self-ID count Register: Type: Offset: Default: Self-ID count Read/Update, Read-only 68h X0XX 0000h Table 4-11. Self-ID Count Register Description BIT 31 FIELD NAME selfIDError TYPE RU DESCRIPTION When this bit is 1, an error was detected during the most recent self-ID packet reception. The contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error. Reserved. Bits 30-24 return 0s when read. The value in this field increments each time a bus reset is detected. This field rolls over to 0 after reaching 255. Reserved. Bits 15-11 return 0s when read. This field indicates the number of quadlets that have been written into the self-ID buffer for the current bits 23-16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0 when the self-ID reception begins. Reserved. Bits 1-0 return 0s when read. 30-24 23-16 15-11 10-2 RSVD selfIDGeneration RSVD selfIDSize R RU R RU 1-0 RSVD R 4-15 4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 4-12 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC X RSC X RSC X RSC X RSC X RSC X 15 RSC X 14 RSC X 13 RSC X 12 RSC X 11 31 30 29 28 27 26 RSC X 10 RSC X 25 RSC X 9 RSC X 24 RSC X 8 RSC X 23 RSC X 7 RSC X 22 RSC X 6 RSC X 21 RSC X 5 RSC X 20 RSC X 4 RSC X 19 RSC X 3 RSC X 18 RSC X 2 RSC X 17 RSC X 1 RSC X 16 RSC X 0 RSC X Isochronous receive channel mask high Isochronous receive channel mask high Register: Type: Offset: Default: Isochronous receive channel mask high Read/Set/Clear 70h set register 74h clear register XXXX XXXXh Table 4-12. Isochronous Receive Channel Mask High Register Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 FIELD NAME isoChannel63 isoChannel62 isoChannel61 isoChannel60 isoChannel59 isoChannel58 isoChannel57 isoChannel56 isoChannel55 isoChannel54 isoChannel53 isoChannel52 isoChannel51 isoChannel50 isoChannel49 isoChannel48 isoChannel47 isoChannel46 isoChannel45 isoChannel44 isoChannel43 isoChannel42 isoChannel41 isoChannel40 isoChannel39 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 63. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 62. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 61. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 60. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 59. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 58. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 57. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 56. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 55. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 54. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 53. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 52. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 51. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 50. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 49. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 48. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 47. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 46. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 45. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 44. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 43. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 42. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 41. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 40. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 39. 4-16 Table 4-12. Isochronous Receive Channel Mask High Register Description (Continued) BIT 6 5 4 3 2 1 0 FIELD NAME isoChannel38 isoChannel37 isoChannel36 isoChannel35 isoChannel34 isoChannel33 isoChannel32 TYPE RSC RSC RSC RSC RSC RSC RSC DESCRIPTION When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 38. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 37. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 36. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 35. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 34. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 33. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 32. 4.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. See Table 4-13 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC X RSC X RSC X RSC X RSC X X RSC X 15 RSC X 14 RSC X 13 RSC X 12 RSC X 11 X 10 RSC 31 30 29 28 27 26 RSC 25 RSC X 9 RSC X 24 RSC X 8 RSC X 23 RSC X 7 RSC X 22 RSC X 6 RSC X 21 RSC X 5 RSC X 20 RSC X 4 RSC X 19 RSC X 3 RSC X 18 RSC X 2 RSC X 17 RSC X 1 RSC X 16 RSC X 0 RSC X Isochronous receive channel mask low Isochronous receive channel mask low Register: Type: Offset: Default: Isochronous receive channel mask low Read/Set/Clear 78h set register 7Ch clear register XXXX XXXXh Table 4-13. Isochronous Receive Channel Mask Low Register Description BIT 31 30 L 1 0 FIELD NAME isoChannel31 isoChannel30 L isoChannel1 isoChannel0 TYPE RSC RSC L RSC RSC DESCRIPTION When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 31. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 30. Bits 29 through 2 follow the same pattern. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 1. When this bit is set, the TSB12LV23A device is enabled to receive from iso channel number 0. 4-17 4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB12LV23A interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the TSB12LV23A device adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 4-14 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 RSCU X X R 0 15 RSC X 14 R 0 13 R 0 12 R 0 11 RSCU X 10 RSCU X 9 X 8 RSCU 31 30 29 28 27 26 25 24 RSCU 23 RSCU X 7 Interrupt event RU X RU X RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X 22 RSCU X 6 21 RSCU X 5 20 RSCU X 4 19 RSCU X 3 18 R 0 2 17 RSCU X 1 16 RSCU X 0 Interrupt event Register: Type: Offset: Default: Interrupt event Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only 80h set register 84h clear register [returns the content of the interrupt event register bitwise ANDed with the interrupt mask register when read] XXXX 0XXXh Table 4-14. Interrupt Event Register Description BIT 31 30 FIELD NAME RSVD vendorSpecific TYPE R RSC Reserved. Bit 31 returns 0 when read. DESCRIPTION This vendor-specific interrupt event is reported when either of the general-purpose interrupts which are enabled via bit 31 (INT_3EN) and bit 23 (INT_2EN) of the GPIO control register (offset FCh, see Section 3.25). Reserved. Bits 29-27 return 0s when read. The TSB12LV23A device has received a PHY register data byte which can be read from bits 23-16 in the PHY layer control register (OHCI offset ECh, see Section 4.30). If bit 21 (cycleMaster) of the link control register (OHCI offset E0h/E4h, see Section 4.28) is set, then this indicates that over 125 s have elapsed between the start of sending a cycle start packet and the end of a subaction gap. The link control register bit 21 (cycleMaster) is cleared by this event. This event occurs when the TSB12LV23A device encounters any error that forces it to stop operations on any or all of its subunits, for example, when a DMA context sets its dead bit. While this bit is set, all normal interrupts for the context(s) that caused this interrupt are blocked from being set. A cycle start was received that had values for cycleSeconds and cycleCount fields that are different from the values in bits 31-25 (cycleSeconds field) and bits 24-12 (cycleCount field) of the isochronous cycle timer register (OHCI offset F0h, see Section 4.31). A lost cycle is indicated when no cycle_start packet is sent/received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. This bit may be set either when a lost cycle occurs or when logic predicts that one will occur. Indicates that the 7th bit of the cycle second counter has changed. Indicates that a new isochronous cycle has started. This bit is set when the low order bit of the cycle count toggles. 29-27 26 25 RSVD phyRegRcvd cycleTooLong R RSCU RSCU 24 unrecoverableError RSCU 23 cycleInconsistent RSCU 22 cycleLost RSCU 21 20 cycle64Seconds cycleSynch RSCU RSCU 4-18 Table 4-14. Interrupt Event Register Description (Continued) BIT 19 18 17 16 15-10 9 8 7 FIELD NAME phy RSVD busReset selfIDcomplete RSVD lockRespErr postedWriteErr isochRx TYPE RSCU R RSCU RSCU R RSCU RSCU RU Reserved. Bit 18 returns 0 when read. Indicates that the PHY device has entered bus reset mode. A self-ID packet stream has been received. It is generated at the end of the bus initialization process. This bit is turned off simultaneously when bit 17 (busReset) is turned on. Reserved. Bits 15-10 return 0s when read. Indicates that the TSB12LV23A device sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. Indicates that a host bus error occurred while the TSB12LV23A device was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous receive interrupt event (OHCI offset A0h/A4h, see Section 4.25) and isochronous receive interrupt mask (OHCI offset A8h/ACh, see Section 4.26) registers. The isochronous receive interrupt event register indicates which contexts have interrupted. Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous transmit interrupt event (OHCI offset 90h/94h, see Section 4.23) and isochronous transmit interrupt mask (OHCI offset 98h/9Ch, see Section 4.24) registers. The isochronous transmit interrupt event register indicates which contexts have interrupted. Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferStatus and resCount fields have been updated. Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferStatus and resCount fields have been updated. Asynchronous receive response DMA interrupt. This bit is conditionally set upon completion of an ARRS DMA context command descriptor. Asynchronous receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA context command descriptor. Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an ATRS DMA command. Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an ATRQ DMA command. DESCRIPTION Indicates that the PHY device requests an interrupt through a status transfer. 6 isochTx RU 5 4 3 2 1 0 RSPkt RQPkt ARRS ARRQ respTxComplete reqTxComplete RSCU RSCU RSCU RSCU RSCU RSCU 4-19 4.22 Interrupt Mask Register The interrupt mask set/clear register is used to enable the various TSB12LV23A interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and VendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4-14. See Table 4-15 for a complete description of bits 31 and 30. This register is fully compliant with the 1394 Open Host Controller Interface Specification and the TSB12LV23A device adds an interrupt function to bit 30. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 RSCU X X RSCU X 15 RSC X 14 R 0 13 R 0 12 R 0 11 RSCU X 10 RSCU X 9 X 8 RSCU 31 30 29 28 27 26 25 24 RSCU 23 Interrupt mask RSCU X 7 Interrupt mask RU X RU X RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X 6 RSCU X 5 RSCU X 4 RSCU X 3 R 0 2 RSCU X 1 RSCU X 0 22 21 20 19 18 17 16 Register: Type: Offset: Default: Interrupt mask Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only 88h set register 8Ch clear register XXXX 0XXXh Table 4-15. Interrupt Mask Register Description BIT 31 FIELD NAME masterIntEnable TYPE RSCU DESCRIPTION Master interrupt enable. If this bit is set, then external interrupts are generated in accordance with the interrupt mask register. If this bit is cleared, then external interrupts are not generated regardless of the interrupt mask register settings. When this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30 (vendorSpecific) of the interrupt event register (OHCI offset 80h/84h, see Section 4.21) is set. See Table 4-14. 30 29-0 VendorSpecific RSC 4-20 4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section 4.21) isochTx (bit 6) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4-16 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RSC X 22 R 0 6 RSC X 21 R 0 5 RSC X 20 R 0 4 RSC X 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous transmit interrupt event Isochronous transmit interrupt event Register: Type: Offset: Default: Isochronous transmit interrupt event Read/Set/Clear, Read-only 90h set register 94h clear register [returns the contents of the isochronous transmit interrupt event register bitwise ANDed with the isochronous transmit interrupt mask register when read] 0000 00XXh Table 4-16. Isochronous Transmit Interrupt Event Register Description BIT 31-8 7 6 5 4 3 2 1 0 FIELD NAME RSVD isoXmit7 isoXmit6 isoXmit5 isoXmit4 isoXmit3 isoXmit2 isoXmit1 isoXmit0 TYPE R RSC RSC RSC RSC RSC RSC RSC RSC Reserved. Bits 31-8 return 0s when read. DESCRIPTION Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt. 4-21 4.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 4-16. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RSC X 22 R 0 6 RSC X 21 R 0 5 RSC X 20 R 0 4 RSC X 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous transmit interrupt mask Isochronous transmit interrupt mask Register: Type: Offset: Default: Isochronous transmit interrupt mask Read/Set/Clear, Read-only 98h set register 9Ch clear register 0000 00XXh 4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section 4.21) isochRx (bit 7) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. An interrupt bit is set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4-17 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous receive interrupt event Isochronous receive interrupt event Register: Type: Offset: Default: BIT 31-4 3 2 1 0 FIELD NAME RSVD isoRecv3 isoRecv2 isoRecv1 isoRecv0 Isochronous receive interrupt event Read/Set/Clear, Read-only A0h set register A4h clear register [returns the contents of the isochronous receive interrupt event register bitwise ANDed with the isochronous receive interrupt mask register when read] 0000 000Xh Table 4-17. Isochronous Receive Interrupt Event Register Description TYPE R RSC RSC RSC RSC DESCRIPTION Reserved. Bits 31-4 return 0s when read. Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt. 4-22 4.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask register is used to enable the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 4-17. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous receive interrupt mask Isochronous receive interrupt mask Register: Type: Offset: Default: Isochronous receive interrupt mask Read/Set/Clear, Read-only A8h set register ACh clear register 0000 000Xh 4.27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4-18 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Fairness control Fairness control Register: Type: Offset: Default: Fairness control Read-only, Read/Write DCh 0000 0000h Table 4-18. Fairness Control Register Description BIT 31-8 7-0 FIELD NAME RSVD pri_req TYPE R R/W DESCRIPTION Reserved. Bits 31-8 return 0s when read. This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY device during a fairness interval. 4-23 4.28 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB12LV23A device. It contains controls for the receiver and cycle timer. See Table 4-19 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 RSC X RSC X R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 RSC X 6 R 0 21 RSCU X 5 R 0 20 RSC X 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Link control Link control Register: Type: Offset: Default: Link control Read/Set/Clear/Update, Read/Set/Clear, Read-only E0h set register E4h clear register 00X0 0X00h Table 4-19. Link Control Register Description BIT 31-23 22 FIELD NAME RSVD cycleSource TYPE R RSC DESCRIPTION Reserved. Bits 31-23 return 0s when read. When this bit is set, the cycle timer uses an external source (CYCLEIN) to determine when to roll over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576-MHz clock (125 s). When bit 21 is set and the PHY device has notified the TSB12LV23A device that the PHY device is root, the TSB12LV23A device generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynxt accepts received cycle start packets to maintain synchronization with the node which is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) of the interrupt event register (OHCI offset 80h/84h, see Section 4.21) is set. Bit 21 cannot be set until bit 25 (cycleTooLong) is cleared. When this bit is set, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over at the appropriate time based on the settings of the above bits. When this bit is cleared, the cycle timer offset does not count. Reserved. Bits 19-11 return 0s when read. When this bit is set, the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled. This does not control receipt of self-ID packets. When this bit is set, the receiver accepts incoming self-ID packets. Before setting this bit to 1, software must ensure that the self-ID buffer pointer register contains a valid address. Reserved. Bits 8-0 return 0s when read. 21 cycleMaster RSCU 20 CycleTimerEnable RSC 19-11 10 9 8-0 RSVD RcvPhyPkt RcvSelfID RSVD R RSC RSC R 4-24 4.29 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynxt chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15-6) and the NodeNumber field (bits 5-0) is referred to as the node ID. See Table 4-20 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RU 0 15 RU 0 14 R 0 13 R 0 12 RU 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 RWU 1 23 R 0 7 RWU 1 22 R 0 6 RWU 1 21 R 0 5 RU X 20 R 0 4 RU X 19 R 0 3 RU X 18 R 0 2 RU X 17 R 0 1 RU X 16 R 0 0 RU X Node identification Node identification Register: Type: Offset: Default: Node identification Read/Write/Update, Read/Update, Read-only E8h 0000 FFXXh Table 4-20. Node Identification Register Description BIT 31 FIELD NAME iDValid TYPE RU DESCRIPTION This bit indicates whether or not the TSB12LV23A device has a valid node number. It is cleared when a 1394 bus reset is detected and set when the TSB12LV23A device receives a new node number from the PHY device. This bit is set during the bus reset process if the attached PHY device is root. Reserved. Bits 29-28 return 0s when read. This bit is set if the PHY device is reporting that cable power status is OK. Reserved. Bits 26-16 return 0s when read. This number is used to identify the specific 1394 bus the TSB12LV23A device belongs to when multiple 1394-compatible buses are connected via a bridge. This number is the physical node number established by the PHY device during self-ID. It is automatically set to the value received from the PHY device after the self-ID phase. If the PHY device sets the NodeNumber to 63, then software should not set bit 15 (run) of the asynchronous context control register (see Section 4.37) for either of the AT DMA contexts. 30 29-28 27 26-16 15-6 5-0 root RSVD CPS RSVD BusNumber NodeNumber RU R RU R RWU RU 4-25 4.30 PHY Layer Control Register The PHY layer control register is used to read or write a PHY register. See Table 4-21 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU 0 RWU 0 R 0 R 0 R/W 0 R/W 0 R/W 0 RU 0 15 R 0 14 R 0 13 R 0 12 RU 0 11 RU 0 10 RU 0 9 31 30 29 28 27 26 25 24 RU 0 8 R/W 0 23 RU 0 7 R/W 0 22 RU 0 6 R/W 0 21 RU 0 5 R/W 0 20 RU 0 4 R/W 0 19 RU 0 3 R/W 0 18 RU 0 2 R/W 0 17 RU 0 1 R/W 0 16 RU 0 0 R/W 0 PHY layer control PHY layer control Register: Type: Offset: Default: PHY layer control Read/Write/Update, Read/Write, Read/Update, Read-only ECh 0000 0000h Table 4-21. PHY Control Register Description BIT 31 30-28 27-24 23-16 15 14 13-12 11-8 7-0 FIELD NAME rdDone RSVD rdAddr rdData rdReg wrReg RSVD regAddr wrData TYPE RU R RU RU RWU RWU R R/W R/W DESCRIPTION This bit is cleared to 0 by the TSB12LV23A device when either bit 15 (rdReg) or bit 14 (wrReg) is set. This bit is set when a register transfer is received from the PHY device. Reserved. Bits 30-28 return 0s when read. This is the address of the register most recently received from the PHY device. This field is the contents of a PHY register that has been read. This bit is set by software to initiate a read request to a PHY register and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set simultaneously. This bit is set by software to initiate a write request to a PHY register and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set simultaneously. Reserved. Bits 13-12 return 0s when read. This field is the address of the PHY register to be written or read. This field is the data to be written to a PHY register and is ignored for reads. 4-26 4.31 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV23A device is cycle master, this register is transmitted with the cycle start message. When the TSB12LV23A device is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. See Table 4-22 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU X RWU X RWU X RWU X RWU X RWU X RWU X 15 RWU X 14 RWU X 13 RWU X 12 RWU X 11 RWU X 10 31 30 29 28 27 26 25 RWU X 9 RWU X 24 RWU X 8 RWU X 23 RWU X 7 RWU X 22 RWU X 6 RWU X 21 RWU X 5 RWU X 20 RWU X 4 RWU X 19 RWU X 3 RWU X 18 RWU X 2 RWU X 17 RWU X 1 RWU X 16 RWU X 0 RWU X Isochronous cycle timer Isochronous cycle timer Register: Type: Offset: Default: Isochronous cycle timer Read/Write/Update F0h XXXX XXXXh Table 4-22. Isochronous Cycle Timer Register Description BIT 31-25 24-12 11-0 FIELD NAME cycleSeconds cycleCount cycleOffset TYPE RWU RWU RWU DESCRIPTION This field counts seconds [rollovers from bits 24-12 (cycleCount field)] modulo 128. This field counts cycles [rollovers from bits 11-0 (cycleOffset field)] modulo 8000. This field counts 24.576-MHz clocks modulo 3072, that is, 125 s. If an external 8-kHz clock configuration is being used, then this bit must be cleared at each tick of the external clock. 4-27 4.32 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the TSB12LV23A device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set. See Table 4-23 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Asynchronous request filter high Asynchronous request filter high Register: Type: Offset: Default: Asynchronous request filter high Read/Set/Clear 100h set register 104h clear register 0000 0000h Table 4-23. Asynchronous Request Filter High Register Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 FIELD NAME asynReqAllBuses asynReqResource62 asynReqResource61 asynReqResource60 asynReqResource59 asynReqResource58 asynReqResource57 asynReqResource56 asynReqResource55 asynReqResource54 asynReqResource53 asynReqResource52 asynReqResource51 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If this bit is set, then all asynchronous requests received by the TSB12LV23A device from nonlocal bus nodes are accepted. If this bit is set for local bus node number 62, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 61, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 60, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 59, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 58, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 57, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 56, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 55, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 54, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 53, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 52, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 51, then asynchronous requests received by the TSB12LV23A device from that node are accepted. 4-28 Table 4-23. Asynchronous Request Filter High Register Description (Continued) BIT 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD NAME asynReqResource50 asynReqResource49 asynReqResource48 asynReqResource47 asynReqResource46 asynReqResource45 asynReqResource44 asynReqResource43 asynReqResource42 asynReqResource41 asynReqResource40 asynReqResource39 asynReqResource38 asynReqResource37 asynReqResource36 asynReqResource35 asynReqResource34 asynReqResource33 asynReqResource32 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If this bit is set for local bus node number 50, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 49, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 48, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 47, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 46, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 45, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 44, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 43, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 42, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 41, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 40, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 39, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 38, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 37, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 36, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 35, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 34, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 33, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 32, then asynchronous requests received by the TSB12LV23A device from that node are accepted. 4-29 4.33 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 4-24 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Asynchronous request filter low Asynchronous request filter low Register: Type: Offset: Default: Asynchronous request filter low Read/Set/Clear 108h set register 10Ch clear register 0000 0000h Table 4-24. Asynchronous Request Filter Low Register Description BIT 31 30 L 1 0 FIELD NAME asynReqResource31 asynReqResource30 L asynReqResource1 asynReqResource0 TYPE RSC RSC L RSC RSC DESCRIPTION If this bit is set for local bus node number 31, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 30, then asynchronous requests received by the TSB12LV23A device from that node are accepted. Bits 29 through 2 follow the same pattern. If this bit is set for local bus node number 1, then asynchronous requests received by the TSB12LV23A device from that node are accepted. If this bit is set for local bus node number 0, then asynchronous requests received by the TSB12LV23A device from that node are accepted. 4-30 4.34 Physical Request Filter High Register The physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and handles the upper node IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the ARRQ context instead of the physical request context. The node ID comparison is done if the source node is on the same bus as the TSB12LV23A device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set. See Table 4-25 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Physical request filter high Physical request filter high Register: Type: Offset: Default: Physical request filter high Read/Set/Clear 110h set register 114h clear register 0000 0000h Table 4-25. Physical Request Filter High Register Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 FIELD NAME physReqAllBusses physReqResource62 physReqResource61 physReqResource60 physReqResource59 physReqResource58 physReqResource57 physReqResource56 physReqResource55 physReqResource54 physReqResource53 physReqResource52 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If this bit is set, then all physical requests received by the TSB12LV23A device from nonlocal bus nodes are accepted. If this bit is set for local bus node number 62, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 61, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 60, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 59, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 58, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 57, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 56, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 55, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 54, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 53, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 52, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. 4-31 Table 4-25. Physical Request Filter High Register Description (Continued) BIT 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD NAME physReqResource51 physReqResource50 physReqResource49 physReqResource48 physReqResource47 physReqResource46 physReqResource45 physReqResource44 physReqResource43 physReqResource42 physReqResource41 physReqResource40 physReqResource39 physReqResource38 physReqResource37 physReqResource36 physReqResource35 physReqResource34 physReqResource33 physReqResource32 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If this bit is set for local bus node number 51, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 50, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 49, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 48, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 47, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 46, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 45, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 44, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 43, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 42, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 41, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 40, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 39, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 38, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 37, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 36, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 35, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 34, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 33, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 32, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. 4-32 4.35 Physical Request Filter Low Register The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the asynchronous request context instead of the physical request context. See Table 4-26 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Physical request filter low Physical request filter low Register: Type: Offset: Default: Physical request filter low Read/Set/Clear 118h set register 11Ch clear register 0000 0000h Table 4-26. Physical Request Filter Low Register Description BIT 31 30 L 1 0 FIELD NAME physReqResource31 physReqResource30 L physReqResource1 physReqResource0 TYPE RSC RSC L RSC RSC DESCRIPTION If this bit is set for local bus node number 31, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 30, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. Bits 29 through 2 follow the same pattern. If this bit is set for local bus node number 1, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. If this bit is set for local bus node number 0, then physical requests received by the TSB12LV23A device from that node are handled through the physical request context. 4.36 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. It returns all 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Physical upper bound Physical upper bound Register: Type: Offset: Default: Physical upper bound Read-only 120h 0000 0000h 4-33 4.37 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 4-27 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSCU 0 R 0 R 0 RSU X RU 0 RU 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RU X 22 R 0 6 RU X 21 R 0 5 RU X 20 R 0 4 RU X 19 R 0 3 RU X 18 R 0 2 RU X 17 R 0 1 RU X 16 R 0 0 RU X Asynchronous context control Asynchronous context control Register: Type: Offset: Default: Asynchronous context control Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only 180h set register [ATRQ] 184h clear register [ATRQ] 1A0h set register [ATRS] 1A4h clear register [ATRS] 1C0h set register [ARRQ] 1C4h clear register [ARRQ] 1E0h set register [ARRS] 1E4h clear register [ARRS] 0000 X0XXh Table 4-27. Asynchronous Context Control Register Description BIT 31-16 15 FIELD NAME RSVD run TYPE R RSCU DESCRIPTION Reserved. Bits 31-16 return 0s when read. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The TSB12LV23A device changes this bit only on a hardware or software reset. Reserved. Bits 14-13 return 0s when read. Software sets this bit to cause the TSB12LV23A device to continue or resume descriptor processing. The TSB12LV23A device clears this bit on every descriptor fetch. The TSB12LV23A device sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). The TSB12LV23A device sets this bit to 1 when it is processing descriptors. Reserved. Bits 9-8 return 0s when read. This field indicates the speed at which a packet was received or transmitted, and only contains meaningful information for receive contexts. This field is encoded as: 000 = 100 Mbits/sec 001 = 200 Mbits/sec 010 = 400 Mbits/sec All other values are reserved. This field holds the acknowledge sent by the link core for this packet, or holds an internally generated error code if the packet was not transferred successfully. 14-13 12 11 10 9-8 7-5 RSVD wake dead active RSVD spd R RSU RU RU R RU 4-0 eventcode RU 4-34 4.38 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV23A device accesses when software enables the context by setting bit 15 (run) of the asynchronous context control register (see Section 4.37). See Table 4-28 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU X RWU X RWU X RWU X RWU X RWU X 15 RWU X 14 RWU X 13 RWU X 12 RWU X 11 31 30 29 28 27 26 RWU X 10 RWU X 25 RWU X 9 RWU X 24 RWU X 8 RWU X 23 RWU X 7 RWU X 22 RWU X 6 RWU X 21 RWU X 5 RWU X 20 RWU X 4 RWU X 19 RWU X 3 RWU X 18 RWU X 2 RWU X 17 RWU X 1 RWU X 16 RWU X 0 RWU X Asynchronous context command pointer Asynchronous context command pointer Register: Type: Offset: Default: Asynchronous context command pointer Read/Write/Update 18Ch [ATRQ] 1ACh [ATRS] 1CCh [ARRQ] 1ECh [ARRS] XXXX XXXXh Table 4-28. Asynchronous Context Command Pointer Register Description BIT 31-4 3-0 FIELD NAME descriptorAddress Z TYPE RWU RWU DESCRIPTION Contains the upper 28 bits of the address of a 16-byte-aligned descriptor block. Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If Z is 0, then it indicates that the descriptorAddress field (bits 31-4) is not valid. 4-35 4.39 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). See Table 4-29 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 R 0 R 0 RSU X RU 0 RU 0 RSCU X 15 RSC X 14 RSC X 13 RSC X 12 RSC X 11 X 10 31 30 29 28 27 26 RSC 25 RSC X 9 R 0 24 RSC X 8 R 0 23 RSC X 7 RU X 22 RSC X 6 RU X 21 RSC X 5 RU X 20 RSC X 4 RU X 19 RSC X 3 RU X 18 RSC X 2 RU X 17 RSC X 1 RU X 16 RSC X 0 RU X Isochronous transmit context control Isochronous transmit context control Register: Type: Offset: Default: Isochronous transmit context control Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only 200h + (16 * n) set register 204h + (16 * n) clear register XXXX X0XXh Table 4-29. Isochronous Transmit Context Control Register Description BIT 31 FIELD NAME cycleMatchEnable TYPE RSCU DESCRIPTION When this bit is set to 1, processing occurs such that the packet described by the context first descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field (bits 30-16). The cycleMatch field (bits 30-16) must match the low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. The effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware clears this bit. This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle timer register (OHCI offset F0h, see Section 4.31) cycleSeconds field (bits 31-25) and the cycleCount field (bits 24-12). If bit 31 (cycleMatchEnable) is set, then this isochronous transmit DMA context becomes enabled for transmits when the low-order two bits of the isochronous cycle timer register cycleSeconds field (bits 31-25) and the cycleCount field (bits 24-12) value equal this field (cycleMatch) value. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The TSB12LV23A device changes this bit only on a hardware or software reset. Reserved. Bits 14-13 return 0s when read. Software sets this bit to cause the TSB12LV23A device to continue or resume descriptor processing. The TSB12LV23A device clears this bit on every descriptor fetch. The TSB12LV23A device sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). The TSB12LV23A device sets this bit to 1 when it is processing descriptors. Reserved. Bits 9-8 return 0s when read. This field is not meaningful for isochronous transmit contexts. Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. 30-16 cycleMatch RSC 15 run RSC 14-13 12 11 10 9-8 7-5 4-0 RSVD wake dead active RSVD spd event code R RSU RU RU R RU RU 4-36 4.40 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV23A device accesses when software enables an isochronous transmit context by setting bit 15 (run) of the isochronous transmit context control register (see Section 4.39). The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 31 30 29 28 27 26 R X 10 R X 25 R X 9 R X 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X Isochronous transmit context command pointer Isochronous transmit context command pointer Register: Type: Offset: Default: Isochronous transmit context command pointer Read-only 20Ch + (16 * n) XXXX XXXXh 4.41 Isochronous Receive Context Control Register The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4-30 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSCU 0 R 0 R 0 RSU X RU 0 0 RSC X 15 RSC X 14 RSCU X 13 RSC X 12 R 0 11 0 10 RU 31 30 29 28 27 26 R 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RU X 22 R 0 6 RU X 21 R 0 5 RU X 20 R 0 4 RU X 19 R 0 3 RU X 18 R 0 2 RU X 17 R 0 1 RU X 16 R 0 0 RU X Isochronous receive context control Isochronous receive context control Register: Type: Offset: Default: Isochronous receive context control Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only 400h + (32 * n) set register 404h + (32 * n) clear register X000 X0XXh Table 4-30. Isochronous Receive Context Control Register Description BIT 31 FIELD NAME bufferFill TYPE RSC DESCRIPTION When this bit is set, received packets are placed back-to-back to completely fill each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. When this bit is 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. The end of the packet is marked with xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet. When this bit is cleared, the packet header is stripped from received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. 30 isochHeader RSC 4-37 Table 4-30. Isochronous Receive Context Control Register Description (Continued) BIT 29 FIELD NAME cycleMatchEnable TYPE RSCU DESCRIPTION When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24-12) in the isochronous receive context match register (see Section 4.43) matches the 13-bit cycleCount field in the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits in this register. When the context has become active, hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. When this bit is set, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high (OHCI offset 70h/74h, see Section 4.19) and isochronous receive channel mask low (OHCI offset 78h/7Ch, see Section 4.20) registers. The isochronous channel number specified in the isochronous receive context match register (see Section 4.43) is ignored. When this bit is cleared, the isochronous receive DMA context receives packets for the single channel specified in the isochronous receive context match register (see Section 4.43). Only one isochronous receive DMA context may use the isochronous receive channel mask registers (see Sections 4.19 and 4.20). If more than one isochronous receive context control register has this bit set, then results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. Reserved. Bits 27-16 return 0s when read. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The TSB12LV23A device changes this bit only on a hardware or software reset. Reserved. Bits 14-13 return 0s when read. Software sets this bit to cause the TSB12LV23A device to continue or resume descriptor processing. The TSB12LV23A device clears this bit on every descriptor fetch. The TSB12LV23A device sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). The TSB12LV23A device sets this bit to 1 when it is processing descriptors. Reserved. Bits 9-8 return 0s when read. This field indicates the speed at which the packet was received. 000 = 100 Mbits/sec 001 = 200 Mbits/sec 010 = 400 Mbits/sec All other values are reserved. For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read, evt_data_write, and evt_unknown. 28 multiChanMode RSC 27-16 15 RSVD run R RSCU 14-13 12 11 10 9-8 7-5 RSVD wake dead active RSVD spd R RSU RU RU R RU 4-0 event code RU 4-38 4.42 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV23A device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 4.41). The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 31 30 29 28 27 26 R X 10 R X 25 R X 9 R X 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X Isochronous receive context command pointer Isochronous receive context command pointer Register: Type: Offset: Default: Isochronous receive context command pointer Read-only 40Ch + (32 * n) XXXX XXXXh 4-39 4.43 Isochronous Receive Context Match Register The isochronous receive context match register is used to start an isochronous receive context running on a specified cycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4-31 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W X R/W X R/W X R/W X R/W X R/W X R/W X 15 R/W X 14 R/W X 13 R/W X 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R/W X 24 R/W X 8 R/W X 23 R/W X 7 R 0 22 R/W X 6 R/W X 21 R/W X 5 R/W X 20 R/W X 4 R/W X 19 R/W X 3 R/W X 18 R/W X 2 R/W X 17 R/W X 1 R/W X 16 R/W X 0 R/W X Isochronous receive context match Isochronous receive context match Register: Type: Offset: Default: Isochronous receive context match Read/Write, Read-only 410Ch + (32 * n) XXXX XXXXh Table 4-31. Isochronous Receive Context Match Register Description BIT 31 30 29 28 27-25 24-12 FIELD NAME tag3 tag2 tag1 tag0 RSVD cycleMatch TYPE R/W R/W R/W R/W R R/W DESCRIPTION If this bit is set, then this context matches on iso receive packets with a tag field of 11b. If this bit is set, then this context matches on iso receive packets with a tag field of 10b. If this bit is set, then this context matches on iso receive packets with a tag field of 01b. If this bit is set, then this context matches on iso receive packets with a tag field of 00b. Reserved. Bits 27-25 return 0s when read. This field contains a 15-bit value corresponding to the two low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart packet. If bit 29 (cycleMatchEnable) of the isochronous receive context control register (see Section 4.41) is set, then this context is enabled for receives when the two low-order bits of the isochronous cycle timer register (OHCI offset F0h, see Section 4.31) cycleSeconds field (bits 31-25) and cycleCount field (bits 24-12) value equal this field (cycleMatch) value. This field contains the four-bit field which is compared to the sync field of each iso packet for this channel when the command descriptor w field is set to 11b. Reserved. Bit 7 returns 0 when read. If this bit and bit 29 (tag1) are set, then packets with tag 01b are accepted into the context if the two most significant bits of the packet sync field are 00b. Packets with tag values other than 01b are filtered according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively) without any additional restrictions. If this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28-31 (tag0-tag3) with no additional restrictions. 11-8 7 6 sync RSVD tag1SyncFilter R/W R R/W 5-0 channelNumber R/W This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets. 4-40 4.44 IR Digital Video Enhancements Register This register is used to enable the DV enhancements in the TSB12LV23A device. The bits in this register may only be modified when both the active and run bits of the corresponding context control register are 0. See Table 4-32 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 RSC 0 RSC 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 RSC 0 24 R 0 8 RSC 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 RSC 0 20 R 0 4 RSC 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 RSC 0 16 R 0 0 RSC 0 IR digital video enhancements IR digital video enhancements Register: Type: Offset: Default: IR digital video enhancements Read/Set/Clear, Read-only A88h set register A8Ch clear register 0000 0000h Table 4-32. IR Digital Video Enhancements Register Description BIT 31-14 13 FIELD NAME RSVD DV_Branch3 TYPE R RSC DESCRIPTION Reserved. Bits 31-14 return 0s when read. When set, this bit will cause isochronous receive context 3 in bufferfill mode to sync reception to the DV frame start tag when input_more.b = 01b, and will jump to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 12 (CIP_Strip3) is 1 and bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 460h/464h, see Section 4.41) is 0. When set, this bit will cause isochronous receive context 3 to strip the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 460h/464h, see Section 4.41) is 0. Reserved. Bits 11-10 return 0s when read. When set, this bit will cause isochronous receive context 2 in bufferfill mode to sync reception to the DV frame start tag when input_more.b = 01b, and will jump to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 8 (CIP_Strip2) is 1 and bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 440h/444h, see Section 4.41) is 0. When set, this bit will cause isochronous receive context 2 to strip the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 440h/444h, see Section 4.41) is 0. Reserved. Bits 7-6 return 0s when read. When set, this bit will cause isochronous receive context 1 in bufferfill mode to sync reception to the DV frame start tag when input_more.b = 01b, and will jump to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 4 (CIP_Strip1) is 1 and bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 420h/424h, see Section 4.41) is 0. When set, this bit will cause isochronous receive context 1 to strip the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 420h/424h, see Section 4.41) is 0. Reserved. Bits 3-2 return 0s when read. 12 CIP_Strip3 RSC 11-10 9 RSVD DV_Branch2 R RSC 8 CIP_Strip2 RSC 7-6 5 RSVD DV_Branch1 R RSC 4 CIP_Strip1 RSC 3-2 RSVD R 4-41 Table 4-32. IR Digital Video Enhancements Register Description (Continued) BIT 1 FIELD NAME DV_Branch0 TYPE RSC DESCRIPTION When set, this bit will cause isochronous receive context 0 in bufferfill mode to sync reception to the DV frame start tag when input_more.b = 01b, and will jump to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is 1 and bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 400h/404h, see Section 4.41) is 0. When set, this bit will cause isochronous receive context 0 to strip the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) of the isochronous receive context control register (OHCI offset 400h/404h, see Section 4.41) is 0. 0 CIP_Strip0 RSC 4-42 5 GPIO Interface The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register. Figure 5-1 shows the logic diagram for GPIO2 and GPIO3 implementation. GPIO0 and GPIO1 are not implemented in the TSB12LV23A device. The terminals for these legacy GPIOs from the TSB12LV22 device have been dedicated to PHY_LINKON (terminal 98) and PHY_LPS (terminal 99), respectively. GPIO Read Data GPIO Port GPIO Write Data D Q GPIO_Invert GPIO Enable Figure 5-1. GPIO2 and GPIO3 Logic Diagram 5-1 5-2 6 Serial ROM Interface The TSB12LV23A device provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial ROM. The TSB12LV23A device communicates with the serial ROM via the 2-wire serial interface. After powerup, the serial interface initializes the locations listed in Table 6-1. While the TSB12LV23A device is accessing the serial ROM, all incoming PCI slave accesses are terminated with retry status. Table 6-2 shows the serial ROM memory map required for initializing the TSB12LV23A registers. NOTE: If a ROM is implemented in the design, it must be programmed. An unprogrammed ROM defaults to all 1s, which will adversely impact device operation. Table 6-1. Registers and Bits Loadable Through Serial ROM ROM OFFSET 00h 01h 03h 05h (bit 6) 05h 06h-0Ah 0Bh-0Eh 10h 11h-12h 13h PCI/OHCI OFFSET PCI register (3Eh) PCI register (2Dh) PCI register (2Ch) OHCI register (50h) PCI register (F4h) OHCI register (24h) OHCI register(28h) PCI register (F4h) PCI register (F0h) PCI register (40h) REGISTER PCI maximum latency, PCI minimum grant Vendor identification Subsystem identification Host controller control Link enhancement control GUID high GUID low Link enhancement control Miscellaneous configuration OHCI control BITS LOADED FROM ROM 15-0 15-0 15-0 23 7, 2, 1 31-0 31-0 13, 12, 9, 8 15, 13, 10, 4-0 0 6-1 Table 6-2. Serial ROM Map BYTE ADDRESS 00 01 02 03 04 [7] Link_enhancementControl.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD PCI maximum latency (0h) PCI vendor ID PCI vendor ID (msbyte) PCI subsystem ID (lsbyte) PCI subsystem ID [4] RSVD [3] RSVD [2] Link_enhancementControl.enab_ insert_idle [1] Link_enhancementControl.enab_accel [0] RSVD BYTE DESCRIPTION PCI minimum grant (0h) 05 06 07 08 09 0A 0B 0C 0D 0E 0F [15] RSVD [14] RSVD Mini ROM address GUID high (lsbyte 0) GUID high (byte 1) GUID high (byte 2) GUID high (msbyte 3) GUID low (lsbyte 0) GUID low (byte 1) GUID low (byte 2) GUID low (msbyte 3) Checksum [13-12] AT threshold [11] RSVD [10] RSVD [9] Enable audio time stamp [1] Disable PCI gate [8] Enable DV CIP time stamp [0] Keep PCI 10 11 [7] RSVD [6] RSVD [5] RSVD [4] Disable Target Abort [12] RSVD [3] GP2IIC [2] Disable SCLK gate 12 [15] PME D3 Cold [14] RSVD [13] PME Support D2 [5] RSVD [11] RSVD [10] D2 support [9] RSVD [8] RSVD 13 14 15-1E 1F [7] RSVD [6] RSVD [4] RSVD [3] RSVD [2] RSVD [1] RSVD [0] Global swap CIS offset address RSVD RSVD 6-2 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCP + 0.5 V Input voltage range for Miscellaneous and PHY interface, VI . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCI + 0.5 V Output voltage range for PCI, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCP + 0.5 V Input voltage range for Miscellaneous and PHY interface, VO . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCP + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies to external input and bidirectional buffers. For 5-V tolerant use VI > VCC. For PCI use VI > VCCP. 2. Applies to external output and bidirectional buffers. For 5-V tolerant use VO > VCC. For PCI use VO > VCCP. 7-1 7.2 Recommended Operating Conditions OPERATION VCC VCCP Core voltage PCI I/O clamping voltage Commercial Commercial 3.3 V 3.3 V 5V 3.3 V PCI VIH High-level High level input voltage PHY interface Miscellaneous 3.3 V PCI VIL Low level input voltage Low-level PHY interface Miscellaneous PCI VI Input voltage g PHY interface Miscellaneous PCI VO tt TA TJ Output voltage g PHY interface Miscellaneous Input transition time (tr and tf) Operating ambient temperature Virtual junction temperature PCI 3.3 V 3.3 V 5V 5V MIN 3 3 4.5 0.475 VCCP 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 25 25 NOM 3.3 3.3 5 MAX 3.6 3.6 5.5 VCCP VCCP VCC VCC 0.325 VCCP 0.8 0.8 0.8 VCCP VCCP VCCP VCCP VCCP VCCP 6 70 115 ns C C V V V V V UNIT V Applies to external inputs and bidirectional buffers without hysteresis. Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT. Applies to external output buffers. The junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature. 7-2 7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) OPERATION PCI VOH High level output High-level out ut voltage PHY interface Miscellaneous PCI VOL Low level output Low-level out ut voltage PHY interface Miscellaneous IOZ IIL IIH 3-state output high-impedance Low-level Low level input current High-level High level input current Output pins Input pins I/O pins PCI Others 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V TEST CONDITIONS IOH = - 0.5 mA IOH = - 2 mA IOH = - 4 A IOH = - 8 mA IOH = - 4 mA IOL = 1.5 mA IOL = 6 mA IOL = 4 mA IOL = 8 mA IOL = 4 mA VO = VCC or GND VI = GND VI = GND VI = VCC VI = VCC MIN 0.9 VCC 2.4 2.8 VCC - 0.6 VCC - 0.6 0.1 VCC 0 0.55 0.4 0.5 20 20 20 20 20 A A A A V V MAX UNIT For I/O pins, input leakage (IIL and IIH) includes IOZ of the disabled output. Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT. 7.4 Switching Characteristics for PCI Interface PARAMETER tsu th Setup time before PCLK Hold time before PCLK MEASURED -50% to 50% -50% to 50% -50% to 50% MIN 7 0 2 11 TYP MAX UNIT ns ns ns td Delay time, PHY_CLK to data valid These parameters are ensured by design. 7.5 Switching Characteristics for PHY-Link Interface PARAMETER tsu th Setup time, Dn, CTLn, LREQ to PHY_CLK Hold time, Dn, CTLn, LREQ before PHY_CLK MEASURED -50% to 50% -50% to 50% -50% to 50% MIN 6 0 1 10 TYP MAX UNIT ns ns ns td Delay time, PHY_CLK to Dn, CTLn These parameters are ensured by design. 7-3 7-4 8 Mechanical Information The TSB12LV23A device is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for the PZ package. PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,50 75 51 0,27 0,17 0,08 M 76 50 100 26 0,13 NOM 1 12,00 TYP 14,20 SQ 13,80 16,20 SQ 15,80 1,45 1,35 25 Gage Plane 0,05 MIN 0,25 0- 7 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 8-1 8-2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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