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| TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 * * * * * * Low rDS(on) . . . 0.35 Typ Voltage Output . . . 60 V Input Protection Circuitry . . . 18 V Pulsed Current . . . 4 A Per Channel Extended ESD Capability . . . 4000 V Direct Logic-Level Interface DW PACKAGE (TOP VIEW) description 8 17 The TPIC1321L is a monolithic gate-protected 9 16 logic-level power DMOS array that consists of six 10 15 electrically isolated N-channel enhancementmode DMOS transistors configured as 3-half 11 14 H-bridges. Each transistor features integrated 12 13 high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-k resistor. OUTPUT1 GATE4 SOURCE4 SOURCE4 GND GND GATE5 SOURCE6 SOURCE6 GATE6 OUTPUT3 OUTPUT3 1 2 3 4 5 6 7 24 23 22 21 20 19 18 OUTPUT1 GATE1 DRAIN1 DRAIN1 DRAIN2 DRAIN2 OUTPUT2 OUTPUT2 GATE2 DRAIN3 DRAIN3 GATE3 The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature of - 40C to 125C. schematic OUTPUT2 17, 18 21, 22 Q1 GATE1 23 ZC1b D1 ZC1a 1, 24 D4 Z1 ZC2b ZC2a GATE5 GATE2 7 16 DRAIN2 19, 20 14, 15 DRAIN1 DRAIN3 Q2 Z2 Z3 Q3 13 ZC3b D2 D3 D5 ZC3a 11, 12 GATE3 OUTPUT3 OUTPUT1 Q4 GATE4 2 ZC4b ZC4a SOURCE4 3, 4 Z4 ZC5b ZC5a Q5 Z5 Z6 Q6 10 ZC6b ZC6a 8, 9 5, 6 GND GATE6 SOURCE6 NOTE A: For correct operation, no terminal may be taken below GND. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1994, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-1 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V SOURCE4, SOURCE6-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 9 V to 18 V Continuous drain current, each output, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 A Continuous source-to-drain diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 A Pulsed drain current, each output, Imax, TC = 25C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 4 A Continuous gate-to-source zener-diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Pulsed gate-to-source zener-diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS, TC = 25C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . . . 96 mJ Continuous total dissipation, TC = 25C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% 2-2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 electrical characteristics, TC = 25C (unless otherwise noted) PARAMETER V(BR)DSX VGS(th) V(BR)GS V(BR)SG V(BR) VDS(on) VF(SD) VF IDSS IGSSF IGSSR Ilk lkg Drain-to-source breakdown voltage Gate-to-source threshold voltage Gate-to-source breakdown voltage Source-to-gate breakdown voltage Reverse drain-to-GND breakdown voltage (across D1 , D2, D3, D4, D5) Drain-to-source on-state voltage TEST CONDITIONS ID = 250 A, ID = 1 mA, See Figure 5 IGS = 250 A ISG = 250 A Drain-to-GND current = 250 A ID = 1.25 A, See Notes 2 and 3 VGS = 5 V, VGS = 0 VDS = VGS, MIN 60 1.5 18 9 100 0.44 0.5 1.75 2.2 TYP MAX UNIT V V V V V V Forward on-state voltage, source-to-drain IS = 1.25 A, VGS = 0 (Z1 - Z6), See Notes 2 and 3 and Figure 12 ID = 1.25 A (D1 - D5) See Notes 2 and 3 VDS = 48 V, , VGS = 0 VGS = 15 V, VSG = 5 V, VDGND = 48 V VGS = 5 V, ID = 1.25 A, , See Notes 2 and 3 and Figures 6 and 7 TC = 25C TC = 125C VDS = 0 VDS = 0 TC = 25C TC = 125C TC = 25C TC = 125C 1.6 0.9 1.1 V Forward on-state voltage, GND-to-drain Zero-gate-voltage Zero gate voltage drain current Forward-gate current, drain short circuited to source Reverse-gate current, drain short circuited to source Leakage current, drain-to-GND current drain to GND 4 0.05 0.5 20 10 0.05 0.5 0.35 0.57 1.74 200 250 220 75 1 10 200 100 1 10 0.4 V A nA nA A rDS( ) DS(on) Static drain-to-source on-state resistance drain to source on state 0.6 S gfs Ciss Coss Crss Forward transconductance Short-circuit input capacitance, common source Short-circuit output capacitance, common source Short-circuit reverse-transfer capacitance, common source VDS = 15 V, ID = 625 mA, See Notes 2 and 3 and Figure 9 VDS = 25 V, f = 1 MHz, VGS = 0, See Figure 11 175 40 pF F NOTES: 2. Technique should limit TJ - TC to 10C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25C PARAMETER trr QRR Reverse-recovery time Total diode charge TEST CONDITIONS IS = 625 mA, VGS = 0, 0 See Figures 1 and 14 VDS = 48 V, di/dt = 100 A/s A/s, Z1, Z2, Z1 Z2 and Z3 50 nC MIN TYP 45 MAX UNIT ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-3 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 resistive-load switching characteristics, TC = 25C PARAMETER td(on) td(off) tr tf Qg Qgs(th) Qgd LD LS Rg Turn-on delay time Turn-off delay time Rise time Fall time Total gate charge Threshold gate-to-source charge Gate-to-drain charge Internal drain inductance Internal source inductance Internal gate resistance VDS = 48 V, V See Figure 3 ID = 625 mA, A VGS = 5 V, V VDD = 25 V, , tdis = 10 ns, RL = 40 , , See Figure 2 ten = 10 ns, , TEST CONDITIONS MIN TYP 34 80 28 15 4.6 0.7 2.5 5 5 0.25 nH MAX 70 150 55 30 5.8 0.88 3.13 nC ns UNIT thermal resistance PARAMETER RJA RJB Junction-to-ambient thermal resistance Junction-to-board thermal resistance TEST CONDITIONS See Notes 4 and 7 See Notes 5 and 7 MIN TYP 90 44.5 28 C/W MAX UNIT RJP Junction-to-pin thermal resistance See Notes 6 and 7 NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power 2-4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 PARAMETER MEASUREMENT INFORMATION 1.5 VDS = 48 V VGS = 0 TJ = 25C Z1, Z2, and Z3 1 I S - Source-to-Drain Diode Current - A trr(SD) Reverse di/dt = 100 A/s 0.5 0 - 0.5 25% of IRM -1 Shaded Area = QRR - 1.5 -2 IRM - 2.5 0 50 100 150 200 250 300 350 400 450 500 Time - ns IRM = maximum recovery current Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode VDD = 25 V RL Pulse Generator ten VDS VGS 0V DUT Rgen 50 50 CL = 30 pF (see Note A) VDS VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. td(on) tf td(off) tr VDD VDS(on) tdis 5V VGS Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-5 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 PARAMETER MEASUREMENT INFORMATION Current Regulator 12-V Battery 0.2 F 50 k 0.3 F VDS IG = 100 A DUT VDD VGS Gate Voltage Time IG CurrentSampling Resistor TEST CIRCUIT ID CurrentSampling Resistor VOLTAGE WAVEFORM Same Type as DUT Qg 5V Qgs(th) Qgd 0 Figure 3. Gate-Charge Test Circuit and Voltage Waveform VDD = 25 V tw 7 mH Pulse Generator (see Note A) VGS 50 Rgen 50 VDS DUT ID VDS VGS 0V IAS (see Note B) 0V V(BR)DSX = 60 V Min tav 5V ID 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration (tw) is increased until peak current IAS = 4 A. I V t av AS (BR)DSX Energy test level is defined as E 96 mJ. AS 2 + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms 2-6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 TYPICAL CHARACTERISTICS GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) - Gate-to-Source Threshold Voltage - V 2.5 VDS = VGS r DS(on) - Static Drain-to-Source 2 ID = 1 mA 1.5 0.8 On-State Resistance - STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 1 ID = 1.25 A 0.6 VGS = 4.5 V 0.4 VGS = 5 V 0.2 1 ID = 100 A 0.5 0 - 40 - 20 0 20 40 60 80 100 120 140 160 0 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 5 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 1 TJ = 25C 4 Figure 6 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE VGS = 0.2 V TJ = 25C VGS = 3 V rDS(on) - Static Drain-to-Source On-State Resistance - VGS = 4.5 V I D - Drain Current - A 3 VGS = 5 V 2 0.1 1 ID - Drain Current - A 10 Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 AA AA AA AA AA AA 1 0 1 2 3 4 5 6 7 8 9 VDS - Drain-to-Source Voltage - V 10 Figure 8 2-7 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 TYPICAL CHARACTERISTICS DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 25 4 Total Number of Units = 1596 VDS = 15 V ID = 625 mA TJ = 25C TJ = - 40C TJ = 25C 3 I D - Drain Current - A TJ = 75C TJ = 125C TJ = 150C 2 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 20 Percentage of Units - % 15 10 1 5 1.600 1.620 1.640 1.660 1.680 1.700 1.720 1.740 1.760 1.780 1.800 1.820 1.840 0 0 0 1 2 3 4 5 VGS - Gate-to-Source Voltage - V gfs - Forward Transconductance - S Figure 9 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 800 720 640 Capacitance - pF 560 480 400 320 240 160 80 0 0 4 8 12 16 20 24 28 32 36 40 VDS - Drain-to-Source Voltage - V Ciss Coss Crss I SD - Source-to-Drain Diode Current - A VGS = 0 f = 1 MHz TJ = 25C Ciss(0) = 307 pF Coss(0) = 437 pF Crss(0) = 141 pF 10 VGS = 0 Figure 10 SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 1 TJ = 125C TJ = 150C TJ = - 40C TJ = 25C TJ = 75C 0.1 1 VSD - Source-to-Drain Voltage - V 10 Figure 11 Figure 12 2-8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 TYPICAL CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 60 ID = 625 mA TJ = 25C See Figure 3 VDD = 20 V 40 VDD = 30 V 30 6 8 12 VDS - Drain-to-Source Voltage - V 20 VDD = 48 V VDD = 20 V 0 0 1 2 3 4 5 6 7 8 Qg - Gate Charge - nC 4 10 2 0 Figure 13 REVERSE-RECOVERY TIME vs REVERSE di/dt 50 45 trr - Reverse-Recovery Time - ns 40 Z1, Z2, and Z3 35 30 25 20 15 10 5 0 0 VDS = 48 V VGS = 0 IS = 625 mA TJ = 25C See Figure 1 100 200 300 400 500 600 Reverse di/dt - A/s Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VGS - Gate-to-Source Voltage - V 50 10 2-9 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 10 I AS - Maximum Peak Avalanche Current - A TC = 25C I D - Maximum Drain Current - A 1 s 10 See Figure 4 MAXIMUM PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 1 ms 10 ms 1 500 s TC = 25C JP JA DC Conditions 0.1 1 10 100 TC = 125C AA AA 2-10 1 0.01 VDS - Drain-to-Source Voltage - V Less than 2% duty cycle Device mounted on FR4 printed-circuit board with no heatsink. Device mounted in intimate contact with infinite heatsink. 0.1 1 10 tav - Time Duration of Avalanche - ms 100 Figure 16 Figure 15 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC1321L 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS042 - NOVEMBER 1994 THERMAL INFORMATION DW PACKAGE JUNCTION - TO -BOARD THERMAL RESISTANCE vs PULSE DURATION 100 DC Conditions d = 0.5 RJB - Junction-to-Board Thermal Resistance - C/W d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 1 d = 0.01 Single Pulse tw tc ID 0 0.1 0.0001 0.001 0.01 0.1 tw - Pulse Duration - s 1 10 100 Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE A: ZB(t) = r(t) RJB tw = pulse duration tc = cycle time d = duty cycle = tw / tc Figure 17 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-11 2-12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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